TMUX136MRSER [TI]
具有断电保护功能的 1.4pF 导通状态电容、5V、2:1 (SPDT)、2 通道模拟开关 | RSE | 10 | -40 to 125;
| 型号： | TMUX136MRSER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有断电保护功能的 1.4pF 导通状态电容、5V、2:1 (SPDT)、2 通道模拟开关 | RSE | 10 | -40 to 125 开关 光电二极管 输出元件 |
| 文件： | 总26页 (文件大小：2904K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUX136
ZHCSGX3E –AUGUST 2017 –REVISED JUNE 2023
TMUX136 具有断电隔离功能的6GHz 双通道2:1 开关
1 特性
3 说明
• VCC 范围2.3V 至4.8V
• 高性能开关特性：
– 带宽(–3dB)：6.1GHz
– RON（典型值）：5.7Ω
– CON（典型值）：1.6pF
• 电流消耗：30µA（典型值）
• 专有特性：
– IOFF 保护可防止在断电状态下产生漏电流
– 1.8V 兼容控制输入（SEL，EN）
• 直通引脚排列可简化PCB 布局
• 与高速I3C 信号兼容
TMUX136 器件是一款高性能 6GHz 双通道 2:1 开关，
同时支持差分和单端信号。该器件具有 2.3V 至 4.8V
的较宽 VCC 范围，支持断电保护功能，当 VCC 引脚断
电时，强制所有 I/O 引脚进入高阻抗模式。TMUX136
的部分引脚支持 1.8V 控制电压，允许它们直接与低电
压处理器的通用 I/O (GPIO) 相连。输入和输出分别位
于器件两侧的直通引脚排列简化了布局布线。这一特性
连同器件的低导通电阻和低导通电容，使得 TMUX136
成为支持切换各种模拟信号和数字通信协议标准（包括
I3C 等高速标准）的出色器件。
TMUX136 采用小型 10 引脚 UQFN 封装，尺寸仅为
1.5mm × 2mm，非常适合PCB 面积有限的情况。
• ESD 性能：
– 5kV 人体放电模型（A114B，II 类）
– 1kV 充电器件模型(C101)
• 紧凑型10 引脚UQFN 封装
封装信息
封装(1)
封装尺寸(2)
器件型号
TMUX136
RSE（UQFN，10） 2mm × 1.5mm
（1.5mm × 2mm，间距为0.5mm）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
(2) 封装尺寸（长× 宽）为标称值，并包括引脚（如适用）。
• I3C (SenseWire)
• 移动行业处理器接口(MIPI)
• 服务器
• 手持终端：智能手机
• 笔记本电脑
• 平板电脑：多媒体
• 电子销售终端
• 现场仪器
• 便携式监视器
COM1
COM2
A1
A2
A
B
VCC
B1
B2
Charge
Pump
SEL
EN
Digital Control
简化原理图
EN (see Note A)
Note A: EN is the internal enable signal applied to the switch.
功能方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS367
TMUX136
www.ti.com.cn
ZHCSGX3E –AUGUST 2017 –REVISED JUNE 2023
Table of Contents
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
9.3 Power Supply Recommendations.............................16
9.4 Layout....................................................................... 16
10 Device and Documentation Support..........................18
10.1 Documentation Support.......................................... 18
10.2 接收文档更新通知................................................... 18
10.3 支持资源..................................................................18
10.4 Trademarks.............................................................18
10.5 静电放电警告.......................................................... 18
10.6 术语表..................................................................... 18
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Dynamic Characteristics............................................. 7
6.7 Timing Requirements..................................................7
6.8 Typical Characteristics................................................8
7 Parameter Measurement Information............................9
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
Information.................................................................... 18
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (August 2020) to Revision E (June 2023)
Page
• 向数据表添加了 I3C (SenseWire) 应用信息........................................................................................................1
• 添加了封装信息 表..............................................................................................................................................1
Changes from Revision C (July 2018) to Revision D (August 2020)
Page
• Added new specification limits to support added temperature range TA = -40°C to +125°C .............................4
Changes from Revision B (November 2017) to Revision C (July 2018)
Page
• Changed pin 6 To: EN, pin 7 To: COM2, and pin 8 To: COM1 in 图9-19 ........................................................17
Changes from Revision A (October 2017) to Revision B (November 2017)
Page
• Changed Pin 7 From: COM1 To: COM2.............................................................................................................3
• Changed Pin 8 From: COM2 To: COM1.............................................................................................................3
Changes from Revision * (August 2017) to Revision A (October 2017)
Page
• Changed the HBM value From: ±3500 To: ±5000 in the ESD Ratings table...................................................... 4
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English Data Sheet: SCDS367
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5 Pin Configuration and Functions
A1
1
9
SEL
A2
B1
2
3
8
7
COM1
COM2
B2
4
6
EN
Not to scale
图5-1. RSE Package, 10-Pin UQFN (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
1
NAME
A1
I/O
I/O
I/O
I/O
Signal path A1
2
A2
Signal path A2
3
B1
Signal path B1
4
B2
Signal path B2
5
GND
EN
Ground
—
I
6
Enable (active low)
Common signal path 2
Common signal path 1
7
COM2
COM1
SEL
VCC
I/O
I/O
I
8
9
Switch select (logic Low = COM to A PORT Logic High = COM to B PORT)
Supply voltage
10
—
(1) I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
–0.3
–0.3
–50
–50
MAX
UNIT
V
VCC
VI/O
VSEL, VEN
IK
Supply voltage(3)
5.5
5.5
5.5
Input-output DC voltage(3)
Digital input voltage (SEL, EN)
Input-output port diode current
Digital logic input clamp current(3)
Continuous current through VCC
Continuous current through GND
Storage temperature
V
V
VI/O < 0
VI < 0
mA
mA
mA
mA
°C
IIK
ICC
100
150
IGND
Tstg
–100
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
±5000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX UNIT
VCC
Supply voltage
2.3
0
4.8
3.6
V
V
VI/O
Analog voltage
VSEL, VEN
TRAMP (VCC
II/O
Digital input voltage (SEL, EN)
Power supply ramp time requirement (VCC
0
VCC
1000
V
)
)
100
μs/V
±20 mA
±10 mA
Continuous current through I/O signal path (COMx, Ax, Bx) TA = –40°C to +85°C
Continuous current through I/O signal path (COMx, Ax, Bx) TA = –40°C to +125°C
Operating free-air temperature
II/O
TA
125
°C
–40
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6.4 Thermal Information
TMUX136
THERMAL METRIC (1)
RSE (UQFN)
10 PINS
191.6
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
94.3
117.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
7.4
117.4
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = –40°C to +85°C, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
A PORT SWITCH
VCC = 2.7 V
VCC = 2.3 V
VCC = 2.7 V
5.7
9
VI/O = 1.65 V, ION = –8 mA
VI/O = 1.65 V, ION = –8 mA
5.7 9.5
13
VI/O = 1.65 V, ION = –8 mA
TA = –40°C to +125°C
RON
ON-state resistance
ON-state resistance
Ω
VCC = 2.3 V
VI/O = 1.65 V, ION = –8 mA
TA = –40°C to +125°C
13
match between signal VCC = 2.3 V
path 1 and 2
0.1
ΔRON
VI/O = 1.65 V, ION = –8 mA
Ω
Ω
RON
ON-state resistance
VCC = 2.3 V
1
VI/O = 1.65 V to 3.45 V, ION = –8 mA
flatness
(FLAT)
Switch OFF, VB = 1.65 V to 3.45 V,
VCOM = 0 V
2
–2
–15
–10
–50
–2
IOZ
OFF leakage current
VCC = 4.8 V
µA
µA
Switch OFF, VB = 1.65 V to 3.45 V,
VCOM = 0 V
TA = –40°C to +125°C
15
10
Switch ON or OFF, VB = 1.65 V to 3.45 V,
VCOM = NC
Power-off leakage
current
IOFF
VCC = 0 V
Switch ON or OFF, VB = 1.65 V to 3.45 V,
VCOM = NC
TA = –40°C to +125°C
50
Switch ON, VB = 1.65 V to 3.45 V,
VCOM = NC
2
VCC = 4.8 V
Switch ON, VB = 1.65 V to 3.45 V,
VCOM = NC
15
–15
TA = –40°C to +125°C
ION
ON leakage current
µA
Switch ON, VB = 1.65 V to 3.45 V,
VCOM = NC
–
125
125
175
VCC = 2.3 V
Switch ON, VB = 1.65 V to 3.45 V,
VCOM = NC
TA = –40°C to +125°C
–
175
B PORT SWITCH
4.6 7.5
12
VI/O = 0.4 V, ION = –8 mA
RON
ON-state resistance
VCC = 2.3 V
Ω
VI/O = 0.4 V, ION = –8 mA
TA = –40°C to +125°C
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6.5 Electrical Characteristics (continued)
TA = –40°C to +85°C, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
ON-state resistance
match between signal VCC = 2.3 V
path 1 and 2
0.1
1
ΔRON
VI/O = 0.4 V, ION = –8 mA
Ω
Ω
RON
ON-state resistance
VCC = 2.3 V
VI/O = 0 V to 0.4 V, ION = –8 mA
flatness
(FLAT)
Switch OFF, VA = 0 V to 3.6 V, VCOM = 0 V
2
–2
IOZ
OFF leakage current
VCC = 4.8 V
µA
µA
Switch OFF, VA = 0 V to 3.6 V, VCOM = 0 V
TA = –40°C to +125°C
15
–15
Switch ON or OFF, VA = 0 V to 3.6 V,
VCOM = NC
10
50
–10
–50
–2
Power-off leakage
current
IOFF
VCC = 0 V
Switch ON or OFF, VA = 0 V to 3.6 V,
VCOM = NC
TA = –40°C to +125°C
Switch ON, VA = 0 V to 3.6 V,
VD± = NC
VCC = 4.8 V
VCC = 4.8 V
2
Switch ON, VA = 0 V to 3.6 V,
VD± = NC
15
–15
TA = –40°C to +125°C
ION
ON leakage current
µA
Switch ON, VA = 0 V to 3.6 V,
VB = NC
–
125
VCC = 2.3 V
VCC = 2.3 V
125
175
Switch ON, VA = 0 V to 3.6 V,
VB = NC
TA = –40°C to +125°C
–
175
DIGITAL CONTROL INPUTS (SEL, EN)
VCC = 2.3 V to 4.8 V
TA = –40°C to +125°C
VIH
Input logic high
1.3
V
VCC = 2.3 V to 4.8 V
TA = –40°C to +125°C
VIL
IIN
Input logic low
0.6
10
V
Input leakage current
VCC = 4.8 V, VI/O = 0 V to 3.6 V, VIN = 0 to 4.8 V
–10
μA
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6.6 Dynamic Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
VCC = 3.3 V, VI/O = 0 or 3.3 V,
f = 240 MHz
PORT B ON capacitance
Switch ON
Switch ON
Switch OFF
Switch OFF
1.6
1.4
1.4
2
2
2
2
pF
pF
pF
CON
VCC = 3.3 V, VI/O = 0 or 3.3 V,
f = 240 MHz
PORT A ON capacitance
PORT B OFF capacitance
VCC = 3.3 V, VI/O = 0 or 3.3 V
f = 240 MHz
COFF
VCC = 3.3 V, VI/O = 0 or 3.3 V
f = 240 MHz
PORT A OFF capacitance
Digital input capacitance
OFF Isolation
1.6
2.2
pF
pF
dB
CI
VCC = 3.3 V, VI = 0 or 2 V
VCC = 2.3 V to 4.8 V, RL = 50 Ω,
f = 240 MHz
OISO
Switch OFF
–34
VCC = 2.3 V to 4.8 V, RL = 50 Ω,
XTALK
Crosstalk
Switch ON
Switch ON
dB
–37
f = 240 MHz
BW
6.1
GHz
–3-dB bandwidth
VCC = 2.3 V to 4.8 V, RL = 50 Ω,
SUPPLY
VCC
Power supply voltage
Positive supply current
2.3
4.8
50
V
VCC = 4.8 V, VIN = VCC or GND, VI/O = 0 V,
Switch ON or OFF
30
5
ICC
µA
VCC = 4.8 V, VIN = VCC or GND, VI/O = 0 V,
Switch ON or OFF
TA = –40°C to +125°C
70
10
20
VCC = 4.8 V, VIN = VCC or GND, VI/O = 0 V,
Switch ON or OFF, OE = H
Power supply current in high-Z
mode
Icc, HZ
µA
VCC = 4.8 V, VIN = VCC or GND, VI/O = 0 V,
Switch ON or OFF, OE = H
TA = –40°C to +125°C
6.7 Timing Requirements
MIN NOM MAX UNIT
tpd
Propagation delay
100
ps
ns
µs
ns
ps
RL = 50 Ω,
CL = 5 pF,
tswitch
Switching time (SEL to output)
600
VCC = 2.3 V to 4.8 V
tZH, ZL Enable time ( EN to output)
tHZ, LZ Disable time ( EN to output)
VI/O = 3.3 V or 0 V
100
200
20
tSK(P)
Skew of opposite transitions of same output
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6.8 Typical Characteristics
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
Vin (V)
C002
.
.
图6-1. ON-Resistance vs VI/O
图6-2. Bandwidth
.
.
图6-3. Off Isolation
图6-4. Cross Talk
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7 Parameter Measurement Information
A
COM
SEL
3 V
1.8 V
B
50 %
50 %
VSEL
CL
RL
RL
0 V
3 V
0 V
tSWITCH
VA/B
tSWITCH
CL
50 %
50 %
VSEL
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A. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr < 5 ns, tf < 5 ns.
B. CL includes probe and jig capacitance.
图7-1. Timing Diagram
VDD
V
OUT1
OUT2
V
ON
V
Channel ON
+
SEL
RON = (VON – VI/O1) / ION or (VON –
VI/O2) / ION
ION
+
VSEL = H or L
VSEL
GND
图7-2. ON-State Resistance (RON
)
VDD
V
OUT1
OUT2
V
+
IOZ
A
SEL
Channel OFF
VSEL = H or L
+
VIN
+
VSEL
GND
图7-3. OFF Leakage Current (IOZ
)
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Network Analyzer
VDD
V
OUT+
RS
VS
V
OUT-
RS
Channel ON
VS
VSEL = H or L
RS=RL=50Ω
GND
R
L
L
R
图7-4. Bandwidth (BW)
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8 Detailed Description
8.1 Overview
The TMUX136 device is a 2-channel, 2:1, switch specifically designed for the switching of high-speed signals in
handset and consumer applications, such as cell phones, tablets, and notebooks but may be used for any high
speed application. The wide bandwidth (6.1 GHz) of this switch allows signals to pass with minimum edge and
phase distortion. The switch is bidirectional and offers little or no attenuation of the high-speed signals at the
outputs and will support both single-ended and differential signals. The device also has a low power mode that
reduces the power consumption to 5 μA for portable applications with a battery or limited power budget.
The TMUX136 device integrates ESD protection cells on all pins, is available in a tiny UQFN package
(1.5 mm × 2 mm) and is characterized over the free-air temperature range from –40°C to +125°C.
8.2 Functional Block Diagram
A
B
VCC
Charge
Pump
EN (see Note A)
Note A: EN is the internal enable signal applied to the switch.
8.3 Feature Description
8.3.1 Low Power Mode
The TMUX136 has a low power mode that reduces the power consumption to 5 μA while the device is not in
use. To put the device in low power mode and disable the switch, the bus-switch enable pin EN must be supplied
with a logic High signal.
8.4 Device Functional Modes
8.4.1 High Impedance Mode
The TMUX136 has a high impedance mode that places all the signal paths in a Hi-Z state while the device is not
in use. As provided in 表 8-1, to put the device in high impedance mode and disable the switch, the bus-switch
enable pin EN must be supplied with a logic High signal.
表8-1. Function Table
SEL
X
EN
High
Low
Low
SWITCH STATUS
Both A PORT and B PORT switches in High-Z
COM to A PORT
Low
High
COM to B PORT
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
There are many applications in which microprocessors or controllers have a limited number of I/Os. The
TMUX136 solution can effectively expand the limited I/Os by switching between multiple buses to interface them
to a single microprocessor or controller. A common application where the TMUX136 is as a I3C 1:2 multiplexer.
In this application, the TMUX136 is used to route communicating between different DDR modules from a single
controller within a server, as shown in 图 9-1. The high bandwidth of the TMUX136 will preserve signal integrity
at even the fastest communication protocols that may be used in server applications, such as I3C.
9.2 Typical Application
3.3 V
0.1 µF
VCC
2-channel SPDT
Memory Controller
SCL
A1
DDR-DRAM
SCL
COM1
COM2
Port A
SDA
A2
SDA
SCL
B1
B2
DDR-DRAM
Port B
SDA
OE
SEL
GND
Switch
Control Logic
图9-1. Typical Application
The TMUX136 supports I3C standard by maintaining signal integrity through the switch. 表 9-1 details how the
TMUX136 specifications make this device optimal for switching I3C signals.
表9-1. TMUX136 I3C Compatibility
I3C Requirements
TMUX136 Specification
0-3.6 V
Voltage (I/O)
Frequency
1.0 V, 1.2 V, 1.8 V, 3.3 V
Up to 12.5 MHz
6 GHz Bandwidth
<2 pF On/Off Capacitance
Capacitance
50 pF maximum bus capacitance
9.2.1 Design Requirements
The TMUX136 has internal 6-MΩ pull-down resistors on SEL and EN, so no external resistors are required on
the logic pins. The internal pull-down resistor on SEL allows the PORT A channel to be selected by default. The
internal pull-down resistor on EN enables the switch when power is applied to VCC
.
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9.2.2 Detailed Design Procedure
The TMUX136 can operate without any external components; however, TI recommends that unused pins must
be connected to ground through a 50-Ωresistor to prevent signal reflections back into the device.
9.2.3 Application Curves
.
图9-3. Time Interval Error Histogram: 0.7 Gbps
图9-2. Eye Pattern: 0.7 Gbps with No Device
with No Device
With Switch
The TMUX136 contributes only 8.4 ps of peak-to-peak jitter for
0.7-Gbps data rate
The TMUX136 contributes only 8.4 ps of peak-to-peak jitter for
0.7-Gbps data rate
图9-4. Eye Pattern: 0.7 Gbps with Switch
图9-5. Time Interval Error Histogram: 0.7 Gbps
with Switch
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.
图9-7. Time Interval Error Histogram: 2.2 Gbps
with No Device
图9-6. Eye Pattern: 2.2 Gbps with No Device
With Switch
The TMUX136 contributes only 3.8 ps of peak-to-peak jitter for
2.2-Gbps data rate
The TMUX136 contributes only 3.8 ps of peak-to-peak jitter for
2.2-Gbps data rate
图9-8. Eye Pattern: 2.2 Gbps with Switch
图9-9. Time Interval Error Histogram: 2.2 Gbps
with Switch
.
图9-11. Time Interval Error Histogram: 3 Gbps with
图9-10. Eye Pattern: 3 Gbps with No Device
No Device
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With Switch
The TMUX136 contributes only 5.8 ps of peak-to-peak jitter for
The TMUX136 contributes only 5.8 ps of peak-to-peak jitter for
3-Gbps data rate
3-Gbps data rate
图9-12. Eye Pattern: 3 Gbps with Switch
图9-13. Time Interval Error Histogram: 3 Gbps with
Switch
.
.
图9-14. Eye Pattern: 4.5 Gbps with No Device
图9-15. Time Interval Error Histogram: 4.5 Gbps
with No Device
With Switch
The TMUX136 contributes only 7.6 ps of peak-to-peak jitter for
4.5-Gbps data rate
The TMUX136 contributes only 7.6 ps of peak-to-peak jitter for
4.5-Gbps data rate
图9-16. Eye Pattern: 4.5 Gbps with Switch
图9-17. Time Interval Error Histogram: 4.5 Gbps
with Switch
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9.3 Power Supply Recommendations
TI recommends placing a bypass capacitor as close to the supply pin VCC as possible to help smooth out lower
frequency noise to provide better load regulation across the frequency spectrum.
9.4 Layout
9.4.1 Layout Guidelines
Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass capacitors near
the high speed traces.
The high-speed signal paths must should be no more than 4 inches long; otherwise, the eye diagram
performance may be degraded.
Route the high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points on twisted pair
lines; through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route high speed signal traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed signals traces because they cause signal reflections. If a stub is unavoidable,
then the stub must be less than 200 mm.
Route all high-speed signal traces over continuous GND planes, with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
Due to high frequencies, a printed circuit board with at least four layers is recommended; two signal layers
separated by a ground and power layer as shown in 图9-18.
Signal 1
GND Plane
Power Plane
Signal 2
图9-18. Four-Layer Board Stack-Up
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must
be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power
plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the
number of signal vias reduces EMI by reducing inductance at high frequencies.
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9.4.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane
VIA to GND Plane
Bypass Capacitor
V+
To Microcontroller
10
VCC
A1
A2
B1
B2
SEL
1
2
3
4
9
8
7
6
Port A
COM1
COM2
EN
To Common Port
Port B
GND
5
To Microcontroller
图9-19. Package Layout Diagram
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, High-Speed Layout Guidelines Application Report
• Texas Instruments, High-Speed Interface Layout Guidelines
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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5-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX136MRSER
TMUX136RSER
ACTIVE
ACTIVE
UQFN
UQFN
RSE
RSE
10
10
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
19H
19G
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jun-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX136MRSER
TMUX136RSER
UQFN
UQFN
RSE
RSE
10
10
3000
3000
180.0
180.0
9.5
9.5
2.2
1.7
1.8
2.2
0.75
0.75
4.0
4.0
8.0
8.0
Q3
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX136MRSER
TMUX136RSER
UQFN
UQFN
RSE
RSE
10
10
3000
3000
189.0
189.0
185.0
185.0
36.0
36.0
Pack Materials-Page 2
PACKAGE OUTLINE
RSE0010A
UQFN - 0.6 mm max height
SCALE 7.000
PLASTIC QUAD FLATPACK - NO LEAD
1.55
1.45
B
A
PIN 1 INDEX AREA
2.05
1.95
C
0.6
0.5
SEATING PLANE
0.05
0.00
0.05 C
0.35
0.25
C A B
C
2X
0.4
0.3
8X
0.1
(0.12)
TYP
0.05
0.45
0.35
2X
5
4
6
SYMM
2X
1.5
0.25
0.15
4X
9
0.1
C A B
C
1
0.05
6X 0.5
10
SYMM
PIN 1 ID
(45 X 0.1)
0.3
0.2
4X
0.1
0.05
C A B
C
4220307/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSE0010A
UQFN - 0.6 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
10
(R0.05) TYP
2X (0.6)
8X (0.55)
9
1
4X (0.25)
SYMM
6X (0.5)
(1.8)
4X
(0.2)
4
6
5
2X (0.3)
(1.35)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
EXPOSED
OPENING
METAL
METAL
UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4220307/A 03/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSE0010A
UQFN - 0.6 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
10
(R0.05) TYP
2X (0.6)
8X (0.55)
1
9
4X (0.25)
SYMM
6X (0.5)
(1.8)
4X (0.2)
4
6
5
2X
(0.3)
(1.35)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICKNESS
SCALE: 30X
4220307/A 03/2020
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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