TMUX154ERSWR [TI]
具有断电保护功能的 7.5pF 导通状态电容、3.3V、2:1 (SPDT)、2 通道模拟开关 | RSW | 10 | -40 to 85;
| 型号： | TMUX154ERSWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有断电保护功能的 7.5pF 导通状态电容、3.3V、2:1 (SPDT)、2 通道模拟开关 | RSW | 10 | -40 to 85 开关 光电二极管 |
| 文件： | 总29页 (文件大小：1340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMUX154E
ZHCSHK9 –FEBRUARY 2018
具有关断保护和 ESD 保护功能的 TMUX154E 低电容双通道 2:1 开关
1 特性
2 应用
1
•
V
CC 工作电压为 3V 至 4.3V
•
•
•
•
•
便携式电子产品
•
•
•
I/O 引脚可耐受电压高达 5.25V 的电压
兼容 1.8V 控制逻辑
打印机和其他外设
电子销售终端
楼宇自动化
服务器
支持关断保护，当 VCC = 0V 时，I/O 引脚处于高阻
抗状态
•
•
•
•
•
•
RON = 10Ω（最大值）
ΔRON = 0.35Ω（典型值）
Cio(ON) = 7.5pF（典型值）
低功耗（最大值为 1uA）
–3dB 带宽 = 900MHz（典型值）
闩锁性能超过
3 说明
TMUX154E 是一款高带宽 2:1 开关，专门针对限制
I/O 的应用中的 高速信号开关 进行设计。此开关具有
较宽的带宽 (900MHz)，这一特性使得信号传递具有最
少的边缘失真和相位失真。此开关为双向开关，高速信
号衰减极少或者没有。它能实现低位间偏移和高通道间
噪声隔离。
(1)
100mA，符合 JESD 78 II 类规范
•
静电放电 (ESD) 性能测试符合 JESD 22 标准
–
8000V 人体放电模型
（A114-B，II 类）
TMUX154E 在所有引脚上集成了 ESD 保护单元，采
用微型 UQFN 封装 (1.8mm × 1.4mm) 或 VSSOP 封
装，自然通风条件下的工作温度范围为 –40°C 至 85°
C。
–
1000V 充电器件模型 (C101)
(2)
•
ESD 性能 I/O 端口接地
–
15000V 人体放电模型
器件信息(1)
器件型号
TMUX154E
封装
VSSOP (10)
UQFN (10)
封装尺寸（标称值）
3.00mm × 3.00mm
1.80mm x 1.40mm
(1) EN 和 SEL 输入除外
(2) 除标准 HBM 测试（A114-B，II 类）外还执行了高压 HBM 测
试，仅适用于进行接地测试的 I/O 端口。
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
空白
空白
功能方框图
A0
A1
A
B0
B1
B
SEL
EN
Control
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SCDS379
TMUX154E
ZHCSHK9 –FEBRUARY 2018
www.ti.com.cn
目录
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions ...................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics .......................................... 5
6.6 Dynamic Electrical Characteristics............................ 6
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 8
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
9
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
12 器件和文档支持 ..................................................... 17
12.1 文档支持................................................................ 17
12.2 接收文档更新通知 ................................................. 17
12.3 社区资源................................................................ 17
12.4 商标....................................................................... 17
12.5 静电放电警告......................................................... 17
12.6 Glossary................................................................ 17
13 机械、封装和可订购信息....................................... 18
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2018 年2 月
*
初始发行版。
2
Copyright © 2018, Texas Instruments Incorporated
TMUX154E
www.ti.com.cn
ZHCSHK9 –FEBRUARY 2018
5 Pin Configuration and Functions
RSW Package
10-PIN UQFN
Top View
DGS Package
10-PIN VSSOP
Top View
VCC
EN
B0
B1
B
SEL
A0
7
1
6
2
8
9
5
4
3
B
EN
V
A1
GND
A
CC
A
10
SEL
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
A0
UQFN
VSSOP
1
7
3
5
2
6
2
8
4
6
3
7
I/O
I/O
I/O
I/O
I/O
I/O
signal path port 0
Common signal path
signal path port 1
B0
A
B
A1
B1
EN = 0 Enable
EN = 1 Disable
EN
8
9
I
Select input:
SEL
10
1
I
SEL = 0 A,B to A0,B0
SEL = 1 A,B to A1,B1
GND
VCC
4
9
5
—
—
Ground
10
Voltage supply
Copyright © 2018, Texas Instruments Incorporated
3
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ZHCSHK9 –FEBRUARY 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (see
(1) (2)
)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC
Supply voltage
7
7
VSEL, VEN Control input voltage
V
VCC > 0
VCC + 0.3
5.25
VI/O
Signal path I/O voltage
V
VCC = 0
VIN < 0
VI/O < 0
IIK
Control input clamp current
I/O port clamp current
–50
mA
mA
mA
mA
°C
II/OK
II/O
–50
ON-state switch current
±64
Continuous current through VCC or GND
Storage temperature
±100
150
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
±8000
UNIT
All pins
Human body model (HBM),
per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
I/O port to GND
±15000
±1000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
(1)
See
.
MIN
3
MAX
4.3
UNIT
VCC
VIH
Supply voltage
V
VCC = 3 V to 3.6 V
VCC = 4.3 V
1.3
1.7
0
VCC
VCC
0.5
High-level control input voltage
V
V
VCC = 3 V to 3.6 V
VCC = 4.3 V
VIL
Low-level control input voltage
0
0.7
VI/O
TA
Data input/output voltage
0
VCC
85
V
Operating ambient temperature
–40
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to Implications of Slow or
Floating CMOS Inputs (SCBA004).
4
Copyright © 2018, Texas Instruments Incorporated
TMUX154E
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ZHCSHK9 –FEBRUARY 2018
6.4 Thermal Information
TMUX154E
DGS (VSSOP) RSW (UQFN)
THERMAL METRIC(1)
UNIT
10 PINS
203.1
88.7
10 PINS
114.5
64.7
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
123.0
21.2
21.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.9
ψJB
121.6
21.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
ISEL , IEN Control inputs
TEST CONDITIONS
MIN TYP(2)
MAX UNIT
VCC = 4.3 V, 0 V, VSEL,VEN = 0 to 4.3 V
±1
μA
VCC = 4.3 V, VO = 0 to 3.6 V, VI = 0,
Switch OFF
IOZ
OFF-state leakage current(3)
Powered off leakage current
Supply current
±1
μA
VCC = 0 V, VAn,Bn = 0 V, VA,B = 0 V to 4.3
V,
VSEL , VEN = VCC or GND
IOFF
±2
μA
VCC = 4.3 V, II/O = 0,
Switch ON or OFF
ICC
1
μA
μA
pF
pF
pF
Difference of supply current due to control
input voltage not VCC or GND
(4)
ΔICC
VCC = 4.3 V, VSELVEN = 2.6 V
10
CSEL
CEN
,
VCC = 0 V,
VSELVEN = VCC or GND
Control inputs digital input capacitance
1
2
VCC = 3.3 V, VI/O = 3.3 V or 0,
Switch OFF
CI/O(OFF) OFF-state input capacitance
VCC = 3.3 V, VI/O = 3.3 V or 0,
Switch ON
CI/O(ON)
ON-state input capacitance
ON-state resistance(5)
7.5
RON
VCC = 3 V, VI = 0.4, IO = –8 mA
6
0.35
2
10
Ω
Ω
Ω
ΔRON
ron(flat)
ON-state resistance match between channels VCC = 3 V, VI = 0.4, IO = –8 mA
ON-state resistance flatness VCC = 3 V, VI = 0 V or 1 V, IO = –8 mA
(1) VI, VO, II, and IO refer to data I/O pins A, B, An, and Bn.
(2) All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each digital control input that is supplied with a voltage other than VCC or GND.
(5) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
Copyright © 2018, Texas Instruments Incorporated
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ZHCSHK9 –FEBRUARY 2018
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6.6 Dynamic Electrical Characteristics
over operating range, TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V
PARAMETER
Crosstalk
TEST CONDITIONS
TYP(1)
UNIT
dB
XTALK
OISO
BW
RL = 50 Ω, f = 1 MHz, See 图 6
RL = 50 Ω, f = 1 MHz, See 图 5
RL = 50 Ω, CL = 5 pF, See 图 7
–97
–85
900
OFF isolation
Bandwidth (–3 dB)
dB
MHz
(1) For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
6.7 Switching Characteristics
over operating range, TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V
PARAMETER
Propagation delay(2) (3)
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
RL = 50 Ω, CL = 5 pF,
See 图 8
tpd
0.25
ns
RL = 50 Ω, CL = 5 pF,
See 图 4
tON
Line enable time, SEL to A, B, An, or Bn
Line disable time, SEL to A, B, An, or Bn
Line enable time, OE to A, B, An, or Bn
Line disable time, OE to A, B, An, or Bn
Output skew between center port to any other port(2)
30
25
30
25
50
20
ns
ns
ns
ns
ps
ps
RL = 50 Ω, CL = 5 pF,
See 图 4
tOFF
tON
RL = 50 Ω, CL = 5 pF,
See 图 4
RL = 50 Ω, CL = 5 pF,
See 图 4
tOFF
tSK(O)
tSK(P)
RL = 50 Ω, CL = 5 pF,
See 图 9
Skew between opposite transitions of the same output RL = 50 Ω, CL = 5 pF,
(2)
(tPHL – tPLH
)
See 图 9
(1) For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
(2) Specified by design
(3) The bus switch contributes no propagational delay other than the RC delay of the on resistance of the switch and the load capacitance.
The time constant for the switch alone is of the order of 0.25 ns for 10-pF load. Since this time constant is much smaller than the rise/fall
times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch, when used in
a system, is determined by the driving circuit on the driving side of the switch and its interactions with the load on the driven side.
6
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TMUX154E
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ZHCSHK9 –FEBRUARY 2018
6.8 Typical Characteristics
0
–2
0
–10
–20
–30
–40
–50
–60
–70
–80
–4
–6
–8
–10
–12
–14
–90
100.0E+3
1.0E+6
10.0E+6
100.0E+6
1.0E+9
10.0E+9
100.0E+3
1.0E+6
10.0E+6
100.0E+6
1.0E+9
10.0E+9
Frequency (Hz)
Frequency (Hz)
图 1. Bandwidth
图 2. OFF Isolation
0
–20
–40
–60
–80
–100
–120
100.0E+3
1.0E+6
10.0E+6
100.0E+6
1.0E+9
10.0E+9
Frequency (Hz)
图 3. Crosstalk
版权 © 2018, Texas Instruments Incorporated
7
TMUX154E
ZHCSHK9 –FEBRUARY 2018
www.ti.com.cn
7 Parameter Measurement Information
V
CC
TEST
R
L
C
L
V
A
V
V
A0
A1
A0
t
50 Ω
50 Ω
5 pF
5 pF
V
ON
CC
CC
A
V
A
(2)
L
C
R
L
A1
t
V
OFF
SEL
EN
1.8 V
0
Logic
Input
or V )
EN
(2)
C
L
R
50%
50%
L
(1)
SEL
V
(V
GND
SEL
t
ON
t
OFF
(1)
V
EN
Switch
Output
V
V
OH
90%
90%
(V or V
A0 A1
)
OL
Copyright © 2018, Texas Instruments Incorporated
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns,
tf < 5 ns.
(2) CL includes probe and jig capacitance.
图 4. Turn-On (tON) and Turn-Off Time (tOFF
)
V
CC
Network Analyzer
50
Channel OFF: A to A0
= V
ꢀ
V
A0
A0
A1
V
SEL
CC
V
A
A
Source
Signal
50
ꢀ
Network Analyzer Setup
Source Power = 0 dBm
V
SEL
SEL
(632-mV P-P at 50- load)
50
ꢀ
ꢀ
+
GND
DC Bias = 350 mV
Copyright © 2018, Texas Instruments Incorporated
图 5. OFF Isolation (OISO
)
V
CC
Network Analyzer
50
Channel ON: A0 to A
Channel OFF: A1 to A
ꢀ
V
V
A0
A0
V
A
V
SEL
= V
CC
Source
Signal
A1
A1
Network Analyzer Setup
Source Power = 0 dBm
ꢀ
50
V
SEL
SEL
50
ꢀ
+
GND
(632-mV P-P at 50- load)
ꢀ
DC Bias = 350 mV
Copyright © 2018, Texas Instruments Incorporated
图 6. Crosstalk (XTALK
)
8
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TMUX154E
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ZHCSHK9 –FEBRUARY 2018
Parameter Measurement Information (接下页)
V
CC
Network Analyzer
50
ꢀ
V
Channel ON: A0 to A
= GND
A0 A0
V
A
V
A
SEL
Source
Signal
A1
Network Analyzer Setup
V
SEL
Source Power = 0 dBm
(632-mV P-P at 50-ꢀ load)
SEL
50
ꢀ
GND
DC Bias = 350 mV
GND
Copyright © 2018, Texas Instruments Incorporated
图 7. Bandwidth (BW)
400 mV
图 8. Propagation Delay
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ZHCSHK9 –FEBRUARY 2018
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Parameter Measurement Information (接下页)
VOH
VOL
Pulse Skew t
SK(P)
VOH
VOL
VOH
VOL
Output Skew t
SK(P)
图 9. Skew Test
10
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TMUX154E
www.ti.com.cn
ZHCSHK9 –FEBRUARY 2018
Parameter Measurement Information (接下页)
V
CC
V
A0
A0
A1
A
V
A
+
Channel ON
VA - VA0
V
A1
r
=
on
IIN
I
A
V
SEL
SEL
V
SEL
= GND
+
GND
Copyright © 2018, Texas Instruments Incorporated
图 10. ON-State Resistance (RON
)
V
CC
V
A0
A0
A1
V
A
A
+
V
A1
+
OFF-State Leakage Current
Channel OFF
V
SEL
= V or V
IH CC
V
SEL
SEL
+
GND
Copyright © 2018, Texas Instruments Incorporated
图 11. OFF-State Leakage Current
V
CC
V
A0
A0
Capacitance
Meter
V
V
= V or GND
CC
BIAS
V
A1
A
A1
= V or GND
SEL
CC
V
A
Capacitance is measured at A0,
A1, A and SEL inputs during on
and off conditions
V
BIAS
V
SEL
SEL
GND
Copyright © 2018, Texas Instruments Incorporated
图 12. Capacitance
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ZHCSHK9 –FEBRUARY 2018
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8 Detailed Description
8.1 Overview
The TMUX154E is a high-bandwidth switch specially designed for the switching and isolating of high-speed
signals in systems with limited I/Os. The wide bandwidth (900 MHz) of this switch allows signals to pass with
minimum edge and phase distortion. The device multiplexes differential or single ended signals from a single
device to one of two corresponding outputs or from two different different devices to one single output. The
switch is bidirectional and offers little or no attenuation of the high-speed signals. It is designed for low bit-to-bit
skew and high channel-to-channel noise isolation.
8.2 Functional Block Diagram
A0
A
A1
B0
B
B1
SEL
Control
EN
Copyright © 2018, Texas Instruments Incorporated
8.3 Feature Description
The TMUX154E has an enable pin EN that can place the signal paths in high impedance. This allows the user to
isolate the signal path when it is not in use and consume less current.
8.4 Device Functional Modes
The device functional modes are shown in 表 1.
表 1. Truth Table
SEL
X
EN
H
FUNCTION
Disconnect
A = A0
L
L
B= B0
H
L
A = A1
B = B1
12
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TMUX154E
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ZHCSHK9 –FEBRUARY 2018
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
There are many applications in which processors and microcontrollers have a limited number of I/Os. The
TMUX154E solution can effectively expand the limited number of I/Os by switching between multiple signal paths
in order to interface them to a single processor or microcontroller. TMUX154E can also be used to connect a
single microcontroller to two signal paths.
9.2 Typical Application
VCC
TMUX154E
A0
A
Device A
A1
Microcontroller
B
B0
Device B
B1
Control
SEL
EN
Copyright © 2018, Texas Instruments Incorporated
图 13. Application Diagram
9.2.1 Design Requirements
TI recommends that the digital control pins SEL and EN be pulled up to VCC or down to GND to avoid undesired
switch positions that could result from the floating pin.
9.2.2 Detailed Design Procedure
The TMUX154E can be properly operated without any external components. However, it is recommended that
unused pins be connected to ground through a 50-Ω resistor to prevent signal reflections back into the device.
版权 © 2018, Texas Instruments Incorporated
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www.ti.com.cn
Typical Application (接下页)
9.2.3 Application Curves
0
–2
–4
–6
–8
–10
–12
–14
100.0E+3
1.0E+6
10.0E+6
100.0E+6
1.0E+9
10.0E+9
Frequency (Hz)
图 14. Bandwidth
14
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TMUX154E
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ZHCSHK9 –FEBRUARY 2018
10 Power Supply Recommendations
TI recommends placing a bypass capacitor as close as possible to the supply pin VCC to help smooth out lower
frequency noise to provide better load regulation across the frequency spectrum.
11 Layout
11.1 Layout Guidelines
Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the
signal traces.
The high-speed traces should always be of equal length and must be no more than 4 inches; otherwise, the eye
diagram performance may be degraded.
Route the high-speed signals using a minimum of vias and corners which will reduce signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the transmission line of the signal and increases the chance
of picking up interference from the other layers of the board. Be careful when designing test points on twisted
pair lines; through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route signal traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices, or IC’s that use or duplicate clock signals.
Avoid stubs on the high-speed signals because they cause signal reflections.
Route all high-speed signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
For high frequency systems, a printed circuit board with at least four layers is recommended: two signal layers
separated by a ground layer and a power layer. The majority of signal traces should run on a single layer,
preferably Signal 1. Immediately next to this layer should be the GND plane, which is solid with no cuts. Avoid
running signal traces across a split in the ground or power plane. When running across split planes is
unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias reduces EMI by reducing
inductance at high frequencies. For more information on layout guidelines, see High Speed Layout Guidelines
(SCAA082)
版权 © 2018, Texas Instruments Incorporated
15
TMUX154E
ZHCSHK9 –FEBRUARY 2018
www.ti.com.cn
11.2 Layout Example
= VIA to GND Plane
0603 Cap
To System
To System
To System
EN
B
VCC
SEL
GND
A
To System
Copyright © 2018, Texas Instruments Incorporated
图 15. Layout Recommendation
16
版权 © 2018, Texas Instruments Incorporated
TMUX154E
www.ti.com.cn
ZHCSHK9 –FEBRUARY 2018
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
如需相关文档，请参阅：
•
•
《CMOS 输入缓慢变化或悬空的影响》，SCBA004
《高速布局指南》，SCAA082
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2018, Texas Instruments Incorporated
17
TMUX154E
ZHCSHK9 –FEBRUARY 2018
www.ti.com.cn
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
18
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX154EDGSR
TMUX154ERSWR
ACTIVE
ACTIVE
VSSOP
UQFN
DGS
RSW
10
10
2500 RoHS & Green
3000 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
1A6
NIPDAU
BXV
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX154EDGSR
TMUX154ERSWR
VSSOP
UQFN
DGS
RSW
10
10
2500
3000
330.0
180.0
12.4
9.5
5.3
1.6
3.4
2.0
1.4
0.8
8.0
4.0
12.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX154EDGSR
TMUX154ERSWR
VSSOP
UQFN
DGS
RSW
10
10
2500
3000
364.0
189.0
364.0
185.0
27.0
36.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
RSW0010A
UQFN - 0.55 mm max height
S
C
A
L
E
7
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
1.45
1.35
A
B
PIN 1 INDEX AREA
1.85
1.75
0.55
0.45
C
NOTE 3
SEATING PLANE
0.05 C
0.05
0.00
2X 0.8
SYMM
(0.13) TYP
3
5
0.45
0.35
9X
2
6
7
SYMM
6X 0.4
1
0.25
10X
0.15
0.07
0.05
C A B
10
8
0.55
0.45
PIN 1 ID
4224897/A 03/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package complies to JEDEC MO-288 variation UDEE, except minimum package height.
www.ti.com
EXAMPLE BOARD LAYOUT
RSW0010A
UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
8
10
SEE SOLDER MASK
DETAIL
10X (0.2)
(0.7)
1
7
SYMM
6X (0.4)
(1.6)
6
2
(R0.05) TYP
9X (0.6)
3
5
(1.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224897/A 03/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSW0010A
UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
8
10
10X (0.2)
6X (0.4)
(0.7)
1
7
SYMM
(1.6)
6
2
(R0.05) TYP
9X (0.6)
3
5
(1.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 30X
4224897/A 03/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
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