TMUX1575YCJR [TI]
具有 1.2V 逻辑电平的低电容、2:1 (SPDT) 4 通道断电保护开关 | YCJ | 16 | -40 to 125;
| 型号： | TMUX1575YCJR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1.2V 逻辑电平的低电容、2:1 (SPDT) 4 通道断电保护开关 | YCJ | 16 | -40 to 125 开关 光电二极管 |
| 文件： | 总31页 (文件大小：1580K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZHCSM11 – OCTOBER 2020
TMUX1575
采用 WCSP 封装并具有 1.2V 逻辑的
TMUX1575 2:1 (SPDT) 4 通道断电保护开关
1 特性
3 说明
•
•
•
宽电源电压范围：1.08V 至 3.6V
低导通电容：5pF
高带宽：1.8GHz
TMUX1575 是一款采用 2:1 (SPDT) 配置的 4 通道互补
金属氧化物半导体 (CMOS) 开关。此器件的体积小
巧，工作电源电压为 1.08V 至 3.6V，可用于从服务器
和通信设备到个人电子设备的广泛应用。此器件可在源
极（SxA、SxB）和漏极 (Dx) 引脚上支持双向模拟和
数字信号，并且能够传递最高 VDD x 2 的信号，最大输
入/输出电压为 3.6V。
• -40°C 至 +125°C 工作温度
•
•
•
•
•
•
兼容 1.2V 逻辑
支持超出电源电压范围的输入电压
逻辑引脚上带有集成下拉电阻器
双向信号路径
TMUX1575 信号路径上的断电保护功能可在移除电源
电压 (VDD = 0V) 时提供隔离。如果没有该保护功能，
开关可通过内部 ESD 二极管为电源轨进行反向供电，
从而对系统造成潜在损坏。
失效防护逻辑
断电保护
2 应用
失效防护逻辑电路允许在电源引脚上施加电压之前，先
在逻辑控制引脚上施加电压，从而保护器件免受潜在的
损害。所有控制输入都具有兼容 1.2V 逻辑的阈值，因
此无需外部逻辑转换。逻辑引脚上带有集成下拉电阻
器，无需外部组件，可减小系统尺寸、降低系统成本。
•
闪存存储器共享
• JTAG 多路复用
• SPI 多路复用
• eMMC 多路复用
器件信息 (1)
•
•
•
智能手表
智能追踪器
手机
封装尺寸（标称值）
器件型号
TMUX1575
封装
WCSP (16)
1.34mm × 1.34mm
• PC 和笔记本电脑
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
•
•
•
•
•
网络接口卡 (NIC)
服务器
数据中心交换机和路由器
无线基础设施
楼宇自动化
• ePOS
TMUX1575
1.2 V
3.3 V
3.3 V
VDD
0.1µF
S1A
D1
FLASH Device #1
S1B
VI/O
VDD
Processor
S1A
S2A
S3A
S4A
MISO
MOSI
SCLK
SS
S2A
D2
S2B
D1
D2
D3
D4
RAM
CPU
S3A
D3
SPI PORT
S3B
FLASH Device #2
S4A
D4
S1B
S2B
S3B
S4B
S4B
MISO
MOSI
SCLK
SS
Peripherals
1.2V Logic
I/O
SEL
EN
LOGIC CONTROL*
GND
GND
SEL
EN
*Internal 6MO Pull-Down on Logic Pins
应用示例
方框图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS423
TMUX1575
ZHCSM11 – OCTOBER 2020
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Table of Contents
7.9 Off Isolation...............................................................15
7.10 Channel-to-Channel Crosstalk................................15
7.11 Bandwidth............................................................... 16
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................18
9 Application and Implementation..................................19
9.1 Typical Application.................................................... 19
10 Power Supply Recommendations..............................20
11 Layout...........................................................................20
11.1 Layout Guidelines................................................... 20
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Documentation Support.......................................... 22
12.2 Receiving Notification of Documentation Updates..22
12.3 Support Resources................................................. 22
12.4 Trademarks.............................................................22
12.5 Electrostatic Discharge Caution..............................22
12.6 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Dynamic Characteristics ............................................ 6
6.7 Timing Requirements .................................................7
6.8 Typical Characteristics................................................8
7 Parameter Measurement Information..........................10
7.1 On-Resistance.......................................................... 10
7.2 Off-Leakage Current................................................. 10
7.3 On-Leakage Current................................................. 11
7.4 IPOFF Leakage Current.............................................. 11
7.5 Transition Time......................................................... 12
7.6 tON (EN) and tOFF (EN) Time......................................... 12
7.7 Break-Before-Make Delay.........................................13
7.8 Charge Injection........................................................14
Information.................................................................... 23
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
October 2020
*
Initial Release
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5 Pin Configuration and Functions
1
2
3
4
A
B
C
D
S2A
S3A
S4A
D1
S1A
S1B
S2B
VDD
SEL
D2
EN
GND
D3
S3B
S4B
D4
Not to scale
图 5-1. WCSP Package 16-Pin Top View
Pin Functions
PIN
TYPE(1)
DESCRIPTION(2)
Source pin 2A. Can be an input or output.
NAME
S2A
NO.
A1
A2
A3
A4
B1
I/O
I/O
I/O
I/O
I/O
S1A
S1B
S2B
S3A
VDD
Source pin 1A. Can be an input or output.
Source pin 1B. Can be an input or output.
Source pin 2B. Can be an input or output.
Source pin 3A. Can be an input or output.
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
B2
P
EN
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
I
Active high enable: Internal 6 MΩ pull-down to GND.
Source pin 3B. Can be an input or output.
Source pin 4A. Can be an input or output.
Select pin: controls state of switches according to 表 8-1. Internal 6 MΩ pull-down to GND.
Ground (0 V) reference
S3B
S4A
SEL
GND
S4B
D1
I/O
I/O
I
P
I/O
I/O
I/O
I/O
I/O
Source pin 4B. Can be an input or output.
Drain pin 1. Can be an input or output.
D2
Drain pin 2. Can be an input or output.
D3
Drain pin 3. Can be an input or output.
D4
Drain pin 4. Can be an input or output.
(1) I = input, O = output, I/O = input and output, P = power.
(2) Refer to 节 8.4 for what to do with unused pins.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
–0.5
–0.5
–30
–0.5
–20
–65
MAX
UNIT
V
VDD
Supply voltage
4
4
VSEL or VEN
ISEL or IEN
VS or VD
IS or ID (CONT)
Tstg
Logic control input pin voltage (SEL or EN)
Logic control input pin current (SEL or EN)
Source or drain pin voltage
V
30
4
mA
V
Source and drain pin continuous current: (SxA, SxB, Dx)
Storage temperature
20
150
150
mA
°C
°C
TJ
Junction temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
3.6
UNIT
V
VDD
Supply voltage
1.08
0
Signal path input/output voltage (source or drain pin), VDD ≥ 1.08 V(1)
Signal path input/output voltage (source or drain pin), VDD =0 V
Logic control input voltage (EN, SEL)
VS or VD
VS_off or VD_off
VSEL or VEN
TA
VDD x 2
3.6
V
0
V
0
3.6
V
Ambient temperature
125
ºC
–40
(1) Device input/output can operate up to VDD x 2, with a maximum input/output voltage of 3.6 V.
6.4 Thermal Information
DEVICE
THERMAL METRIC(1)
YCJ (WCSP)
16 PINS
89.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
21.4
0.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJT
21.3
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VDD = 1.08 V to 3.6 V, GND = 0V, TA = –40°C to +125°C
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VSEL = 0 V, 1.2V or VDD
VS = 0 V to 3.6 V
TA = –40°C to +85°C
IDD
Active supply current
Active supply current
7
7
10
14
µA
µA
VSEL = 0 V, 1.2V or VDD
VS = 0 V to 3.6 V
IDD
TA = –40°C to +125°C
DC CHARACTERISTICS
RON ON-state resistance
VS = 0 V to VDD
ISD = 8 mA
1.7
3
6.5
8
Ω
Ω
VS = 0 V to VDD * 2
VS(max) = 3.6 V
ISD = 8 mA
RON
On-resistance
VS = VDD
ISD = 8 mA
On-resistance match between channels
On-resistance flatness
0.1
1
0.4
3.5
ΔRON
Ω
Ω
RON(FLAT)
VS = 0 V to VDD
ISD = 8 mA
VDD = 0 V
IPOFF
Powered-off I/O pin leakage current
OFF leakage current
VS = 0 V to 3.6 V
VD = 0 V
0.01
0.01
2
µA
nA
–2
Switch Off
VD = 0.8*VDD / 0.2*VDD
VS = 0.2*VDD / 0.8*VDD
TA = –40°C to +85°C
IS(OFF)
ID(OFF)
10
–10
Switch Off
VD = 0.8*VDD / 0.2*VDD
VS = 0.2*VDD / 0.8*VDD
TA = –40°C to +125°C
IS(OFF)
ID(OFF)
OFF leakage current
ON leakage current
0.01
0.01
100
10
nA
nA
–100
–10
Switch On
VD = 0.8 x VDD / 0.2 x VDD, S pins floating
or
VS = 0.8 x VDD / 0.2 x VDD, D pins floating
ID(ON)
IS(ON)
TA = –40°C to +85°C
Switch On
VD = 0.8*VDD / 0.2*VDD, S pins floating
or
VS = 0.8*VDD / 0.2*VDD, D pins floating
ID(ON)
IS(ON)
ON leakage current
0.01
160
nA
–160
TA = –40°C to +125°C
LOGIC INPUTS
VIH
VIL
IIH
Input logic high
0.8
0
3.6
0.45
2.5
V
Input logic low
V
Input high leakage current
Input low leakage current
Internal pull-down resistor on logic pins
VSEL = 1.8 V, VDD
VSEL = 0 V
0.5
0.1
6
μA
μA
MΩ
IIL
–1
RPD
VSEL = 0 V, 1.8 V or VDD
f = 1 MHz
CI
Logic input capacitance
3
pF
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6.6 Dynamic Characteristics
VDD = 1.08 V to 3.6 V, GND = 0V, TA = –40°C to +125°C
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VS = 2.5 V
VSEL= 0 V
f = 1 MHz
Switch
OFF
COFF
Source and drain off capacitance
3.5
pF
VS = 2.5 V
VSEL= 0 V
f = 1 MHz
Switch
ON
CON
Source and drain on capacitance
Charge Injection
10
5
pF
VS = VDD/2
RS = 0 Ω, CL =1 nF
Switch
ON
QC
pC
dB
Switch
OFF
RL = 50 Ω
f = 100 kHz
–95
–70
–90
1.8
OISO
Off isolation
Switch
OFF
RL = 50 Ω
f = 1 MHz
dB
Switch
ON
RL = 50 Ω
f = 100 kHz
XTALK
BW
Channel to Channel crosstalk
Bandwidth
dB
Switch
ON
GHz
dB
RL = 50 Ω
Switch
ON
RL = 50 Ω
f = 1 MHz
ILOSS
Insertion loss
–0.15
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6.7 Timing Requirements
VDD = 1.08 V to 3.6 V, GND = 0V, TA = –40°C to +125°C
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VDD = 1.8 V to 3.6 V
VS = VDD
tTRAN
Transition time from control input
35
80
ns
RL = 200 Ω, CL = 15pF
VDD < 1.8 V
VS = VDD
RL = 200 Ω, CL = 15pF
tTRAN
Transition time from control input
Device turn on time from enable pin
40
115
ns
VS = VDD
RL = 200 Ω, CL = 15pF
tON(EN)
55
30
130
60
ns
ns
VS = VDD
RL = 200 Ω, CL = 15pF
tOFF(EN) Device turn off time from enable pin
tON(VDD) Device turn on time (VDD to output)
VS = VDD
VDD rise time = 1us
RL = 200 Ω, CL = 15pF
300
1
990
12
µs
VS = VDD
VDD fall time = 1us
RL = 200 Ω, CL = 15pF
tOFF(VDD) Device turn off time (VDD to output)
µs
ns
VS = 1 V
RL = 200 Ω, CL = 15pF
tOPEN
Break before make time
1
(BBM)
tSK(P)
tPD
Inter - channel skew
Propagation delay
6
ps
ps
60
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6.8 Typical Characteristics
At TA = 25°C, VDD = 3.3 V (unless otherwise noted).
4
5
4
3
2
1
125èC
85èC
25èC
-40èC
125èC
85èC
25èC
-40èC
3
2
1
0
1 2
Source or Drain Voltage (V)
3
3.6
0
0.5
1
1.5
2
Source or Drain Voltage (V)
2.5
3
3.5
D001
D002
VDD = 3.3 V
VDD = 1.8 V
图 6-1. On-Resistance vs Temperature
图 6-2. On-Resistance vs Temperature
3
10
8
VDD = 3.3 V
VDD = 1.8 V
6
2.5
2
4
2
0
-2
-4
-6
-8
-10
1.5
1
0
1 2
Source or Drain Voltage (V)
3
3.6
0
0.6
1.2
1.8
Source or Drain Voltage (V)
2.4
3
3.3
D003
DB0o1o1k
TA = 25°C
VDD = 3.3 V
图 6-3. On-Resistance vs Source or Drain Voltage
图 6-4. On-Leakage vs Source or Drain Voltage
9
70
VDD = 3.6 V
VDD = 1.8 V
VDD = 1.08 V
Transiton_Falling
Transiton_Rising
65
60
55
50
45
40
35
30
25
8.5
8
7.5
7
6.5
6
5.5
5
0
0.5
1
1.5
Logic Voltage (V
2
2.5
3
3.5
1
1.5
2
Supply Voltage (V)
2.5
3
3.3
D006
D007
TA = 25°C
TA = 25°C
图 6-5. Supply Current vs Logic Voltage
图 6-6. TTRANSITION vs Supply Voltage
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160
140
120
100
80
60
50
40
30
20
60
40
1
1.5
2
Supply Voltage (V)
2.5
3
3.3
1
1.5
2
Supply Voltage (V)
2.5
3
3.3
D004
D010
TA = 25°C
TA = 25°C
图 6-7. TON (EN) vs Supply Voltage
图 6-8. TOFF (EN) vs Supply Voltage
75
65
55
45
35
25
15
5
0
Propagation Delay
Skew
Crosstalk
Off Isolation
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
1.5
2
2.5
Supply Voltage (V)
3
3.3
100k
1M
10M 100M
Frequency (Hz)
1G
D008
D009
TA = 25°C
TA = 25°C
图 6-9. Skew and Propagation Delay vs Supply
图 6-10. Off Isolation and Crosstalk vs Frequency
Voltage
0
-1
-2
-3
-4
-5
-6
100k
1M
10M 100M
Frequency (Hz)
1G
D005
TA = 25°C
图 6-11. On-Response vs Frequency
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-
resistance. The measurement setup used to measure RON is shown in 图 7-1. Voltage (V) and current (ISD) are
measured using this setup, and RON is computed as shown below with RON = V / ISD
:
V
ISD
Sx
Dx
VS
图 7-1. On-Resistance Measurement Setup
7.2 Off-Leakage Current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS (OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID (OFF)
.
The setup used to measure both off-leakage currents is shown in 图 7-2.
VDD
VDD
IS (OFF)
A
VDD
VDD
ID (OFF)
S1A
S1B
S1A
D1
D1
A
S1B
VS
VD
VD
VD
VS
ID (OFF)
A
IS (OFF)
A
S4A
S4B
D4
S1A
S1B
D1
VD
VS
VS
VD
GND
GND
VD
图 7-2. Off-Leakage Measurement Setup
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS (ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID (ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VDD
IS (ON)
VDD
VDD
ID (ON)
S1A
S1A
S1B
A
N.C.
D1
D1
A
N.C.
S1B
N.C.
N.C.
VS
VD
IS (ON)
ID (ON)
A
S4A
S4B
S4A
S4B
N.C.
N.C.
A
D4
D4
N.C.
N.C.
VS
VD
GND
GND
图 7-3. On-Leakage Measurement Setup
7.4 IPOFF Leakage Current
IPOFF leakage current is defined as the leakage current flowing into or out of the source pin when the device is
powered off. This current is denoted by the symbol IPOFF
.
The setup used to measure both IPOFF leakage current is shown in 图 7-4.
VDD
IPOFF
VDD
S1A
A
D1
S1B
N.C.
VS
VD
IPOFF
S4A
S4B
A
D4
N.C.
VS
VD
GND
图 7-4. IPOFF Leakage Measurement Setup
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7.5 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the select signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device. The time constant from the load resistance and load capacitance can be added to the transition time
to calculate system level timing. 图 7-5 shows the setup used to measure transition time, denoted by the symbol
tTRANSITION
.
VDD
0.1ꢀF
VDD
VDD
ADDRESS
DRIVE
tf < 5ns
tr < 5ns
VIH
S1A
S1B
(VSEL
)
VS
VIL
OUTPUT
RL
D1
D4
0 V
CL
tTRANSITION
tTRANSITION
S4A
S4B
VS
OUTPUT
RL
CL
90%
OUTPUT
SEL
GND
VSEL
10%
0 V
图 7-5. Transition-Time Measurement Setup
7.6 tON (EN) and tOFF (EN) Time
The tON (EN) time is defined as the time taken by the output of the device to rise to 90% after the enable has
fallen past the logic threshold. The 90% measurement is used to provide the timing of the device being enabled
in the system. 图 7-6 shows the setup used to measure the enable time, denoted by the symbol tON (EN)
.
VDD
0.1ꢀF
VDD
VDD
ENABLE
DRIVE
tr < 5ns
tf < 5ns
S1A
S1B
VIH
VS
OUTPUT
D1
(VEN
)
VIL
CL
RL
0 V
S4A
S4B
VS
tOFF
tON (EN)
(EN)
OUTPUT
RL
D4
90%
CL
OUTPUT
0 V
EN
10%
VEN
GND
图 7-6. tON (EN) and tOFF (EN) Time Measurement Setup
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7.7 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. 图 7-7 shows the
setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
0.1ꢀF
VDD
VDD
VSEL
0 V
S1A
S1B
VS
OUTPUT
RL
D1
D4
tr < 5ns
tf < 5ns
CL
S4A
S4B
VS
OUTPUT
RL
90%
Output
0 V
tBBM
1
tBBM
2
CL
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
SEL
VSEL
GND
图 7-7. Break-Before-Make Delay Measurement Setup
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7.8 Charge Injection
The amount of charge injected into the source or drain of the device during the falling or rising edge of the gate
signal is known as charge injection, and is denoted by the symbol QC. 图 7-8 shows the setup used to measure
charge injection from source (Sx) to drain (Dx).
VDD
0.1ꢀF
VDD
VDD
S1A
VS
OUTPUT
D1
VOUT
CL
VEN
0 V
S1B
S4A
S4B
VS
Output
VS
OUTPUT
D4
VOUT
CL
VOUT
QC = CL
×
VOUT
EN
VEN
GND
图 7-8. Charge-Injection Measurement Setup
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7.9 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图 7-9 shows
the setup used to measure off isolation. Use off isolation equation to compute off isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
S
D
50Ω
VSIG
VOUT
RL
SxA / SxB / Dx
50Ω
RL
GND
50Ω
图 7-9. Off Isolation Measurement Setup
≈
∆
«
’
VOUT
VS
Off Isolation = 20 ∂ Log
÷
◊
(1)
7.10 Channel-to-Channel Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图 7-10
shows the setup used to measure, and the equation used to compute crosstalk.
VDD
0.1µF
NETWORK
VDD
ANALYZER
D1
D4
S1A
VOUT
RL
RL
50Ω
50Ω
VS
S4A
RL
50Ω
50Ω
SxA / SxB / Dx
VSIG = 200 mVpp
VBIAS = VDD / 2
RL
50Ω
GND
图 7-10. Channel-to-Channel Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(2)
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7.11 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The
characteristic impedance, Z0, for the measurement is 50 Ω. 图 7-11 shows the setup used to measure
bandwidth.
VDD
0.1µF
NETWORK
VDD
ANALYZER
VS
50Ω
S
D
VSIG
VOUT
RL
50Ω
SxA / SxB / Dx
RL
GND
50Ω
图 7-11. Bandwidth Measurement Setup
#PPAJQ=PEKJ = 20 × .KC (8
)
176
8
5
(3)
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8 Detailed Description
8.1 Overview
The TMUX1575 is a high speed 2:1 (SPDT) 4-ch. switch with powered-off protection. Wide operating supply of
1.08 V to 3.6 V allows for use in a wide array of applications from servers and communication equipment to
personal electronics. The device supports bidirectional analog and digital signals on the source (SxA, SxB) and
drain (Dx) pins. The wide bandwidth of this switch allows little or no attenuation of high-speed signals at the
outputs to pass with minimum edge and phase distortion as well as propagation delay.
8.2 Functional Block Diagram
TMUX1575
S1A
D1
S1B
S2A
D2
S2B
S3A
D3
S3B
S4A
D4
S4B
LOGIC CONTROL*
SEL
EN
*Internal 6MO Pull-Down on Logic Pins
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX1575 conducts equally well from source (SxA, SxB) to drain (Dx) or from drain (Dx) to source (SxA,
SxB). Each channel has very similar characteristics in both directions and supports both analog and digital
signals.
8.3.2 Beyond Supply Operation
When the TMUX1575 is powered from 1.08 V to 3.6 V, the valid signal path input and output voltage ranges from
GND to VDD x 2, with a maximum input/output voltage of 3.6 V.
Example 1: If the TMUX1575 is powered at 1.2 V, the signal range is 0 V to 2.4 V.
Example 2: If the TMUX1575 is powered at 1.8 V, the signal range is 0 V to 3.6 V.
Example 3: If the TMUX1575 is powered at 3.6 V, the signal range is 0 V to 3.6 V.
Other voltage levels not mentioned in the examples support Beyond Supply Operation as long as the supply
voltage falls within the recommended operation conditions of 1.08 V to 3.6 V.
8.3.3 1.2 V Logic Compatible Inputs
The TMUX1575 has 1.2-V logic compatible control inputs. Regardless of the VDD voltage, the control input
thresholds remain fixed, allowing a 1.8-V processor GPIO to control the TMUX1575 without the need for an
external translator. This saves both space and BOM cost. For more information on 1.2 V and 1.8 V logic
implementations, refer to Simplifying Design with 1.8 V logic Muxes and Switches.
8.3.4 Powered-off Protection
Powered-off protection up on the signal path of the TMUX1575 provides isolation when the supply voltage is
removed (VDD = 0 V). When the TMUX1575 is powered-off, the I/Os of the device remain in a high-Z state.
Powered-off protection minimizes system complexity by removing the need for power supply sequencing on the
signal path. The device performance remains within the leakage performance mentioned in the Electrical
Specifications. For more information on powered-off protection, refer to Eliminate Power Sequencing with
Powered-off Protection Signal Switches.
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8.3.5 Fail-Safe Logic
The TMUX1575 has Fail-Safe Logic on the control input pins (SELx) which allows for operation up to 3.6 V,
regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before the
supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by
removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX1575 to be ramped to 3.6 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX1575 with VDD = 1.08 V while allowing the select pins to interface with a logic
level of another device up to 3.6 V.
8.3.6 Integrated Pull-Down Resistors
The TMUX1575 has internal weak pull-down resistors (6 MΩ) to GND to ensure the logic pins are not left
floating. This feature integrates external components and reduces system size and cost.
8.4 Device Functional Modes
The enable (EN) pin is an active-high logic pin that controls the connection between the source (SxA, SxB) and
drain (Dx) pins of the device. When the enable pin is pulled low, all switches are turned off. When the enable is
pulled high, the select pin controls the signal path selection. The select pin (SEL) controls the state of all four
channels of the TMUX1575 and determines which source pin is connected to the drain pins. When the select pin
is pulled low, the SxA pin conducts to the corresponding Dx pins. When the select pin is pulled high, the SxB pin
conducts to the corresponding Dx pins. The TMUX1575 logic pins have internal weak pull-down resistors (6
MΩ) to GND so that it powers-on in a known state.
The TMUX1575 can be operated without any external components except for the supply decoupling capacitors.
Unused logic control pins should be tied to GND or VDD in order to ensure the device does not consume
additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs
(SxA, SxB, or Dx) should be connected to GND.
8.4.1 Truth Tables
表 8-1. TMUX1575 Truth Table
INPUTS
Selected Source Pins Connected To Drain Pins
(Dx)
EN
SEL
S1A connected to D1
S2A connected to D2
S3A connected to D3
S4A connected to D4
1
0
S1B connected to D1
S2B connected to D2
S3B connected to D3
S4B connected to D4
1
0
1
X(1)
Hi-Z (OFF)
(1) X denotes don't care.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Typical Application
Common applications that require the features of the TMUX1575 include multiplexing various protocols from a
possessor or MCU such as SPI, JTAG, eMMC, or standard GPIO signals. The TMUX1575 provides superior
isolation performance when the device is powered. The added benefit of powered-off protection allows a system
to minimize complexity by eliminating the need for power sequencing in hot-swap and live insertion applications.
The example shown in 图 9-1 illustrates the use of the TMUX1575 to multiplex an SPI bus to multiple flash
memory devices.
1.2 V
3.3 V
3.3 V
0.1µF
FLASH Device #1
VI/O
VDD
VDD
Processor
S1A
S2A
S3A
S4A
MISO
MOSI
SCLK
SS
D1
D2
D3
D4
RAM
CPU
SPI PORT
FLASH Device #2
S1B
S2B
S3B
S4B
MISO
MOSI
SCLK
SS
Peripherals
1.2V Logic
I/O
SEL
EN
GND
GND
图 9-1. Multiplexing Flash Memory
9.1.1 Design Requirements
For this design example, use the parameters listed in 表 9-1.
表 9-1. Design Parameters
PARAMETERS
VALUES
3.3 V
Supply (VDD
)
Input / Output signal range
Control logic thresholds
0 V to 3.3 V
1.2 V compatible
9.1.2 Detailed Design Procedure
The TMUX1575 can be operated without any external components except for the supply decoupling capacitors.
The TMUX1575 has internal weak pull-down resistors (6 MΩ) to GND so that it powers-on with the switches in a
known state. All inputs signals passing through the switch must fall within the recommend operating conditions of
the TMUX1575 including signal range and continuous current. For this design example, with a supply of 3.3 V,
the signals can range from 0 V to 3.3 V when the device is powered. This example can also utilize the Powered-
off protection feature where the inputs can range from 0 V to 3.6 V when VDD = 0 V. Due to the voltage range
and high speed capability, the TMUX1575 example is suitable for use in SPI, JTAG, eMMC, and I2S
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applications. Refer to Enabling SPI-based flash memory expansion by using multiplexers for more information on
using switches and multiplexers for SPI protocol expansion.
10 Power Supply Recommendations
The TMUX1575 operates across a wide supply range of 1.08 V to 3.6 V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to
ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-
impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers
the overall inductance and is beneficial for connections to ground planes.
11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. 图 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
2W
1W min.
W
图 11-1. Trace Example
Route the high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, through-hole
pins are not recommended at high frequencies.
Do not route high speed signal traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed signals traces because they cause signal reflections.
Route all high-speed signal traces over continuous GND planes, with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
When working with high frequencies, a printed circuit board with at least four layers is recommended; two signal
layers separated by a ground and power layer as shown in 图 11-2.
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Signal 1
GND Plane
Power Plane
Signal 2
图 11-2. Example Layout
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must
be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power
plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the
number of signal vias reduces EMI by reducing inductance at high frequencies. 图 11-3 illustrates an example of
a PCB layout with the TMUX1575. Some key considerations are:
Decouple the VDD pin with a 0.1-μF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
High-speed switches require proper layout and design procedures for optimum performance.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Example:
Top Layer Routing
SxA
To A port
To B port
Bottom Layer Routing
Via
SxB
Dx
To common port
To Control
Logic
S2A
S3A
S4A
D1
S1A
VDD
SEL
D2
S1B
EN
S2B
To input/output
port A
S3B
S4B
D4
To input/output
port B
GND
D3
Decoupling capacitor under
part on bottom layer for
lowest inductance
To common
input/output port
图 11-3. Example Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
Texas Instruments, Enabling SPI-based flash memory expansion by using multiplexers.
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.
Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.
Texas Instruments, High-Speed Interface Layout Guidelines.
Texas Instruments, High-Speed Layout Guidelines.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
YCJ0016-C01
DSBGA - 0.35 mm max height
SCALE 12.000
DIE SIZE BALL GRID ARRAY
1.359
1.319
A
B
BALL A1
CORNER
1.359
1.319
0.35 MAX
C
SEATING PLANE
0.05 C
0.125
0.075
1.05 TYP
SYMM
D
C
1.05
SYMM
TYP
B
A
0.35
TYP
1
4
2
3
0.195
0.155
16X
0.35 TYP
0.015
C A B
4225953/A 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YCJ0016-C01
DSBGA - 0.35 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
1
16X ( 0.18)
4
3
2
A
(0.35) TYP
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
0.0375 MIN
0.0375 MAX
METAL UNDER
SOLDER MASK
( 0.18)
METAL
EXPOSED
METAL
(
0.18)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4225953/A 05/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YCJ0016-C01
DSBGA - 0.35 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
(R0.05) TYP
3
16X ( 0.21)
2
1
4
A
(0.35) TYP
B
C
SYMM
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 50X
4225953/A 05/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX1575YCJR
ACTIVE
DSBGA
YCJ
16
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1575
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE OUTLINE
YCJ0016
DSBGA - 0.35 mm max height
SCALE 12.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
0.35 MAX
C
SEATING PLANE
0.05 C
0.125
0.075
1.05 TYP
SYMM
D
C
1.05
TYP
SYMM
D: Max = 1.329 mm, Min =1.269 mm
E: Max = 1.329 mm, Min =1.269 mm
B
A
0.35
TYP
1
4
2
3
0.195
0.155
16X
0.015
0.35 TYP
C A B
4226577/A 02/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YCJ0016
DSBGA - 0.35 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
1
16X ( 0.18)
4
3
2
A
(0.35) TYP
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
0.0375 MIN
0.0375 MAX
METAL UNDER
SOLDER MASK
(
0.18)
METAL
EXPOSED
METAL
(
0.18)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4226577/A 02/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YCJ0016
DSBGA - 0.35 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
(R0.05) TYP
16X ( 0.21)
2
1
3
4
A
(0.35) TYP
B
C
SYMM
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 50X
4226577/A 02/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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