TMUX4157NDCKR [TI]
输入切换时无过冲的 2Ω 低 RON、-12V、2:1 (SPDT) 通用开关 | DCK | 6 | -55 to 125;
| 型号： | TMUX4157NDCKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 输入切换时无过冲的 2Ω 低 RON、-12V、2:1 (SPDT) 通用开关 | DCK | 6 | -55 to 125 开关 通用开关 光电二极管 |
| 文件： | 总25页 (文件大小：1851K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUX4157N
ZHCSMU3A –MARCH 2020 –REVISED MARCH 2021
TMUX4157N
具有1.8V 逻辑控制器的-12V 低RON、2:1 (SPDT) 负电压开关
1 特性
3 说明
• 负电压支持：-4V 至-12V
• 轨到轨运行
• 双向信号路径
• 兼容1.8V 逻辑电平
• 失效防护逻辑
TMUX4157N 是一款仅支持负电源轨的通用2:1 单极双
投 (SPDT) 开关。电源电压范围为 -4V 至 -12V，而且
该器件可在源极 (Sx) 和漏极 (D) 引脚上支持从 GND
到 VSS 范围的双向模拟和数字信号。选择引脚 (SEL)
的状态决定连接到漏极引脚的源极引脚。
• 持续高电流支持：150mA
• 低导通电阻：1.8Ω
• -55°C 至+125°C 工作温度
• 先断后合开关
虽然 在电源引脚和信号路径上支持负电压，但逻辑输
入引脚却通过正电压进行控制，以实现与典型控制逻辑
电路（比如 GPIO 信号）的连接。逻辑输入引脚具有
兼容 1.8V 逻辑电平的阈值，并可在高达 5.5V 的电压
下运行以增加系统灵活性。失效防护逻辑电路允许先在
控制引脚上施加电压，然后在电源引脚上施加电压，从
而保护器件免受潜在的损害。
• ESD 保护HBM：2000V
2 应用
• 模拟和数字开关
• GaN 功率放大器栅极开关
• 远程射频单元(RRU)
• 有源天线系统mMIMO (AAS)
• 基带单元(BBU)
快 速 转 换 时 间 和 通 过 开 关 的 持 续 高 电 流 使
TMUX4157N 非常适合需要在两个不同的电压输入之
间快速切换的系统应用。
器件信息
• 无线通信测试
器件型号(1)
TMUX4157N
封装尺寸（标称值）
封装
SC70 (6)
2.00mm × 1.25mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
。
。
TMUX4157N
RF Input
RF Output
S1
S2
0 V
TMUX4157N
D
-12 V
DAC
SEL
1.8 V
SEL
应用示例
TMUX4157N 方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS428
TMUX4157N
ZHCSMU3A –MARCH 2020 –REVISED MARCH 2021
www.ti.com.cn
Table of Contents
7.10 Crosstalk.................................................................14
7.11 Bandwidth............................................................... 15
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................16
8.5 Truth Tables.............................................................. 16
9 Application and Implementation..................................17
9.1 Application Information............................................. 17
9.2 Typical Application.................................................... 17
10 Power Supply Recommendations..............................18
11 Layout...........................................................................19
11.1 Layout Guidelines................................................... 19
11.2 Layout Example...................................................... 19
12 Device and Documentation Support..........................20
12.1 Documentation Support.......................................... 20
12.2 Receiving Notification of Documentation Updates..20
12.3 支持资源..................................................................20
12.4 Trademarks.............................................................20
12.5 静电放电警告.......................................................... 20
12.6 术语表..................................................................... 20
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Dynamic Characteristics ............................................ 6
6.7 Timing Characteristics ................................................7
6.8 Typical Characteristics................................................8
7 Parameter Measurement Information..........................10
7.1 On-Resistance.......................................................... 10
7.2 Off-Leakage Current................................................. 10
7.3 On-Leakage Current................................................. 11
7.4 Transition Time..........................................................11
7.5 Break-Before-Make...................................................12
7.6 Prop Delay................................................................ 12
7.7 Device Turn on Time.................................................13
7.8 Charge Injection........................................................13
7.9 Off Isolation...............................................................14
Information.................................................................... 20
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (March 2020) to Revision A (March 2021)
Page
• 将文档状态从预告信息更改为量产数据.............................................................................................................1
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5 Pin Configuration and Functions
S2
VSS
S1
1
2
3
6
5
4
SEL
GND
D
Not to scale
图5-1. DCK Package 6-Pin SC70 Top View
表5-1. Pin Functions
DESCRIPTION(2)
PIN
TYPE(1)
NAME
NO.
S2
1
I/O
P
Source pin 2. Can be an input or output.
Negative power supply. This pin is the most negative power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
2
S1
3
4
5
6
I/O
I/O
P
Source pin 1. Can be an input or output.
D
Drain pin. Can be an input or output.
GND
SEL
Ground (0 V) reference
I
Select pin: controls state of the switch according to 表8-1. (Logic Low = S1 to D, Logic High = S2 to D)
(1) I = input, O = output, I/O = input and output, P = power.
(2) Refer to 节8.4 for what to do with unused pins.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
–13
MAX
0.5
6
UNIT
VSS
Supply voltage
VSEL
Logic control input pin voltage (SEL)
V
–0.5
VS or VD
ISEL
Source or drain voltage (Sx, D)
0.5
VSS–0.5
–50
Logic control input pin diode current (SEL)
Switch source or drain pin diode current (Sx, D)
Continuous current through switch (Sx, D pins) –40°C to +125°C
Continuous current through switch (Sx, D pins) –40°C to +85°C
IIOK
50
100
150
–50
mA
IS or ID (CONT)
IS or ID (CONT)
–100
–150
Source and drain peak current: (1 ms period max, 10% duty cycle
maximum) (Sx, D)
IS or ID (PEAK)
150
mA
–150
PD
Tstg
TJ
Power dissipation
80
150
150
mW
Storage temperature
Junction temperature
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
–4
UNIT
V
VSS
Supply voltage
–12
VSS
VS or VD
VSEL
Signal path input/output voltage (source or drain pin) (Sx, D)
Logic control input pin voltage (SEL)
GND
5.5
V
0
V
IS or ID (CONT)
IS or ID (CONT)
TA
100
150
125
mA
mA
°C
Continuous current through switch (Sx, D pins) –40°C to +125°C
Continuous current through switch (Sx, D pins) –40°C to +85°C
Ambient temperature
–100
–150
–55
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6.4 Thermal Information
TMUX4157N
THERMAL METRIC(1)
SC70 (DCK)
6 PINS
181.7
132.6
73.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
56.3
ΨJT
72.9
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Typical values measured at nominal VSS and TA = 25°C.
–55°C to 125°C
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
VSS
UNIT
MIN
TYP
MAX
1.8
1.8
1.9
2
6.5
6.5
6.5
6.5
8
–12 V
–10 V
–8 V
–6 V
–4 V
–12 V
–10 V
–8 V
–6 V
–4 V
–12 V
–10 V
–8 V
–6 V
–4 V
VS = VSS to GND
ISD = 50 mA
RON
On-state switch resistance
Ω
2.6
1.8
1.8
1.8
1.6
1.4
0.2
0.2
0.25
0.25
0.3
On-state switch resistance
flatness
VS = VSS to GND
ISD = 50 mA
RON FLAT
Ω
On-state switch resistance
matching between inputs
VS = VSS to GND
ISD = 50 mA
ΔRON
Ω
Switch Off
IS(OFF)
Source off-state leakage current VD = VSS / GND
VS = GND / VSS
±1
±15
±15
µA
–10 V
ID(ON)
IS(ON)
Switch On
VS = VD = GND to VSS
Channel on-state leakage current
±1
10
20
µA
pF
pF
–10 V
–10 V
–10 V
VS = VSS / 2
f = 1 MHz
CSOFF
Source off capacitance
On capacitance
CSON
CDON
VS = VSS / 2
f = 1 MHz
POWER SUPPLY
Logic inputs = GND or 3.3 V
VS = VSS or GND
–12 V to –4
V
ISS
VSS supply current
20
70
µA
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6.5 Electrical Characteristics (continued)
Typical values measured at nominal VSS and TA = 25°C.
–55°C to 125°C
PARAMETER
LOGIC INPUT (SEL)
TEST CONDITIONS
VSS
UNIT
MIN
TYP
MAX
1.35
1.35
1.35
1.35
1.35
0
5
5
–12 V
–10 V
–8 V
–6 V
–4 V
–12 V
–10 V
–8 V
–6 V
–4 V
VIH
Input logic high
5
V
V
5
5
0.8
0.8
0.8
0.8
0.8
0
VIL
Input logic low
0
0
0
IIH
IIL
–12 V to –4
V
Logic input leakage current
Logic input capacitance
±1
3
±30
µA
pF
–12 V to –4
V
CIN
6.6 Dynamic Characteristics
Typical values measured at nominal VSS and TA = 25°C.
–55°C to 125°C
PARAMETER
TEST CONDITIONS
VSS
UNIT
MIN
TYP
–80
–70
–55
–40
–25
MAX
–12 V
–10 V
–8 V
–6 V
–4 V
VS = VSS / 2
RS = 0 Ω, CL = 100 pF
QINJ
Charge Injection
pC
VBIAS = VSS / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
f = 1 MHz
–12 V to –4
V
OISO
OISO
XTALK
Off Isolation
Off Isolation
Crosstalk
dB
dB
dB
–65
–40
–65
VBIAS = VSS / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
f = 10 MHz
–12 V to –4
V
VBIAS = VSS / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
f = 1 MHz
–12 V to –4
V
VBIAS = VSS / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
f = 10 MHz
–12 V to –4
V
XTALK
Crosstalk
dB
–42
VBIAS = VSS / 2
VS = 200 mVpp
RL = 50 Ω, CL = 5 pF
–12 V to –4
V
BW
Bandwidth
340
MHz
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6.7 Timing Characteristics
Typical values measured at nominal VSS and TA = 25°C.
–55°C to 125°C
PARAMETER
TEST CONDITIONS
VSS
–12 V
UNIT
MIN
TYP
0.4
0.4
0.4
0.4
0.5
MAX
2
2
–10 V
–8 V
–6 V
–4 V
–12 V
–10 V
–8 V
–6 V
–4 V
–12 V
–10 V
–8 V
–6 V
–4 V
–12 V
–10 V
–8 V
–6 V
–4 V
Propagation delay
Sx to D, D to Sx
tPD
CL = 100 pF
2
ns
ns
ns
2
2.5
210
200
205
215
280
210
210
215
225
260
Transition-time between inputs
tTRAN HIGH turning on (high)
SEL to D, SEL to Sx
RL = 250 Ω, CL = 100 pF
VS = VSS
Transition-time between inputs
turning off (low)
SEL to D, SEL to Sx
RL = 250 Ω, CL = 100 pF
VS = VSS
tTRAN LOW
5
5
RL = 50 Ω, CL = 100 pF
VS = –2.5 V
tBBM
Break before make time
10
10
40
ns
µs
Device turn on time (VSS to
output)
RL = 250 Ω, CL = 100 pF
VS = VSS
–12 V to –4
V
TON (VSS)
20
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6.8 Typical Characteristics
At TA = 25°C, VSS = -10 V (unless otherwise noted).
4.5
6
5
4
3
2
1
0
VSS = -12 V
TA = 125èC
TA = 85èC
TA = 25èC
TA = -55èC
VSS = -10 V
VSS = -8 V
VSS = -4 V
4
3.5
3
2.5
2
1.5
-12
-10
-8
Source or Drain Voltage (V)
-6
-4
-2
0
-12
-10
-8
Source or Drain Voltage (V)
-6
-4
-2
0
D001
D002
TA = 25°C
VSS = -12 V
图6-1. On-Resistance vs Signal Voltage
图6-2. On-Resistance vs Signal Voltage
6
5
4
3
2
1
0
-6
-8
TA = 125èC
TA = 85èC
TA = 25èC
TA = -55èC
-10
-12
-14
-16
-18
-20
-22
-24
-6
-5
-4
Source or Drain Voltage (V)
-3
-2
-1
0
-12
-11
-10
-9
Supply Voltage (V)
-8
-7
-6
-5
-4
D003
D004
VSS = -6 V
TA = 25°C
图6-3. On-Resistance vs Signal Voltage
图6-4. Supply Current vs Supply Voltage
180
170
160
150
140
130
120
110
100
200
190
180
170
160
150
140
130
120
110
100
TA = 125èC
TA = 125èC
TA = 85èC
TA = 25èC
TA = -55èC
TA = 85èC
TA = 25èC
TA = -55èC
-10
-8
-6
Source or Drain Voltage (V)
-4
-2
-10
-8
-6
Source or Drain Voltage (V)
-4
-2
D005
D006
VSS = -10 V
VSS = -10 V
图6-5. Transition Time vs Signal Voltage
图6-6. Transition Time vs Signal Voltage
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6.8 Typical Characteristics (continued)
At TA = 25°C, VSS = -10 V (unless otherwise noted).
152
0
-20
Output Rising Edge
Output Falling Edge
VSS: -12
VSS: -8
VSS: -6
150
148
146
144
142
140
138
136
134
132
130
128
126
124
-40
-60
-80
-100
-12
-11
-10
-9
Supply Voltage (V)
-8
-7
-6
-5
-4
-12
-10
-8
-6
Drain Voltage (V)
-4
-2
0
D007
D008
TA = 25°C
TA = 25°C
图6-7. Transition Time vs Supply Voltage
图6-8. Charge Injection vs Drain Voltage
0
-20
0
-2
VSS = -12
VSS = -6
VSS = -8
-4
-40
VSS = -12
VSS = -6
VSS = -8
-6
-60
-8
-80
-10
-100
-12
100k
1M
10M
Frequency (Hz)
100M
1G
100k
1M
10M
Frequency (Hz)
100M
1G
D009
D010
TA = 25°C
TA = 25°C
图6-10. Frequency Response
图6-9. Crosstalk and Off-Isolation vs Frequency
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-
resistance. 图 7-1 shows the measurement setup used to measure RON. Voltage (V) and current (ISD) are
measured using this setup, and RON is computed with RON = V / ISD
:
V
ISD
Sx
D
VS
图7-1. On-Resistance Measurement Setup
7.2 Off-Leakage Current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
图7-2 shows the setup used to measure off-leakage current.
VSS
Is (OFF)
S1
A
D
S2
VS
VD
GND
图7-2. Off-Leakage Measurement Setup
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VSS
VSS
IS (ON)
S1
S2
S1
S2
ID (ON)
N.C.
A
D
D
A
N.C.
Vs
VS
VS
VD
GND
GND
图7-3. On-Leakage Measurement Setup
7.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 50% after the logic control
signal has risen or fallen past the 50% threshold. System level timing can then account for the time constant
added from the load resistance and load capacitance. 图 7-4 shows the setup used to measure transition time,
denoted by the symbol tTRANSITION
.
VSS
0.1…F
1.8 V
50%
50%
VSEL
tr < 5ns
tf < 5ns
S2
S1
VS
OUTPUT
D
0 V
tTRAN_HIGH
tTRAN_LOW
RL
CL
0 V
Output
SEL
50%
50%
VSEL
GND
图7-4. Transition-Time Measurement Setup
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7.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. 图7-5 shows the
setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VSS
0.1…F
3.3 V
S1
S2
VSEL
tr < 5ns
tf < 5ns
VS
OUTPUT
D
0 V
RL
CL
90%
Output
SEL
tBBM
1
tBBM 2
0 V
VSEL
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
GND
图7-5. Break-Before-Make Delay Measurement Setup
7.6 Prop Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. 图 7-6 shows the setup used to measure propagation delay, denoted
by the symbol tPD
.
VSS
0.1…F
0 V
Input
(VS)
50%
50%
S1
S2
VS
OUTPUT
D
VSS
tPD_1
tPD_2
CL
0 V
SEL
50%
50%
Output
tProp Delay = max ( tPD_1, tPD_2
)
GND
图7-6. Prop Delay Measurement Setup
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7.7 Device Turn on Time
The TON (VSS) time is defined as the time taken by the output of the device to rise to 90% after the supply has
risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in
the system. 图7-7 shows the setup used to measure turn on time, denoted by the symbol TON (VSS)
.
VSS
VSS
0 V
Supply
Ramp
tr = 1 µs
œ 4 V
VS
S2
S1
OUTPUT
D
VSS
tON
RL
CL
0 V
Output
SEL
3 V
90%
GND
图7-7. Device Turn on Time Measurement Setup
7.8 Charge Injection
The TMUX4157N has a transmission-gate topology. Any mismatch in capacitance between the NMOS and
PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate
signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QC. 图 7-8 shows the setup used to measure charge injection from Drain (D) to Source
(Sx).
VSS
0.1…F
3.3 V
VSEL
0 V
S2
N.C.
D
VD
OUTPUT
S1
VOUT
CL
Output
VOUT
SEL
VS
QC = CL
×
VOUT
VSEL
GND
图7-8. Charge-Injection Measurement Setup
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7.9 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. 图 7-9 shows the setup used to measure, and the equation used to calculate
off isolation.
0.1µF
NETWORK
VSS
ANALYZER
VS
50Q
S
VSIG
D
VOUT
RL
SX
50Q
GND
RL
50Q
图7-9. Off Isolation Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
(1)
7.10 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. 图 7-10 shows the setup used to measure, and the equation used to
calculate crosstalk.
0.1µF
NETWORK
VSS
ANALYZER
S1
VOUT
RL
D
50Q
VS
RL
S2
50Q
50Q
VSIG
GND
图7-10. Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(2)
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7.11 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. 图 7-11
shows the setup used to measure bandwidth.
0.1µF
NETWORK
VSS
ANALYZER
VS = VSS / 2
S
50Q
VSIG
D
VS = VSS / 2
VOUT
RL
50Q
SX
GND
RL
50Q
图7-11. Bandwidth Measurement Setup
8 Detailed Description
8.1 Overview
The TMUX4157N is an 2:1 (SPDT), 1-channel switch where the input is controlled with a single select (SEL)
control pin.
8.2 Functional Block Diagram
TMUX4157N
S1
D
S2
SEL
图8-1. TMUX4157N Functional Block Diagram
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX4157N conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). The
device has very similar characteristics in both directions and supports both analog and digital signals.
8.3.2 Rail-to-Rail Operation
The valid signal path input or output voltage for TMUX4157N ranges from GND to VSS
.
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8.3.3 1.8 V Logic Compatible Inputs
The TMUX4157N has 1.8 V logic compatible control for the logic control input (SEL). The logic input threshold
scales with supply but still provides 1.8 V logic control when operating at 5.5 V supply voltage. 1.8 V logic level
inputs allow the TMUX4157N to interface with processors that have lower logic I/O rails and eliminates the need
for an external translator, which saves both space and BOM cost. Refer to Simplifying Design with 1.8 V logic
Muxes and Switches for more information on 1.8 V logic implementations.
8.3.4 Fail-Safe Logic
The TMUX4157N supports Fail-Safe Logic on the control input pin (SEL) allowing for operation up to 5.5 V,
regardless of the state of the supply pin. This feature allows voltages on the control pin to be applied before the
supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by
removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pin of the TMUX4157N to be ramped to 5.5 V while VSS = 0 V. Additionally, the feature
enables operation of the TMUX4157N with VSS = 1.2 V while allowing the select pin to interface with a logic level
of another device up to 5.5 V.
8.4 Device Functional Modes
The select (SEL) pin of the TMUX4157N controls which switch is connected to the drain of the device. When a
given input is not selected, that source pin is in high impedance mode (HI-Z). The control pins can be as high as
5.5 V.
The TMUX4157N can be operated without any external components except for the supply decoupling
capacitors. Implications of Slow or Floating CMOS Inputs highlights how the unused logic control pins should be
tied to GND or logic high in order to ensure the device does not consume additional current. Unused signal path
inputs (Sx or D) should be connected to GND.
8.5 Truth Tables
表8-1. TMUX4157N Truth Table
CONTROL
Selected Source (Sx) Connected To Drain (D) Pin
LOGIC (SEL)
0
1
S1
S2
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TMUX4157N system flexibilty in GaN power amlifier biasing by supporting neative voltages across a wide
operating supply (-4 V to -12 V). This device includes a 1.8 V logic compatible control input pin that enables
operation in systems with 1.8 V I/O rails. These features allow the switch to reduce system complexity, board
size, and overall system cost.
9.2 Typical Application
9.2.1 Negative Voltage Input Control for Power Amplifier
One application of the TMUX4157N is for input control of a power amplifier. Utilizing a switch allows a system to
control when the DAC is connected to the power amplifier, and can stop biasing the power amplifier by switching
the gate voltage. The ability to dynamically control the power amplifier is beneficial in multiple applications within
communication equipment. 图9-1 shows the TMUX4157N configured for control of the power amplifier.
RF Input
RF Output
0 V
TMUX4157N
-12 V
DAC
1.8 V
SEL
图9-1. Input Control of Power Amplifier
9.2.1.1 Design Requirements
表9-1 lists the parameters that are used in this design example.
表9-1. Design Parameters
PARAMETERS
VALUES
-12 V
Supply (VSS
)
Switch I/O signal range
0 V to VSS (Rail-to-Rail)
1.8 V compatible (up to 5.5 V)
Control logic thresholds (SEL)
9.2.1.2 Detailed Design Procedure
The application shown in 图 9-1 demonstrates how to toggle between the DAC output and GND for control of a
GaN power amplifier using a single control input. The DAC output is utilized to bias the gate of the power
amplifier and can be disconnected from the circuit using the select pin of the switch. The TMUX4157N can
support 1.8-V logic signals on the control input, allowing the device to interface with low logic controls of an
FPGA or MCU. The TMUX4157N can be operated without any external components except for the supply
decoupling capacitors. The select pin is recommended to have a pull-down or pull-up resistor to ensure the input
is in a known state if the control signal becomes disconnected. All inputs to the switch must fall within the
recommend operating conditions of the TMUX4157N including signal range and continuous current.
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9.2.1.3 Application Curve
A key parameter for this application is the transition time of the device. Faster transition time allows the system
to toggle between input sources at a faster rate and allows the output to settle to the final value. No Overshoot
When Switching Between Inputs shows how the transition times varies with supply voltage.
152
Output Rising Edge
Output Falling Edge
150
148
146
144
142
140
138
136
134
132
130
128
126
124
-12
-11
-10
-9
-8
-7
Supply Voltage (V)
-6
-5
-4
D007
TA = 25°C
图9-2. No Overshoot When Switching Between Inputs
10 Power Supply Recommendations
The TMUX4157N operates across a wide supply range of -4 V to -12 V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VSS supply
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VSS to
ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-
impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers
the overall inductance and is beneficial for connections to ground planes.
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11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection primarily occurs because the
width of the trace changes. At the apex of the turn, the trace width increases to 1.414 times its width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. 图 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
2W
1W min.
W
图11-1. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference
from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
图11-2 illustrates an example of a PCB layout with the TMUX4157N. Some key considerations are:
• Decouple the VSS pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VSS supply.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Via to
GND plane
TMUX4157N
Wide (low inductance)
trace for power
C
图11-2. TMUX4157N Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
• Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches application
brief.
• Texas Instruments, Improve Stability Issues with Low CON Multiplexers appication brief.
• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief.
• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application report.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX4157NDCKR
ACTIVE
SC70
DCK
6
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
1II
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX4157NDCKR
SC70
DCK
6
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SC70 DCK
SPQ
Length (mm) Width (mm) Height (mm)
180.0 180.0 18.0
TMUX4157NDCKR
6
3000
Pack Materials-Page 2
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