TMUX6136PWR [TI]
0.5pA 导通状态电容、±16.5V、2:1 (SPDT)、2 通道精密模拟开关 | PW | 16 | -40 to 125;
| 型号： | TMUX6136PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 0.5pA 导通状态电容、±16.5V、2:1 (SPDT)、2 通道精密模拟开关 | PW | 16 | -40 to 125 开关 PC 光电二极管 |
| 文件： | 总31页 (文件大小：1484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUX6136
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
TMUX6136 ±16.5V、低电容、低漏电流、精密
双路SPDT 开关
1 特性
3 说明
• 宽电源电压范围：±5V 至±16.5V（双电源）或
10V 至16.5V（单电源）
• 所有引脚的闩锁性能都达到100mA，符合JESD78
II 类A 级要求
• 低导通电容：5.5pF
• 低输入漏电流：0.5pA
TMUX6136 是一款具有两个独立可选 SPDT 开关的互
补金属氧化物半导体 (CMOS) 模拟开关。该器件在双
电源（±5V 至 ±16.5V）、单电源（10V 至 16.5V）或
非对称电源供电时均能正常运行。数字选择引脚
(SELx) 具有兼容晶体管到晶体管逻辑 (TTL) 的阈值，
这些阈值可确保TTL/CMOS 逻辑兼容性。
• 低电荷注入：-0.4 pC
• 轨到轨运行
• 低导通电阻：120Ω
• 快速转换时间：66ns
• 先断后合开关操作
• SELx 引脚可连接至带集成下拉电阻器的VDD
• 逻辑电平：2V 至VDD
TMUX6136 会根据 SELx 引脚的状态将两个输入 (Sx)
之一切换为共模输出 (D)。每个开关在“ON”位置时
在两个方向上表现得都很好，而且支持最高到电源的输
入信号范围。在 OFF 状态下，则会阻止最高到电源的
信号电平。所有开关都具有先断后合 (BBM) 开关操
作。
TMUX6136 是德州仪器 (TI) 精密开关和多路复用器系
列中的一款产品。该器件具有非常低的漏电流和电荷注
入，因此可用于高精度测量应用。当开关处于 OFF 位
置时，该器件还可通过阻断到达电源的信号电平来提供
出色的隔离能力。17μA 的低电源电流使其可用于多
种便携式应用。
• 低电源电流：17µA
• 人体放电模型(HBM) ESD 保护：所有引脚上均为
±2kV
• 业界通用TSSOP 封装
2 应用
• 工厂自动化和工业过程控制
• 可编程逻辑控制器(PLC)
• 模拟输入模块
• ATE 测试设备
• 数字万用表
• 电池监控系统
封装信息(1)
封装尺寸（标称值）
器件型号
TMUX6136
封装
PW (TSSOP, 16)
5.00mm × 4.40mm
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
VSS
VDD
S1A
S1B
D1
SEL1
S2A
S2B
D2
SEL2
TMUX6136
Copyright © 2018, Texas Instruments Incorporated
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS397
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
Table of Contents
7.4 Device Functional Modes..........................................19
8 Application and Implementation..................................20
8.1 Application Information............................................. 20
8.2 Typical Application.................................................... 20
9 Power Supply Recommendations................................22
10 Layout...........................................................................23
10.1 Layout Guidelines................................................... 23
10.2 Layout Example...................................................... 23
11 Device and Documentation Support..........................24
11.1 Documentation Support.......................................... 24
11.2 接收文档更新通知................................................... 24
11.3 支持资源..................................................................24
11.4 Trademarks............................................................. 24
11.5 Electrostatic Discharge Caution..............................24
11.6 术语表..................................................................... 24
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Thermal Information....................................................4
6.4 Recommended Operating Conditions.........................5
6.5 Electrical Characteristics (Dual Supplies: ±15 V)........5
6.6 Switching Characteristics (Dual Supplies: ±15 V).......6
6.7 Electrical Characteristics (Single Supply: 12 V)..........7
6.8 Switching Characteristics (Single Supply: 12 V).........7
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................18
7.3 Feature Description...................................................18
Information.................................................................... 24
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2018) to Revision A (October 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Updated the Transition-Time Measurement Setup figure ................................................................................ 13
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
5 Pin Configuration and Functions
SEL1
S1A
D1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
N.C.
N.C.
N.C.
S1B
V
ꢀ
DD
V
ꢀ
S2B
D2
SS
GND
N.C.
N.C.
S2A
SEL2
Not to scale
图5-1. PW Package, 16-Pin TSSOP (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
SEL1
S1A
NO.
1
I
Select line 0
2
I/O
I/O
I/O
Source pin 1A. Can be an input or output.
Drain pin D1. Can be an input or output.
Source pin 1B. Can be an input or output.
D1
3
S1B
4
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
5
P
GND
N.C.
6
Ground (0 V) reference
No internal connection
7, 8, 14,
15, 16
No
Connect
SEL2
S2A
D2
9
I
Select line 1
10
11
12
I/O
I/O
I/O
Source pin 2A. Can be an input or output.
Drain pin D2. Can be an input or output.
Source pin 2B. Can be an input or output.
S2B
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
13
P
(1) I = input, O = output, P = power
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
36
UNIT
V
VDD to VSS
VDD to GND
VSS to GND
VDIG
18
V
Supply voltage
–0.3
–18
0.3
V
Digital input pin (SEL1, SEL2) voltage
Digital input pin (SEL1, SEL2) current
Analog input pin (Sx) voltage
Analog input pin (Sx) current
Analog output pin (D) voltage
Analog output pin (D) current
Ambient temperature
VDD+0.3
30
V
GND –0.3
–30
IDIG
mA
V
VANA_IN
IANA_IN
VANA_OUT
IANA_OUT
TA
VDD+0.3
30
VSS–0.3
–30
mA
V
VDD+0.3
30
VSS–0.3
–30
mA
°C
°C
°C
140
–55
TJ
Junction temperature
150
Tstg
Storage temperature
150
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
TMUX6136
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
111.0
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
41.7
57.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.1
ΨJT
56.6
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD to VSS
Power supply voltage differential
10
33
V
(1)
VDD to
Positive power supply voltage (singlle supply, VSS = 0 V)
GND
10
5
16.5
16.5
–5
V
V
V
VDD to
Positive power supply voltage (dual supply)
GND
VSS to
Negative power supply voltage (dual supply)
GND
–16.5
(1)
VS
Source pins voltage
VSS
VSS
0
VDD
VDD
VDD
25
V
V
VD
Drain pin voltage
VDIG
ICH
TA
Digital input pin (SEL1, SEL2) voltage
Channel current (TA = 25°C )
Ambient temperature
V
mA
°C
–25
–40
125
(1) VDD and VSS can be any value as long as 10 V ≤(VDD –VSS) ≤33 V.
6.5 Electrical Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG SWITCH
VA
Analog signal range
On-resistance
VSS
VDD
135
160
210
245
6
V
TA = –40°C to +125°C
VS = 0 V, IS = 1 mA
120
140
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
RON
VS = ±10 V, IS = 1 mA
TA = –40°C to +85°C
TA = –40°C to +125°C
2.5
23
On-resistance mismatch
between channels
9
VS = ±10 V, IS = 1 mA
TA = –40°C to +85°C
TA = –40°C to +125°C
ΔRON
11
33
VS = –10 V, 0 V, +10 V, IS
= 1 mA
35
RON_FLAT
On-resistance flatness
TA = –40°C to +85°C
TA = –40°C to +125°C
37
Ω
RON_DRIFT On-resistance drift
VS = 0 V
0.42
%/°C
Switch state is off, VS =
+10 V/ –10 V, VD = –10
V/ + 10 V
0.005
0.05
0.1
nA
nA
nA
–0.05
–0.17
–1
Switch state is off, VS =
+10 V/ –10 V, VD = –10 TA = –40°C to +85°C
V/ + 10 V
IS(OFF)
Source off leakage current(1)
Switch state is off, VS =
+10 V/ –10 V, VD = –10 TA = –40°C to +125°C
V/ + 10 V
0.25
0.008
0.06
0.15
0.4
nA
nA
nA
–0.06
–0.25
–1.6
Switch state is on, VS
+10 V/ –10 V, VD = –10 TA = –40°C to +85°C
V/ +10 V
=
ID(ON)
Drain on leakage current
TA = –40°C to +125°C
DIGITAL INPUT (SELx pins)
VIH
VIL
Logic voltage high
Logic voltage low
2
V
V
0.8
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
6.5 Electrical Characteristics (Dual Supplies: ±15 V) (continued)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TEST CONDITIONS
MIN
TYP
MAX UNIT
Pull-down resistance on SELx
pins
RPD(SELx)
6
MΩ
POWER SUPPLY
17
8
21
22
23
10
11
12
µA
µA
µA
µA
µA
µA
IDD
VDD supply current
VA = 0 V or 3.3 V, VS = 0 V TA = –40°C to +85°C
TA = –40°C to +125°C
ISS
VSS supply current
VA = 0 V or 3.3 V, VS = 0 V TA = –40°C to +85°C
TA = –40°C to +125°C
(1) When VS is positive, VD is negative, and vice versa.
6.6 Switching Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
66
78
ns
ns
VS = 10 V, RL = 300 Ω, CL = 35 pF
VS = 10 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+85°C
107
tTRAN
Transition time
VS = 10 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+125°C
117
ns
ns
VS = 10 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+125°C
tBBM
Break-before-make time delay
20
40
QJ
Charge injection
Off-isolation
pC
dB
VS = 0 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 1 MHz
–0.4
–85
OISO
RL = 50 Ω, CL = 5 pF, f = 1 MHz (Inter-channel: S1x
and S2x)
dB
dB
–105
–92
XTALK
Channel-to-channel crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz (Intra-channel: SxA
and SxB)
IL
Insertion loss
dB
dB
dB
MHz
%
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 10 kΩ, CL = 5 pF, VPP= 0.62 V on VDD, f= 1 MHz
RL = 10 kΩ, CL = 5 pF, VPP= 0.62 V on VSS, f= 1 MHz
RL = 50 Ω, CL = 5 pF
–7
–59
–59
670
0.08
1.5
AC Power Supply Rejection
Ratio
ACPSRR
BW
-3dB Bandwidth
THD
CIN
Total harmonic distortion + noise
Digital input capacitance
Source off-capacitance
RL = 10 kΩ, CL = 5 pF, f= 20 Hz to 20 kHz
VIN = 0 V or VDD
pF
CS(OFF)
VS = 0 V, f = 1 MHz
2.4
3.3
7.5
pF
CS(ON),
CD(ON)
Source and drain on-
capacitance
VS = 0 V, f = 1 MHz
5.5
pF
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
6.7 Electrical Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG SWITCH
VA
Analog signal range
On-resistance
VSS
VDD
345
400
440
12
V
235
Ω
Ω
Ω
Ω
Ω
RON
VS = 10 V, IS = 1 mA
TA = –40°C to +85°C
TA = –40°C to +125°C
4
On-resistance mismatch
between channels
19
VS = 10 V, IS = 1 mA
VS = 0 V
TA = –40°C to +85°C
TA = –40°C to +125°C
ΔRON
23
Ω
%/°C
nA
RON_DRIFT On-resistance drift
0.47
0.005
0.03
0.07
0.2
–0.03
–0.1
Switch state is off, VS = 10
V/ 1 V, VD = 1 V/ 10 V
IS(OFF)
Source off leakage current(1)
nA
nA
nA
nA
nA
TA = –40°C to +85°C
TA = –40°C to +125°C
–0.8
0.01
0.04
0.09
0.3
–0.04
–0.16
–1.2
Switch state is on, VS
floating, VD = 1 V/ 10 V
=
ID(ON)
Drain on leakage current
TA = –40°C to +85°C
TA = –40°C to +125°C
DIGITAL INPUT (SELx pins)
VIH
VIL
Logic voltage high
Logic voltage low
2
V
V
0.8
Pull-down resistance on SELx
pins
RPD(SELx)
6
MΩ
POWER SUPPLY
13
16
17
18
µA
µA
µA
IDD
VDD supply current
VA = 0 V or 3.3 V, VS = 0 V TA = –40°C to +85°C
TA = –40°C to +125°C
(1) When VS is positive, VD is negative, and vice versa.
6.8 Switching Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
72
84
ns
ns
VS = 8 V, RL = 300 Ω, CL = 35 pF
VS = 8 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+85°C
117
tTRAN
Transition time
VS = 8 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+125°C
128
ns
ns
VS = 8 V, RL = 300 Ω, CL = 35 pF, TA = –40°C to
+125°C
tBBM
Break-before-make time delay
20
40
QJ
Charge injection
Off-isolation
pC
dB
VS = 6 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 1 MHz
–0.7
OISO
-85
RL = 50 Ω, CL = 5 pF, f = 1 MHz (Inter-channel: S1x
and S2x)
dB
–110
XTALK
Channel-to-channel crosstalk
Insertion loss
RL = 50 Ω, CL = 5 pF, f = 1 MHz (Intra-channel: SxA
and SxB)
dB
dB
–95
–13
IL
RL = 50 Ω, CL = 5 pF, f = 1 MHz
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
6.8 Switching Characteristics (Single Supply: 12 V) (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AC Power Supply Rejection
Ratio
ACPSRR
dB
RL= 10 kΩ, CL = 5 pF, VPP= 0.62 V, f= 1 MHz
–58
BW
-3dB Bandwidth
650
1.7
2.6
MHz
pF
RL = 50 Ω, CL = 5 pF
VIN = 0 V or VDD
CIN
Digital input capacitance
Source off-capacitance
CS(OFF)
VS = 6 V, f = 1 MHz
3.7
8.5
pF
pF
CS(ON)
CD(ON)
,
Source and drain on-
capacitance
VS = 6 V, f = 1 MHz
6.3
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
250
200
150
100
50
650
600
550
500
450
400
350
300
250
200
150
100
VDD= 13.5V
VSS = -13.5V
VDD= 12V
VSS = -12V
VDD= 12V
VSS = 0V
VDD= 10V
VSS = 0V
VDD= 16.5V
VSS = -16.5V
VDD= 15V
VSS = -15V
VDD= 14V
VSS = 0V
0
0
2
4
6
8
10
Source or Drain Voltage (V)
12
14
-20
-15
-10
-5
0
5
Source or Drain Voltage (V)
10
15
20
D002
D001
Single Supply Operation (TA = 25°C)
图6-2. On-Resistance vs Source or Drain Voltage
Dual Supply Operation (TA = 25°C)
图6-1. On-Resistance vs Source or Drain Voltage
250
700
TA = 125èC
TA = 125èC
TA = 85èC
600
500
400
300
200
100
0
200
150
100
50
TA = 85èC
TA = 25èC
TA = -40èC
TA = -40èC
TA = 25èC
0
-15
-10
-5
Source or Drain Voltage (V)
0
5
10
15
0
2
4
Source or Drain Voltage (V)
6
8
10
12
D003
D004
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = –15 V
图6-4. On-Resistance vs Source or Drain Voltage
图6-3. On-Resistance vs Source or Drain Voltage
400
400
ID(ON)+
IS(OFF)_10V
IS(OFF)+
ID(ON)_10V
200
0
200
0
-200
-400
-600
-800
-1000
-200
-400
-600
-800
-1000
IS(OFF)_1V
IS(OFF)-
ID(ON)_1V
ID(ON)-
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Ambient Temperature (èC)
Ambient Temperature (èC)
D005
D006
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = –15 V
图6-5. Leakage Current vs Temperature
图6-6. Leakage Current vs Temperature
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
2
1
120
tON(VDD= 12V, VSS= 0V)
tON(VDD= 15V, VSS= -15V)
90
60
30
0
VDD= 15V
VSS = -15V
VDD= 12V
VSS = 0V
0
tOFF(VDD= 15V, VSS= -15V)
-1
VDD= 10V
VSS = -10V
tOFF(VDD= 12V, VSS= 0V)
-2
-50
-25
0
25
50
75
100
125
150
-15
-10
-5
0
Drain Voltage (V)
5
10
15
Ambient Temperature (èC)
D008
D007
.
TA = 25°C
图6-8. Transition Times vs Temperature
图6-7. Charge Injection vs Source Voltage
0
-20
0
-20
VDD = 12V
VSS= 0V
Intra-Channel (SxA to SxB)
-40
-40
-60
-60
-80
-80
VDD = 15V
VSS= -15V
-100
-120
-140
-100
-120
-140
Inter-Channel (S1x to S2x)
1E+5
1E+6
1E+7
Frequency (Hz)
1E+8
5E+8
1E+5
1E+6
1E+7
Frequency (Hz)
1E+8
5E+8
D009
D001
TA = 25°C
VDD = 15 V, VSS = –15 V, TA = 25°C
图6-10. Crosstalk vs Frequency
图6-9. Off Isolation vs Frequency
0
-20
100
50
VDD= 5V
VSS= -5V
20
10
5
-40
Intra-Channel (SxA to SxB)
VDD= 15V
VSS= -15V
2
1
-60
-80
0.5
0.2
0.1
-100
-120
-140
0.05
Inter-Channel (S1x to S2x)
0.02
0.01
1E+5
1E+6
1E+7
Frequency (Hz)
1E+8
5E+8
1E+1
1E+2
1E+3
Frequency (Hz)
1E+4
1E+5
D001
D001
VDD = 12 V, VSS = 0 V, TA = 25°C
TA = 25°C
图6-11. Crosstalk vs Frequency
图6-12. THD+N vs Frequency
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
-5
10
8
CS(ON), CD(ON)
-10
-15
-20
6
CS(OFF)
4
2
0
1E+5
1E+6
1E+7
Frequency(Hz)
1E+8
1E+9
-15 -12
-9
-6
-3
0
3
Source Voltage (V)
6
9
12
15
D001
D001
VDD = 15 V, VSS = –15 V, TA = 25°C
图6-13. On Response vs Frequency
VDD = 15 V, VSS = –15 V, TA = 25°C
图6-14. Capacitance vs Source Voltage
10
0
CS(ON), CD(ON)
-20
-40
8
6
4
2
0
VSS
CS(OFF)
-60
VDD
-80
-100
1E+5
2E+53E+5 5E+5 1E+6
Frequency (Hz)
2E+63E+6 5E+6
1E+7
0
2
4
6
Source Voltage (V)
8
10
12
D001
D001
VDD = 15 V, VSS = –15 V, TA = 25°C
图6-16. ACPSRR vs Frequency
VDD = 12 V, VSS = 0 V, TA = 25°C
图6-15. Capacitance vs Source Voltage
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
7 Detailed Description
7.1 Overview
7.1.1 On-Resistance
The on-resistance of the TMUX6136 is the ohmic resistance across the source (Sx) and drain (D) pins of the
device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-
resistance. The measurement setup used to measure RON is shown in 图 7-1. Voltage (V) and current (ICH) are
measured using this setup, and RON is computed as shown in 方程式1.
V
S
D
ICH
VS
图7-1. On-Resistance Measurement Setup
RON = V / ICH
(1)
7.1.2 Off-Leakage Current
Source off-leakage current is defined as the leakage current that flows into or out of the source pin when the
switch is in the off state. This current is denoted by the symbol IS(OFF). Drain off-leakage measurement is not
characterization since the drain pin is always connected to one of the two source pins.
The setup used to measure both off-leakage currents is shown in 图7-2.
Is (OFF)
A
ID (OFF)
A
S
D
VS
VD
图7-2. Off-Leakage Measurement Setup
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
7.1.3 On-Leakage Current
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the on state. The source pin is left floating during the measurement. 图 7-3 shows the circuit used for measuring
the on-leakage current, denoted by ID(ON)
.
ID (ON)
S
D
NC
A
NC = No Connection
VD
图7-3. On-Leakage Measurement Setup
7.1.4 Transition Time
Transition time is defined as the time taken by the output of the TMUX6136 to rise or fall to 90% of the transition
after the digital address signal has fallen or risen to 50% of the transition. 图 7-4 shows the setup used to
measure transition time, denoted by the symbol tTRAN
.
VDD
VSS
VDD
VSS
3 V
VS
SA
SB
Output
D
tr < 20 ns
tf < 20 ns
50%
50%
VSEL
0 V
VS
SEL
300
35 pF
0.9 VS
tTRAN
tTRAN
2
1
Output
VSEL
GND
0.1 VS
tTRAN = max ( tTRAN 1, tTRAN 2)
图7-4. Transition-Time Measurement Setup
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
7.1.5 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the TMUX6136 is
switching. The TMUX6136 output first breaks from the on-state switch before making the connection with the
next on-state switch. The time delay between the break and the make is known as break-before-make delay. 图
7-5 shows the setup used to measure break-before-make delay, denoted by the symbol tBBM
.
VDD
VSS
VDD
VSS
3 V
VS
SB
SA
Output
D
tr < 20 ns
tf < 20 ns
VSEL
0 V
VS
SELx
300 Ω
35 pF
0.8 VS
VSEL
Output
0 V
GND
tBBM
1
tBBM 2
tBBM = min ( tBBM 1, tBBM 2)
图7-5. Break-Before-Make Delay Measurement Setup
7.1.6 Charge Injection
The TMUX6136 have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS
and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the
gate signal. The amount of charge injected into the source of the device is known as charge injection, and is
denoted by the symbol QINJ. 图 7-6 shows the setup used to measure charge injection from drain (D) to source
(Sx).
VDD
VSS
VDD
VSS
3 V
0 V
Output
SB
SA
D
VSEL
NC
RS
VS
1 nF
SEL
Output
VS
VOUT
QINJ = CL ×
VOUT
VSEL
GND
图7-6. Charge-Injection Measurement Setup
7.1.7 Off Isolation
Off isolation is defined as the voltage at the drain pin (D) of the TMUX6136 when a 1-VRMS signal is applied to
the source pin (Sx) of an off-channel. 图 7-7 shows the setup used to measure off isolation. Use 方程式 2 to
compute off isolation.
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
VDD
VSS
VDD
VSS
Network Analyzer
SA
SB
NC
50 Ω
50 Ω
VOUT
D
VS
50 Ω
SEL
GND
VSEL
图7-7. Off Isolation Measurement Setup
≈
∆
«
’
VOUT
VS
Off Isolation = 20 ∂ Log
÷
◊
(2)
7.1.8 Channel-to-Channel Crosstalk
There are two types of crosstalk that can be defined for the TMUX6136:
1. Intra-channel crosstalk: the voltage at the source pin (Sx) of an off-switch input, when a 1-VRMS signal is
applied at the source pin of an on-switch input in the same channel, as shown in 图7-8.
2. Inter-channel crosstalk: the voltage at the source pin (Sx) of an on-switch input, when a 1-VRMS signal is
applied at the source pin of an on-switch input in a different channel, as shown in 图7-9.
VDD
VSS
VDD
VSS
Network Analyzer
SxA
SxB
Dx
VOUT
50 Ω
50 Ω
SEL
VS
50 Ω
VSEL
GND
图7-8. Intra-Channel Crosstalk Measurement Setup
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
VDD
VSS
VDD
VSS
Network Analyzer
S1A
S1B
D1
D2
50 Ω
N.C.
N.C.
50 Ω
VS
VOUT
S2A
S2B
50 Ω
50 Ω
SEL
GND
VSEL
图7-9. Inter-Channel Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(3)
7.1.9 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to the
source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the TMUX6136. 图 7-10
shows the setup used to measure bandwidth of the mux. Use 方程式4 to compute the attenuation.
VDD
VSS
VDD
VSS
Network Analyzer
SA
SB
NC
50 Ω
VOUT
D
VS
50 Ω
SEL
GND
VSEL
图7-10. Bandwidth Measurement Setup
≈
∆
«
’
÷
◊
V2
Attenuation = 20 ∂ Log
V
1
(4)
7.1.10 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the
mux output. The on-resistance of the TMUX6136 varies with the amplitude of the input signal and results in
distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is
denoted as THD+N.
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
VDD
VSS
VDD
VSS
Audio Precision
SA
SB
NC
RS
VS
VOUT
D
10k Ω
SEL
GND
VSEL
图7-11. THD+N Measurement Setup
7.1.11 AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply
voltage pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a
sine wave of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated
signal is the AC PSRR.
VDD
Network Analyzer
DC Bias
Injector
VSS
VDD
VSS
620 mVPP
VIN
VBIAS
SW
SW
S1
S2
NC
VOUT
D
VSEL
10k Ω
5 pF
SEL
50 Ω
GND
VBIAS = 0 V
PSRR= 20 × Log (VOUT/ VIN
)
图7-12. AC PSRR Measurement Setup
For a top-level block diagram of the TMUX6136, see 节 7.2. The TMUX6136 is a 4-channel, single-ended,
analog multiplexer. Each channel is turned on or turned off based on the state of the address lines and enable
pin.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
7.2 Functional Block Diagram
VSS
VDD
S1A
D1
S1B
SEL1
S2A
S2B
D2
SEL2
TMUX6136
Copyright © 2018, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Ultralow Leakage Current
The TMUX6136 provides extremely low on- and off-leakage currents. The TMUX6136 is capable of switching
signals from high source-impedance inputs into a high input-impedance op amp with minimal offset error
because of the ultralow leakage currents. 图 7-13 shows typical leakage currents of the TMUX6136 versus
temperature.
400
ID(ON)+
IS(OFF)+
200
0
-200
-400
IS(OFF)-
-600
ID(ON)-
-800
-1000
-50
-25
0
25
50
75
100
125
150
Ambient Temperature (èC)
D005
图7-13. Leakage Current vs Temperature
7.3.2 Ultralow Charge Injection
The TMUX6136 is implemented with simple transmission gate topology, as shown in 图 7-14. Any mismatch in
the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch
is opened or closed.
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
OFF ON
CGDN
CGSN
D
S
CGSP
CGDP
OFF ON
图7-14. Transmission Gate Topology
The TMUX6136 utilizes special charge-injection cancellation circuitry that reduces the drain (D)-to-source (Sx)
charge injection to as low as –0.4 pC at VS = 0 V, as shown in 图7-15.
2
1
VDD= 15V
VSS = -15V
VDD= 12V
VSS = 0V
0
-1
VDD= 10V
VSS = -10V
-2
-15
-10
-5
0
Drain Voltage (V)
5
10
15
D007
图7-15. Charge Injection vs Drain Voltage
7.3.3 Bidirectional and Rail-to-Rail Operation
The TMUX6136 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each
TMUX6136 channel has very similar characteristics in both directions. The valid analog signal for TMUX6136
ranges from VSS to VDD. The input signal to the TMUX6136 swings from VSS to VDD without any significant
degradation in performance.
7.4 Device Functional Modes
7.4.1 Truth Table
表7-1. TMUX6136 Truth Table
Switch A
(S1A to D1 or S2A to D2)
Switch B
(S1B to D1 or S2B to D2)
SELx
0
1
OFF
ON
ON
OFF
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TMUX6136 offers outstanding input and output leakage currents and ultralow charge injection. The device
operates up to 33 V (VDD to VSS dual supply) or 16.5 V (VDD single supply), and offers true rail-to-rail input and
output. The on-capacitance of the TMUX6136 is low. These features make the TMUX6136 a precision, robust,
high-performance analog multiplexer for high-voltage, industrial applications.
8.2 Typical Application
One example of the TMUX6136 precision performance to take advantage of is the implementation of parametric
measurement unit (PMU) in the semiconductor automatic test equipment (ATE) application. The PMU is
frequently used to characterize and measure the digital pin’s DC characteristics of a device under test (DUT).
Among all the PMU’s capabilities, force voltage measure current (FVMC) and force current measure voltage
(FCMV) are the two most typical configurations in DC characterizations.
Force
Amplifier
Force
Amplifier
VIN
VIN
+
RSENSE
+
RSENSE
Force
Force
œ
œ
DUT
DUT
Current
Sense
Amplifier
Current
Sense
Amplifier
Sense
Sense
Av
Av
Voltage
Sense
Amplifier
+
+
Voltage
Sense
Amplifier
VOUT
œ
VOUT
œ
图8-2. FCMV Measurement in PMU
图8-1. FVMC Measurement in PMU
图 8-1 shows a simplified diagram of the PMU in FVMC configuration. The control loop consists of the force
amplifier with the voltage sense amplifier (unity gain in this example) making up the feedback path. Current
flowing through the DUT is measured by sensing the current flowing through a sense resistor (RSENSE) in series
with the DUT. The current sense amplifier with a gain of Av generates a voltage (VOUT) at its output and the
voltage can then be measured by an ADC. The voltage produced at the DUT pin stays at the input voltage level
(IN) as long as the force amplifier does not rail out (for example, IDUT × RSENSE x Av stays within the input
voltage range of the force amplifier). Depending on the level of the DUT current to be measured, different gain
settings need to be configured for the current sense amplifier.
图 8-2 shows a simplified diagram of the PMU in FCMV mode. The voltage VIN is now converted to a current
through the following relationship:
Force Current = VIN / (RSENSE x Av)
(5)
The control loop consists of the force amplifier with the current sense amplifier making up the feedback path.
The voltage at the DUT is sensed across the voltage sense amplifier (unity gain in this example) and presented
at the output for sample.
8.2.1 Design Requirements
The goal of this design example is to simplify the FVMC and FCMV functions of a PMU design using a SPDT
switch. The FVMC configuration is useful to test a device being used as a power supply, or in continuity or
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
leakage testing. In this configuration, the input voltage is directly applied to the DUT pin, and the current into or
out of the DUT pin is converted to a voltage by a sense resistor and measured by an analog to digital converter
(ADC). In the FCMV mode, an input current is forced to the DUT and the produced voltage on the DUT pin is
directly measured. In this example, the PMU design is required to meet the following specifications:
• Force voltage range: –15 volts to +15 volts
• Force current range: ±5 µA to ±50 mA
• Measure voltage range: –15 volts to +15 volts
• Measure current range: ±5 µA to ±50 mA
In addition to the voltage and current requirements, fast throughput is also a key requirement in ATE because it
relates directly to the cost of manufacturing the DUT.
8.2.2 Detailed Design Procedure
Force
Amplifier
Force
Amplifier
DAC
+
DAC
+
RSENSE
RSENSE
DUT
DUT
œ
œ
Current
Sense
Amplifier
Current
Sense
Amplifier
+
+
A
Av
œ
A
Av
œ
B
A
B
A
ADC
ADC
+
+
B
B
œ
œ
TMUX6136
TMUX6136
Voltage
Sense
Amplifier
Voltage
Sense
Amplifier
图8-3. FVMC Implementation in PMU Using the
图8-4. FCMV Implementation in PMU Using the
TMUX6136
TMUX6136
The implementation of the FVMC and FCMV modes can be combined with the use of a dual SPDT switch such
as the TMUX6136. 图 8-3 and 图 8-4 shows simplified diagrams of such implementations. In the FVMC mode,
the switch is toggled to position A and this allows the voltage sense amplifier to become part of the feedback
loop and the voltage output of the current sense amplifier to be sampled by the ADC. In the FCMV mode, the
switch is toggled to position B, and this allows the current sense amplifier to become part of the feedback loop
and the voltage output of the voltage sense amplifier to be sampled by the ADC.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
8.2.3 Application Curve
The fast transition time of the TMUX6136 and low input or output parasitic capacitance help minimize the settling
time, making the TMUX6136 an excellent candidate to implement the FVMC and FCMV functions of the PMU. 图
8-5 shows the plot for the transition time versus temperature for the TMUX6136.
120
tON(VDD= 12V, VSS= 0V)
tON(VDD= 15V, VSS= -15V)
90
60
tOFF(VDD= 15V, VSS= -15V)
30
tOFF(VDD= 12V, VSS= 0V)
0
-50
-25
0
25
50
75
100
125
150
Ambient Temperature (èC)
D008
图8-5. Transition Time vs Temperature for TMUX6136
9 Power Supply Recommendations
The TMUX6136 operates across a wide supply range of ±5 V to ±16.5 V (10 V to 16.5 V in single-supply mode).
The device also performs well with unsymmetric supplies such as VDD = 12 V and VSS= –5 V. For reliable
operation, use a supply decoupling capacitor ranging between 0.1 µF to 10 µF at both the VDD and VSS pins to
ground.
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
10 Layout
10.1 Layout Guidelines
图10-1 shows an example of a PCB layout with the TMUX6136.
Some key considerations are as follows:
1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
2. Keep the input lines as short as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
10.2 Layout Example
Via to
ground plane
SEL1
S1A
D1
NC
NC
C
NC
VDD
S2B
D2
S1B
VSS
TMUX6136
GND
NC
C
S2A
SEL2
NC
Via to
ground plane
Copyright © 2018, Texas Instruments Incorporated
图10-1. TMUX6136 Layout Example
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TMUX6136
TMUX6136
www.ti.com.cn
ZHCSJ28A –NOVEMBER 2018 –REVISED OCTOBER 2022
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, ADS8664 12-Bit, 500-kSPS, 4- and 8-Channel, Single-Supply, SAR ADCs with Bipolar
Input Ranges
• Texas Instruments, OPA192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias
Current Op Amp with e-Trim™
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TMUX6136
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX6136PWR
ACTIVE
TSSOP
PW
16
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
MUX6136
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Sep-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX6136PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Sep-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 16
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
TMUX6136PWR
2000
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TMUX6201RQXR
36-V, latch-up immune, 1:1 (SPST) 1 channel precision switch with 1.8V Logic (Active High) | RQX | 8 | -40 to 125
TI
TMUX6202RQXR
36-V, latch-up immune, 1:1 (SPST) 1 channel precision switch with 1.8V Logic (active low)
| RQX | 8 | -40 to 125
TI
TMUX6208
TMUX620x 36 V, Low-Ron, 8:1 1-Channel and 4:1, 2-Channel Precision Multiplexers with 1.8 V Logic
TI
TMUX6208PWR
TMUX620x 36 V, Low-Ron, 8:1 1-Channel and 4:1, 2-Channel Precision Multiplexers with 1.8 V Logic
TI
TMUX6208RUMR
TMUX620x 36 V, Low-Ron, 8:1 1-Channel and 4:1, 2-Channel Precision Multiplexers with 1.8 V Logic
TI
TMUX6208_V01
TMUX620x 36-V, Low-Ron, 8:1 1-Channel and 4:1, 2-Channel Precision Multiplexers with 1.8-V Logic
TI
TMUX6208_V02
TMUX620x 36 V, Low-Ron, 8:1 1-Channel and 4:1, 2-Channel Precision Multiplexers with 1.8 V Logic
TI
TMUX6209
TMUX620x 36 V, Low-Ron, 8:1 1-Channel and 4:1, 2-Channel Precision Multiplexers with 1.8 V Logic
TI
TMUX6209PWR
TMUX620x 36 V, Low-Ron, 8:1 1-Channel and 4:1, 2-Channel Precision Multiplexers with 1.8 V Logic
TI
TMUX6209RUMR
TMUX620x 36 V, Low-Ron, 8:1 1-Channel and 4:1, 2-Channel Precision Multiplexers with 1.8 V Logic
TI
©2020 ICPDF网 联系我们和版权申明