TMUX646_技术文档

TMUX646

SCDS432 – JUNE 2021

TMUX646 6 GHz, 5 V, 2:1 (SPDT) 10-Channel MIPI Switch with 1.8-V Logic Support

1 Features

3 Description

•

Supply range of 1.5 V to 5.5 V

10-Channel 2:1 bidirectional switch

Supports MIPI CSI/DSI, SATA, LVDS, RGMII,

DDR, ethernet interfaces

Powered-off protection:

I/Os Hi-Z when V_DD= 0 V

Low R_ON: 6-Ω typical

The TMUX646 is an optimized 10-channel (5

differential) single-pole, double-throw bi-directional

switch for use in high speed applications. The

TMUX646 is designed to facilitate multiple MIPI

compliant devices to connect to a single CSI/DSI, C-

PHY/D-PHY module. The device also supports SATA,

SAS, MIPI DSI/CSI, LVDS, RGMII, DDR and Ethernet

interfaces.

•

High bandwidth : 6 GHz

Ultra low crosstalk: -40 dB

Low power disable mode

1.2 V logic compatible

Bidirectional signal path

ESD protection:

The device has a bandwidth of 6 GHz, low channel-

to-channel skew with little signal degradation, and

wide margins to compensate for layout losses. The

device's low current consumption meets the needs of

low power applications, including mobile phones and

other personal electronics.

– 6-kV human body model (HBM)

– 2-kV human body model (CDM)

Device Information⁽¹⁾

2 Applications

PART NUMBER

PACKAGE

BODY SIZE (NOM)

•

Mobile phones

Tablet

TMUX646

nFBGA (ZEC)

2.45 mm × 2.45 mm

(1) For all available package, see the orderable addendum at the

end of the data sheet.

PC and notebooks

Virtual and augmented reality

Drones

Camera-based carcode scanner

Medical

IP netcam

1.5 V to 5.5 V

100 nF

2.2 µF

100 nF

2.2 µF

VDD

CLK

Trio[1:3]

Data[1:4]

CLK

MIPI Module 1

Trio[1:3]

Data[1:4]

50 Ω

TMUX646

MIPI Switch

TMUX646

MIPI Switch

Processor

CLK

Trio [1:3]

50 Ω

Data[1:4]

MIPI Module 2

SEL

/OE

SEL

/OE

50 Ω

Simplified D-PHY Schematic

Simplified C-PHY Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMUX646

SCDS432 – JUNE 2021

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings ....................................... 5

6.2 ESD Ratings .............................................................. 5

6.3 Recommended Operating Conditions ........................5

6.4 Thermal Information ...................................................5

6.5 Electrical Characteristics ............................................6

6.6 Typical Characteristics..............................................10

7 Parameter Measurement Information..........................13

8 Detailed Description......................................................19

8.1 Overview...................................................................19

8.2 Functional Block Diagram.........................................19

8.3 Feature Description...................................................20

8.4 Device Functional Modes..........................................21

9 Application and Implementation..................................22

9.1 Application Information............................................. 22

9.2 Typical Application.................................................... 22

10 Power Supply Recommendations..............................27

11 Layout...........................................................................28

11.1 Layout Guidelines................................................... 28

11.2 Layout Example...................................................... 28

12 Device and Documentation Support..........................29

12.1 Documentation Support.......................................... 29

12.2 Receiving Notification of Documentation Updates..29

12.3 Support Resources................................................. 29

12.4 Trademarks.............................................................29

12.5 Electrostatic Discharge Caution..............................29

12.6 Glossary..................................................................29

13 Mechanical, Packaging, and Orderable

Information.................................................................... 29

4 Revision History

DATE

REVISION

NOTES

June 2021

*

Initial Release

2

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5 Pin Configuration and Functions

1

2

3

4

5

6

A

B

C

D

E

F

VDD

DB4N

DB3N

DB2N

DB1N

CLKBN

GND

DB4P

DB3P

DB2P

DB1P

CLKBP

DA4N

DA4P

OE

SEL

DA3N

DA3P

D4N

D4P

D3P

D2P

D1P

NC

D3N

DA2N

DA1N

CLKAN

DA2P

DA1P

CLKAP

D2N

D1N

CLKN

CLKP

Not to scale

Figure 5-1. nFBGA Package 36 Pin (ZEC) Top View

Table 5-1. Pin Functions

I/O

DESCRIPTION

NAME

CLKAN

CLKAP

CLKBN

CLKBP

CLKN

CLKP

D1N

NO.

F3

F4

F1

F2

F5

F6

E5

E6

D5

D6

C5

C6

B5

B6

E3

E4

D3

D4

B3

B4

A3

A4

I/O

Differential I/O

D1P

D2N

D2P

D3N

D3P

D4N

D4P

DA1N

DA1P

DA2N

DA2P

DA3N

DA3P

DA4N

DA4P

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Table 5-1. Pin Functions (continued)

NAME

DB1N

DB1P

DB2N

DB2P

DB3N

DB3P

DB4N

DB4P

GND

I/O

DESCRIPTION

NO.

E1

E2

D1

D2

C1

C2

B1

B2

A2

C3

C4

A5

A6

A1

I/O

P

Differential I/O

Device Ground

NC

—

I

No internal connection

Output enable (active low), has internal pull-down resistor

Channel select, has internal pull-down resistor

Power supply input

NC

OE

SEL

I

VDD

P

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V_DD

V_SW

Supply Voltage

–0.5

6

4

V

Switch signal voltage (CLKP/N, CLKAP/N, CLKBP/N, DxP/N,

DAxP/N, DBxP/N)

–0.5

V

V_SEL, V_OE

T_J

Logic control input pin voltage (SEL, OE)

Junction temperature

–0.5

–65

6

125

150

V

°C

T_stg

Storage temperature

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±6000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±2000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_DD

V_SW

Supply Voltage

1.5

5.5

V

Switch signal voltage (CLKP/N, CLKAP/N, CLKBP/N, DxP/N, DAxP/N,

DBxP/N)

0

3.6

5.5

V

V_(SEL)

V_(OE)

Logic control input pin voltage

I_Sor I_D

Continuous current through switch

Operating ambient temperature

–35⁽¹⁾

–40

35⁽¹⁾

85

mA

°C

(CONT)

T_A

(1) At T_J= 85°C

6.4 Thermal Information

TMUX646

THERMAL METRIC⁽¹⁾

ZEC (nFBGA)

36 PINS

111.7

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

49.2

54.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

2.0

Ψ_JB

54.7

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6.4 Thermal Information (continued)

TMUX646

ZEC (nFBGA)

36 PINS

THERMAL METRIC⁽¹⁾

UNIT

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

N/A

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

30

MAX UNIT

POWER SUPPLY

V_DD= 1.5 V to 5.5 V

OE = 0 V

I_DD

VDD active supply current

Power-down supply current

55

1

µA

SEL = 0 V or 5.5 V

Dn, CLKn = 0 V

V_DD= 1.5 V to 5.5 V

OE = V_DD

SEL = 0 V or 5.5 V

Dn, CLKn = 0 V

I_{DD_PD}

0.1

1.3

2.5

V_DD= 2.5 V

OE = 1.8 V

SEL = 0 V or V_DD

Dn, CLKn = 0 V

Increase in supply current per

logic pin at 1.8 V

ΔI_DD

V_DD= 5 V

OE = 1.8 V

SEL = 0 V or V_DD

Dn, CLKn = 0 V

DC CHARACTERISTICS

V_DD= 1.5 V to 5.5 V

OE = 0 V, SEL = 0 V or V_DD

Dn, CLKn = –8 mA, 0.2 V

DAn, DBn, CLKAn, CLKBn = 0.2 V, –8 mA

,

R_{ON_HS}

On-state resistance

6

9

Ω

V_DD= 1.5 V to 5.5 V

OE = 0 V, SEL = 0 V or V_DD

Dn, CLKn = –8 mA, 1.2 V

,

R_{ON_LP}

On-state resistance

10

DAn, DBn, CLKAn, CLKBn = 1.2 V, –8 mA

V_DD= 1.5 V to 5.5 V

OE = 0 V, SEL = 0 V or V_DD

,

R_{ON_flat_HS}

On-state resistance flatness

Dn, CLKn = –8 mA, 0 V to 0.3 V

DAn, DBn, CLKAn, CLKBn = 0 V to 0.3 V, –8

mA

0.1

0.9

Ω

V_DD= 1.5 V to 5.5 V

OE = 0 V, SEL = 0 V or V_DD

,

R_{ON_flat_LP}

On-state resistance flatness

Dn, CLKn = –8 mA, 0 V to 1.3 V

DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V, –8

mA

V_DD= 1.5 V to 5.5 V

On-state resistance match

between + and – paths

OE = 0 V, SEL = 0 V or V_DD

Dn, CLKn = –8 mA, 0.2 V

DAn, DBn, CLKAn, CLKBn = 0.2 V, –8 mA

V_DD= 1.5 V to 5.5 V

OE = 0 V, SEL = 0 V or V_DD

Dn, CLKn = –8 mA, 1.3 V

,

D_{RON_HS}

0.1

Ω

On-state resistance match

between + and – paths

,

D_{RON_LP}

DAn, DBn, CLKAn, CLKBn = 1.3 V, –8 mA

6

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6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_DD= 1.5 V to 5.5 V

OE = 0 V or 5.5 V

I_OFF

Switch off leakage current

SEL = 0 V or 5.5 V

Dn, CLKn = 0 V to 1.3 V

DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V

–0.5

0.5

10

µA

VDD = 0 V, 1.5 V, 1.65 V, 3.3 V, 5.5 V

OE = 0 V or 5.5 V

SEL= 0 V or 5.5 V

DX,CLKX = 3.6 V

DAX,DBx,CLKAX,CLKBX = 3.6 V

I_{OFF_3_6}

Switch off leakage current

Switch on leakage current

–10

–0.5

–50

V_DD= 1.5 V to 5.5 V

OE = 0 V

SEL = 0 V or 5.5 V

Dn, CLKn = 0 V to 1.3 V

DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V

I_ON

0.5

50

VDD = 1.5 V to 5.5 V

OE = 0 V

SEL= 0 V or 5.5 V

DX, CLKX = 3.6 V

I_{ON_3_6}

DAX ,DBx, CLKAX, CLKBX = 3.6 V

DYNAMIC CHARACTERISTICS

V_DD= 1.5 V to 5.5 V

OE = 0 V

t_SWITCH

Switching time SEL to output

Dn, CLKn = 1.2 V

DAn, DBn, CLKAn, CLKBn:

R_L= 50 Ω, C_L= 15pF

1.5

µs

V_DD= 1.5 V to 5.5 V

Turnon time from OE to output Dn, CLKn = 1.2 V

t_{ON_OE}

50

300

1

µs

DAn, DBn, CLKAn, CLKBn:

R_L= 50 Ω, C_L= 15 pF

V_DD= 1.5 V to 5.5 V

Dn, CLKn = 1.2 V

DAn, DBn, CLKAn, CLKBn:

R_L= 50 Ω, C_L= 15 pF

t_{OFF_OE}

Turnoff time from OE to output

0.5

V_DD= 1.5 V to 5.5 V

Dn, CLKn = 1.2 V

DAn, DBn, CLKAn, CLKBn:

R_L= 50 Ω, C_L= 2 pF

Maximum toggling frequency

for the SEL line

f_{SEL_MAX}

100

kHz

V_DD= 0 V to 5.5 V

V_DDramp rate = 1 µs

Dn, CLKn = 1.2 V

DAn, DBn, CLKAn, CLKBn:

R_L= 50 Ω, C_L= 15 pF

Turnon time from VDD to

output

t_{ON_VDD}

50

300

1

µs

V_DD= 5 V to 0 V

Dn, CLKn = 1.2 V

DAn, DBn, CLKAn, CLKBn:

R_L= 50 Ω, C_L= 15 pF

Turnoff time from VDD to

output

t_{OFF_VDD}

t_{MIN_OE}

t_BBM

0.5

ms

ns

V_DD= 1.5 V to 5.5 V

Dn, CLKn = 1.2 V

DAn, DBn, CLKAn, CLKBn:

R_L= 50 Ω, C_L= 2 pF

Minimum pulse width for OE

Break before make time

500

50

V_DD= 1.5 V to 5.5 V

OE = 0 V

Dn, CLKn = R_L= 50 Ω, C_L= 15 pF

DAn, DBn, CLKAn, CLKBn: 1.2 V

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6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_DD= 1.5 V to 5.5 V

OE = 0 V

Intrapair skew

t_SKEW

(opposite transitions of same

output)

Dn, CLKn =0.3 V

DnX, DBn, CLKAn, CLKBn:

R_L= 50 Ω, C_L= 5 pF

1

ps

V_DD= 1.5 V to 5.5 V

OE = 0 V

Dn, CLKn = 0.3 V

DAn, DBn, CLKAn, CLKBn: R_L= 50 Ω, C_L=

5 pF

Interpair Skew

(Channel−to−Channel Skew)

t_SKEW

4

V_DD= 1.5 V to 5.5 V

OE = 0 V

Propagation delay with 100 ps Dn, CLKn = 1.2 V

t_PD

40

ps

rise time

DAn, DBn, CLKAn, CLKBn:

R_L= 50 Ω, C_L= 5 pF

t_RISE= 100 ps

V_DD= 1.5 V to 5.5 V

OE = 0 V, V_DD

SEL = 0 V, V_DD

O_ISO

Differential off isolation

Dn, CLKn, DAn, DBn, CLKAn, CLKBn:

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF

V_SW= 200 mVpp (differential)

f = 1250 MHz

–20

dB

V_DD= 1.5 V to 5.5 V

OE = 0 V, V_DD

SEL = 0 V, V_DD

Differential channel to channel

crosstalk

X_TALK

Dn, CLKn, DAn, DBn, CLKAn, CLKBn:

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF

V_SW= 200 mVpp (differential)

f = 1250 MHz

–40

dB

GHz

dB

V_DD= 1.5 V to 5.5 V

OE = 0 V

SEL = 0 V, V_DD

Dn, CLKn, DAn, DBn, CLKAn, CLKBn:

V_SW= 200 mVpp (differential)

f = 1250 MHz

Differential Bandwidth

BW

6

V_DD= 1.5 V to 5.5 V

OE = 0 V

SEL = 0 V, V_DD

Dn, CLKn, DAn, DBn, CLKAn, CLKBn:

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF

V_SW= 200 mVpp (differential)

f = 100 kHz

I_LOSS

Insertion Loss

–0.65

V_DD= 1.5 V to 5.5 V

OE = 0 V, V_DD

SEL = 0 V, V_DD

Dn, CLKn, DAn, DBn, CLKAn, CLKBn = 0 V,

0.2 V

f = 1250 MHz

C_OFF

Off capacitance

On capacitance

1.5

pF

V_DD= 1.5 V to 5.5 V

OE = 0 V

SEL = 0 V, V_DD

Dn, CLKn, DAn, DBn, CLKAn, CLKBn = 0 V,

C_ON

0.2 V

f = 1250 MHz

DIGITAL CHARACTERISTICS

V_IH

V_IL

I_IH

Input logic high

SEL, OE

1

0

5.5

0.4

5

V

Input logic low

Input high leakage current

–5

µA

8

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6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_IL

Input low leakage current

SEL, OE

–5

5

µA

Internal pull-down resistance

on digital input pins

R_PD

6

5

MΩ

V_SEL= 0 V, 1.8 V or V_DD

f = 1 MHz

C_I

Digital Input capacitance

pF

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6.6 Typical Characteristics

At T_A= 25°C (unless otherwise noted).

Figure 6-1. R_ONvs Input Voltage. V_DD= 1.5 V

Figure 6-2. R_ONvs Input Voltage. V_DD= 3.3 V

Figure 6-3. R_ONvs Input Voltage. V_DD= 5.5 V

Figure 6-4. R_ONvs Input Voltage, V_DD= 1.5 V to 5.5 V

Figure 6-5. On-Leakage vs Input Voltage

Figure 6-6. Off-Leakage vs Input Voltage

10

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6.6 Typical Characteristics (continued)

At T_A= 25°C (unless otherwise noted).

Figure 6-7. Supply Current vs Temperature

Figure 6-8. Supply Current vs Logic Voltage

Figure 6-9. Switching Time (t_SWITCH) vs Supply Voltage

Figure 6-10. Propagation Delay (t_PD) vs Supply Voltage

Figure 6-11. t_{ON_VDD}vs Supply Voltage

Figure 6-12. t_{OFF_VDD}vs Supply Voltage

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6.6 Typical Characteristics (continued)

At T_A= 25°C (unless otherwise noted).

Figure 6-13. Interpair Skew vs Supply Voltage

Figure 6-15. Differential Bandwidth

Figure 6-17. Differential Crosstalk

Figure 6-14. Intrapair Skew vs Supply Voltage

Figure 6-16. Off Isolation

Figure 6-18. Capacitance vs Frequency

12

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7 Parameter Measurement Information

Channel ON

R_ON= V/I_ON

V

V_SW

I_ON

Switch

Figure 7-1. On Resistance

V_SW

A

Switch

Figure 7-2. Off Leakage

V_SW

A

Switch

Figure 7-3. On Leakage

V_SWA

V_SWB

V_SW

C_L

R_L

SEL

C_L

V_SEL

1.5 V

V_SEL

t_SWITCH

V_SWA

V_IL

V_IH

V_SEL

t_SWITCH

V_SWB

V_IH

V_IL

0 V

V_SW

0 V

V_SW

0 V

t_SWITCH

10 %

t_SWITCH

10 %

90 %

A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω , t_r= 3 ns, t_f= 3 ns.

B. C_Lincludes probe and jig capacitance.

Figure 7-4. t_SWITCHTiming

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V_DD

V_SW

/OE

V_SW

1.5 V

0 V

V_IL

V_IH

V_/OE

C_L

R_L

t_ON

t_OFF

V_SW

0 V

90 %

10 %

V_SW

V_/OE

A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω , t_r= 3 ns, t_f= 3 ns.

B. C_Lincludes probe and jig capacitance.

Figure 7-5. t_ONand t_OFFTiming for OE

Network Analyzer

Switch

50 ꢀ

DXP

DXN

50 ꢀ

Source

Signal

50 ꢀ

Source

Signal

50 ꢀ

Figure 7-6. Off Isolation

14

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Network Analyzer

Switch

50 ꢀ

DXP

DXN

50 ꢀ

Source

Signal

50 ꢀ

Source

Signal

50 ꢀ

DXP

DXN

50 ꢀ

Figure 7-7. Crosstalk

Network Analyzer

Switch

50 ꢀ

DXN

50 ꢀ

Source

Signal

50 ꢀ

DXP

50 ꢀ

Source

Signal

50 ꢀ

Figure 7-8. Bandwidth and Insertion Loss

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Generator

Switch

50 ꢀ

D1P

D1N

D2P

D2N

DX1P

DX1N

50 ꢀ

Source

Signal

50 ꢀ

Source

Signal

50 ꢀ

DX2P

Source

Signal

DX2N

Source

Signal

50 ꢀ

D3P

DX3P

Source

Signal

D3N

DX3N

Source

Signal

50 ꢀ

D4P

DX4P

Source

Signal

D4N

DX4N

Source

Signal

50 ꢀ

CLKP

CLKN

CLKXP

Source

Signal

CLKXN

Source

Signal

50 ꢀ

Figure 7-9. t_PD, t_SKEW(INTRA)and t_SKEW(INTER)Setup

16

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DXX/CLKX

50%

t_PD

DXXX/CLKXX

50%

A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω , t_r= 100 ps, t_f= 100 ps.

B. C_Lincludes probe and jig capacitance.

Figure 7-10. t_PD

DXX/CLKX

50%

t_SKEW

DXXX/CLKXX

50%

A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω , t_r= 100 ps, t_f= 100 ps.

B. C_Lincludes probe and jig capacitance.

Figure 7-11. t_SKEW(INTRA)

t_SKEW

DX/CLKX

t_SKEW

DX1

DX2

DX3

DX4

CLK

50%

A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω , t_r= 100 ps, t_f= 100 ps.

B. C_Lincludes probe and jig capacitance.

C. t_SKEWis the maximum skew between all channels. The diagram exaggerates t_SKEWto show the measurement technique.

Figure 7-12. t_SKEW(INTER)

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0.6 V

V_SW

V_SEL

C_L

R_L

SEL

0.6 V

t_BBM

80 %

V_SW

V_SEL

t_BBM

A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω , t_r= 3 ns, t_f= 3 ns.

B. C_Lincludes probe and jig capacitance.

Figure 7-13. t_BBM

18

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8 Detailed Description

8.1 Overview

The TMUX646 is a high-speed 4 data lane 2:1 MIPI Switch. The device includes 10 channels (5 differential) with

4 differential data lanes and 1 differential clock lane for D-PHY, CSI or DSI. The clock and data lanes can be

interchanged as necessary to facilitate the best layout possible for the application. The switch allows a single

MIPI port to interface between two MIPI modules, expanding the number of potential MIPI devices that can be

used within a system that is MIPI port limited.

8.2 Functional Block Diagram

VDD

SEL

6 MO

Control

Logic

/OE

CLKAP

CLKBP

CLKP

CLKN

D1P

D1N

D2P

D2N

D3P

D3N

D4P

D4N

CLKAN

CLKBN

DA1P

DB1P

DA1N

DB1N

DA2P

DB2P

DA2N

DB2N

DA3P

DB3P

DA3N

DB3N

DA4P

DB4P

DA4N

DB4N

GND

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8.3 Feature Description

8.3.1 1.2-V Logic Compatible Inputs

The TMUX646 has 1.2-V logic compatible control inputs. Regardless of the V_DDvoltage, the 1.2-V logic level

inputs allow the TMUX646 to interface with processors that have lower logic I/O rails and eliminates the need for

an external voltage translator, which saves both space and BOM cost. For more information on 1.2 V and 1.8 V

logic implementations, refer to Simplifying Design with 1.8 V logic Muxes and Switches.

8.3.2 Bidirectional Operation

The TMUX646 conducts equally well from A to COM, B to COM, COM to A, or COM to B. Each channel has very

similar characteristics in both directions and supports analog and digital signals.

8.3.3 Powered-Off Protection

When the TMUX646 is powered off (V_DD= 0 V) the I/Os and digital logic pins of the device remains in a

high impedance state. The crosstalk, off-isolation, and leakage will remain within the electrical specifications.

This prevents errant voltages from reaching the rest of the system and maintains isolation when the system is

powering up:

Figure 8-1 shows an example system containing a switch without powered-off protection with the following

system level scenario.

1. Subsystem A powers up and starts sending information to Subsystem B that remains unpowered.

2. The I/O voltage back powers the supply rail in Subsystem B.

3. The digital logic is back powered and turns on the switch. The signal is transmitted to Subsystem B before it

is powered and damages it.

Unpowered

Powered

LDO

2

VDD

1

ESD

Subsystem A

Subsystem B

SEL

3

Switch

Figure 8-1. System Without Powered-Off Protection

With powered-off protection, the switch prevents back powering the supply and the switch remains high-

impedance. Subsystem B remains protected.

Unpowered

Powered

LDO

2

VDD

Protection

ESD

Subsystem A

Subsystem B

SEL

Hi-Z

Switch

Figure 8-2. System With Powered-Off Protection

20

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This features has the following system level benefits:

•

Protects the system from damage.

Prevents data from being transmitted unintentionally.

Eliminates the need for power sequencing solutions, reducing BOM count and cost, simplifying system

design, and improving reliability.

8.3.4 Low Power Disable Mode

The TMUX646 has a low power mode that places all the signal paths in a high impedance state and lowers the

current consumption while the device is not in use. To put the device in low power mode and disable the switch,

the output enable pin OE must be supplied with a logic high signal.

8.4 Device Functional Modes

8.4.1 Pin Functions

The SEL and OE pins have a weak 6-MΩ pull-down to prevent floating input logic.

Table 8-1. Function Table

OE

SEL

Function

I/O pins High-Impedance

CLK(P/N) = CLKA(P/N)

Dn(P/N) = DAn(P/N)

H

X

L

CLK(P/N) = CLKB(P/N)

Dn(P/N) = DBn(P/N)

H

8.4.2 Low Power Disable Mode

While the output enable pin OE is supplied with a logic high, the device remains in the low power disabled

state. This reduces the current consumption substantially and the switches are high impedance. The SEL pin is

ignored while the OE remains high. Upon exiting low power mode, the switch status reflects the SEL pin as seen

in Table 8-1.

8.4.3 Switch Enabled Mode

While the output enable pin OE is supplied with a logic low, the device remains in switch enabled mode.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The TMUX646 is a 2:1, 10 channel MIPI switch designed to facilitate multiple MIPI compliant devices to connect

to a single CSI/DSI, C-PHY/D-PHY module.

9.2 Typical Application

Figure 9-1 represents a typical application of the TMUX646 MIPI switch. The TMUX646 is used to switch signals

between multiple MIPI modules and a single MIPI port on a processor. This expands the capabilities of a single

port to handle multiple MIPI modules.

1.5 V to 5.5 V

100 nF

2.2 µF

VDD

CLK

Data[1:4]

CLK

MIPI Module 1

Data[1:4]

TMUX646

MIPI Switch

Processor

CLK

Data[1:4]

MIPI Module 2

SEL

/OE

Figure 9-1. Typical D-PHY Application

22

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1.5 V to 5.5 V

100 nF

2.2 µF

VDD

Trio[1:3]

MIPI Module 1

Trio[1:3]

50 Ω

TMUX646

MIPI Switch

Processor

Trio [1:3]

50 Ω

MIPI Module 2

SEL

/OE

50 Ω

Figure 9-2. Typical C-PHY Application

9.2.1 Design Requirements

Design requirements of the MIPI standard must be followed. Supply pin decoupling capacitors of 2.2 µF and 100

nF are recommended for best performance. The TMUX646 has internal 6-MΩ pulldown resistors on SEL and

OE. The pulldown on these pins ensure that the digital remains in a non-floating state during system power-up to

prevent shoot through current spikes and an unknown switch status. By default the switch will power up enabled

and with the A path selected until driven externally by the processor.

9.2.2 Detailed Design Procedure

The TMUX646 can be properly operated without any external components. However, TI recommends that

unused I/O signal pins be connected to ground through a 50 Ω resistor to prevent signal reflections and maintain

device performance. The NC pins of the device do not require any external connections or terminations and

have no connection to the rest of the device internally.

The clock and data lanes can be interchanged as necessary to facilitate the best layout possible for the

application. For example, the clock can be placed on the D1 channel and a data lane can be used on the CLK

channel if this improves the layout. In addition, the signal lines of the TMUX646 are routed single ended on the

chip die. This makes the device suitable for differential and single-ended high-speed systems.

9.2.2.1 MIPI D-PHY Application

The clock and data lanes can be interchanged as necessary to facilitate the best layout possible for the

application. In addition, the signal lines of the TMUX646 are routed single ended on the chip die. This makes the

device suitable for differential and single-ended high-speed systems. This also allows the positive and negative

lines to be interchanged as necessary to facilitate the best layout possible for the application.

D-PHY application includes a differential clock and 4 differential data lanes. All the channels of the device

perform similar and the clock or data signals can be interchanged as necessary to facilitate the best layout

possible for the application.

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VDD

D-PHY

Module A

SEL

/OE

6 Mꢀ

Control

Logic

D-PHY

Module B

MIPI_CSI_CLKP_Module A

MIPI_CSI_CLKP_Module B

CLKAP

CLKBP

CLKP

CLKN

D1P

D1N

D2P

D2N

D3P

D3N

D4P

D4N

MIPI_CSI_CLKP

MIPI_CSI_CLKN

+/- Clock

MIPI_CSI_CLKN_Module A

MIPI_CSI_CLKN_Module B

CLKAN

CLKBN

MIPI_CSI_DATA1P_Module A

MIPI_CSI_DATA1P_Module B

DA1P

DB1P

MIPI_CSI_DATA1P

MIPI_CSI_DATA1N

MIPI_CSI_DATA2P

MIPI_CSI_DATA2N

MIPI_CSI_DATA3P

+/- DATA1

+/- DATA2

MIPI_CSI_DATA1N_Module A

MIPI_CSI_DATA1N_Module B

DA1N

DB1N

MIPI_CSI_DATA2P_Module A

MIPI_CSI_DATA2P_Module B

DA2P

DB2P

MIPI_CSI_DATA2N_Module A

MIPI_CSI_DATA2N_Module B

DA2N

DB2N

MIPI_CSI_DATA3P_Module A

MIPI_CSI_DATA3P_Module B

DA3P

DB3P

MIPI_CSI_DATA3N_Module A

MIPI_CSI_DATA3N_Module B

DA3N

DB3N

+/- DATA3

+/- DATA4

MIPI_CSI_DATA3N

MIPI_CSI_DATA4P

MIPI_CSI_DATA4N

MIPI_CSI_DATA4P_Module A

MIPI_CSI_DATA4P_Module B

DA4P

DB4P

MIPI_CSI_DATA4N_Module A

MIPI_CSI_DATA4N_Module B

DA4N

DB4N

GND

Figure 9-3. MIPI D-PHY Example Pinout

24

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9.2.2.2 MIPI C-PHY Application

The clock and data lanes can be interchanged as necessary to facilitate the best layout possible for the

application. In addition, the signal lines of the TMUX646 are routed single ended on the chip die. This makes the

device suitable for differential and single-ended high-speed systems. This also allows the positive and negative

lines to be interchanged as necessary to facilitate the best layout possible for the application.

C-PHY application includes 3 trios of signals, which may be routed on any channel, which means there will be

one unused channel on the TMUX646. TI recommends that the unused I/O signal pin be connected to ground

through a 50 Ω resistor to prevent signal reflections and maintain device performance.

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VDD

C-PHY

Module A

SEL

/OE

6 Mꢀ

Control

Logic

C-PHY

Module B

MIPI_CSI_A0_Module A

MIPI_CSI_A0_Module B

CLKAP

CLKBP

CLKP

CLKN

D1P

D1N

D2P

D2N

D3P

D3N

D4P

D4N

MIPI_CSI_A0

MIPI_CSI_B0

MIPI_CSI_B0_Module A

MIPI_CSI_B0_Module B

CLKAN

CLKBN

Trio 0

MIPI_CSI_C0_Module A

MIPI_CSI_C0_Module B

DA1P

DB1P

MIPI_CSI_C0

MIPI_CSI_A1

MIPI_CSI_B1

MIPI_CSI_C1

MIPI_CSI_A2

MIPI_CSI_A1_Module A

MIPI_CSI_A1_Module B

DA1N

DB1N

MIPI_CSI_B1_Module A

MIPI_CSI_B1_Module B

DA2P

DB2P

Trio 1

MIPI_CSI_C1_Module A

MIPI_CSI_C1_Module B

DA2N

DB2N

MIPI_CSI_A2_Module A

MIPI_CSI_A2_Module B

DA3P

DB3P

MIPI_CSI_B2_Module A

MIPI_CSI_B2_Module B

DA3N

DB3N

MIPI_CSI_B2

Trio 2

MIPI_CSI_C2_Module A

DA4P

DB4P

MIPI_CSI_C2

MIPI_CSI_C2_Module B

50 Ω

50 ꢀ

DA4N

DB4N

GND

50 Ω

GND

Figure 9-4. MIPI C-PHY Example Pinout

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9.2.3 Application Curves

Figure 9-5. 4.5 Gbps Through Path (500-mV_pp)

Figure 9-6. 4.5 Gbps with TMUX646 (500-mV_pp)

Figure 9-7. 6 Gbps Through Path (200-mV_pp)

Figure 9-8. 6 Gbps with TMUX646 (200-mV_pp)

10 Power Supply Recommendations

When the TMUX646 is powered off (V_DD= 0 V), the I/Os of the device remains in a high-Z state. The crosstalk,

off-isolation, and leakage remain within the electrical characteristics Section 6. Power to the device is supplied

through the VDD pin. Decoupling capacitors of 100 nF and 2.2 µF are recommended on the supply.

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11 Layout

11.1 Layout Guidelines

Place the supply de-coupling capacitors as close to the VDD and GND pin as possible. The spacing between the

power traces, supply and ground, and the signal I/O lines, clock and data, should be a minimum of three times

the race width of the signal I/O lines to maintain signal integrity.

The characteristic impedance of one or more traces must match that of the receiver and transmitter to maintain

signal integrity. Route the high-speed traces using a minimum amount of vias and corners. This will reduce the

amount of impedance changes.

When it becomes necessary to make the traces turn 90°, use two 45° turns or an arc instead of making a single

90° turn.

Do not route high-speed traces near crystals, oscillators, external clock signals, switching regulators, mounting

holes or magnetic devices.

Avoid stubs on the signal lines.

All I/O signal traces should be routed over a continuous ground plane with no interruptions. The minimum width

from the edge of the trace to any break in the ground plane must be 3 times the trace width. When routing on

PCB inner signal layers, the high speed traces should be between two ground planes and maintain characteristic

impedance.

High speed signal traces must be length matched as much as possible to minimize skew between data and

clock lines.

11.2 Layout Example

Top Layer Routing

Bottom Layer Routing

VIA to

power plane

ground plane

Via

C

To Control

Logic

DA4

P

VDD

GND

N

/OE

D4N

D3N

D2N

D1N

SEL

D4P

D3P

D2P

D1P

DB4

N

DB4

P

DA3

N

DA3

P

DB3

N

DB3

P

To MIPI

Modules

NC

To MIPI Port

DB2

N

DB2

P

DA2

N

DA2

P

DB1

N

DB1

P

DA1

N

DA1

P

CLK

BN

CLK

BP

CLK

AN

CLK

AP

CLK

N

CLK

P

Figure 11-1. Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

See the following for related documenation:

•

Texas Instruments, 1.8 V Logic for Muxes and Signal Switches application brief

Texas Instruments, High-Speed Interface Layout Guidelines application report

Texas Instruments, High-Speed Layout Guidelines application report

Texas Instruments, Multiplexers and Signal Switches Glossary application report

Texas Instruments, nFBGA Packaging application report

Texas Instruments, Small Body nFBGA Packages application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

13-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TMUX646NZECR

TMUX646ZECR

NFBGA

ZEC

36

2500

330.0

8.4

2.62

2.8

2.62

2.8

0.78

0.8

4.0

8.0

Q1

12.4

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Oct-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TMUX646NZECR

TMUX646ZECR

NFBGA

ZEC

36

2500

338.1

336.6

338.1

336.6

20.6

31.8

Pack Materials-Page 2

PACKAGE OUTLINE

NFBGA - 0.65 mm max height

PLASTIC BALL GRID ARRAY

ZEC0036A

B

2.55

2.35

BALL A1

CORNER

2.55

2.35

0.65 MAX

C

SEATING PLANE

0.08 C

0.24

0.14

BALL TYP

2 TYP

(0.225) TYP

F

(0.225) TYP

E

D

SYMM

2

TYP

C

B

A

0.3

36X Ø

0.2

0.4 TYP

1

2

3

4

5

6

0.15

0.05

C A B

C

SYMM

0.4 TYP

4226214/A 09/2020

NanoFree is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

NFBGA - 0.65 mm max height

PLASTIC BALL GRID ARRAY

ZEC0036A

(0.4) TYP

3

1

2

4

5

6

A

B

(0.4) TYP

C

D

E

F

SYMM

36X (Ø 0.23)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 25X

0.0375 MAX

ALL AROUND

0.0375 MIN

ALL AROUND

EXPOSED

METAL

EXPOSED

METAL

(Ø 0.23)

SOLDER MASK

OPENING

(Ø 0.23)

METAL

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON- SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4226214/A 09/2020

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments

Literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

NFBGA - 0.65 mm max height

PLASTIC BALL GRID ARRAY

ZEC0036A

(0.4) TYP

3

1

2

4

5

6

A

B

(0.4) TYP

C

D

E

F

SYMM

(R0.05)

36X (SQ 0.23)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.100 mm THICK STENCIL

SCALE: 25X

4226214/A 09/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TMUX646
厂家：	TEXAS INSTRUMENTS
描述：	TMUX646 6 GHz, 5 V, 2:1 (SPDT) 10-Channel MIPI Switch with 1.8-V Logic Support 光电二极管
文件：	总37页 (文件大小：3050K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMUX646 [TI]

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