TMUX7348F [TI]
具有故障阈值、闩锁效应抑制和 1.8V 逻辑电平的 ±60V 故障保护、8:1 多路复用器;
| 型号： | TMUX7348F |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有故障阈值、闩锁效应抑制和 1.8V 逻辑电平的 ±60V 故障保护、8:1 多路复用器 复用器 |
| 文件： | 总64页 (文件大小：3663K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUX7348F, TMUX7349F
ZHCSPC6A –MARCH 2022 –REVISED NOVEMBER 2022
TMUX734xF 具有可调节故障阈值、闩锁效应抑制和1.8V 逻辑电平的±60V 故障
保护、8:1 和双路4:1 多路复用器
1 特性
3 说明
• 宽电源电压范围：
TMUX7348F 和 TMUX7349F 是现代互补金属氧化物
半导体 (CMOS) 模拟多路复用器，可采用 8:1（单端）
和4:1（差分）配置。这些器件在双电源（±5 V 至±22
V）、单电源（8 V 至 44 V）或非对称电源（例如 VDD
= 12 V，VSS = –5 V）供电时均能正常运行。
TMUX7348F 和 TMUX7349F 器件在通电和断电情况
下均提供过压保护，适用于无法精确控制电源时序的应
用。
– 双电源：±5 V 至±22 V
– 单电源：8 V 至44 V
• 集成故障保护：
– 过压保护（从源极到电源或到漏极）： ±85V
– 过压保护： ±60 V
– 断电保护： ±60 V
– 可调节过压触发阈值
• VFP：3 V 至VDD、VFN：0 V 至VSS
– 中断标志用于指示全面和特定的故障通道信息
– 无故障通道在低泄漏电流下继续运行
– 在过压条件下，输出被钳位到故障电源
• 由器件构造实现的闩锁效应抑制
• 支持的逻辑电平：1.8V
• 失效防护逻辑：高达44V（与电源无关）
• 先断后合开关
• 行业标准TSSOP 封装和较小的WQFN 封装
在通电和断电条件下，该器件可阻断最高达 +60 V 和
-60 V 的接地故障电压。无论开关输入条件和逻辑控制
状态如何，在没有电源的情况下，开关通道将保持关断
状态。在正常工作条件下，如果任何 Sx 引脚上的模拟
输入信号电平超过正极故障电源 (VFP) 或负极故障电源
(VFN)，且超出幅度达到阈值电压 (VT)，那么通道将会
关闭，并且 Sx 引脚将变为高阻态。选择故障通道后，
漏极引脚（D 或 Dx）将被拉至所超过的故障电源电压
（VFP 或 VFN）。该器件提供两个低电平有效中断标志
（FF 和 SF），用于指示故障详情。FF 标志指示是否
有任何源输入出现故障，而 SF 标志用于说明出现故障
状态的特定输入。
2 应用
• 工厂自动化和控制
• 可编程逻辑控制器(PLC)
• 模拟输入模块
• 半导体测试设备
• 电池测试设备
TMUX7348F 和 TMUX7349F 器件具有低电容、低电
荷注入和集成式故障保护功能，因此可用于注重高性能
和高稳健性的前端数据采集应用。这些器件可采用标准
TSSOP 封装和较小的 WQFN 封装（非常适合 PCB 空
间受限的情况）。
• 伺服驱动器控制模块
• 数据采集系统(DAQ)
VDD VSS
VFN VFP
VDD VSS
VFN VFP
封装信息(1)(2)
SW
SW
SW
封装尺寸（标称值）
器件型号
TMUX7348F
封装
S1
S2
S1A
DA
DB
PW（TSSOP，20） 6.50mm × 4.40mm
RTJ（WQFN，20） 4.00mm × 4.00mm
SW
SW
S4A
S1B
TMUX7349F
D
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
SW
SW
S4B
S8
(2) 请参阅器件比较表。
A0
A1
A2
EN
A0
A1
EN
Fault Detec on/
Switch Driver/
Logic Decoder
Fault Detec on/
Switch Driver/
Logic Decoder
FF
SF
FF
SF
TMUX7348F
TMUX7349F
功能模块图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS400
TMUX7348F, TMUX7349F
ZHCSPC6A –MARCH 2022 –REVISED NOVEMBER 2022
www.ti.com.cn
Table of Contents
8.10 Fault Flag Response Time......................................33
8.11 Fault Flag Recovery Time....................................... 33
8.12 Charge Injection......................................................34
8.13 Off Isolation.............................................................34
8.14 Crosstalk.................................................................35
8.15 Bandwidth............................................................... 36
8.16 THD + Noise........................................................... 36
9 Detailed Description......................................................37
9.1 Overview...................................................................37
9.2 Functional Block Diagram.........................................37
9.3 Feature Description...................................................38
9.4 Device Functional Modes..........................................41
10 Application and Implementation................................44
10.1 Application Information........................................... 44
10.2 Typical Application.................................................. 44
11 Power Supply Recommendations..............................46
12 Layout...........................................................................46
12.1 Layout Guidelines................................................... 46
12.2 Layout Example...................................................... 46
13 Device and Documentation Support..........................49
13.1 Documentation Support.......................................... 49
13.2 接收文档更新通知................................................... 49
13.3 支持资源..................................................................49
13.4 Trademarks.............................................................49
13.5 Electrostatic Discharge Caution..............................49
13.6 术语表..................................................................... 49
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Thermal Information....................................................7
7.4 Recommended Operating Conditions.........................7
7.5 Electrical Characteristics (Global)...............................8
7.6 ±15 V Dual Supply: Electrical Characteristics.............9
7.7 ±20 V Dual Supply: Electrical Characteristics...........12
7.8 12 V Single Supply: Electrical Characteristics.......... 15
7.9 36 V Single Supply: Electrical Characteristics.......... 18
7.10 Typical Characteristics............................................21
8 Parameter Measurement Information..........................28
8.1 On-Resistance.......................................................... 28
8.2 Off-Leakage Current................................................. 28
8.3 On-Leakage Current................................................. 29
8.4 Input and Output Leakage Current Under
Overvoltage Fault........................................................29
8.5 Break-Before-Make Delay.........................................30
8.6 Enable Delay Time....................................................31
8.7 Transition Time......................................................... 31
8.8 Fault Response Time................................................32
8.9 Fault Recovery Time.................................................32
Information.................................................................... 49
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (April 2022) to Revision A (November 2022)
Page
• 将TMUX7349F 器件的WQFN 和TSSOP (20) 封装状态从预发布更改为正在供货.........................................1
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5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX7348F
TMUX7349F
+60 V/ –60 V tolerant, fault-protected, latch-up immune, single-ended 8:1 multiplexers with adjustable fault threshold
+60 V/ –60 V tolerant, fault-protected, latch-up immune, dual 4:1 multiplexers with adjustable fault threshold
6 Pin Configuration and Functions
A0
EN
VSS
S1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A1
A2
GND
VDD
S5
VSS
S1
1
2
3
4
5
15
14
13
12
11
VDD
S5
S2
Thermal
Pad
S2
S6
S3
S6
S3
S7
S4
S7
S4
S8
D
S8
VFN
SF
VFP
FF
Not to scale
Not to scale
图6-2. RTJ Package, 20-Pin WQFN (Top View)
图6-1. PW Package, 20-Pin TSSOP (Top View)
表6-1. Pin Functions: TMUX7348F
PIN
TYPE(1)
DESCRIPTION
NAME
TSSOP
WQFN
Logic control input address 0 (A0). The pin has a 4-MΩinternal pull-down resistor. This pin can also
be used together with the specific fault pin (SF) to indicate which input is under fault. For more
details, see 节9.4.3.
A0
1
19
I
Logic control input address 1 (A1). The pin has a 4-MΩinternal pull-down resistor. This pin can also
be used together with the specific fault pin (SF) to indicate which input is under fault. For more
details, see 节9.4.3.
A1
20
18
I
Logic control input address 2 (A2). The pin has a 4-MΩinternal pull-down resistor. This pin can also
be used together with the specific fault pin (SF) to indicate which input is under fault. For more
details, see 节9.4.3.
A2
D
19
8
17
6
I
I/O
I
Drain pin. Can be an input or output. The drain pin is not overvoltage protected and shall remain
within the recommended operating range.
Active high logic enable (EN) pin. The pin has a 4-MΩinternal pull-down resistor. The device is
disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax
logic inputs determine individual switch states. For more details, see 节9.4.3.
EN
2
20
General fault flag. This pin is an open drain output and is asserted low when overvoltage condition is
detected on any of the source (Sx) input pins. Connect this pin to an external supply (1.8 V to 5.5 V)
through a 1-kΩpull-up resistor.
FF
11
9
O
GND
S1
S2
S3
S4
S5
S6
S7
S8
18
4
16
2
P
Ground (0 V) reference.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Overvoltage protected source pin 1. Can be an input or output.
Overvoltage protected source pin 2. Can be an input or output.
Overvoltage protected source pin 3. Can be an input or output.
Overvoltage protected source pin 4. Can be an input or output.
Overvoltage protected source pin 5. Can be an input or output.
Overvoltage protected source pin 6. Can be an input or output.
Overvoltage protected source pin 7. Can be an input or output.
Overvoltage protected source pin 8. Can be an input or output.
5
3
6
4
7
5
16
15
14
13
14
13
12
11
Specific fault flag. 表9-1 shows how this pin is an open drain output and is asserted low when
overvoltage condition is detected on a specific pin, depending on the state of A0, A1, and A2.
Connect this pin to an external supply (1.8 V to 5.5 V) through a 1-kΩpull-up resistor.
SF
10
8
O
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表6-1. Pin Functions: TMUX7348F (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
TSSOP
WQFN
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
17
15
P
Negative fault voltage supply that determines the overvoltage protection triggering threshold on the
negative side. Connect to VSS if the triggering threshold will be the same as the device's negative
supply. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between
VFN and GND.
VFN
9
7
P
P
Positive fault voltage supply that determines the overvoltage protection triggering threshold on the
positive side. Connect to VDD if the triggering threshold will be the same as the device's positive
supply. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between
VFP and GND.
VFP
12
3
10
1
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
P
Thermal pad. The thermal pad is not connected internally. It is recommended that the pad be tied to
GND or VSS for best performance.
Thermal Pad
—
(1) I = input, O = output, I/O = input and output, P = power
A0
EN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A1
GND
VDD
S1B
S2B
S3B
S4B
DB
VSS
S1A
S2A
S3A
S4A
DA
VSS
S1A
S2A
S3A
S4A
1
2
3
4
5
15
14
13
12
11
S1B
S2B
S3B
S4B
DB
Thermal
Pad
VFN
SF
VFP
FF
Not to scale
Not to scale
图6-3. PW Package, 20-Pin TSSOP (Top View)
图6-4. RTJ Package, 20-Pin WQFN (Top View)
表6-2. Pin Functions: TMUX7349F
PIN
TYPE(1)
DESCRIPTION
NAME
TSSOP
WQFN
Logic control input address 0 (A0). The pin has a 4-MΩinternal pull-down resistor. This pin can also
be used together with the specific fault pin (SF) to indicate which input is under fault. For more details,
see 节9.4.3.
A0
1
19
I
Logic control input address 1 (A1). The pin has a 4-MΩinternal pull-down resistor. This pin can also
be used together with the specific fault pin (SF) to indicate which input is under fault. For more details,
see 节9.4.3.
A1
20
18
I
Drain terminal A. Can be an input or output. The drain pin is not overvoltage protected and shall
remain within the recommended operating range.
DA
DB
8
6
I/O
I/O
Drain terminal B. Can be an input or output. The drain pin is not overvoltage protected and shall
remain within the recommended operating range.
13
11
Active high logic enable (EN) pin. The pin has a 4-MΩinternal pull-down resistor. The device is
disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax
logic inputs determine individual switch states. This pin can also be used together with the specific
fault pin (SF) to indicate which input is under fault. For more details, see 节9.4.3.
EN
FF
2
20
9
I
General fault flag. This pin is an open drain output and is asserted low when overvoltage condition is
detected on any of the source (Sx) input pins. Connect this pin to an external supply (1.8 V to 5.5 V)
through a 1-kΩpull-up resistor.
11
O
GND
S1A
19
4
17
2
P
Ground (0 V) reference
I/O
Overvoltage protected source pin 1A. Can be an input or output.
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表6-2. Pin Functions: TMUX7349F (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
S1B
S2A
S2B
S3A
S3B
S4A
S4B
TSSOP
WQFN
17
5
15
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Overvoltage protected source pin 1B. Can be an input or output.
Overvoltage protected source pin 2A. Can be an input or output.
Overvoltage protected source pin 2B. Can be an input or output.
Overvoltage protected source pin 3A. Can be an input or output.
Overvoltage protected source pin 3B. Can be an input or output.
Overvoltage protected source pin 4A. Can be an input or output.
Overvoltage protected source pin 4B. Can be an input or output.
16
6
14
4
15
7
13
5
14
12
Specific fault flag. 表9-2 provides how this pin is an open drain output and is asserted low when
overvoltage condition is detected on a specific pin, depending on the state of A0, A1, and EN. Connect
this pin to an external supply (1.8 V to 5.5 V) through a 1-kΩpull-up resistor.
SF
10
18
8
O
P
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
16
Negative fault voltage supply that determines the overvoltage protection triggering threshold on the
negative side. Connect to VSS if the triggering threshold will be the same as the device's negative
supply. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between
VFN and GND.
VFN
9
7
P
P
Positive fault voltage supply that determines the overvoltage protection triggering threshold on the
positive side. Connect to VDD if the triggering threshold will be the same as the device's positive
supply. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between
VFP and GND.
VFP
12
3
10
1
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
P
Thermal pad. The thermal pad is not connected internally. It is recommended to tie the pad to GND or
VSS for best performance.
Thermal Pad
—
(1) I = input, O = output, I/O = input and output, P = power
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VDD to VSS
48
48
VDD to GND
VSS to GND
VFP to GND
VFN to GND
VS to GND
VS to VDD
VS to VSS
VD
V
Supply voltage
–0.3
–48
0.3
V
Positive fault clamping voltage
VDD + 0.3
0.3
V
–0.3
Negative fault clamping voltage
Source input pin (Sx) voltage to GND
Source input pin (Sx) voltage to VDD
Source input pin (Sx) voltage to VSS
Drain pin (D or Dx) voltage
V
VSS –0.3
–65
65
V
V
–90
90
V
VFP+0.7
V
VFN–0.7
GND –0.7
GND –0.7
–30
VEN or VAx
VxF
Logic control input pin voltage (EN, A0, A1, A2)(2)
Logic output pin (SF, FF) voltage(2)
Logic control input pin current (EN, A0, A1, A2)(2)
Logic output pin (SF, FF) current(2)
Source or drain continuous current (Sx or D)
Storage temperature
48
V
6
V
IEN or IAx
IxF
IS or ID (CONT)
Tstg
30
mA
mA
mA
°C
°C
°C
mW
mW
10
IDC ± 10 %(3)
150
–10
IDC ± 10 %(3)
–65
TA
Ambient temperature
150
–55
TJ
Junction temperature
150
(4)
Ptot
Total power dissipation (QFN)
1900
(5)
Ptot
Total power dissipation (TSSOP)
800
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) Stresses have to be kept at or below both voltage and current ratings at all time.
(3) Refer to Recommended Operating Conditions for IDC ratings.
(4) For QFN package: Ptot derates linearly above TA = 70°C by 28.5 mW/°C
(5) For TSSOP package: Ptot derates linearly above TA = 70°C by 12.0 mW/°C
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±3500
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-
C101 or ANSI/ESDA/JEDEC JS-002(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible if necessary precautions are taken.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible if necessary precautions are taken.
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7.3 Thermal Information
TMUX7348F/ TMUX7349F
THERMAL METRIC(1)
PW (TSSOP)
20 PINS
84.3
RTJ (WQFN)
20 PINS
35.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
22.7
28.3
37.3
13.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.0
0.3
ΨJT
36.7
13.5
ΨJB
RθJC(bot)
N/A
4.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
8
NOM
MAX UNIT
(1)
Power supply voltage differential
Positive power supply voltage
44
44
V
V
V
V
V
V
VDD –VSS
VDD
5
VFP
Positive fault clamping voltage
3
VDD
0
VFN
Negative fault clamping voltage
VSS
VFN
–60
VS
Source pin (Sx) voltage (non-fault condition)
Source pin (Sx) voltage (fault condition)
VFP
60
VS to GND
Source pin (Sx) voltage
to VDD or VD (fault
condition)
(2)
VS to VDD
Source pin (Sx) voltage to VDD or VD (fault condition)
Source pin (Sx) voltage to VSS or VD (fault condition)
V
V
–85
Source pin (Sx) voltage
to VSS or VD (fault
condition)
(2)
VS to VSS
VD
85
Drain pin (D, Dx) voltage
VFN
0
VFP
44
V
V
VEN or VAx
Logic control input pin voltage (EN, A0, A1, A2)
Logic output pin (SF, FF) voltage
Ambient temperature
VxF
TA
0
5.5
125
9
V
°C
–40
TA = 25°C
TA = 85°C
TA = 125°C
(3)
IDC
Continuous current through switch
6.5 mA
5
(1) VDD and VSS can be any value as long as 8 V ≤(VDD –VSS) ≤44 V.
(2) Under a fault condition, the potential difference between source pin (Sx) and supply pins (VDD and VSS.) or source pin (Sx) and drain
pins (D, Dx) may not exceed 85 V.
(3) Fault supplies are tied to the primary supplies (VFP= VDD, VFN = VSS
)
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7.5 Electrical Characteristics (Global)
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
Threshold voltage for fault
detector
VT
25°C
0.7
V
LOGIC INPUT/ OUTPUT
VIH
High-level input voltage
Low-level input voltage
Low-level output voltage
EN, Ax pins
EN, Ax pins
1.3
0
44
0.8
V
V
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
VIL
VOL(FLAG)
POWER SUPPLY
FF and SF pins, IO = 5 mA
0.35
Rising edge, single supply
Falling edge, single supply
5.1
5
6
6.4
6.3
V
V
–40°C to +125°C
–40°C to +125°C
Undervoltage lockout (UVLO)
threshold voltage (VDD –VSS
VUVLO
)
5.8
VDD Undervoltage lockout
(UVLO) hysteresis
VHYS
Single supply
0.2
40
V
–40°C to +125°C
RD(OVP)
Drain resistance to supply rail during overvoltage event on selected source pin 25°C
kΩ
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7.6 ±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
180
250
VS = –10 V to +10 V,
IS = –1 mA
330
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
390
8
2.5
1.5
On-resistance mismatch between VS = –10 V to +10 V,
12
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
channels
IS = –1 mA
13
3.5
VS = –10 V to +10 V,
IS = –1 mA
4
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
4
RON_DRIFT
1
VS = 0 V, IS = –1 mA
Ω/°C
0.1
1
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
–1
–1
IS(OFF)
Source off leakage current(1)
1
4
nA
nA
nA
–40°C to +85°C
–40°C to +125°C
25°C
–4
0.1
0.3
1
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
–1
ID(OFF)
Drain off leakage current(1)
Output on leakage current(2)
3
–40°C to +85°C
–40°C to +125°C
25°C
–3
14
1.5
5
–14
–1.5
–5
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
22
–22
FAULT CONDITION
VS = ± 60 V, GND = 0 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V
Input leakage current
durring overvoltage
IS(FA)
±110
±135
µA
µA
–40°C to +125°C
–40°C to +125°C
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
IS(FA) Grounded
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
IS(FA) Floating
±135
±10
µA
nA
–40°C to +125°C
25°C
50
70
–50
–70
VS = ± 60 V, GND = 0 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
–15.5 V ≤VD ≤16.5 V
Output leakage current
during overvoltage
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
90
–90
±1
50
–50
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
ID(FA) Grounded
100
500
nA
µA
–40°C to +85°C
–40°C to +125°C
25°C
–100
–500
±3
±5
±8
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
LOGIC INPUT/ OUTPUT
IIH High-level input current
25°C
± 0.6
± 0.6
2
2
–2
–2
VEN = VAx = VDD
VEN = VAx = 0 V
µA
µA
–40°C to +125°C
25°C
1.1
1.2
–1.1
–1.2
IIL
Low-level input current
–40°C to +125°C
SWITCHING CHARACTERISTICS
25°C
165
265
285
300
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
tON (EN)
Enable turn-on time
–40°C to +85°C
–40°C to +125°C
ns
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7.6 ±15 V Dual Supply: Electrical Characteristics (continued)
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
350
400
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
400
420
225
245
260
tOFF (EN)
Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
ns
ns
170
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
tTRAN
Transition time
–40°C to +85°C
–40°C to +125°C
VFP = 15 V, VFN = –15 V,
RL = 4 kΩ, CL= 12 pF
tRESPONSE
Fault response time
Fault recovery time
25°C
25°C
25°C
25°C
300
1.4
110
0.9
ns
µs
ns
µs
VFP = 15 V, VFN = –15 V,
RL = 4 kΩ, CL= 12 pF
tRECOVERY
VFP = 15 V, VFN = –15 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
tRESPONSE(FLAG) Fault flag response time
tRECOVERY(FLAG) Fault flag recovery time
VFP = 15 V, VFN = –15 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
tBBM
QINJ
Break-before-make time delay
Charge injection
50
120
ns
VS = 10 V, RL = 4 kΩ, CL= 12 pF
–40°C to +125°C
VS = 0 V, CL = 1 nF
25°C
pC
–15
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
OISO
Off-isolation
25°C
25°C
25°C
dB
dB
dB
–82
–95
Intra-channel crosstalk
RS = 50 Ω, RL = 50 Ω, CL = 5 pF, VS
200 mVRMS, VBIAS = 0 V, f = 1 MHz
=
XTALK
Inter-channel crosstalk
(TMUX7349F)
–103
25°C
25°C
150
280
MHz
MHz
–3 dB bandwidth (TMUX7348F)
–3 dB bandwidth (TMUX7349F)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
BW
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
ILOSS
Insertion loss
25°C
dB
–9
Total harmonic distortion plus
noise
RS = 40 Ω, RL = 10 kΩ, VS = 15 VPP
VBIAS = 0 V, f = 20 Hz to 20 kHz
,
THD+N
CS(OFF)
25°C
25°C
25°C
0.0014
3.5
%
pF
pF
Input off-capacitance
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
Output off-capacitance
(TMUX7348F)
28
CD(OFF)
Output off-capacitance
(TMUX7349F)
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
25°C
25°C
25°C
15
30
17
pF
pF
pF
Input/Output on-capacitance
(TMUX7348F)
CS(ON)
CD(ON)
Input/Output on-capacitance
(TMUX7349F)
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7.6 ±15 V Dual Supply: Electrical Characteristics (continued)
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
POWER SUPPLY
25°C
0.24
0.5
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
0.5
0.5
0.4
0.4
0.4
IDD
VDD supply current
VSS supply current
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
0.14
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS
–40°C to +85°C
–40°C to +125°C
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND
GND current
25°C
25°C
25°C
0.075
10
mA
µA
µA
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IFP
VFP supply current
VFN supply current
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IFN
10
25°C
0.25
1
1
VS = ± 60 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD(FA)
VDD supply current under fault
VSS supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
1
0.15
0.5
0.5
0.5
VS = ± 60 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS(FA)
–40°C to +85°C
–40°C to +125°C
VS = ± 60 V,
IGND(FA)
IFP(FA)
IFN(FA)
GND current under fault
25°C
25°C
25°C
0.15
9
mA
µA
µA
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
VS = ± 60 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
VFP supply current under fault
VFN supply current under fault
VS = ± 60 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
9
25°C
0.15
0.5
0.5
0.5
0.4
0.4
0.4
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
IDD(DISABLE)
VDD supply current (disable mode)
VSS supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
0.1
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
ISS(DISABLE)
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive,VD is negative. And when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.7 ±20 V Dual Supply: Electrical Characteristics
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
180
250
VS = –15 V to +15 V,
IS = –1 mA
330
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
390
8
2.5
8
On-resistance mismatch between VS = –15 V to +15 V,
12
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
channels
IS = –1 mA
13
10
VS = –15 V to +15 V,
IS = –1 mA
12
RFLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
Ω
12
1.5
3.5
VS = –13.5 V to +13.5 V,
IS = –1 mA
4
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
4
RON_DRIFT
1
VS = 0 V, IS = –1 mA
Ω/°C
0.1
1
VDD = 22 V, VSS = –22 V
Switch state is off
VS = +15 V / –15 V
VD = –15 V / + 15 V
–1
–1
IS(OFF)
Source off leakage current(1)
1
4
nA
nA
nA
–40°C to +85°C
–40°C to +125°C
25°C
–4
0.1
0.3
1
VDD = 22 V, VSS = –22 V
Switch state is off
VS = +15 V / –15 V
VD = –15 V / + 15 V
–1
ID(OFF)
Drain off leakage current(1)
Output on leakage current(2)
3
–40°C to +85°C
–40°C to +125°C
25°C
–3
14
1.5
5
–14
–1.5
–5
VDD = 22 V, VSS = –22 V
Switch state is on
VS = VD = ±15 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
22
–22
FAULT CONDITION
VS = ± 60 V, GND = 0 V,
VDD = VFP = 22 V, VSS = VFN = –22 V
Input leakage current
durring overvoltage
IS(FA)
±95
µA
µA
–40°C to +125°C
–40°C to +125°C
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
IS(FA) Grounded
±135
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
IS(FA) Floating
±135
±10
µA
nA
–40°C to +125°C
25°C
50
70
–50
–70
VS = ± 60 V, GND = 0 V,
VDD = VFP = 22 V, VSS = VFN = –22 V
–21 V ≤VD ≤22 V
Output leakage current
during overvoltage
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
90
–90
±1
50
–50
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
ID(FA) Grounded
100
500
nA
µA
–40°C to +85°C
–40°C to +125°C
25°C
–100
–500
±3
±5
±8
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
LOGIC INPUT/ OUTPUT
IIH High-level input current
25°C
± 0.6
± 0.6
2.2
2.2
1.1
1.2
–2.2
–2.2
–1.1
–1.2
VEN = VAx = VDD
VEN = VAx = 0 V
µA
µA
–40°C to +125°C
25°C
IIL
Low-level input current
–40°C to +125°C
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7.7 ±20 V Dual Supply: Electrical Characteristics (continued)
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
175
300
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
325
350
400
400
420
245
270
285
tON (EN)
tOFF (EN)
tTRAN
Enable turn-on time
Enable turn-off time
Transition time
–40°C to +85°C
–40°C to +125°C
25°C
ns
ns
ns
350
170
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
VS = 10 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
VFP = 20 V, VFN = –20 V,
RL = 4 kΩ, CL= 12 pF
tRESPONSE
Fault response time
Fault recovery time
25°C
25°C
25°C
25°C
300
1.3
110
0.9
ns
µs
ns
µs
VFP = 20 V, VFN = –20 V,
RL = 4 kΩ, CL= 12 pF
tRECOVERY
VFP = 20 V, VFN = –20 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
tRESPONSE(FLAG) Fault flag response time
tRECOVERY(FLAG) Fault flag recovery time
VFP = 20 V, VFN = –20 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
tBBM
QINJ
Break-before-make time delay
Charge injection
50
120
ns
VS = 10 V, RL = 4 kΩ, CL= 12 pF
–40°C to +125°C
VS = 0 V, CL = 1 nF
25°C
pC
–17
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
OISO
Off-isolation
25°C
25°C
25°C
25°C
25°C
25°C
dB
dB
–85
–95
–103
150
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
Intra-channel crosstalk
XTALK
Inter-channel crosstalk
(TMUX7349F)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
–3 dB bandwidth (TMUX7348F)
–3 dB bandwidth (TMUX7349F)
Insertion loss
BW
MHz
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
285
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
ILOSS
–9
Total harmonic distortion plus
noise
RS = 40 Ω, RL = 10 kΩ, VS = 20 VPP
VBIAS = 0 V, f = 20 Hz to 20 kHz
,
THD+N
CS(OFF)
25°C
25°C
25°C
0.0014
3.5
%
Input off-capacitance
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
pF
Output off-capacitance
(TMUX7348F)
28
CD(OFF)
pF
pF
Output off-capacitance
(TMUX7349F)
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
25°C
25°C
25°C
14
30
16
Input/Output on-capacitance
(TMUX7348F)
CS(ON)
CD(ON)
Input/Output on-capacitance
(TMUX7349F)
POWER SUPPLY
25°C
0.24
0.14
0.5
0.5
0.5
0.4
0.4
0.4
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD
VDD supply current
VSS supply current
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS
–40°C to +85°C
–40°C to +125°C
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7.7 ±20 V Dual Supply: Electrical Characteristics (continued)
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND
GND current
25°C
25°C
0.075
mA
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IFP
VFP supply current
VFN supply current
10
µA
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IFN
25°C
25°C
10
µA
0.25
1
VS = ± 60 V,
1
1
IDD(FA)
VDD supply current under fault
VSS supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
0.15
0.5
0.5
0.5
VS = ± 60 V,
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS(FA)
–40°C to +85°C
–40°C to +125°C
VS = ± 60 V,
IGND(FA)
IFP(FA)
IFN(FA)
GND current under fault
25°C
25°C
25°C
0.15
9
mA
µA
µA
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
VS = ± 60 V,
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
VFP supply current under fault
VFN supply current under fault
VS = ± 60 V,
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
9
25°C
0.15
0.5
0.5
0.5
0.4
0.4
0.4
mA
mA
mA
mA
mA
mA
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
IDD(DISABLE)
VDD supply current (disable mode)
VSS supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
25°C
0.1
VDD = VFP = 22 V, VSS = VFN = –22 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
ISS(DISABLE)
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive,VD is negative. And when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.8 12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
180
250
VS = 0 V to 7.8 V,
IS = –1 mA
330
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
390
8
2.5
7
VS = 0 V to 7.8 V,
IS = –1 mA
On-resistance mismatch between
channels
12
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
13
30
VS = 0 V to 7.8 V,
IS = –1 mA
45
RFLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
Ω
75
7
1.5
VS = 1 V to 7.8 V,
IS = –1 mA
8
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
8
RON_DRIFT
1
VS = 6 V, IS = –1 mA
Ω/°C
0.1
1
–1
–1
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
IS(OFF)
Source off leakage current(1)
1
4
nA
nA
nA
–40°C to +85°C
–40°C to +125°C
25°C
VD = 1 V / 10 V
–4
0.1
0.3
1
–1
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
ID(OFF)
Drain off leakage current(1)
Output on leakage current(2)
3
–40°C to +85°C
–40°C to +125°C
25°C
–3
VD = 1 V / 10 V
14
1.5
5
–14
–1.5
–5
VDD = 13.2 V, VSS = 0 V
Switch state is on
VS = VD = 10 V or 1 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
22
–22
FAULT CONDITION
Input leakage current
durring overvoltage
VS = ± 60 V, GND = 0 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V
IS(FA)
±145
±135
µA
µA
–40°C to +125°C
–40°C to +125°C
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
IS(FA) Grounded
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
IS(FA) Floating
±135
±10
µA
nA
–40°C to +125°C
25°C
50
70
–50
–70
VS = ± 60 V, GND = 0 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V
1 V ≤VD ≤13.2 V
Output leakage current
during overvoltage
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
90
–90
±1
50
–50
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
ID(FA) Grounded
100
500
nA
µA
–40°C to +85°C
–40°C to +125°C
25°C
–100
–500
±3
±5
±8
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
LOGIC INPUT/ OUTPUT
IIH High-level input current
25°C
± 0.6
± 0.6
2
2
µA
µA
–2
–2
VEN = VAx = VDD
VEN = VAx = 0 V
–40°C to +125°C
25°C
1.1
1.2
–1.1
–1.2
IIL
Low-level input current
µA
–40°C to +125°C
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7.8 12 V Single Supply: Electrical Characteristics (continued)
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
160
265
VS = 8 V,
RL = 4 kΩ, CL= 12 pF
285
300
485
485
500
215
230
240
tON (EN)
tOFF (EN)
tTRAN
Enable turn-on time
Enable turn-off time
Transition time
–40°C to +85°C
–40°C to +125°C
25°C
ns
ns
ns
420
160
VS = 8 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
VS = 8 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
VFP = 12 V, VFN = 0 V,
RL = 4 kΩ, CL= 12 pF
tRESPONSE
Fault response time
Fault recovery time
25°C
25°C
25°C
25°C
220
0.69
110
ns
µs
ns
µs
VFP = 12 V, VFN = 0 V,
RL = 4 kΩ, CL= 12 pF
tRECOVERY
VFP = 12 V, VFN = 0 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
tRESPONSE(FLAG) Fault flag response time
tRECOVERY(FLAG) Fault flag recovery time
VFP = 12 V, VFN = 0 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
0.65
tBBM
QINJ
Break-before-make time delay
Charge injection
30
90
ns
VS = 8 V, RL = 4 kΩ, CL= 12 pF
–40°C to +125°C
VS = 6 V, CL = 1 nF
25°C
pC
–11
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
OISO
Off-isolation
25°C
25°C
25°C
dB
dB
dB
–76
–93
XTALK
XTALK
Intra-channel crosstalk
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
Inter-channel crosstalk
(TMUX7349F)
–103
25°C
25°C
130
250
–3 dB bandwidth (TMUX7348F)
–3 dB bandwidth (TMUX7349F)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V
BW
MHz
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
ILOSS
Insertion loss
25°C
–9
Total harmonic distortion plus
noise
RS = 40 Ω, RL = 10 kΩ, VS = 6 VPP, VBIAS
= 6 V, f = 20 Hz to 20 kHz
THD+N
CS(OFF)
25°C
25°C
25°C
0.0022
%
Input off-capacitance
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
4
pF
Output off-capacitance
(TMUX7348F)
31
CD(OFF)
pF
pF
Output off-capacitance
(TMUX7349F)
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
25°C
25°C
25°C
16
34
20
Input/Output on-capacitance
(TMUX7348F)
CS(ON)
CD(ON)
Input/Output on-capacitance
(TMUX7349F)
POWER SUPPLY
25°C
0.24
0.14
0.5
0.5
0.5
0.4
0.4
0.4
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD
VDD supply current
VSS supply current
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS
–40°C to +85°C
–40°C to +125°C
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND
IFP
GND current
25°C
25°C
0.075
10
mA
µA
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
VFP supply current
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7.8 12 V Single Supply: Electrical Characteristics (continued)
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
10
MAX UNIT
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IFN
VFN supply current
25°C
25°C
µA
0.25
1
VS = ± 60 V,
1
1
IDD(FA)
VDD supply current under fault
VSS supply current under fault
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
0.15
0.5
0.5
0.5
VS = ± 60 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS(FA)
–40°C to +85°C
–40°C to +125°C
VS = ± 60 V,
IGND(FA)
IFP(FA)
IFN(FA)
GND current under fault
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
25°C
25°C
25°C
0.17
9
mA
µA
µA
VS = ± 60 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
VFP supply current under fault
VFN supply current under fault
VS = ± 60 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
7.5
25°C
0.15
0.5
0.5
0.5
0.4
0.4
0.4
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
IDD(DISABLE)
VDD supply current (disable mode)
VSS supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
0.1
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
ISS(DISABLE)
–40°C to +85°C
–40°C to +125°C
(1) When VS is 10 V, VD is 1 V. Or when VS is 1 V, VD is 10 V.
(2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.9 36 V Single Supply: Electrical Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
180
250
VS = 0 V to 28 V,
IS = –1 mA
330
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
390
8
2.5
8
VS = 0 V to 28 V,
IS = –1 mA
On-resistance mismatch between
channels
12
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
13
65
75
90
VS = 0 V to 30 V,
IS = –1 mA
RFLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
Ω
1.5
3
VS = 1 V to 28 V,
IS = –1 mA
4
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
4
RON_DRIFT
1
VS = 18 V, IS = –1 mA
Ω/°C
0.1
1
–1
–1
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
IS(OFF)
Source off leakage current(1)
1
4
nA
nA
nA
–40°C to +85°C
–40°C to +125°C
25°C
VD = 1 V / 30 V
–4
0.1
0.3
1
–1
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
ID(OFF)
Output on leakage current(2)
Output on leakage current(1)
3
–40°C to +85°C
–40°C to +125°C
25°C
–3
VD = 1 V / 30 V
14
1.5
5
–14
–1.5
–5
VDD = 39.6 V, VSS = 0 V
Switch state is on
VS = VD = 30 V or 1 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
22
–22
FAULT CONDITION
Input leakage current
durring overvoltage
VS = 60 / –40 V, GND = 0 V
VDD = VFP = 39.6 V, VSS = VFN = 0 V
IS(FA)
±110
±135
µA
µA
–40°C to +125°C
–40°C to +125°C
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V
VDD = VSS = VFP = VFN= 0 V
IS(FA) Grounded
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V
VDD = VSS = VFP = VFN= floating
IS(FA) Floating
±135
±10
µA
nA
–40°C to +125°C
25°C
50
70
–50
–70
VS = 60 / –40 V, GND = 0 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V
1 V ≤VD ≤39.6 V
Output leakage current
during overvoltage
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
90
–90
±1
50
–50
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
ID(FA) Grounded
100
500
nA
µA
–40°C to +85°C
–40°C to +125°C
25°C
–100
–500
±3
±5
±8
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
LOGIC INPUT/ OUTPUT
IIH High-level input current
25°C
± 0.6
± 0.6
3.2
3.2
1.1
1.2
–3.2
–3.2
–1.1
–1.2
VEN = VAx = VDD
VEN = VAx = 0 V
µA
µA
–40°C to +125°C
25°C
IIL
Low-level input current
–40°C to +125°C
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7.9 36 V Single Supply: Electrical Characteristics (continued)
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
185
390
VS = 18 V,
RL = 4 kΩ, CL= 12 pF
460
530
450
450
450
230
245
255
tON (EN)
tOFF (EN)
tTRAN
Enable turn-on time
Enable turn-off time
Transition time
–40°C to +85°C
–40°C to +125°C
25°C
ns
ns
ns
380
185
VS = 18 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
VS = 18 V,
RL = 4 kΩ, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
VFP = 36 V, VFN = 0 V,
RL = 4 kΩ, CL= 12 pF
tRESPONSE
Fault response time
Fault recovery time
25°C
25°C
25°C
25°C
210
0.67
110
ns
µs
ns
µs
VFP = 36 V, VFN = 0 V,
RL = 4 kΩ, CL= 12 pF
tRECOVERY
VFP = 36 V, VFN = 0 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
tRESPONSE(FLAG) Fault flag response time
tRECOVERY(FLAG) Fault flag recovery time
VFP = 36 V, VFN = 0 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
0.65
tBBM
QINJ
Break-before-make time delay
Charge injection
50
100
ns
VS = 18 V, RL = 4 kΩ, CL= 12 pF
–40°C to +125°C
VS = 18 V, CL = 1 nF
25°C
pC
–16
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
OISO
Off-isolation
25°C
25°C
25°C
25°C
25°C
25°C
dB
dB
–78
–95
–103
130
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
Intra-channel crosstalk
XTALK
Inter-channel crosstalk
(TMUX7349F)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V
–3 dB bandwidth (TMUX7348F)
–3 dB bandwidth (TMUX7349F)
Insertion loss
BW
MHz
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V
255
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
ILOSS
–9
Total harmonic distortion plus
noise
RS = 40 Ω, RL = 10 kΩ, VS = 18 VPP
VBIAS = 18 V, f = 20 Hz to 20 kHz
,
THD+N
CS(OFF)
25°C
25°C
25°C
0.0014
%
Input off-capacitance
f = 1 MHz, VS = 18 V
f = 1 MHz, VS = 18 V
4
pF
Output off-capacitance
(TMUX7348F)
31
CD(OFF)
pF
pF
Output off-capacitance
(TMUX7349F)
f = 1 MHz, VS = 18 V
f = 1 MHz, VS = 18 V
f = 1 MHz, VS = 18 V
25°C
25°C
25°C
16
34
19
Input/Output on-capacitance
(TMUX7348F)
CS(ON)
CD(ON)
Input/Output on-capacitance
(TMUX7349F)
POWER SUPPLY
25°C
0.24
0.14
0.5
0.5
0.5
0.4
0.4
0.4
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
mA
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS
VSS supply current
GND current
–40°C to +85°C
–40°C to +125°C
mA
mA
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IGND
25°C
0.075
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7.9 36 V Single Supply: Electrical Characteristics (continued)
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
IFP
IFN
VFP supply current
25°C
10
µA
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
VFN supply current
25°C
25°C
10
µA
0.25
1
VS = 60 / –40 V,
1
1
IDD(FA)
VDD supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
0.15
0.5
0.5
0.5
VS = 60 / –40 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
ISS(FA)
VSS supply current under fault
–40°C to +85°C
–40°C to +125°C
VS = 60 / –40 V,
IGND(FA)
IFP(FA)
IFN(FA)
GND current under fault
25°C
25°C
25°C
0.12
9
mA
µA
µA
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
VS = 60 / –40 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
VFP supply current under fault
VFN supply current under fault
VS = 60 / –40 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 5 V or VDD
7.5
25°C
0.15
0.5
0.5
0.5
0.4
0.4
0.4
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
IDD(DISABLE)
VDD supply current (disable mode)
VSS supply current (disable mode)
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
0.1
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VAx = 0 V, 5 V, or VDD, VEN = 0 V
ISS(DISABLE)
–40°C to +85°C
–40°C to +125°C
(1) When VS is 30 V, VD is 1 V. Or when VS is 1 V, VD is 30 V.
(2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.10 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
1800
1600
1400
1200
1000
800
600
400
200
0
420
VDD = 13.5 V, VSS = -13.5 V
VDD = 15 V, VSS = -15 V
VDD = 16.5 V, VSS = -16.5 V
VDD = 18 V, VSS = -18 V
VDD = 20 V, VSS = -20 V
VDD = 22 V, VSS = -22 V
VDD = 13.5 V, VSS = -13.5 V
VDD = 15 V, VSS = -15 V
VDD = 16.5 V, VSS = -16.5 V
VDD = 18 V, VSS = -18 V
VDD = 20 V, VSS = -20 V
VDD = 22 V, VSS = -22 V
380
340
300
260
220
180
140
100
-22 -18 -14 -10 -6
-2
2
6
10 14 18 22
-22 -18 -14 -10 -6
-2
2
6
10 14 18 22
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
Dual Supply Voltages
Dual Supply Flat RON Region
图7-1. On-Resistance vs Source or Drain Voltage
240
图7-2. On-Resistance vs Source or Drain Voltage
350
VDD = 13.5 V, VSS = -13.5 V
VDD = 15 V, VSS = -15 V
VDD = 16.5 V, VSS = -16.5 V
VDD = 18 V, VSS = -18 V
VDD = 20 V, VSS = -20 V
VDD = 22 V, VSS = -22 V
TA = 125C
230
220
210
200
190
180
170
160
300
250
200
150
100
TA = 85C
TA = 25C
TA = -40C
-10
-6
-2
2
6
10
-18
-14
-10
-6
-2
2
6
10
14
18
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
Flattest RON region for all supply voltages shown
±15 V Supply Flattest RON Region
图7-3. On-Resistance vs Source or Drain Voltage
350
图7-4. On-Resistance vs Source or Drain Voltage
1800
VDD = 7.2 V, V SS = 0 V
VDD = 8 V, V SS = 0 V
VDD = 8.8 V, V SS = 0 V
TA = 125C
1600
1400
1200
1000
800
600
400
200
0
300
250
200
150
100
VDD = 10.8 V, V
= 0 V
SS
VDD = 12 V, V SS = 0 V
VDD = 13.2 V, V = 0 V
TA = 85C
SS
TA = 25C
TA = -40C
0
2
4
6
8
10
12 13.2
-18
-14
-10
-6
-2
2
6
10
14
18
VS or V D - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
Single Supply Voltages
±20 V Supply Flattest RON Region
图7-6. On-Resistance vs Source or Drain Voltage
图7-5. On-Resistance vs Source or Drain Voltage
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
480
420
360
300
240
180
120
60
350
TA = 125C
300
250
200
150
100
TA = 85C
TA = 25C
VDD = 8 V, V SS = 0 V
VDD = 8.8 V, V SS = 0 V
VDD = 12 V, V SS = 0 V
VDD = 13.2 V, V SS = 0 V
TA = -40C
VDD = 10.8 V, V
= 0 V
SS
0
2
4
6
8
10
12 13.2
1
2
3
4
5
6
7
8
9
VS or V D - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
Single Supply Flat RON Region
12 V Supply Flattest RON Region
图7-7. On-Resistance vs Source or Drain Voltage
图7-8. On-Resistance vs Source or Drain Voltage
Single Supply Voltages
Single Supply Flat RON Region
图7-9. On-Resistance vs Source or Drain Voltage
图7-10. On-Resistance vs Source or Drain Voltage
350
TA = 125C
300
250
200
150
100
TA = 85C
TA = 25C
TA = -40C
1
5
9
13
17
21
25
29
33
VS or VD - Source or Drain Voltage (V)
44 V Supply Flattest RON Region
36 V Supply Flattest RON Region
图7-12. On-Resistance vs Source or Drain Voltage
图7-11. On-Resistance vs Source or Drain Voltage
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
12
IDOFF VS = -10 V, VD = 10 V
IDOFF VS = 10 V, VD = -10 V
IDON VS = -10 V, VD = -10 V
IDON VS = 10 V, VD = 10 V
ISOFF VS = -10 V, VD = 10 V
ISOFF VS = 10 V, VD = -10 V
11
10
9
8
7
6
5
4
3
2
1
0
-1
0
25
50
75
100
125
Temperature (C)
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = −15 V
图7-13. Leakage Current vs Temperature
图7-14. Leakage Current vs Temperature
12
11
10
9
12
11
10
9
IDOFF VS = 1 V, VD = 30 V
IDOFF VS = 30 V, VD = 1 V
IDON VS = 1 V, VD = 1 V
IDON VS = 30 V, VD = 30 V
ISOFF VS = 1 V, VD = 30 V
ISOFF VS = 30 V, VD = 1 V
IDOFF VS = -15 V, VD = 15 V
IDOFF VS = 15 V, VD = -15 V
IDON VS = -15 V, VD = -15 V
IDON VS = 15 V, VD = 15 V
ISOFF VS = -15 V, VD = 15 V
ISOFF VS = 15 V, VD = -15 V
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
-1
-1
0
25
50
75
100
125
0
25
50
75
100
125
Temperature (C)
Temperature (C)
VDD = 36 V, VSS = 0 V
VDD = 20 V, VSS = −20 V
图7-15. Leakage Current vs Temperature
图7-16. Leakage Current vs Temperature
200
100
200
100
IDOFF VS = 1 V, VD = 30 V
IDOFF VS = 30 V, VD = 1 V
IDON VS = 1 V, VD = 1 V
IDON VS = 30 V, VD = 30 V
ISOFF VS = 1 V, VD = 30 V
ISOFF VS = 30 V, VD = 1 V
IDOFF VS = -15 V, VD = 15 V
IDOFF VS = 15 V, VD = -15 V
IDON VS = -15 V, VD = -15 V
IDON VS = 15 V, VD = 15 V
ISOFF VS = -15 V, VD = 15 V
ISOFF VS = 15 V, VD = -15 V
10
1
10
1
0.1
0.1
0.01
0.01
0.0005
0.0005
0
25
50
75
100
125
0
25
50
75
100
125
Temperature (C)
Temperature (C)
VDD = 36 V, VSS = 0 V
VDD = 20 V, VSS = −20 V
图7-17. Leakage Current vs Temperature
图7-18. Leakage Current vs Temperature
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
16
14
12
10
8
16
VS = -60 V, VD = 15 V
VS = -30 V, VD = 15 V
VS = 60 V, VD = -14 V
VS = 30 V, VD = -14 V
VS = -60 V, VD = 20 V
VS = -30 V, VD = 20 V
VS = 60 V, VD = -19 V
VS = 30 V, VD = -19 V
14
12
10
8
6
6
4
4
2
2
0
0
-2
-2
0
25
50
75
100
125
0
25
50
75
100
125
Temperature (C)
Temperature (C)
VDD = 15 V, VSS = −15 V
VDD = 20 V, VSS = −20 V
图7-19. ID(FA) Overvoltage Leakage Current vs Temperature
图7-20. ID(FA) Overvoltage Leakage Current vs Temperature
16
VS = -40 V, VD = 36 V
14
12
10
8
VS = -30 V, VD = 36 V
VS = 60 V, VD = 1 V
VS = 30 V, VD = 1 V
6
4
2
0
-2
0
25
50
75
100
125
Temperature (C)
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
图7-21. ID(FA) Overvoltage Leakage Current vs Temperature
图7-22. ID(FA) Overvoltage Leakage Current vs Temperature
120
90
0.1
VDD = 15 V, VSS = -15 V
VDD = 20 V, VSS = -20 V
0.05
0.03
0.02
VDD = 36 V, VSS = 0 V
VDD = 44 V, VSS = 0 V
60
30
0.01
0
0.005
-30
-60
-90
-120
0.003
0.002
0.001
0.0005
0.0003
0.0002
VS = -60 V
VS = -30 V
VS = 30 V
VS = 60 V
-150
-180
0.0001
0
4k
8k
12k
16k
20k
0
25
50
75
100
125
Frequency (Hz)
Temperature (C)
VDD = 15 V, VSS = −15 V
图7-24. THD+N vs Frequency
图7-23. IS(FA) Overvoltage Leakage Current vs Temperature
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
2
-2
2
-2
-6
-6
-10
-14
-18
-22
-26
-30
-34
-10
-14
-18
-22
-26
-30
VDD = 8 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
VDD = 44 V, VSS = 0 V
VDD = 15 V, VSS = -15 V
VDD = 20 V, VSS = -20 V
-20 -16 -12
-8
-4
0
4
8
12
16
20
0
4
8
12 16 20 24 28 32 36 40 44
VS - Source Voltage (V)
VS - Source Voltage (V)
图7-25. Charge Injection vs Source Voltage –Dual Supply
图7-26. Charge Injection vs Source Voltage –Single Supply
210
VDD: 15 V, VSS: -15 V, Falling Edge
200
190
180
170
160
150
140
130
120
VDD: 15 V, VSS: -15 V, Rising Edge
VDD: 20 V, VSS: -20 V, Falling Edge
VDD: 20 V, VSS: -20 V, Rising Edge
-40
-15
10
35
60
85
110 125
Temperature (C)
图7-27. Transition Times vs Temperature
图7-28. Transition Times vs Temperature
350
330
310
290
270
250
230
210
190
170
150
130
450
420
390
360
330
TOFF ꢁ15 V
TOFF +8 V
TON +8 V
TOFF +12 V
TON +12 V
TOFF +36 V
TON +36 V
TON ꢁ15 V
TOFF ꢁ20 V
TON ꢁ20 V
300
270
240
210
180
150
120
-40
-15
10
35
60
85
110 125
-40
-15
10
35
60
85
110 125
Temperature ( ꢀC)
Temperature ( ꢀC)
图7-29. Turn-On and Turn-Off Times vs Temperature
图7-30. Turn-On and Turn-Off Times vs Temperature
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
0
Off-Isolation
CrossTalk: Adjacent Channel
CrossTalk: Nonadjacent Channel
-20
-40
-60
-80
-100
-120
10k
100k
1M
10M
100M
1G
Frequency (Hz)
图7-32. On Response vs Frequency
CDOFF TMUX7348F
图7-31. Off Isolation and Crosstalk vs Frequency
120
120
100
80
60
40
20
0
CDOFF TMUX7348F
CON TMUX7348F
CSOFF
CON TMUX7348F
CSOFF
CDOFF TMUX7349F
CON TMUX7349F
100
CDOFF TMUX7349F
CON TMUX7349F
80
60
40
20
0
-15 -12
-9
-6
-3
0
3
6
9
12
15
0
2
4
6
8
10
12
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = −15 V
图7-34. Capacitance vs Source or Drain Voltage
图7-33. Capacitance vs Source or Drain Voltage
0.9
0.8
0.7
0.6
0.5
0.4
0.4
VT Falling
VT Rising
VDD = +10 V
VSS = -10 V
VS = ꢀ10 V
0.36
0.32
0.28
0.24
0.2
0.16
0.12
0.08
0.04
100k
1M
Frequency (Hz)
10M
50M
-40
-15
10
35
60
85
110 125
Temperature (C)
图7-35. Threshold Voltage vs Temperature
图7-36. Large Signal Voltage Off Isolation vs Frequency
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
25
10
7.5
5
2.5
0
-2.5
-5
-7.5
-10
-12.5
-15
-17.5
-20
-22.5
-25
SOURCE
FF/SF
22.5
20
50 V/s Fault Ramp
17.5
15
VFP
12.5
10
DRAIN
VFN
7.5
5
FF/SF
DRAIN
2.5
0
-2.5
-5
50 V/s Fault Ramp
SOURCE
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Time (s)
3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Time (s)
3
图7-37. Drain Output Response –Positive Overvoltage
图7-38. Drain Output Response –Negative Overvoltage
10
FF/SF
7.5
5
2.5
0
-2.5
-5
DRAIN
VFN
-7.5
-10
-12.5
-15
-17.5
-20
-22.5
-25
50 V/s Fault Ramp
SOURCE
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Time (s)
3
图7-39. Drain Output Recovery –Positive Overvoltage
图7-40. Drain Output Recovery –Negative Overvoltage
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8 Parameter Measurement Information
8.1 On-Resistance
The on-resistance of the TMUX7348F and TMUX7349F is the ohmic resistance across the source (Sx) and drain
(Dx) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used
to denote on-resistance. 图 8-1 shows the measurement setup used to measure RON. ΔRON represents the
difference between the RON of any two channels, while RON_FLAT denotes the flatness that is defined as the
difference between the maximum and minimum value of on-resistance measured over the specified analog
signal range.
V
VDD
VSS
8
410
=
+
5
VDD
VSS
IS
SW
Sx
Dx
VS
GND
图8-1. On-Resistance Measurement Setup
8.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current IS(OFF): the leakage current flowing into or out of the source pin when the switch
is off.
2. Drain off-leakage current ID(OFF): the leakage current flowing into or out of the drain pin when the switch is
off.
图8-2 shows the setup used to measure both off-leakage currents.
VDD VSS
VFP
VFN
VDD VSS
VFP
VFN
Is (OFF)
SW
SW
SW
SW
S1
S1
A
S2
S8
S2
ID (OFF)
VS
D
D
A
GND
VD
SW
SW
S8
VD
GND
VS
GND
GND
GND
GND
IS(OFF)
ID(OFF)
图8-2. Off-Leakage Measurement Setup
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8.3 On-Leakage Current
Source on-leakage current (IS(ON)) and drain on-leakage current (ID(ON)) denote the channel leakage currents
when the switch is in the on state. IS(ON) is measured with the drain floating, while ID(ON) is measured with the
source floating. 图8-3 shows the circuit used for measuring the on-leakage currents.
VDD VSS
VFP VFN
VDD VSS
VFP VFN
IS(ON)
A
SW
SW
SW
SW
S1
S2
S1
S2
N.C.
ID(ON)
A
D
D
VS
GND
N.C.
SW
SW
VD
S8
S8
GND
VS
VS
GND
GND
GND
GND
IS(ON)
ID(ON)
图8-3. On-Leakage Measurement Setup
8.4 Input and Output Leakage Current Under Overvoltage Fault
If the voltage for any of the source pins rises above the fault supplies (VFP or VFN), the overvoltage protection
feature of the TMUX7348F and TMUX7349F is triggered to turn off the switch under fault, keeping the fault
channel in high-impedance state. IS(FA) and ID(FA) denotes the input and output leakage current under
overvoltage fault conditions, respectively. For ID(FA), the device is disabled to measure leakage current on the
drain pin without being impacted by the 40 kΩimpedance to the fault supply. When the overvoltage fault occurs,
the supply (or supplies) can either be in normal operating condition (图 8-4) or abnormal operating condition (图
8-5). During abnormal operating condition, the supply (or supplies) can either be unpowered (VDD= VSS = VFN
=
VFP = 0 V) or floating (VDD= VSS = VFN = VFP = no connection), and remains within the leakage performance
specifications.
VDD VSS
VFP
VFN
IS (FA)
A
N.C.
SW
SW
S1
S2
S8
ID (FA)
A
VS
D
GND
SW
N.C.
VD
GND
GND
IS(FA) / ID(FA)
( |VS| > |VFP + VT| or |VFN - VT| )
图8-4. Measurement Setup for Input and Output Leakage Current under Overvoltage Fault with Normal
Supplies
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N.C.
VFP
GND
VDD
VSS
VDD
VSS
VFP
VFN
VFN
IS (FA)
A
N.C.
IS (FA)
A
N.C.
SW
SW
SW
SW
S1
S2
S1
S2
ID (FA)
A
ID (FA)
A
VS
VS
D
D
GND
GND
SW
SW
S8
S8
GND
GND
N.C.
N.C.
GND
GND
Unpowered
(VDD = VSS = VFP = VFN = 0 V)
Floating
(VDD = VSS = VFP = VFN = N.C.)
图8-5. Measurement Setup for Input and Output Leakage Current Under Overvoltage Fault with
Unpowered or Floating Supplies
8.5 Break-Before-Make Delay
The break-before-make delay is a safety feature of the TMUX7348F and TMUX7349F. The ON switches first
break the connection before the OFF switches make connection. The time delay between the break and the
make is known as break-before-make delay. 图 8-6 shows the setup used to measure break-before-make delay,
denoted by the symbol tBBM
.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD VSS
VFP VFN
SW
SW
S1
S2
3 V
D
tr < 20 ns
tf < 20 ns
VA
0 V
VD
CL
RL
GND
SW
SW
S7
S8
GND
GND
0.8 VD
Output
A0
A1
tBBM
1
tBBM 2
VS
EN
0 V
Decoder
tBBM = min ( tBBM 1, tBBM 2)
A2
GND
VEN
VA
GND
GND
GND
图8-6. Break-Before-Make Delay Measurement Setup
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8.6 Enable Delay Time
tON(EN) time is defined as the time taken by the output of the TMUX7348F and TMUX7349F to rise to a 90% final
value after the EN signal has risen to a 50% final value. tOFF(EN) is defined as the time taken by the output of the
TMUX7348F and TMUX7349F to fall to a 10% initial value after the EN signal has fallen to a 50% initial value. 图
8-7 shows the setup used to measure the enable delay time.
VDD
VSS
0.1 µF
GND
VDD VSS
VFP VFN
0.1 µF
GND
SW
SW
S1
S2
3 V
VS
D
tr < 20 ns
tf < 20 ns
50%
50%
VEN
GND
0 V
VD
RL
CL
SW
S8
0.9 VD
tON(EN)
GND
GND
tOFF(EN)
0.1 VD
GND
Output
A0
A1
EN
Decoder
A2
VEN
GND
GND
GND
图8-7. Enable Delay Measurement Setup
8.7 Transition Time
Transition time is defined as the time taken by the output of the device to rise (to 90% of the transition) or fall (to
10% of the transition) after the address signal (Ax) has fallen or risen to 50% of the transition. 图 8-8 shows the
setup used to measure transition time, denoted by the symbol tTRAN
.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD VSS
VFP VFN
SW
SW
S1
3 V
S2
tr < 20 ns
tf < 20 ns
50%
50%
VA
VS
D
0 V
VD
GND
RL
CL
0.9 VD
tTRAN
SW
S8
Output
0 V
tTRAN
1
2
GND
GND
0.1 VD
GND
tTRAN = max ( tTRAN 1, tTRAN 2)
A0
A1
EN
Decoder
A2
VEN
VA
GND
GND
GND
图8-8. Transition Time Measurement Setup
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8.8 Fault Response Time
Fault response time (tRESPONSE) measures the delay between the source voltage exceeding the fault supply
voltage (VFP or VFN) by 0.5 V and the drain voltage failing to 50% of the maximum output voltage. 图 8-9 shows
the setup used to measure tRESPONSE
.
VSS
VFP
0.1 µF
GND
0.1 µF
GND
VDD
VFN
0 V
Max positive fault
VFP + 0.5 V
60 V/µs
ramp
60 V/µs
ramp
0.1 µF
GND
0.1 µF
GND
VS
VS
VFN - 0.5 V
tRESPONSE (FN)
VDD VSS
VFP VFN
0 V
Max negative fault
SW
SW
Sx
tRESPONSE (FP)
VFP
0 V
Output
(VD)
Output
(VD)
VS
Output × 50%
Output × 50%
Output
CL
D/ DX
All other
source
pins
VFN
tRESPONSE = max ( tRESPONSE(FP), tRESPONSE(FN)
0 V
GND
)
RL
SW
GND
GND
GND
图8-9. Fault Response Time Measurement Setup
8.9 Fault Recovery Time
Fault recovery time (tRECOVERY) measures the delay between the source voltage falling from overvoltage
condition to below fault supply voltage (VFP or VFN) plus 0.5 V and the drain voltage rising from 0 V to 50% of the
final output voltage. 图8-10 shows the setup used to measure tRECOVERY
.
VSS
VFP
0.1 µF
0.1 µF
GND
VDD
VFN
0 V
GND
VFP + 0.5 V
VFN - 0.5 V
0.1 µF
GND
0.1 µF
GND
VS
VS
VDD VSS
VFP VFN
0 V
tRECOVERY (FP)
tRECOVERY (FN)
SW
SW
Sx
0 V
Output
(VD)
VS
Output × 50%
Output
(VD)
Output × 50%
Output
CL
D/ DX
All other
source
pins
0 V
GND
tRECOVERY = max ( tRECOVERY(FP), tRECOVERY(FN)
)
RL
SW
GND
GND
GND
图8-10. Fault Recovery Time Measurement Setup
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8.10 Fault Flag Response Time
Fault flag response time (tRESPONSE(FLAG)) measures the delay between the source voltage exceeding the fault
supply voltage (VFP or VFN) by 0.5 V and the general fault flag (FF) pin or specific fault flag (SF) pin to go below
10% of its original value. 图8-11 shows the setup used to measure tRESPONSE(FLAG)
.
VSS
VFP
0.1 µF
0.1 µF
GND
VDD
VFN
GND
0.1 µF
0.1 µF
GND
0 V
VDD VSS
VFP VFN
VFP + 0.5 V
GND
VS
VS
SW
SW
Sx
VFN - 0.5 V
0 V
tRESPONSE(FLAG)_FP
5 V
tRESPONSE(FLAG)_FN
5 V
VS
Output
D/ DX
All other
source
pins
Output (VXF
)
Output (VXF
0 V
tRESPONSE(FLAG) = max ( tRESPONSE(FLAG)_FP, tRESPONSE(FLAG)_FN
)
GND
5 V
RL
CL
0.5 V
0.5 V
SW
0 V
RPU
GND
GND
)
GND
xF
CL_xF
GND
图8-11. Fault Flag Response Time Measurement Setup
8.11 Fault Flag Recovery Time
Fault flag recovery time (tRECOVERY(FLAG)) measures the delay between the source voltage falling from
overvoltage condition to below fault supply voltage (VFP or VFN) plus 0.5 V and the general fault flag (FF) pin or
the specific fault flag (SF) pin to rise above 3 V with 5 V external pull-up. 图 8-12 shows the setup used to
measure tRECOVERY(FLAG)
.
VSS
VFP
0.1 µF
GND
0.1 µF
GND
VDD
VFN
0 V
0.1 µF
GND
0.1 µF
GND
VDD VSS
VFP VFN
VFP + 0.5 V
VFN - 0.5 V
VS
SW
SW
Sx
0 V
tRECOVERY(FLAG)_FN
tRECOVERY(FLAG)_FP
VS
5 V
Output (VXF
5 V
Output
D/ DX
All other
source
pins
3 V
3 V
)
Output (VXF
)
GND
5V
0 V
0 V
RL
CL
SW
tRECOVERY(FLAG) = max ( tRECOVERY(FLAG)_FP, tRECOVERY(FLAG)_FN
)
RPU
GND
GND
GND
xF
CL_xF
GND
图8-12. Fault Flag Recovery Time Measurement Setup
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8.12 Charge Injection
Charge injection is a measure of the glitch impulse transferred from the logic input to the analog output during
switching, and is denoted by the symbol QINJ. 图 8-13 shows the setup used to measure charge injection from
the source to drain.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD VSS
VFP VFN
SW
SW
S1
S2
Output
VS
D
3 V
VEN
0 V
GND
CL
SW
S8
tr < 20 ns
tf < 20 ns
GND
GND
A0
A1
Output
VS
EN
VOUT
QINJ = CL ×
VOUT
Decoder
A2
VEN
GND
GND
GND
图8-13. Charge-Injection Measurement Setup
8.13 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. 图 8-14 shows the setup used to measure, and the equation used to calculate
off isolation.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD VSS
VFP VFN
Network Analyzer
VS
SW
SW
SX
50
Other
50
Sx Pins
SW
50
VOUT
50
D/ DX
VSIG
Ax, EN
VAX
VEN
GND
VOUT
Off Isolation = 20 x Log
VS
图8-14. Off Isolation Measurement Setup
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8.14 Crosstalk
There are two types of crosstalk that can be defined for the devices:
1. Intra-channel crosstalk (XTALK(INTRA)): 图8-15 shows the voltage at the source pin (Sx) of an off-switch input
when a signal is applied at the source pin of an on-switch input in the same channel.
2. Inter-channel crosstalk (XTALK(INTER)): 图8-16 shows the voltage at the source pin (Sx) of an on-switch input,
when a signal is applied at the source pin of an on-switch input in a different channel. Inter-channel crosstalk
applies only to the TMUX7349F device.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD VSS
VFP VFN
Network Analyzer
VOUT
GND
SW
S1/S1X
S2/S2X
D/ DX
SW
RS
RL
Other
Sx/ Dx
Pins
50
SW
VS
50
Ax, EN
GND
VAX
VEN
VOUT
Intra - channel Crosstalk = 20 x Log
VS
图8-15. Intra-Channel Crosstalk Measurement Setup
VDD
VSS
0.1 µF
GND
0.1 µF
VDD VSS
VFP VFN
Network Analyzer
GND
SW
SxA
DA
Other
SxA Pins
SW
RS
50
RL
SW
SW
VOUT
SxB
DB
Other
SxB Pins
50
VS
50
RL
Ax, EN
GND
VAX
VEN
VOUT
VS
Inter – channel Crosstalk = 20 x Log
图8-16. Inter-Channel Crosstalk Measurement Setup
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8.15 Bandwidth
Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to
the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D or Dx) of the TMUX7348F
and TMUX7349F. 图8-17 shows the setup used to measure bandwidth of the switch.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD VSS
VFP VFN
Network Analyzer
SW
SW
SX
50
50
Other
Sx/ Dx
Pins
RS
SW
VOUT
D/ DX
VS
50
Ax, EN
VAX
VEN
GND
VOUT
Bandwidth = 20 x Log
VS
图8-17. Bandwidth Measurement Setup
8.16 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the
multiplexer output. The on-resistance of the TMUX7348F and TMUX7349F varies with the amplitude of the input
signal and results in distortion when the drain pin is connected to a low-impedance load. Total harmonic
distortion plus noise is denoted as THD+N. 图8-18 shows the setup used to measure THD+N of the devices.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD VSS
VFP VFN
Audio Precision
SW
SW
SX
N.C.
N.C.
Other
Sx/ Dx
Pins
RS
SW
VOUT
D/ DX
VS
RL
Ax, EN
GND
VAX
VEN
图8-18. THD+N Measurement Setup
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9 Detailed Description
9.1 Overview
The TMUX7348F and TMUX7349F are a modern complementary metal-oxide semiconductor (CMOS) analog
multiplexers in 8:1 (single ended) and 4:1 (differential) configurations. The devices work well with dual supplies
(±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD = 15 V, VSS = –5 V). The
devices have an overvoltage protection feature on the source pins under powered and powered-off conditions,
allowing them to be used in harsh industrial environments.
9.2 Functional Block Diagram
VDD VSS
VFN VFP
VDD VSS
VFN VFP
SW
SW
SW
S1
S2
S1A
DA
DB
SW
SW
S4A
S1B
D
SW
SW
S4B
S8
A0
A1
A2
EN
A0
A1
EN
Fault Detec on/
Switch Driver/
Logic Decoder
Fault Detec on/
Switch Driver/
Logic Decoder
FF
SF
FF
SF
TMUX7348F
TMUX7349F
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9.3 Feature Description
9.3.1 Flat ON- Resistance
The TMUX7348F and TMUX7349F are designed with a special switch architecture to produce ultra-flat on-
resistance (RON) across most of the switch input operation region. The flat RON response allows the device to be
used in precision sensor applications since the RON is controlled regardless of the signals sampled. The
architecture is implemented without a charge pump so no unwanted noise is produced from the device to affect
sampling accuracy.
9.3.2 Protection Features
The TMUX7348F and TMUX7349F offer a number of protection features to enable robust system
implementations.
9.3.2.1 Input Voltage Tolerance
The maximum voltage that can be applied to any source input pin is +60 V or −60 V, regardless of the supply
voltage. This allows the device to handle typical voltage fault conditions in industrial applications. Take caution:
the device is rated to handle a maximum stress of 85 V across different pins, such as the following:
1. Between source pins and supply rails:
For example, if the device is powered by VDD supply of 20 V, then the maximum negative signal level on any
source pin is –60 V to maintain the 60 V maximum rating on any source pin. If the device is powered by
V
DD supply of 40 V, then the maximum negative signal level on any source pin is reduced to –45 V to
maintain the 85 V maximum rating across the source pin and the supply.
2. Between source pins and one or more of the drain pins:
For example, if channel S1(A) is ON and the voltage on S1(A) pin is 40 V. In this case, the drain voltage is
also 40 V. The maximum negative voltage on any of the other source pins is –45 V to maintain the 85 V
maximum rating across the source pin and the drain pin.
9.3.2.2 Powered-Off Protection
When the supplies of TMUX7348F and TMUX7349F are removed (VDD/ VSS = 0 V or floating), the source (Sx)
pins of the device remain in the high impedance (Hi-Z) state, and the source (Sx) and drain (Dx) pins of the
device remain within the leakage performance mentioned in the Electrical Characteristics. Powered-off
protection minimizes system complexity by removing the need to control the power supply sequencing of the
system. The feature prevents errant voltages on the input source pins from reaching the rest of the system and
maintains isolation when the system is powering up. Without powered-off protection, the signal on the input
source pins can back-power the supply rails through the internal ESD diodes and potentially cause damage to
the system. For more information on powered-off protection, refer to the Eliminate Power Sequencing with
Powered-Off Protection Signal Switches application brief.
The switch remains OFF regardless of whether the VDD and VSS supplies are 0 V or floating. A GND reference
must always be present to ensure proper operation. Source and drain voltage levels of up to ±60 V are blocked
in the powered-off condition.
9.3.2.3 Fail-Safe Logic
Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting
the device from potential damage. The switch is specified to be in the OFF state, regardless of the state of the
logic signals. The logic inputs are protected against positive faults of up to +44 V in the powered-off condition,
but do not offer protection against the negative overvoltage condition.
Fail-safe logic also allows the TMUX7348F and TMUX7349F devices to interface with a voltage greater than VDD
during normal operation to add maximum flexibility in system design. For example, with a VDD of = 15 V, the logic
control pins could be connected to +24 V for a logic high signal which allows different types of signals, such as
analog feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the
logic inputs can be interfaced as high as 44 V.
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9.3.2.4 Overvoltage Protection and Detection
The TMUX7348F and TMUX7349F detect overvoltage inputs by comparing the voltage on a source pin (Sx) with
the fault supplies (VFP and VFN). A signal is considered overvoltage if it exceeds the fault supply voltages by the
threshold voltage (VT).
When an overvoltage is detected, the switch automatically turns OFF regardless of the logic controls. The source
pin becomes high impedance and ensures only small leakage current flows through the switch and the
overvoltage does not appear on the drain. When the overvoltage channel is selected by the logic control, the
drain pin (D or Dx) is pulled to the supply that was exceeded. For example, if the source voltage exceeds VFP,
then the drain output is pulled to VFP. If the source voltage exceeds VFN, then the drain output is pulled to VFN
.
The pull-up impedance is approximately 40 kΩ, and as a result, the drain current is limited to roughly 1 mA
during a shorted load (to GND) condition.
图 9-1 shows a detailed view of how the pullup or down controls the output state of the drain pin under a fault
scenario.
VDD VSS
VFP
Ax
Sx
Logic &
Fault
Detection
40 kΩ
40 kΩ
Dx
ESD
Protection
VFN
GND
图9-1. Detailed Functional Diagram
VFP and VFN are required fault supplies that set the level at which the overvoltage protection is engaged. VFP can
be supplied from 3 V to VDD, while the VFN can be supplied from VSS to 0 V. If the fault supplies are not available
in the system, then the VFP pin must be connected to VDD, while the VFN pin must be connected to VSS. In this
case, overvoltage protection then engages at the primary supply voltages VDD and VSS
.
9.3.2.5 Adjacent Channel Operation During Fault
When the logic pins are set to a channel under a fault, the overvoltage detection will trigger, the switch will open,
and the drain pin will be pulled up or down as described in 节 9.3.2.4. During such an event, all other channels
not under a fault can continue to operate as normal. For example, if S1 voltage exceeds VFP, and the logic pins
are set to S1, the drain output is pulled to VFP. Then if the logic pins are changed to set S4, which is not in
overvoltage or undervoltage, the drain will disconnect from the pullup to VFP and the S4 switch will be enabled
and connected to the drain, operating as normal. If the logic pins are switched back to S1, the S4 switch will be
disabled, the drain pin will be pulled up to VFP again, and the switch from S1 to drain will not be enabled until the
overvoltage fault is removed.
9.3.2.6 ESD Protection
All pins on the TMUX7348F and TMUX7349F support HBM ESD protection level up to ±3.5 kV, which helps the
device from getting ESD damages during the manufacturing process.
The drain pins (D or Dx) have internal ESD protection diodes to the fault supplies VFP and VFN. Therefore, the
voltage at the drain pins must not exceed the fault supply voltages to prevent excessive diode current. The
source pins have specialized ESD protection that allows the signal voltage to reach ±60 V regardless of the
supply voltage level. Exceeding ±60 V on any source input may damage the ESD protection circuitry on the
device and cause the device to malfunction if the damage is excessive.
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9.3.2.7 Latch-Up Immunity
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the
low impedance path.
The TMUX7348F and TMUX7349F devices are constructed on silicon on insulator (SOI) based process where
an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic
structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up
events due to overvoltage or current injections. The latch-up immunity feature allows the TMUX7348F and
TMUX7349F to be used in harsh environments. For more information on latch-up immunity refer to the Using
Latch-Up Immune Multiplexers to Help Improve System Reliability application report.
9.3.2.8 EMC Protection
The TMUX7348F and TMUX7349F are not intended for standalone electromagnetic compatibility (EMC)
protection in industrial applications. There are three common high voltage transient specifications that govern
industrial high voltage transient specifications: IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and IEC61000-4-5
(surge immunity). A transient voltage suppressor (TVS), along with some low-value series current limiting
resistors, are required to prevent source input voltages from going above the rated ±60 V limits.
When selecting a TVS protection device, it is critical to ensure that the maximum working voltage is greater than
both the normal operating range of the input source pins to be protected and any known system common-mode
overvoltage that may be present due to incorrect wiring, loss of power, or short circuit. 图 9-2 shows an example
of the proper design window when selecting a TVS device.
Region 1 denotes the normal operation region of TMUX7348F and TMUX7349F where the input source voltages
stay below the fault supplies VFP and VFN. Region 2 represents the range of possible persistent DC (or long
duration AC overvoltage fault) presented on the source input pins. Region 3 represents the margin between any
known DC overvoltage level and the absolute maximum rating of the TMUX7348F and TMUX7349F. The TVS
breakdown voltage must be selected to be less than the absolute maximum rating of the TMUX7348F and
TMUX7349F, but greater than any known possible persistent DC or long duration AC overvoltage fault to avoid
triggering the TVS inadvertently. Region 4 represents the margin system designers must impose when selecting
the TVS protection device to prevent accidental triggering of ESD cells of the TMUX7348F and TMUX7349F
devices.
Internal ESD
Trigger Voltage
4
Device Absolute
Max Rating
TVS
Breakdown
Voltage
3
2
System
Overvoltage
Overvoltage
Protection Window
Fault Voltage
Supply VFP
0 V
1
Normal Operation
Fault Voltage
Supply VFN
2
3
4
System
Overvoltage
Overvoltage
Protection Window
TVS
Breakdown
Voltage
Device Absolute
Max Rating
Internal ESD
Trigger Voltage
图9-2. System Operation Regions and Proper Region of Selecting a TVS Protection Device
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9.3.3 Overvoltage Fault Flags
The voltages on the source input pins of the TMUX7348F and TMUX7349F are continuously monitored, and the
status of whether an overvoltage condition occurs is indicated by an active low general fault flag (FF). The
voltage on the FF pin indicates if any of the source input pins are experiencing an overvoltage condition. If any
source pin voltage exceeds the fault supply voltages by a VT, the FF output is pulled-down to below VOL
.
The specific fault (SF) output pins, on the other hand, can be used to decode which inputs are experiencing an
overvoltage condition. As provided in 表 9-1 and 表 9-2, the SF pin is pulled-down to below VOL when an
overvoltage condition is detected on a specific source input pin, depending on the state of the A0, A1, A2, and
EN logic pins.
Both the FF pin and SF pin are open-drain output and external pull-up resistors of 1 kΩ are recommended. The
pull-up voltage can be in the range of 1.8 V to 5.5 V, depending on the controller voltage the device interfaces
with.
9.3.4 Bidirectional and Rail-to-Rail Operation
The TMUX7348F and TMUX7349F conducts equally well from source (Sx) to drain (D or Dx) or from drain (D or
Dx) to source (Sx). Each signal path has very similar characteristics in both directions. It is important to note,
however, that the overvoltage protection is implemented only on the source (Sx) side. The voltage on the drain is
only allowed to swing between VFP and VFN and no overvoltage protection is available on the drain side.
The primary supplies (VDD and VSS) define the on-resistance profile of the switch channel, whereas the fault
voltage supplies (VFP and VFN) define the signal range that can be passed through from source to drain of the
device. It is good practice to use voltages on VFP and VFN that are lower than VDD and VSS to take advantage of
the flat on-resistance region of the device for better input-to-output linearity. The flatest on-resistance region
extends from VSS to roughly 3 V below VDD. Once the signal is within 3 V of VDD the on-resistance will
exponentially increase and may impact desired signal transmission.
9.3.5 1.8 V Logic Compatible Inputs
The TMUX7348F and TMUX7349F devices have 1.8 V logic compatible control for all logic control inputs. 1.8 V
logic level inputs allows the TMUX7348F and TMUX7349F to interface with processors that have lower logic I/O
rails and eliminates the need for an external translator, which saves both space and BOM cost. For more
information on 1.8 V logic implementations refer to Simplifying Design with 1.8 V Logic Muxes and Switches.
9.3.6 Integrated Pull-Down Resistor on Logic Pins
The TMUX7348F and TMUX7349F have internal weak pull-down resistors to GND to ensure the logic pins are
not left floating. The value of this pull-down resistor is approximately 4 MΩ, but is clamped to about 1 µA at
higher voltages. This feature integrates up to four external components and reduces system size and cost.
9.4 Device Functional Modes
The TMUX7348F and TMUX7349F offer two modes of operation (Normal mode and Fault mode) depending on
whether any of the input pins experience an overvoltage condition.
9.4.1 Normal Mode
In Normal mode operation, signals of up to VFP and VFN can be passed through the switch from source (Sx) to
drain (D or Dx) or from drain (D or Dx) to source (Sx). As provided in 表 9-1 and 表 9-2, the address (Ax) pins
and the enable (EN) pin determine which switch path to turn on. The following conditions must be satisfied for
the switch to stay in the ON condition:
• The difference between the primary supples (VDD –VSS) must be higher or equal to 8 V. With a minimum
VDD of 5 V.
• VFP must be between 3 V and VDD, and VFN must be between VSS and 0 V.
• The input signals on the source (Sx) or the drain (D or Dx) must be be between VFP+ VT and VFN –VT.
• The logic control (Ax and EN) must have selected the switch.
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9.4.2 Fault Mode
The TMUX7348F and TMUX7349F enters into Fault mode when any of the input signals on the source (Sx) pins
exceed VFP or VFN by a threshold voltage VT. Under the overvoltage condition, the switch input experiencing the
fault automatically turns OFF regardless of the logic status, and the source pin becomes high impedance with a
negligible amount of leakage current flowing through the switch. When the fault channel is selected by the logic
control, the drain pin (D or Dx) is pulled to the fault supply that was exceeded through a 40 kΩinternal resistor.
In the Fault mode, the general fault flag (FF) is asserted low. 表 9-1 and 表 9-2 provides how the specific flag
(SF) is asserted low when a specific input path is selected.
The overvoltage protection is provided only for the source (Sx) input pins. The drain (D or Dx) pin, if used as
signal input, must stay in between VFP and VFN at all time since no overvoltage protection is implemented on the
drain pin.
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9.4.3 Truth Tables
表9-1 shows the truth tables for the TMUX7348F under normal and fault conditions.
表9-1. TMUX7348F Truth Table
Fault Condition
State of Specific Flag (SF) when fault occurs on
Normal Condition
EN
A2
A1
A0
On Switch
None
None
None
None
None
None
None
None
S1
S1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
S2
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
S3
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
S4
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
S5
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
S6
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
S7
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
S8
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
S2
S3
S4
S5
S6
S7
S8
表9-2 shows the truth tables for the TMUX7349F under normal and fault conditions.
表9-2. TMUX7349F Truth Table
Fault Condition
Normal Condition
EN
A1
A0
State of Specific Flag (SF) when fault occurs on
On Switch
None
None
None
None
S1x
S1A
0
S2A
1
S3A
1
S4A
1
S1B
1
S2B
1
S3B
1
S4B
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
S2x
1
1
1
1
1
0
1
1
S3x
1
1
1
1
1
1
0
1
S4x
1
1
1
1
1
1
1
0
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The TMUX7348F and TMUX7349F are part of the fault protected switches and multiplexers family of devices.
The ability to protect downstream components from overvoltage events up to ±60 V makes these switches and
multiplexers suitable for harsh environments.
10.2 Typical Application
In analog input programmable logic controllers (PLC) a multiplexer is often used to switch multiple sensors to a
single ADC. By using a multiplexer, the number of components in the system can be reduced to save system
cost and size. In a PLC module a ±10 V input signal range is common for interfacing with external field
transmitters and sensors; however, there are a number of fault cases that may occur that can be damaging to
many of the integrated circuits. Such fault conditions may include, but are not limited to, human error from wiring
connections incorrectly, component failure or wire shorts, electromagnetic interference (EMI) or transient
disturbances, and so forth.
Supply
Power Module
GND
VDD VSS VFP VFN
PLC Analog
Input Module
Bridge Sensor
TMUX7348F
S1
5 V
S2
S3
S4
S5
S6
S7
S8
REF5025
Thermocouple
Current Sensing
D
Gain / Filter
Network
Fault
Protected
Mux Inputs
Signal
Processing
ISO77xx
ADS125H01
Photo
LED
A2
A1
V
Detector
A0
GND
1.8 V Logic
Signals
Op cal Sensor
Sensors
图10-1. Typical Application
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10.2.1 Design Requirements
表10-1. Design Parameters
PARAMETER
VALUE
+15 V
−15 V
+10 V
−10 V
Positive supply (VDD) mux
Negative supply (VSS) mux
Positive fault voltage supply (VFP) mux and ADC
Negative fault voltage supply (VFN) mux and ADC
Power board supply voltage
Input or output signal range non-faulted
Overvoltage protection levels
24 V
−10 V to 10 V
−60 V to 60 V
Control logic thresholds
Temperature range
1.8 V compatible, up to 44 V
−40°C to +125°C
10.2.2 Detailed Design Procedure
The previous image shows the case where an incorrect wiring condition occurred and one of the input
connectors shorted to the power board supply voltage. If the board supply voltage is higher than the fault voltage
supply of the multiplexer, then the TMUX7348F or TMUX7349F will disconnect the source input from passing the
signal to protect the downstream ADC. The drain pin of the mux will be pulled up to the fault voltage supply
voltage VFP through a 40 kΩresistor to allow the ADC to determine a fault condition has occurred.
10.2.3 Application Curves
The previous example shows how the fault protection of the TMUX7348F or TMUX7349F is utilized to protect
downstream components from damage due to wiring the connections incorrectly from the power module. 图10-2
shows an example of positive overvoltage fault response with a fast fault ramp rate of 58 V/µs. 图 10-3 shows
the extremely flat on-resistance across source voltage while operating within a common signal range of ±10 V.
These features make the TMUX7348F or TMUX7349F an ideal solution for factory automation applications that
can face various fault conditions but also require excellent linearity and low distortion.
240
230
220
210
200
190
180
170
160
25
22.5
20
VDD = 13.5 V, VSS = -13.5 V
VDD = 15 V, VSS = -15 V
VDD = 16.5 V, VSS = -16.5 V
VDD = 18 V, VSS = -18 V
VDD = 20 V, VSS = -20 V
VDD = 22 V, VSS = -22 V
SOURCE
VFP
50 V/s Fault Ramp
17.5
15
12.5
10
7.5
5
FF/SF
DRAIN
2.5
0
-2.5
-5
-10
-6
-2
2
6
10
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Time (s)
3
VS or VD - Source or Drain Voltage (V)
图10-3. RON Flatness in Non-Fault Region
图10-2. Positive Overvoltage Response
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11 Power Supply Recommendations
The TMUX7348F and TMUX7349F operate across a wide supply range of ±5 V to ±22 V (8 V to 44 V in single-
supply mode). They also perform well with asymmetrical supplies such as VDD = 12 V and VSS= –5 V. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 µF to 10 µF at both the VDD
and VSS pins to ground. Always ensure the ground (GND) connection is established before supplies are ramped.
The fault supplies (VFP and VFN) provide the current required to operate the fault protection, and thus, must be
low impedance supplies. They can be derived from the primary supplies by using a resistor divider and buffer or
be an independent supply rail. The fault supplies must not exceed the primary supplies as it might cause
unexpected behavior of the switch. Use a supply decoupling capacitor ranging from 0.1 µF to 10 µF at both the
VFP and VFN pins to ground for improved supply noise immunity.
The positive supply (VDD) must be ramped before the positive fault rail (VFP) for proper power sequencing of the
TMUX7348F and TMUX7349F. Similarly, the negative supply (VSS) must be ramped before the negative fault
voltage rail (VFN).
12 Layout
12.1 Layout Guidelines
The following images illustrate examples of a PCB layout with the TMUX7348F and TMUX7349F. Some key
considerations are as follows:
• For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and VSS to
GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as
possible. Make sure that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
• Multiple decoupling capacitors can be used if there is a lot of noise in the system. For example, a 0.1-µF and
1-µF can be placed on the supply pins. If multiple capacitors are used, then placing the lowest value
capacitor closest to the supply pin is recommended.
• Keep the input lines as short as possible.
• Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
12.2 Layout Example
A0
EN
VSS
Wide (low inductance)
trace for power
A1
A2
Wide (low inductance)
trace for power
C
C
GND
VDD
S1
S2
S3
S4
D
S5
S6
S7
S8
TMUX7348F
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
C
C
VFN
SF
VFP
FF
Via to ground plane
Via to signal plane
1 k
1 k
Wide (low inductance)
trace for power
图12-1. TMUX7348FPW Layout Example
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A0
EN
VSS
A1
Wide (low inductance)
C
Wide (low inductance)
trace for power
C
trace for power
GND
VDD
S1B
S1A
S2A
S3A
S4A
DA
S2B
S3B
S4B
DB
TMUX7349F
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
C
C
VFN
SF
VFP
FF
Via to ground plane
Via to signal plane
1 k
1 k
Wide (low inductance)
trace for power
图12-2. TMUX7349FPW Layout Example
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
VDD
S5
VSS
S1
Via to ground plane
Via to signal plane
S6
S2
S7
S3
S8
S4
Wide (low inductance)
trace for power
1 kΩ
1 kΩ
C
C
Wide (low inductance)
trace for power
图12-3. TMUX7348FQFN Layout Example
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Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
S1B
S2B
S3B
S4B
DB
VSS
S1A
S2A
S3A
S4A
Via to ground plane
Via to signal plane
Wide (low inductance)
trace for power
1 kΩ
1 kΩ
C
C
Wide (low inductance)
trace for power
图12-4. TMUX7349FQFN Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
• Texas Instruments, Eliminate Power Sequencing with Powered-Off Protection Signal Switches application
brief
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
• Texas Instruments, Improving Analog Input Modules Reliability Using Fault Protected Multiplexers application
report
• Texas Instruments, Multiplexers and Signal Switches Glossary application report
• Texas Instruments, Protection Against Overvoltage Events, Miswiring, and Common Mode Voltages
application report
• Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability application
report
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX7348FRTJR
ACTIVE
QFN
RTJ
20
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TMUX
7348F
Samples
TMUX7349FPWR
TMUX7349FRTJR
ACTIVE
ACTIVE
TSSOP
QFN
PW
20
20
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
TM7349F
Samples
Samples
RTJ
TMUX
7349F
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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21-Jul-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX7348FRTJR
TMUX7349FPWR
TMUX7349FRTJR
QFN
TSSOP
QFN
RTJ
PW
RTJ
20
20
20
3000
2000
3000
330.0
330.0
330.0
12.4
16.4
12.4
4.25
6.95
4.25
4.25
7.1
1.15
1.6
8.0
8.0
8.0
12.0
16.0
12.0
Q2
Q1
Q2
4.25
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX7348FRTJR
TMUX7349FPWR
TMUX7349FRTJR
QFN
TSSOP
QFN
RTJ
PW
RTJ
20
20
20
3000
2000
3000
367.0
356.0
367.0
367.0
356.0
367.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RTJ 20
4 x 4, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224842/A
www.ti.com
DATA BOOK
PACKAGE OUTLINE
LEADFRAME EXAMPLE
4222370
DRAFTSMAN:
DATE:
DATE:
DATE:
DATE:
DATE:
DATE:
DATE:
H. DENG
09/12/2016
09/12/2016
09/12/2016
DESIGNER:
CHECKER:
ENGINEER:
APPROVED:
RELEASED:
CODE IDENTITY
NUMBER
H. DENG
01295
SEMICONDUCTOR OPERATIONS
V. PAKU & T. LEQUANG
T. TANG
ePOD, RTJ0020D / WQFN,
20 PIN, 0.5 MM PITCH
09/12/2016
10/06/2016
10/24/2016
E. REY & D. CHIN
WDM
SCALE
SIZE
REV
PAGE
OF
TEMPLATE INFO:
4219125
A
15X
04/07/2016
A
EDGE# 4218519
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RTJ0020D
A
4.1
3.9
B
PIN 1 INDEX AREA
4.1
3.9
DIM A
OPT 1
(0.1)
OPT 2
(0.2)
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
16X 0.5
(A) TYP
6
10
EXPOSED
THERMAL PAD
5
11
SYMM
ꢀꢁꢂꢃꢁꢄ
4X 2
21
15
1
0.5
0.3
20X
PIN 1 ID
(OPTIONAL)
20
16
SYMM
0.29
0.19
0.1
20X
C A B
C
0.05
4219125 / A 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
RTJ0020D
PLASTIC QUAD FLATPACK - NO LEAD
2.7)
SYMM
20
16
20X (0.6)
1
20X (0.24)
15
(1.1)
TYP
21
SYMM
(3.8)
(0.5)
TYP
ꢅꢃꢁꢀꢆꢇ7<3
VIA
5
11
(R0.05)
TYP
6
10
(3.8)
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219125 / A 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their
locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
RTJ0020D
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.69)
TYP
20
16
20X (0.6)
1
20X (0.24)
15
(0.69)
TYP
SYMM
(3.8)
(0.5)
TYP
5
11
(R0.05)
TYP
21
6
10
4X ( 1.19)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219125 / A 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
R E V I S I O N S
REV
A
DESCRIPTION
ECR
DATE
ENGINEER / DRAFTSMAN
T. TANG / H. DENG
RELEASE NEW DRAWING
2160736
10/24/2016
SCALE
SIZE
REV
PAGE
4219125
5 OF 5
A
NTS
A
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Copyright © 2023，德州仪器 (TI) 公司
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