TMUX7411FRRPR [TI]
具有 1.8V 逻辑电平的 ±60V 故障保护、1:1 (SPST) 四通道开关（四个低电平有效） | RRP | 16 | -40 to 125;
| 型号： | TMUX7411FRRPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1.8V 逻辑电平的 ±60V 故障保护、1:1 (SPST) 四通道开关（四个低电平有效） | RRP | 16 | -40 to 125 开关 |
| 文件： | 总42页 (文件大小：2368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUX7411F, TMUX7412F, TMUX7413F
SCDS404A – MARCH 2021 – REVISED NOVEMBER 2021
TMUX741xF ±60 V Fault-Protected, 1:1 (SPST), 4-Channel Switches
with Latch-Up Immunity and 1.8-V Logic
1 Features
3 Description
•
Wide supply voltage range:
The TMUX7411F, TMUX7412F, and TMUX7413F
are complementary metal-oxide semiconductor
(CMOS) analog switches in 1:1 (SPST), 4-channel
configurations. The devices work well with dual
supplies (±5 V to ±22 V), a single supply (8 V to
44 V), or asymmetric supplies (such as VDD = 12 V,
VSS = –5 V). The overvoltage protection is available
in powered and powered-off conditions, making
the TMUX741xF devices suitable for applications
where power supply sequencing cannot be precisely
controlled.
– Single supply: 8 V to 44 V
– Dual supply: ±5 V to ±22 V
Integrated fault protection:
– Overvoltage protection, source to supplies or
source to drain: ±85 V
– Overvoltage protection: ±60 V
– Powered-off protection: ±60 V
– Interrupt flags to indicate fault status
– Output open circuited during fault
Latch-up immunity by device construction
6 kV human body model (HBM) ESD rating
Low On-Resistance: 8.3 Ω typical
Flat On-Resistance: 10 mΩ typical
1.8-V Logic capable
•
•
•
•
•
•
•
•
The devices block fault voltages up to +60 V or
−60 V relative to ground in powered and powered-off
conditions. When no power supplies are present the
switch channels remain in the OFF state regardless of
switch input conditions, and any control signal present
on the logic pins is ignored. If the signal path input
voltage on any Sx pin exceeds the supply voltage
(VDD or VSS) by a threshold voltage (VT), the channel
turns OFF and the Sx pin becomes high impedance.
The drain pin (Dx) of a selected channel under a fault
condition is floating. The TMUX741xF devices provide
an active-low interrupt flag (FF) to indicate if any of
the source inputs are experiencing a fault condition to
help system diagnostics.
Failsafe logic: up to 44 V independent of supply
Industry-standard TSSOP and smaller WQFN
packages
2 Applications
•
•
•
•
•
•
•
Factory automation and control
Programmable logic controllers (PLC)
Analog input modules
Semiconductor test equipment
Battery test equipment
Servo drive control module
Data acquisition systems (DAQ)
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TMUX7411F
TMUX7412F
TMUX7413F
TSSOP (16) (2)
5.00 mm × 4.40 mm
WQFN (16)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Preview package.
VDD
VSS
VDD
VSS
VDD
VSS
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
Fault Detection/
Switch Driver/
Logic Decoder
Fault Detection/
Switch Driver/
Logic Decoder
Fault Detection/
Switch Driver/
Logic Decoder
FF
FF
FF
TMUX7411F
TMUX7412F
TMUX7413F
(SELx = Logic 1)
(SELx = Logic 1)
(SELx = Logic 1)
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX7411F, TMUX7412F, TMUX7413F
SCDS404A – MARCH 2021 – REVISED NOVEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Thermal Information....................................................5
7.4 Recommended Operating Conditions.........................5
7.5 Electrical Characteristics: Global................................ 6
7.6 ±15 V Dual Supply: Electrical Characteristics.............7
7.7 ±20 V Dual Supply: Electrical Characteristics.............9
7.8 12 V Single Supply: Electrical Characteristics.......... 11
7.9 36 V Single Supply: Electrical Characteristics.......... 13
7.10 Typical Characteristics............................................15
8 Parameter Measurement Information..........................22
8.1 On-Resistance.......................................................... 22
8.2 Turn-On and Turn-Off Time.......................................22
8.3 Off-Leakage Current................................................. 23
8.4 On-Leakage Current................................................. 23
8.5 Input and Output Leakage Current Under
8.9 Fault Flag Recovery Time.........................................26
8.10 Charge Injection......................................................27
8.11 Off Isolation............................................................. 27
8.12 Inter-Channel Crosstalk.......................................... 28
8.13 Bandwidth............................................................... 28
8.14 THD + Noise........................................................... 29
9 Detailed Description......................................................30
9.1 Overview...................................................................30
9.2 Functional Block Diagram.........................................30
9.3 Feature Description...................................................30
9.4 Device Functional Modes..........................................33
10 Application and Implementation................................35
10.1 Application Information........................................... 35
10.2 Typical Application.................................................. 35
11 Power Supply Recommendations..............................37
12 Layout...........................................................................37
12.1 Layout Guidelines................................................... 37
12.2 Layout Example...................................................... 37
13 Device and Documentation Support..........................38
13.1 Documentation Support.......................................... 38
13.2 Receiving Notification of Documentation Updates..38
13.3 Support Resources................................................. 38
13.4 Trademarks.............................................................38
13.5 Electrostatic Discharge Caution..............................38
13.6 Glossary..................................................................38
14 Mechanical, Packaging, and Orderable
Overvoltage Fault........................................................24
8.6 Fault Response Time................................................25
8.7 Fault Recovery Time.................................................25
8.8 Fault Flag Response Time........................................26
Information.................................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (March 2021) to Revision A (November 2021)
Page
•
Changed the status of the data sheet from: Advanced Information to: Production Data ...................................1
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SCDS404A – MARCH 2021 – REVISED NOVEMBER 2021
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5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX7411F
TMUX7412F
TMUX7413F
±60 V Fault-protected, Latch-up Immune, Quad SPST Switch (Logic Low)
±60 V Fault-protected, Latch-up Immune, Quad SPST Switch (Logic High)
±60 V Fault-protected, Latch-up Immune, Quad SPST Switch (Logic Low + Logic High)
6 Pin Configuration and Functions
SEL1
D1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL2
D2
S1
S2
S1
VSS
GND
S4
1
2
3
4
12
11
10
9
S2
VSS
GND
S4
VDD
FF
VDD
FF
Thermal
Pad
S3
S3
D4
D3
SEL4
SEL3
Not to scale
Not to scale
Figure 6-2. RRP Package
16-Pin WQFN, Top View
Figure 6-1. (Preview) PW Package
16-Pin TSSOP, Top View
Table 6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
D1
TSSOP(2)
WQFN
2
15
10
7
16
13
8
I/O
I/O
I/O
I/O
Drain pin 1. Can be an input or output. The drain pin is not overvoltage protected.
Drain pin 2. Can be an input or output. The drain pin is not overvoltage protected.
Drain pin 3. Can be an input or output. The drain pin is not overvoltage protected.
Drain pin 4. Can be an input or output. The drain pin is not overvoltage protected.
D2
D3
D4
5
General fault flag. This pin is an open drain output and is asserted low when overvoltage
condition is detected on any of the source (Sx) input pins. Connect this pin to an external
supply (1.8 V to 5.5 V) through a 1 kΩ pull-up resistor.
FF
12
10
O
GND
S1
5
3
3
1
P
I/O
I/O
I/O
I/O
I
Ground (0 V) reference
Overvoltage protected source pin 1. Can be an input or output.
Overvoltage protected source pin 2. Can be an input or output.
Overvoltage protected source pin 3. Can be an input or output.
Overvoltage protected source pin 4. Can be an input or output.
Logic control input 1.
S2
14
11
6
12
9
S3
S4
4
SEL1
SEL2
SEL3
SEL4
1
15
14
7
16
9
I
Logic control input 2.
I
Logic control input 3.
8
6
I
Logic control input 4.
Positive power supply. This pin is the most positive power-supply potential. Connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND for reliable
operation.
VDD
13
11
2
P
Negative power supply. This pin is the most negative power-supply potential. This pin can be
connected to ground in single-supply applications. Connect a decoupling capacitor ranging
from 0.1 µF to 10 µF between VSS and GND for reliable operation.
VSS
4
P
The thermal pad is not connected internally. It is recommended that the pad be tied to GND or
VSS for best performance.
Thermal Pad
—
(1) I = input, O = output, I/O = input and output, P = power.
(2) Preview package.
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SCDS404A – MARCH 2021 – REVISED NOVEMBER 2021
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
48
UNIT
V
VDD to VSS
VDD to GND
VSS to GND
VS to GND
VS to VDD
VS to VSS
VD
Supply voltage
–0.3
–48
–65
–90
48
V
0.3
65
V
Source input pin (Sx) voltage to GND
Source input pin (Sx) voltage to VDD
Source input pin (Sx) voltage to VSS
Drain pin (Dx) voltage
V
V
90
V
VSS–0.7
GND –0.7
GND –0.7
–30
VDD+0.7
V
VSEL
Logic control input pin voltage (SELx)(2)
Logic output pin voltage (FF)(2)
Logic control input pin current (SELx)(2)
Logic output pin current (FF)(2)
Source or drain continuous current (Sx or Dx)
Storage temperature
48
V
VFF
6
V
ISEL
30
mA
mA
mA
°C
°C
°C
mW
IFF
–10
10
IDC ± 10 %(3)
150
IS or ID (CONT)
Tstg
IDC ± 10 %(3)
–65
TA
Ambient temperature
–55
150
TJ
Junction temperature
150
(4)
Ptot
Total power dissipation (QFN)
1600
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) Stresses have to be kept at or below both voltage and current ratings at all time.
(3) Refer to Recommended Operating Conditions for IDC ratings.
(4) For QFN package: Ptot derates linearly above TA = 70°C by 23.5 mW/°C
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±6000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all
pins(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Thermal Information
TMUX7411F/ TMUX7412F/
TMUX7413F
THERMAL METRIC(1)
UNIT
PW (TSSOP)
RRP (WQFN)
16 PINS
42.8
16 PINS
TBD
TBD
TBD
TBD
TBD
N/A
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
28.5
17.9
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJB
17.9
RθJC(bot)
4.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
8
NOM
MAX UNIT
(1)
VDD – VSS
VDD
Power supply voltage differential
44
V
44
Positive power supply voltage
5
VS
Source pin (Sx) voltage (non-fault condition)
Source pin (Sx) voltage to GND (fault condition)
Source pin (Sx) voltage to VDD or VD (fault condition)
Source pin (Sx) voltage to VSS or VD (fault condition)
Drain pin (Dx) voltage
VSS
–60
–85
VDD
60
VS to GND
(2)
VS to VDD
VS to VSS
VD
V
(2)
85
VSS
GND
GND
–40
VDD
VSEL
Logic control input pin voltage (SELx)
Logic output pin voltage (FF)
44
V
5.5
(3)
VFF
TA
Ambient temperature
125
150
°C
TA = 25°C
TA = 85°C
TA = 125°C
IDC
Continuous current through switch, WQFN package
100 mA
60
(1) VDD and VSS can be any value as long as 8 V ≤ (VDD – VSS) ≤ 44 V, and the minimum VDD is met.
(2) Source pin voltage (Sx) under a fault condition may not exceed 85 V from supply pins (VDD and VSS.) or drain pins (D, Dx).
(3) Logic output pin (FF) is an open drain output and should be pulled up to a voltage within the max ratings
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7.5 Electrical Characteristics: Global
at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG SWITCH
VT
Threshold voltage for fault detector
25°C
0.7
V
LOGIC INPUT/ OUTPUT
VIH
High-level input voltage
SELx pins
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
1.3
0
44
0.8
3
V
V
VIL
Low-level input voltage
High-level input current
Low-level input current
Low-level output voltage
SELx pins
IIH
VSELx = VDD
VSELx = 0 V
FF pin, IO = 5 mA
0.4
µA
µA
V
IIL
–1 –0.65
VOL(FLAG)
0.35
POWER SUPPLY
Rising edge, single supply
Falling edge, single supply
–40°C to +125°C
–40°C to +125°C
5.1
5
5.8
5.7
6.4
6.3
V
V
Undervoltage lockout (UVLO)
VUVLO
threshold voltage (VDD – VSS
)
VDD Undervoltage
lockout (UVLO) hysteresis
VHYS
Single supply
–40°C to +125°C
0.2
V
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7.6 ±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
8.3
11
VS = –10 V to +10 V
ID = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
14
16.5
0.45
0.5
Ω
Ω
0.06
0.01
On-resistance mismatch between VS = –10 V to +10 V
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
channels
ID = –10 mA
0.6
0.4
VS = –10 V to +10 V
ID = –10 mA
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
0.4
Ω
0.4
RON_DRIFT
VS = 0 V, IS = –10 mA
0.04
0.03
Ω/°C
nA
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
–0.7
–2
0.7
2
IS(OFF)
Input leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
VD = –10 V / + 10 V
–10
–0.7
–2
10
0.7
2
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
0.03
0.5
ID(OFF)
Output off leakage current(1)
Output on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
nA
nA
VD = –10 V / + 10 V
–12
–0.7
–2
12
0.7
2
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
–15
15
FAULT CONDITION
Input leakage current
durring overvoltage
VS = ± 60 V, GND = 0 V,
VDD = 16.5 V, VSS = –16.5 V
IS(FA)
–40°C to +125°C
–40°C to +125°C
±100
±125
µA
µA
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V
VDD = VSS = 0 V
IS(FA) Grounded
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
IS(FA) Floating
–40°C to +125°C
±125
±0.1
µA
nA
25°C
–20
–30
–60
20
30
60
30
50
90
Output leakage current
during overvoltage
VS = ± 60 V, GND = 0 V,
VDD = 16.5 V, VSS = –16.5 V
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
–30 ±0.01
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = 0 V
ID(FA) Grounded
–40°C to +85°C
–40°C to +125°C
25°C
–50
–90
±2
nA
µA
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
±3
±4
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7.6 ±15 V Dual Supply: Electrical Characteristics (continued)
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
480
680
VS = 10 V,
RL = 300 Ω, CL= 12 pF
tON
Turn-on time
–40°C to +85°C
–40°C to +125°C
25°C
710
710
ns
ns
ns
50
100
100
VS = 10 V,
RL = 300 Ω, CL= 12 pF
tOFF
Turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
120
150
350
tRESPONSE
Fault response time
Fault recovery time
RL = 300 Ω, CL= 12 pF
RL = 300 Ω, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
380
400
1600
4500
4800
4800
tRECOVERY
–40°C to +85°C
–40°C to +125°C
ns
ns
RL = 300 Ω, CL= 12 pF,
RPU = 1k Ω, CL_FF = 12 pF
tRESPONSE(FLAG) Fault flag response time
tRECOVERY(FLAG) Fault flag recovery time
25°C
180
RL = 300 Ω, CL= 12 pF,
RPU = 1k Ω, CL_FF = 12 pF
25°C
25°C
25°C
1.2
–300
–60
µs
pC
dB
QJ
Charge injection
Off-isolation
VS = 0 V, CL = 1 nF
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
OISO
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
XTALK
BW
Crosstalk
25°C
25°C
25°C
–100
650
dB
MHz
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
–3 dB bandwidth
Insertion loss
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
ILOSS
–0.7
RS = 50 Ω, RL = 10 kΩ,
VS = 15 VPP, VBIAS = 0 V,
f = 20 Hz to 20k Hz
Total harmonic distortion plus
noise
THD+N
25°C
0.0006
%
CS(OFF)
CD(OFF)
Input off-capacitance
Output off-capacitance
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
25°C
25°C
10
12
pF
pF
CS(ON)
CD(ON)
Input/Output on-capacitance
f = 1 MHz, VS = 0 V
25°C
14
pF
POWER SUPPLY
25°C
0.32
0.5
0.5
0.6
0.4
0.4
0.5
VDD = 16.5 V, VSS = –16.5 V,
VSELx = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
mA
0.26
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
mA
VDD = 16.5 V, VSS = –16.5 V,
VSELx = 0 V, 5 V, or VDD
IGND
GND current
0.06
0.27
25°C
0.5
0.5
0.6
0.3
0.3
0.4
VS = ± 60 V,
VDD = 16.5 V, VSS = –16.5 V,
VSELx = 0 V, 5 V, or VDD
IDD(FA)
VDD supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
0.2
VS = ± 60 V,
VDD = 16.5 V, VSS = –16.5 V,
VSELx = 0 V, 5 V, or VDD
ISS(FA)
VSS supply current under fault
GND current under fault
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
IGND(FA)
0.15
(1) When VS is positive,VD is negative. And when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.7 ±20 V Dual Supply: Electrical Characteristics
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
8.3
11
VS = –15 V to +15 V
ID = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
14
17
Ω
Ω
0.06
0.35
0.5
0.5
0.4
0.5
0.5
On-resistance mismatch between VS = –15 V to +15 V
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
channels
ID = –10 mA
0.015
VS = –15 V to +15 V
ID = –10 mA
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
RON_DRIFT
VS = 0 V, IS = –10 mA
0.04
0.03
Ω/°C
nA
VDD = 22 V, VSS = –22 V
Switch state is off
VS = +15 V / –15 V
VD = –15 V / + 15 V
–0.7
–2
0.7
2
IS(OFF)
Input leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
–10
–0.7
–2
10
0.7
2
VDD = 22 V, VSS = –22 V
Switch state is off
VS = +15 V / –15 V
VD = –15 V / + 15 V
0.03
0.05
ID(OFF)
Output off leakage current(1)
Output on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
nA
nA
–12
–0.7
–2
12
0.7
2
VDD = 22 V, VSS = –22 V
Switch state is on
VS = VD = ±15 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
–15
15
FAULT CONDITION
Input leakage current
durring overvoltage
VS = ± 60 V, GND = 0 V,
VDD = 22 V, VSS = –22 V
IS(FA)
–40°C to +125°C
–40°C to +125°C
±85
µA
µA
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = 0 V
IS(FA) Grounded
±125
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
IS(FA) Floating
–40°C to +125°C
±125
±5
µA
nA
25°C
–50
–70
–90
–30
–50
–90
50
70
90
30
50
90
Output leakage current
during overvoltage
VS = ± 60 V, GND = 0 V,
VDD = 22 V, VSS = –22 V,
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
±10
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = 0 V
ID(FA) Grounded
–40°C to +85°C
–40°C to +125°C
25°C
nA
µA
±2
±3
±4
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
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7.7 ±20 V Dual Supply: Electrical Characteristics (continued)
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
510
740
VS = 10 V,
RL = 300 Ω, CL= 12 pF
tON
Turn-on time
–40°C to +85°C
–40°C to +125°C
25°C
780
780
ns
ns
ns
50
150
100
VS = 10 V,
RL = 300 Ω, CL= 12 pF
tOFF
Turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
120
150
400
tRESPONSE
Fault response time
Fault recovery time
RL = 300 Ω, CL= 12 pF
RL = 300 Ω, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
430
450
1100
4500
4900
4900
tRECOVERY
–40°C to +85°C
–40°C to +125°C
ns
ns
RL = 300 Ω, CL= 12 pF,
RPU = 1k Ω, CL_FF = 12 pF
tRESPONSE(FLAG) Fault flag response time
tRECOVERY(FLAG) Fault flag recovery time
25°C
200
RL = 300 Ω, CL= 12 pF,
RPU = 1k Ω, CL_FF = 12 pF
25°C
25°C
25°C
0.9
–330
–60
µs
pC
dB
QJ
Charge injection
Off-isolation
VS = 0 V, CL = 1 nF
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
OISO
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
XTALK
BW
Inter-channel crosstalk
–3 dB bandwidth
Insertion loss
25°C
25°C
25°C
–100
650
dB
MHz
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
ILOSS
–0.7
RS = 50 Ω, RL = 10 kΩ,
VS = 20 VPP, VBIAS = 0 V,
f = 20 Hz to 20k Hz
Total harmonic distortion plus
noise
THD+N
25°C
0.0006
%
CS(OFF)
CD(OFF)
Input off-capacitance
Output off-capacitance
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
25°C
25°C
10
12
pF
pF
CS(ON)
CD(ON)
Input/Output on-capacitance
f = 1 MHz, VS = 0 V
25°C
14
pF
POWER SUPPLY
25°C
0.32
0.5
0.5
0.6
0.4
0.4
0.5
VDD = 22 V, VSS = –22 V,
VSELx = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
mA
0.26
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
mA
VDD = 22 V, VSS = –22 V,
VSELx = 0 V, 5 V, or VDD
IGND
GND current
0.06
0.27
25°C
0.5
0.5
0.6
0.3
0.3
0.4
VS = ± 60 V,
VDD = 22 V, VSS = –22 V,
VSELx = 0 V, 5 V, or VDD
IDD(FA)
VDD supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
0.2
VS = ± 60 V,
VDD = 22 V, VSS = –22 V,
VSELx = 0 V, 5 V, or VDD
ISS(FA)
VSS supply current under fault
GND current under fault
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
IGND(FA)
0.15
(1) When VS is positive,VD is negative. And when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.8 12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
8.3
11
VS = 0 V to 7.8 V,
IS = –10mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
15
18
Ω
Ω
0.06
0.06
0.5
0.6
0.7
0.4
0.5
0.5
On-resistance mismatch between VS = 0 V to 7.8 V,
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
channels
IS = –10mA
VS = 0 V to 7.8 V,
IS = –10mA
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
RON_DRIFT
VS = 6 V, IS = –10 mA
0.04
0.03
Ω/°C
nA
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
–0.7
–2
0.7
2
IS(OFF)
Input leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
VD = 1 V / 10 V
–10
–0.7
–2
10
0.7
2
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
0.03
0.05
ID(OFF)
Output off leakage current(1)
Output on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
nA
nA
VD = 1 V / 10 V
–12
–0.7
–2
12
0.7
2
VDD = 13.2 V, VSS = 0 V
Switch state is on
VS = VD = 10 V or 1 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
–14
14
FAULT CONDITION
Input leakage current
durring overvoltage
VS = ± 60 V, GND = 0 V,
VDD = 13.2 V, VSS = 0 V
IS(FA)
–40°C to +125°C
–40°C to +125°C
±130
±125
µA
µA
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = 0 V
IS(FA) Grounded
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
IS(FA) Floating
–40°C to +125°C
±125
±2
µA
nA
25°C
–20
–30
–50
–30
–50
–90
20
30
50
30
50
90
Output leakage current
during overvoltage
VS = ± 60 V, GND = 0 V,
VDD = 13.2 V, VSS = 0 V
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
±10
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = 0 V
ID(FA) Grounded
–40°C to +85°C
–40°C to +125°C
25°C
nA
µA
±2
±3
±4
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
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7.8 12 V Single Supply: Electrical Characteristics (continued)
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
410
660
VS = 8 V,
RL = 300 Ω, CL= 12 pF
tON
Turn-on time
–40°C to +85°C
–40°C to +125°C
25°C
750
750
ns
ns
ns
85
500
850
200
VS = 8 V,
RL = 300 Ω, CL= 12 pF
tOFF
Turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
210
210
600
tRESPONSE
Fault response time
Fault recovery time
RL = 300 Ω, CL= 12 pF
RL = 300 Ω, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
650
700
2400
2900
2900
tRECOVERY
–40°C to +85°C
–40°C to +125°C
ns
ns
RL = 300 Ω, CL= 12 pF,
RPU = 1k Ω, CL_FF = 12 pF
tRESPONSE(FLAG) Fault flag response time
tRECOVERY(FLAG) Fault flag recovery time
25°C
105
RL = 300 Ω, CL= 12 pF,
RPU = 1k Ω, CL_FF = 12 pF
25°C
25°C
25°C
0.8
–230
–53
µs
pC
dB
QJ
Charge injection
Off-isolation
VS = 6 V, CL = 1 nF
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
OISO
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
XTALK
BW
Crosstalk
25°C
25°C
25°C
–100
620
dB
MHz
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
–3 dB bandwidth
Insertion loss
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
ILOSS
–0.7
RS = 50 Ω, RL = 10k Ω,
VS = 6 VPP, VBIAS = 6 V,
f = 20Hz to 20 kHz
Total harmonic distortion plus
noise
THD+N
25°C
0.0007
%
CS(OFF)
CD(OFF)
Input off-capacitance
Output off-capacitance
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
25°C
25°C
11
13
pF
pF
CS(ON)
CD(ON)
Input/Output on-capacitance
f = 1 MHz, VS = 6 V
25°C
16
pF
POWER SUPPLY
25°C
0.3
0.5
0.5
0.6
mA
VDD = 13.2 V, VSS = 0 V,
VSELx = 0 V, 5 V, or VDD
IDD
VDD supply current
GND current
–40°C to +85°C
–40°C to +125°C
mA
mA
VDD = 13.2 V, VSS = 0 V,
VSELx = 0 V, 5 V, or VDD
IGND
25°C
0.06
0.25
25°C
0.5
0.5
0.6
VS = ± 60 V,
VDD = 13.2 V, VSS = 0 V,
VSELx = 0 V, 5 V, or VDD
IDD(FA)
VDD supply current under fault
GND current under fault
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
IGND(FA)
0.15
(1) When VS is 10 V, VD is 1 V. Or when VS is 1 V, VD is 10 V.
(2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.9 36 V Single Supply: Electrical Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
8.3
11
VS = 0 V to 30 V,
IS = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
14
17
Ω
Ω
0.06
0.07
0.5
0.6
0.7
0.4
0.5
0.5
On-resistance mismatch between VS = 0 V to 30 V,
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
channels
IS = –10 mA
VS = 0 V to 30 V,
IS = –10 mA
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
RON_DRIFT
VS = 18 V, IS = –1 mA
0.04
0.05
Ω/°C
nA
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
–0.7
–2
0.7
2
IS(OFF)
Input leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
VD = 1 V / 30 V
–10
–0.7
–2
10
0.7
2
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
0.05
0.1
ID(OFF)
Output off leakage current(1)
Output on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
nA
nA
VD = 1 V / 30 V
–12
–0.7
–2
12
0.7
2
VDD = 39.6 V, VSS = 0 V
Switch state is on
VS = VD = 30 V or 1 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
–15
15
FAULT CONDITION
Input leakage current
durring overvoltage
VS = 60 / –40 V,
VDD = 39.6 V, VSS = 0 V, GND = 0 V
IS(FA)
–40°C to +125°C
–40°C to +125°C
±90
µA
µA
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V,
VDD = VSS = 0 V, GND = 0 V
IS(FA) Grounded
±125
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V,
VDD = VSS = floating, GND = 0 V,
IS(FA) Floating
–40°C to +125°C
±125
±2
µA
nA
25°C
–20
–30
–60
–30
–50
–90
20
30
60
30
50
90
Output leakage current
during overvoltage
VS = 60 / –40 V,
VDD = 39.6 V, VSS = 0, GND = 0V
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
±10
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = 0 V
ID(FA) Grounded
–40°C to +85°C
–40°C to +125°C
25°C
nA
µA
±2
±3
±4
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
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7.9 36 V Single Supply: Electrical Characteristics (continued)
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
450
750
VS = 18 V,
RL = 300 Ω, CL= 12 pF
tON
Turn-on time
–40°C to +85°C
–40°C to +125°C
25°C
830
930
ns
ns
ns
100
150
210
VS = 18 V,
RL = 300 Ω, CL= 12 pF
tOFF
Turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
230
230
310
tRESPONSE
Fault response time
Fault recovery time
RL = 300 Ω, CL= 12 pF
RL = 300 Ω, CL= 12 pF
–40°C to +85°C
–40°C to +125°C
25°C
330
350
1100
2200
2700
2700
tRECOVERY
–40°C to +85°C
–40°C to +125°C
ns
ns
RL = 300 Ω, CL= 12 pF,
RPU = 1k Ω, CL_FF = 12 pF
tRESPONSE(FLAG) Fault flag response time
tRECOVERY(FLAG) Fault flag recovery time
25°C
120
RL = 300 Ω, CL= 12 pF,
RPU = 1k Ω, CL_FF = 12 pF
25°C
25°C
25°C
0.6
–330
–53
µs
pC
dB
QJ
Charge injection
Off-isolation
VS = 18 V, CL = 1 nF
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
OISO
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
XTALK
BW
Crosstalk
25°C
25°C
25°C
–100
650
dB
MHz
dB
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V
–3 dB bandwidth
Insertion loss
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 6 V, f = 1 MHz
ILOSS
–0.7
RS = 50 Ω, RL = 10k Ω,
VS = 18 VPP, VBIAS = 18 V,
f = 20Hz to 20 kHz
Total harmonic distortion plus
noise
THD+N
25°C
0.0006
%
CS(OFF)
CD(OFF)
Input off-capacitance
Output off-capacitance
f = 1 MHz, VS = 18 V
f = 1 MHz, VS = 18 V
25°C
25°C
12
14
pF
pF
CS(ON)
CD(ON)
Input/Output on-capacitance
f = 1 MHz, VS = 18 V
25°C
16
pF
POWER SUPPLY
25°C
0.3
0.5
0.5
0.6
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
mA
mA
VDD = 39.6 V, VSS = 0 V,
VSELx = 0 V, 5 V, or VDD
IGND
GND current
0.06
0.25
25°C
0.5
0.5
0.6
VS = 60 / –40 V,
VDD = 39.6 V, VSS = 0 V,
VSELx = 0 V, 5 V, or VDD
IDD(FA)
VDD supply current under fault
GND current under fault
–40°C to +85°C
–40°C to +125°C
25°C
IGND(FA)
0.1
(1) When VS is 30 V, VD is 1 V. Or when VS is 1 V, VD is 30 V.
(2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.10 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
Dual Supply Flat Ron Region
Dual Supply Voltages
Figure 7-2. On-Resistance vs Source or Drain Voltage
Figure 7-1. On-Resistance vs Source or Drain Voltage
Flatest RON region for all supply voltages shown
±15 V Supply Flatest Ron Region
Figure 7-3. On-Resistance vs Source or Drain Voltage
Figure 7-4. On-Resistance vs Source or Drain Voltage
Single Supply Voltages
±20 V Supply Flatest Ron Region
Figure 7-6. On-Resistance vs Source or Drain Voltage
Figure 7-5. On-Resistance vs Source or Drain Voltage
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
Single Supply Flat Ron Region
12 V VDD Flatest Ron Region
Figure 7-7. On-Resistance vs Source or Drain Voltage
Figure 7-8. On-Resistance vs Source or Drain Voltage
Single Supply Voltages
Single Supply Flat Ron Region
Figure 7-9. On-Resistance vs Source or Drain Voltage
Figure 7-10. On-Resistance vs Source or Drain Voltage
36 V VDD Flatest Ron Region
44 V VDD Flatest Ron Region
Figure 7-11. On-Resistance vs Source or Drain Voltage
Figure 7-12. On-Resistance vs Source or Drain Voltage
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = -15 V
Figure 7-13. Leakage Current vs Temperature
Figure 7-14. Leakage Current vs Temperature
VDD = 36 V, VSS = 0 V
VDD = +20 V, VSS = -20 V
Figure 7-15. Leakage Current vs Temperature
Figure 7-16. Leakage Current vs Temperature
VDD = 36 V, VSS = 0 V
VDD = +20 V, VSS = -20 V
Figure 7-17. Leakage Current vs Temperature
Figure 7-18. Leakage Current vs Temperature
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
±20 V Dual Supply
±15 V Dual Supply
Figure 7-20. ID(FA) Overvoltage Leakage Current vs Temperature
Figure 7-19. ID(FA) Overvoltage Leakage Current vs Temperature
VDD = 12 V Single Supply
VDD = 36 V Single Supply
Figure 7-21. ID(FA) Overvoltage Leakage Current vs Temperature Figure 7-22. ID(FA) Overvoltage Leakage Current vs Temperature
±15 V Dual Supply
.
Figure 7-23. IS(FA) Overvoltage Leakage Current vs Temperature
Figure 7-24. THD+N vs Frequency
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
.
.
Figure 7-25. Charge Injection vs Source Voltage – Dual Supply Figure 7-26. Charge Injection vs Source Voltage – Single Supply
.
.
Figure 7-27. tON and tOFF vs Source Voltage
Figure 7-28. tON and tOFF vs Temperature
.
.
Figure 7-29. Crosstalk and Off Isolation vs Frequency
Figure 7-30. Insertion Loss vs Frequency
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
.
.
Figure 7-31. Threshold Voltage vs Temperature
Figure 7-32. Fault Response and Recovery
50 V/µs Ramp Rate
4 V/µs Ramp Rate
Figure 7-33. Drain Output Response – Positive Overvoltage
Figure 7-34. Drain Output Response – Positive Overvoltage
50 V/µs Ramp Rate
4 V/µs Ramp Rate
Figure 7-35. Drain Output Response – Negative Overvoltage
Figure 7-36. Drain Output Response – Negative Overvoltage
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7.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
.
.
Figure 7-37. Drain Output Recovery – Positive Overvoltage
Figure 7-38. Drain Output Recovery – Negative Overvoltage
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8 Parameter Measurement Information
8.1 On-Resistance
The on-resistance of the TMUX7411F, TMUX7412F, and TMUX7413F is the ohmic resistance across the source
(Sx) and drain (Dx) pins of the device. The on-resistance varies with input voltage and supply voltage. The
symbol RON is used to denote on-resistance. Figure 8-1 shows the measurement setup used to measure RON
.
ΔRON represents the difference between the RON of any two channels, while RON_FLAT denotes the flatness that
is defined as the difference between the maximum and minimum value of on-resistance measured over the
specified analog signal range.
V
VDD
VSS
8
410
=
+
5
VDD
VSS
IS
SW
Sx
Dx
VS
GND
Figure 8-1. On-Resistance Measurement Setup
8.2 Turn-On and Turn-Off Time
Turn-on time (tON) is defined as the time taken by the output of the TMUX7411F, TMUX7412F, and TMUX7413F
to rise to a 90% final value after the SELx signal has past the 50% threshold. Turn off time (tOFF) is defined as
the time taken by the output of the TMUX7411F, TMUX7412F, and TMUX7413F to fall to a 10% initial value after
the SELx signal has past the 50% threshold. Figure 8-2 shows the setup used to measure tON and tOFF
.
VDD
VSS
0.1 µF
Output
0.1 µF
GND
3 V
VDD
VSS
GND
tr < 20 ns
tf < 20 ns
50%
50%
VSEL
SW
Sx
Dx
0 V
VS
VS
RL
CL
0.9 VS
tON
SELx
tOFF
GND
Output
GND
GND
0.1 VS
VSEL
GND
GND
Figure 8-2. tON and tOFF Measurement Setup
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8.3 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current IS(OFF): the leakage current flowing into or out of the source pin when the switch
is off.
2. Drain off-leakage current ID(OFF): the leakage current flowing into or out of the drain pin when the switch is
off.
Figure 8-3 shows the setup used to measure both off-leakage currents.
VDD
VSS
VDD
VSS
Is (OFF)
A
ID (OFF)
A
SW
SW
SW
SW
S1
S4
S1
S4
D1
D4
D1
D4
VD
VD
VS
VS
GND
GND
GND
GND
ID (OFF)
A
Is (OFF)
A
VD
VD
VS
VS
GND
GND
GND
GND
GND
GND
IS(OFF)
ID(OFF)
Figure 8-3. Off-Leakage Measurement Setup
8.4 On-Leakage Current
Source on-leakage current (IS(ON)) and drain on-leakage current (ID(ON)) denote the channel leakage currents
when the switch is in the on state. IS(ON) is measured with the drain floating, while ID(ON) is measured with the
source floating. Figure 8-4 shows the circuit used for measuring the on-leakage currents.
VDD
VSS
VDD
VSS
Is (OFF)
A
ID (OFF)
A
SW
SW
S1
S1
D1
D4
D1
D4
N.C. N.C.
VS
VS
GND
GND
GND
Is (OFF)
A
ID (OFF)
A
SW
SW
S4
S4
N.C. N.C.
VS
VS
GND
GND
GND
IS(ON)
ID(ON)
Figure 8-4. On-Leakage Measurement Setup
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8.5 Input and Output Leakage Current Under Overvoltage Fault
If any of the source pin voltage goes above the supplies (VDD or VSS) by one threshold voltage (VT), the
overvoltage protection feature of the TMUX7411F, TMUX7412F, and TMUX7413F is triggered to turn off the
switch under fault, keeping the fault channel in a high-impedance state. IS(FA) and ID(FA) denotes the input and
output leakage current under overvoltage fault conditions, respectively. When the overvoltage fault occurs, the
supply (or supplies) can either be in normal operating condition (Figure 8-5) or abnormal operating condition
(Figure 8-6). During abnormal operating condition, the supply (or supplies) can either be unpowered (VDD= VSS
0 V) or floating (VDD= VSS = no connection), and remains within the leakage performance specifications.
=
VDD
VSS
Is (FA)
A
ID (FA)
A
VD
SW
SW
S1
S4
D1
D4
VS
Is (FA)
A
ID (FA)
A
VD
VS
GND
IS(FA) / ID(FA)
( |VS| > |VDD + VT| or |VSS - VT| )
Figure 8-5. Measurement Setup for Input and Output Leakage Current under Overvoltage Fault with
Normal Supplies
N.C.
GND
VDD
VSS
VDD
VSS
Is (FA)
A
Is (FA)
A
ID (FA)
A
ID (FA)
A
SW
SW
SW
SW
S1
S1
D1
D1
RL
RL
VS
VS
GND
GND
GND
GND
GND
Is (FA)
A
ID (FA)
A
Is (FA)
A
ID (FA)
A
D4
D4
S4
S4
RL
RL
VS
VS
GND
GND
GND
GND
GND
Unpowered
(VDD = VSS = GND = 0 V)
Floating
(VDD = VSS = N.C.)
Figure 8-6. Measurement Setup for Input and Output Leakage Current under Overvoltage Fault with
Unpowered or Floating Supplies
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8.6 Fault Response Time
Fault response time (tRESPONSE) measures the delay between the source voltage exceeding the supply voltage
(VDD or VSS) by 0.5 V and the drain voltage failing to 90% of the fault supply voltage exceeded. Figure 8-7 shows
the setup used to measure tRESPONSE
.
VDD
VSS
0.1 µF
Max positive fault
0.1 µF
0 V
VDD
VSS
VDD + 0.5 V
60V/µs
ramp
60V/µs
ramp
VS
VS
SW
Sx
VSS - 0.5 V
Dx
Output
CL
0 V
Max negative fault
tRESPONSE (VDD)
VDD
tRESPONSE (VSS)
VS
0 V
Output
RL
All other source &
drain pins
Output × 90%
Output
Output × 90%
0 V
VSS
tRESPONSE = max ( tRESPONSE(VDD), tRESPONSE(VSS)
)
Figure 8-7. Fault Response Time Measurement Setup
8.7 Fault Recovery Time
Fault recovery time (tRECOVERY) measures the delay between the source voltage falling from overvoltage
condition to below supply voltage (VDD or VSS) plus 0.5 V and the drain voltage rising from 0 V to 50% of
the fault supply voltage exceeded. Figure 8-8 shows the setup used to measure tRECOVERY
.
VDD
VSS
0 V
0.1 µF
Output
0.1 µF
GND
VDD
VSS
VSS + 2 V
VDD + 0.5 V
VSS - 0.5 V
GND
VDD - 2 V
VS
VS
tRECOVERY (VSS)
0 V
SW
Sx
Dx
0 V
tRECOVERY (VDD)
All other
source &
drain pins
VS
GND
RL
CL
Output
VSS × 0.5
VDD × 0.5
GND
GND
Output
GND
0 V
GND
tRECOVERY = max ( tRECOVERY(VDD), tRECOVERY(VSS)
)
Figure 8-8. Fault Recovery Time Measurement Setup
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8.8 Fault Flag Response Time
Fault flag response time (tRESPONSE(FLAG)) measures the delay between the source voltage exceeding the fault
supply voltage (VDD or VSS) by 0.5 V and the general fault flag (FF) pin to go below 10% of its original value.
Figure 8-9 shows the setup used to measure tRESPONSE(FLAG)
.
VDD
VSS
0.1 µF
0.1 µF
GND
VDD
VSS
0 V
GND
VDD + 0.5 V
SW
Sx
Dx
VS
VS
VFN - 0.5 V
0 V
tRESPONSE(FLAG)_VDD
5 V
VS
5V
RL
CL
tRESPONSE(FLAG)_VSS
All other
source &
drain pins
GND
5 V
0 V
RPU
GND
GND
VFF
VFF
0.5 V
0.5 V
FF
0 V
GND
tRESPONSE(FLAG) = max ( tRESPONSE(FLAG)_VDD, tRESPONSE(FLAG)_VSS
)
CL_FF
GND
GND
Figure 8-9. Fault Flag Response Time Measurement Setup
8.9 Fault Flag Recovery Time
Fault flag recovery time (tRECOVERY(FLAG)) measures the delay between the source voltage falling from
overvoltage condition to below fault supply voltage (VDD or VSS) plus 0.5 V and the general fault flag (FF)
pin to rise above 3 V with 5 V external pull-up. Figure 8-10 shows the setup used to measure tRECOVERY(FLAG)
.
VDD
VSS
0.1 µF
0.1 µF
GND
VDD
VSS
0 V
GND
SW
VDD + 0.5 V
Sx
VDD - 0.5 V
Dx
VS
VS
VS
0 V
5V
tRECOVERY(FLAG)_VSS
RL
CL
tRECOVERY(FLAG)_VDD
All other
source &
drain pins
GND
RPU
5 V
VFF
5 V
VFF
GND
GND
3 V
3 V
FF
0 V
0 V
GND
tRECOVERY(FLAG) = max ( tRECOVERY(FLAG)_VDD, tRECOVERY(FLAG)_VSS
)
CL_FF
GND
GND
Figure 8-10. Fault Flag Recovery Time Measurement Setup
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8.10 Charge Injection
Charge injection is a measure of the glitch impulse transferred from the logic input to the signal path during logic
pin switching, and is denoted by the symbol QINJ. Figure 8-11 shows the setup used to measure charge injection
from the source to drain.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
Output
D1
D4
3 V
VSELx
0 V
tr < 20 ns
tf < 20 ns
CL
VS
GND
GND
GND
S4
Output
CL
Output
VS
VOUT
QINJ = CL ×
VOUT
VS
SELx
GND
VSELx
GND
Figure 8-11. Charge-Injection Measurement Setup
8.11 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. Figure 8-12 shows the setup used to measure off isolation.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Network Analyzer
GND
SW
SX
VOUT
RS
Dx
VS
50Ω
SELx
Other
Sx/ Dx
pins
VSELx
GND
50Ω
8176
1BB +OKH=PEKJ = 20 × .KC
8
5
Figure 8-12. Off Isolation Measurement Setup
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8.12 Inter-Channel Crosstalk
Figure 8-13 shows how the inter-channel crosstalk (XTALK(INTER)) measures the voltage at the source pin (Sx) of
a switch channel when a signal is applied at the source pin of an different switch channel.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Network Analyzer
GND
SW
SW
SX
SY
DX
DY
50Ω
RS
VOUT
Other
Sx/ Dx
pins
50Ω
VS
50Ω
50Ω
SELx
VSELx
GND
8176
+JPAN F ?D=JJAH %NKOOP=HG = 20 × .KC
8
5
Figure 8-13. Inter-Channel Crosstalk Measurement Setup
8.13 Bandwidth
Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to
the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. Figure 8-14
shows the setup used to measure bandwidth of the switch.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Network Analyzer
GND
SW
SX
VOUT
RS
Dx
Other
Sx/ Dx
pins
VS
50Ω
SELx
VSELx
50Ω
GND
8176
$=J@SE@PD = 20 × .KC
8
5
Figure 8-14. Bandwidth Measurement Setup
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8.14 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined
as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency
at the switch output. The on-resistance of the device varies with the amplitude of the input signal and results
in distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is
denoted as THD+N. Figure 8-15 shows the setup used to measure THD+N of the devices.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Audio Precision
GND
SW
SX
RS
Dx
VOUT
VS
RL
Other
Sx/ Dx
pins
SELx
VSELX
GND
50Ω
Figure 8-15. THD+N Measurement Setup
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9 Detailed Description
9.1 Overview
The TMUX741xF devices are 44-V fault protected switches in a 1:1, 4 channel configuration. The devices work
well with dual supplies (±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD
= 15 V, VSS = –5 V). The overvoltage protection feature on the source pins works under powered and powered-
off conditions, allowing for use in harsh industrial environments. The powered-off condition includes floating
power supplies, grounded power supplies, or power supplies at any level that are below the undervoltage (UV)
threshold.
9.2 Functional Block Diagram
VDD
VSS
VDD
VSS
VDD
VSS
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
Fault Detection/
Switch Driver/
Logic Decoder
Fault Detection/
Switch Driver/
Logic Decoder
Fault Detection/
Switch Driver/
Logic Decoder
FF
FF
FF
TMUX7411F
TMUX7412F
TMUX7413F
(SELx = Logic 1)
(SELx = Logic 1)
(SELx = Logic 1)
9.3 Feature Description
9.3.1 Flat ON-Resistance
The TMUX7411F, TMUX7412F, and TMUX7413F are designed with a special switch architecture to produce
ultra-flat on-resistance (RON) across most of the switch input operation region. The flat RON response allows the
device to be used in precision sensor applications since the RON is controlled regardless of the signals sampled.
The architecture is implemented without a charge pump so no unwanted noise is produced from the device to
affect sampling accuracy.
9.3.2 Protection Features
The TMUX7411F, TMUX7412F, and TMUX7413F offer a number of protection features to enable robust system
implementations.
9.3.2.1 Input Voltage Tolerance
The maximum voltage that can be applied to any source input pin is +60 V or -60 V, allowing the device to
handle typical voltage fault condition in industrial applications. Caution: the device has different maximum stress
ratings across different pin combinations and are defined as the following:
1. Between source pins and supply rails: 85 V
For example, if the device is powered by VDD supply of 25 V, then the maximum negative signal level on any
source pin is –60 V. If the device is powered by VDD supply of 40 V, then the maximum negative signal level
on any source pin is reduced to –45 V to maintain the 85 V maximum rating across the source pin and the
supply.
2. Between source pins and the same drain pins: 85 V
For example, if channel S1 is ON and an overvoltage voltage fault of –60 V occurs on the source pin, then
the maximum positive voltage signal level driven on the drain pin channel D1 is 25 V to maintain the 85 V
maximum rating across the source pin and the drain pin.
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9.3.2.2 Powered-Off Protection
When the supplies of TMUX7411F, TMUX7412F, and TMUX7413F are removed (VDD/ VSS = 0 V or floating), the
source (Sx) pins of the device remain in high impedance (Hi-Z) state, and the device performance remains within
the leakage performance. Powered-off protection minimizes system complexity by removing the need to control
power supply sequencing of the system. The feature prevents errant voltages on the input source pins from
reaching the rest of the system and maintains isolation when the system is powering up. Without powered-off
protection, signals on the input source pins can back-power the supply rails through internal ESD diodes and
cause potential damage to the system.
A GND reference must always be present to ensure proper operation. Source and drain voltage levels of up to
±60 V are blocked in the powered-off condition.
9.3.2.3 Fail-Safe Logic
Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting
the device from potential damage. The switch is specified to be in the OFF state, regardless of the state of the
logic signals. The logic inputs are protected against positive faults of up to +44 V in powered-off condition, but do
not offer protection against negative overvoltage condition.
Fail-safe logic also allows the TMUX741xF devices to interface with a voltage greater than VDD during normal
operation to add maximum flexibility in system design. For example, with a VDD of = 15 V, the logic control
pins could be connected to +24 V for a logic high signal which allows different types of signals, such as analog
feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the logic
inputs can be interfaced as high as 44 V.
9.3.2.4 Overvoltage Protection and Detection
The TMUX7411F, TMUX7412F, and TMUX7413F detect overvoltage inputs by comparing the voltage on a
source pin (Sx) with the supplies (VDD and VSS). A signal is considered overvoltage if it exceeds the supply
voltages by the threshold voltage (VT).
The switch automatically turns OFF regardless of the logic controls when an overvoltage is detected. The source
pin becomes high impedance and ensures only small leakage current flows through the switch. The drain pin
(Dx) is left floating when the fault channel is selected by the logic control. For example, if the source voltage
exceeds VDD or VSS, the drain output is left floating and the circuit connected to the drain pin, such as RL and CL,
determines the final voltage.
9.3.2.5 ESD Protection
All pins on the TMUX7411F, TMUX7412F, and TMUX7413F support HBM ESD protection level up to ±6 kV,
which helps prevent the device from being damaged by ESD events during manufacturing process.
The drain pins (Dx) have internal ESD protection diodes to the supplies VDD and VSS, therefore the voltage at
the drain pins must not exceed the supply voltages to prevent excessive diode current. The source pins have
specialized ESD protection that allows the signal voltage to reach ±60 V regardless of supply voltage level.
Exceeding ±60 V on any source input may damage the ESD protection circuitry on the device and cause the
device to malfunction if the damage is excessive.
9.3.2.6 Latch-Up Immunity
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The Latch-up condition typically requires a power cycle to eliminate the
low impedance path.
In the TMUX7411F, TMUX7412F, and TMUX7413F devices, an insulating oxide layer is placed on top of the
silicon substrate to prevent any parasitic junctions from forming. As a result, the devices are latch-up immune
under all circumstances by device construction.
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9.3.2.7 EMC Protection
The TMUX7411F, TMUX7412F, and TMUX7413F are not intended for standalone electromagnetic compatibility
(EMC) protection in industrial applications. There are three common high voltage transient specifications
that govern industrial high voltage transient specification: IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and
IEC61000-4-5 (surge immunity). A transient voltage suppressor (TVS), along with some low-value series current
limiting resistor, are required to prevent source input voltages from going above the rated ±60 V limits.
When selecting a TVS protection device, it is critical to ensure that the maximum working voltage is greater than
both the normal operating range of the input source pins to be protected and any known system common-mode
overvoltage that may be present due to miswiring, loss of power, or short circuit. Figure 9-1 shows ane example
of the proper design window when selecting a TVS device.
Region 1 denotes normal operation region of TMUX7411F, TMUX7412F, and TMUX7413F, where the input
source voltages stay below the supplies VDD and VSS. Region 2 represents the range of possible persistent
DC (or long duration AC overvoltage fault) presented on the source input pins. Region 3 represents the
margin between any known DC overvoltage level and the absolute maximum rating of the TMUX741xF. The
TVS breakdown voltage must be selected to be less than the absolute maximum rating of the TMUX7411F,
TMUX7412F, and TMUX7413F, but greater than any known possible persistent DC or long duration AC
overvoltage fault to avoid triggering the TVS inadvertently. Region 4 represents the margin system designers
must impose when selecting the TVS protection device to prevent accidental triggering of ESD cells of the
TMUX7411F, TMUX7412F, and TMUX7413F devices.
Internal ESD
Trigger Voltage
4
Device Absolute
Max Rating
TVS
Breakdown
Voltage
3
2
System
Overvoltage
Overvoltage
Protection Window
Positive Supply
VDD
0 V
1
Normal Operation
Negative Supply
VSS
2
3
4
System
Overvoltage
Overvoltage
Protection Window
TVS
Breakdown
Voltage
Device Absolute
Max Rating
Internal ESD
Trigger Voltage
Figure 9-1. System Operation Regions and Proper Region of Selecting a TVS Protection Device
9.3.3 Overvoltage Fault Flags
The voltages on the source input pins of the TMUX7411F, TMUX7412F, and TMUX7413F are continuously
monitored, and the status of whether an overvoltage condition occurs is indicated by an active low general fault
flag (FF). The voltage on the FF pin indicates if any of the source input pins are experiencing an overvoltage
condition. If any source pin voltage exceeds the fault supply voltages by a VT, the FF output is pulled-down to
below VOL
.
The FF pin is an open-drain output and an external pull-up resistor of 1 kΩ is recommended. The pull-up voltage
can be in the range of 1.8 V to 5.5 V, depending on the controller voltage the device interfaces with.
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9.3.4 Bidirectional Operation
The TMUX7411F, TMUX7412F, and TMUX7413F conduct equally well from source (Sx) to drain (Dx) or from
drain (Dx) to source (Sx). However, it is noted that the overvoltage protection is implemented only on the source
(Sx) side. The voltage on the drain is only allowed to swing between VDD and VSS and no overvotlage protection
is available on the drain side.
The flatest on-resistance region extends from VSS to roughly 3 V below VDD. Once the signal is within 3 V of VDD
the on-resistance will expoentially increase and may impact desired signal transmission.
9.4 Device Functional Modes
The TMUX7411F, TMUX7412F, and TMUX7413F offer two modes of operation (normal mode and fault mode)
depending on whether any of the input pins experience an overvoltage condition.
9.4.1 Normal Mode
Signals of up to VDD and VSS can be passed through the switch from source (Sx) to drain (Dx) or from drain (Dx)
to source (Sx) in normal mode operation. According to Table 9-1, Table 9-2, and Table 9-3 the select pins (SELx)
and determines which switch path to turn on. The following conditions must be satisfied for the switch to stay in
the ON condition:
•
•
•
The difference between the supples (VDD – VSS) must be greater than or equal to 8 V.
The input signals on the source (Sx) or the drain (Dx) must be be between VDD+ VT and VSS – VT.
The select control logic (SELx) must have selected the switch.
9.4.2 Fault Mode
The TMUX7411F, TMUX7412F, and TMUX7413F enter into fault mode when any of the input signals on the
source (Sx) pins exceed VDD or VSS by a threshold voltage VT. Under the overvoltage condition, the switch
input experiencing the fault automatically turns off regardless of the logic status, and the source pin becomes
high impedance with negligible amount of leakage current flowing through the switch. When the fault channel is
turned-on by the select control logic (SELx), the drain pin (Dx) left floating and the final voltage is determined by
the circuitry connected to the drain pin.
In the fault mode, the general fault flag (FF) is asserted low.
The overvoltage protection is provided only for the source (Sx) input pins. The drain (Dx) pin, if used as signal
input, must stay in between VDD and VSS at all time since no overvoltage protection is implemented on the drain
pin.
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9.4.3 Truth Tables
Table 9-1, Table 9-2, and Table 9-3 show the truth tables for the TMUX7411F, TMUX7412F, and TMUX7413F,
respectively. Each switch is independently controlled by its own select pin.
Table 9-1. TMUX7411F Truth Table
SELx
Switch x (S1 to S4)
0
1
Channel x ON
Channel x OFF
Table 9-2. TMUX7412F Truth Table
SELx
Switch x (S1 to S4)
Channel x OFF
Channel x ON
0
1
Table 9-3. TUMUX7413F Truth Table
SELx
STATE
Switch 1, 4 OFF
Switch 2, 3 ON
0
Switch 1, 4 ON
Switch 2, 3 OFF
1
If unused, SELx pins must be tied to GND in order to ensure the device does not consume additional current
as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx or Dx) should be
connected to GND.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TMUX7411F, TMUX7412F, and TMUX7413F are part of the fault protected switches and multiplexers family
of devices. The abilty to protect downstream components from overvoltage events up to ±60 V and latch-up
immunity features makes these switches and multiplexers suitable for harsh environments.
10.2 Typical Application
The need to monitor remote sensors is common among factory automation control systems. For example,
an analog input module or mixed module (AI, AO, DI, and DO) of a programmable logic controller (PLC)
will interface to a field transmitter to monitor various process sensors at remote locations around the factory.
A switch or multiplexer is often used to connect multiple inputs from the system and reduce the number of
downstream channels.
There are a number of fault cases that may occur that can be damaging to many of the integrated circuits.
Such fault conditions may include, but are not limited to, human error from wiring the connections incorrectly,
component failure, wire shorts, electromagnetic interference (EMI), transient distrubances, and more.
Supply
Power Module
GND
Local Control Side
TMUX7412F
+15V -15V
VDD VSS
+
-
+24V
Field Side
Differential
Output
S1
S2
S3
S4
D1
D2
D3
+15V
Sensors
Sensors
Sensors
Sensors
Fault
Protected
Mux Inputs
+
Control
& Processing
DAC
ADC
ADC
RG
œ
+
-
D4
Differential
Output
-15V
+60V
Logic Select Pins
SEL4
SEL3
1.8V Logic
Signals
V
SEL2
SEL1
Figure 10-1. Typical Application
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10.2.1 Design Requirements
Table 10-1. Design Parameters
PARAMETER
VALUE
+15 V
Positive supply (VDD) mux
Negative supply (VSS) mux
Power board supply voltage
-15 V
24 V
Input or output signal range non-faulted
Overvoltage protection levels
Control logic thresholds
-15 V to 15 V
-60 V to 60 V
1.8 V compatible, up to 44 V
-40°C to +125°C
Temperature range
10.2.2 Detailed Design Procedure
The normal operation of the application is to take multiple differential inputs and use a multi-channel switch to
pass the signal to the downstream instrumentation amplifier. A fault protected switch can add extra robustness to
the sytem against fault conditions while also reducing the number of components required to interface with the
systems physical input channels.
The image shows the case where a human wired the condition incorrectly and one of the input connectors
shorted to the power board supply voltage. If the board supply voltage is higher than the power supply of the
multiplexer, then the TMUX741xF device will disconnect the source input from passing the signal to protect the
downstream components. The drain pin of the mux channels under fault will be left floating.
10.2.3 Application Performance Plots
The example application utilizes fault protection of the TMUX741xF to protect downstream components from
potential miswiring conditions from the Power Module board. Figure 10-2 shows an example of positive
overvoltage fault response with a fast fault ramp rate of 50 V/us. Figure 10-3 shows the extremely flat on-
resistance across source voltage while operating within a common signal range of ±10 V. These features make
the TMUX741xF an ideal solution for factory automation applications that may face various fault conditions but
also require excellent linearity and low distortion.
Figure 10-2. Positive Overvoltage Response
Figure 10-3. RON Flatness in Non-Fault Region
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11 Power Supply Recommendations
The TMUX7411F, TMUX7412F, and TMUX7413F operates across a wide supply range of ±5 V to ±22 V (8 V to
44 V in single-supply mode). They also perform well with asymmetrical supplies such as VDD = 12 V and VSS
= –5 V. Use a supply decoupling capacitor ranging from 1 µF to 10 µF at the VDD and VSS pins to ground for
improved supply noise immunity. Always ensure the ground (GND) connection is established before supplies are
ramped.
12 Layout
12.1 Layout Guidelines
Figure 12-1 and Figure 12-2 illustrates an example of a PCB layout with the TMUX7412F. The following are
some key considerations:
•
Decouple the VDD and VSS pins with a 1-µF capacitor, placed as close to the pin as possible. Make sure that
the capacitor voltage rating is sufficient for the VDD and VSS supplies.
•
Multiple decoupling capacitors can be used if their is a lot of noise in the system. For example, a 0.1-µF and
1-µF can be placed on the supply pins. If multiple capacitors are used, placing the lowest value capacitor
closest to the supply pin is recommended.
•
•
•
Keep the input lines as short as possible.
Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
12.2 Layout Example
SEL1
D1
SEL2
Wide (low inductance)
trace for power
D2
S2
Wide (low inductance)
trace for power
S1
VSS
GND
S4
VDD
FF
TMUX741xF
To Pull-up resistor
S3
D3
D4
SEL3
SEL4
Via to ground plane
Figure 12-1. TSSOP Layout Example
S2
VDD
FF
S1
VSS
GND
S4
To Pull-up resistor
S3
Via to ground plane
Via to power plane
Figure 12-2. WQFN Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
•
•
Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
Texas Instruments, Improving Analog Input Modules Reliability Using Fault Protected Multiplexers application
report
•
•
Texas Instruments, Multiplexers and Signal Switches Glossary application report
Texas Instruments, Protection Against Overvoltage Events, Miswiring, and Common Mode Voltages
application report
•
Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability application
report
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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9-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX7412FRRPR
ACTIVE
WQFN
RRP
16
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TMUX
7412F
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX7412FRRPR
WQFN
RRP
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Nov-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RRP 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TMUX7412FRRPR
3000
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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TMUX810x 100-V, Flat RON, Single 8:1 and Dual 4:1 Multiplexers with Latch-Up Immunity and 1.8-V LogicWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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具有闩锁效应抑制和 1.8V 逻辑电平的 100V、扁平 RON、单路 8:1 多路复用器 | PW | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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