TMUX7436FPWR_技术文档

TMUX7436F

ZHCSPX3A –OCTOBER 2022 –REVISED NOVEMBER 2022

TMUX7436F 具有故障保护功能、闩锁

效应抑制和1.8V 逻辑的±60V 双路2:1 多路复用器

1 特性

3 说明

• 宽电源电压范围：

TMUX7436F 是一款具有闩锁效应抑制的互补金属氧化

物半导体 (CMOS) 模拟多路复用器，采用双通道 2:1

配置。该器件在双电源（±5V 至±22V）、单电源（8V

至 44V）或非对称电源（例如 V_DD= 12V，V_SS= –

5V）供电情况下运行良好。TMUX7436F 器件在通电

和断电情况下均提供过压保护，适用于无法精确控制电

源时序的应用。

– 单电源：8V 至44V

– 双电源：±5V 至±22V

• 集成故障保护：

– 过压保护（从源极到电源或到漏极）：±85V

– 过压保护：±60V

– 断电保护：±60V

– 指示故障状态的中断标志

– 故障期间的输出开路

在通电和断电条件下，该器件可阻断最高+60V 或

-60V 的对地故障电压。在没有电源的情况下，无论开

关输入条件如何，开关通道都将保持关断状态，并且逻

辑引脚上的任何控制信号都会被忽略。如果任何 Sx 引

• 器件构造可实现闩锁效应抑制

• 6kV 人体放电模型(HBM) ESD 等级

• 低导通电阻：8.6Ω典型值

• 平缓的导通电阻：10mΩ典型值

• 支持1.8V 逻辑电平

脚上的信号路径输入电压超过电源电压（V_DD或V_SS

）

一个阈值电压 (V_T)，那么通道将会关闭，并且 Sx 引脚

将变为高阻态。漏极引脚 (Dx) 将被拉至超出范围的故

障电源电压或保持悬空，具体取决于 DR 控制逻辑。

TMUX7436F 器件提供两个低电平有效中断标志（FF

和 SF），用于指示故障详情并有助于系统诊断。FF

标志指示是否有任何源输入出现故障，而 SF 标志用于

说明出现故障状态的特定输入。

• 失效防护逻辑：高达44V（与电源无关）

• 业界通用的TSSOP 封装和较小的WQFN 封装

2 应用

• 工厂自动化和控制

• 可编程逻辑控制器(PLC)

• 模拟输入模块

封装信息⁽¹⁾

• 半导体测试设备

• 电池测试设备

• 伺服驱动器控制模块

• 数据采集系统(DAQ)

封装尺寸（标称值）

器件型号

封装

PW（TSSOP，16） 5.00mm × 4.40mm

RRP（WQFN，16）

TMUX7436F

4.00mm × 4.00mm

(2)

V_DD

V_SS

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

S1A

S1B

(2) 预发布封装

D1

D2

S2A

S2B

SEL1

SEL2

EN

Fault Detection/

Switch Driver/

Logic Decoder

FF

SF

DR

TMUX7436F

功能模块图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCDS459

TMUX7436F

ZHCSPX3A –OCTOBER 2022 –REVISED NOVEMBER 2022

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Table of Contents

7.11 Fault Flag Recovery Time....................................... 30

7.12 Charge Injection......................................................31

7.13 Off Isolation.............................................................31

7.14 Crosstalk.................................................................32

7.15 Bandwidth............................................................... 33

7.16 THD + Noise........................................................... 33

8 Detailed Description......................................................34

8.1 Overview...................................................................34

8.2 Functional Block Diagram.........................................34

8.3 Feature Description...................................................34

8.4 Device Functional Modes..........................................38

9 Application and Implementation..................................40

9.1 Application Information............................................. 40

9.2 Typical Application.................................................... 40

10 Power Supply Recommendations..............................42

11 Layout...........................................................................42

11.1 Layout Guidelines................................................... 42

11.2 Layout Example...................................................... 42

12 Device and Documentation Support..........................43

12.1 Documentation Support.......................................... 43

12.2 接收文档更新通知................................................... 43

12.3 支持资源..................................................................43

12.4 Trademarks.............................................................43

12.5 Electrostatic Discharge Caution..............................43

12.6 术语表..................................................................... 43

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Thermal Information....................................................5

6.4 Recommended Operating Conditions.........................5

6.5 Electrical Characteristics: Global................................ 6

6.6 ±15 V Dual Supply: Electrical Characteristics.............7

6.7 ±20 V Dual Supply: Electrical Characteristics...........10

6.8 12 V Single Supply: Electrical Characteristics.......... 13

6.9 36 V Single Supply: Electrical Characteristics.......... 16

6.10 Typical Characteristics............................................19

7 Parameter Measurement Information..........................25

7.1 On-Resistance.......................................................... 25

7.2 Off-Leakage Current................................................. 25

7.3 On-Leakage Current................................................. 26

7.4 Input and Output Leakage Current Under

Overvoltage Fault........................................................26

7.5 Enable Delay Time....................................................27

7.6 Break-Before-Make Delay.........................................27

7.7 Transition Time......................................................... 28

7.8 Fault Response Time................................................28

7.9 Fault Recovery Time.................................................29

7.10 Fault Flag Response Time......................................29

Information.................................................................... 43

4 Revision History

Changes from Revision * (October 2022) to Revision A (November 2022)

Page

• 将数据表的状态从预告信息更改为“量产数据”.............................................................................................. 1

2

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5 Pin Configuration and Functions

SEL1

S1A

D1

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SF

FF

D1

S1B

VSS

GND

1

2

3

4

12

11

10

9

EN

VDD

S2B

D2

S1B

VSS

GND

NC

VDD

S2B

D2

Thermal

Pad

S2A

SEL2

DR

Not to scale

图5-2. RRP (Preview) Package,

Not to scale

16-Pin WQFN (Top View)

图5-1. PW Package,

16-Pin TSSOP (Top View)

表5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

D1

TSSOP

WQFN⁽²⁾

3

1

9

I/O

Drain pin 1. Can be an input or output. The drain pin is not overvoltage protected.

Drain pin 2. Can be an input or output. The drain pin is not overvoltage protected.

Drain Response (DR) input. Tying the DR pin to GND enables the drain to be pulled to V_DDor

D2

11

DR

EN

FF

8

5

I

V

_SSthrough a 40 kΩresistor during an overvoltage fault event. The drain pin becomes open

circuit when the DR pin is a logic high or left floating.

Active high logic enable (EN) pin, has internal 4 MΩpull-down resistor. The device is disabled

and all switches become high impedance when the pin is low. As provided in 表8-1, when the

pin is high, the SELx logic inputs determine individual switch states.

14

15

12

13

General fault flag. This pin is an open drain output and is asserted low when overvoltage

condition is detected on any of the source (Sxy) input pins. Connect this pin to an external

supply (1.8 V to 5.5 V) through a 1 kΩpull-up resistor.

O

P

GND

N.C.

S1A

6

7

4

7

Ground (0 V) reference

No internal connection. This pin can be shorted to GND or left floating.

Overvoltage protected source pin 1A. Can be an input or output.

Overvoltage protected source pin 1B. Can be an input or output.

Overvoltage protected source pin 2A. Can be an input or output.

Overvoltage protected source pin 2B. Can be an input or output.

Logic control input 1.

—

I/O

I

2

16

2

S1B

4

S2A

10

12

1

8

S2B

10

15

6

SEL1

SEL2

9

I

Logic control input 2.

Specific fault flag. This pin is an open drain output and is asserted low when an overvoltage

condition is detected on a specific (Sxy) input pin, depending on the state of the SELx pins, as

provided in 表8-1. Connect this pin to an external supply (1.8 V to 5.5 V) through a 1 kΩpull-

up resistor.

SF

16

14

O

P

Positive power supply. This pin is the most positive power-supply potential. Connect a

decoupling capacitor ranging from 0.1 µF to 10 µF between V_DDand GND for reliable

operation.

V_DD

13

5

11

3

Negative power supply. This pin is the most negative power-supply potential. This pin can be

connected to ground in single-supply applications. Connect a decoupling capacitor ranging

from 0.1 µF to 10 µF between V_SSand GND for reliable operation.

V_SS

P

The thermal pad is not connected internally. It is recommended to tie the pad to GND or VSS

for best performance.

Thermal Pad

—

(1) I = input, O = output, I/O = input and output, P = power.

(2) Preview package.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

48

UNIT

V

V_DDto V_SS

V_DDto GND

V_SSto GND

V_Sto GND

V_Sto V_DD

V_Sto V_SS

V_D

48

V

Supply voltage

–0.3

–48

–65

–90

0.3

65

V

Source input pin (Sx) voltage to GND

Source input pin (Sx) voltage to V_DD

Source input pin (Sx) voltage to V_SS

Drain pin (Dx) voltage

V

90

V

V_DD+0.7

V

V_SS–0.7

GND –0.7

–30

V_LOGIC

V_xF

Logic control input pin voltage (EN, SELx, DR)⁽²⁾

Logic output pin voltage (FF, SF)⁽²⁾

Logic control input pin current (EN, SELx, DR)⁽²⁾

Logic output pin current (FF, SF)⁽²⁾

Source or drain continuous current (Sx or Dx)

Storage temperature

48

V

6

V

I_LOGIC

30

mA

°C

mW

I_xF

10

I_DC± 10 %⁽³⁾

150

–10

I_Sor I_{D (CONT)}

T_stg

I_DC± 10 %⁽³⁾

–65

T_A

Ambient temperature

150

–55

T_J

Junction temperature

150

(4)

P_tot

Total power dissipation (TSSOP)

650

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not

sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,

performance, and shorten the device lifetime.

(2) Stresses have to be kept at or below both voltage and current ratings at all time.

(3) Refer to Recommended Operating Conditions for I_DCratings.

(4) For TSSOP package: P_totderates linearly above T_A= 70°C by 10.1 mW/°C.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±4000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all

pins⁽²⁾

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4

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6.3 Thermal Information

TMUX7436F

THERMAL METRIC⁽¹⁾

PW (TSSOP)

16 PINS

100.4

31.3

RRP (WQFN)

16 PINS

TBD

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

TBD

46.4

TBD

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.7

TBD

Ψ_JT

45.8

TBD

Ψ_JB

R_θJC(bot)

N/A

TBD

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

8

NOM

MAX UNIT

(1)

Power supply voltage differential

44

V

44

V_DD–V_SS

V_DD

Positive power supply voltage

5

V_S

Source pin (Sx) voltage (non-fault condition)

Source pin (Sx) voltage to GND (fault condition)

Source pin (Sx) voltage to V_DDor V_D(fault condition)

Source pin (Sx) voltage to V_SSor V_D(fault condition)

Drain pin (Dx) voltage

V_SS

–60

–85

V_DD

60

V_Sto GND

(2)

V

V_Sto V_DD

V_Sto V_SS

V_D

(2)

85

V_SS

GND

–40

V_DD

V_LOGIC

Logic control input pin voltage (EN, SELx, DR)

Logic output pin voltage (FF, SF)

44

V

5.5

(3)

V_xF

T_A

Ambient temperature

125

°C

T_A= 25°C

T_A= 85°C

T_A= 125°C

T_A= 25°C

T_A= 85°C

T_A= 125°C

115 mA

85 mA

115 mA

60 mA

Continuous current through switch operating 1 channel,

TSSOP package

I_DC

Continuous current through switch operating max number of

channels at the same time, TSSOP package

I_DC

(1) V_DDand V_SScan be any value as long as 8 V ≤(V_DD–V_SS) ≤44 V, and the minimum V_DDis met.

(2) Source pin voltage (Sx) under a fault condition may not exceed 85 V from supply pins (V_DDand V_SS.) or drain pins (D, Dx).

(3) Logic output pin (FF) is an open drain output and should be pulled up to a voltage within the maximum ratings.

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6.5 Electrical Characteristics: Global

at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ANALOG SWITCH

V_T

Threshold voltage for fault detector

25°C

0.7

V

LOGIC INPUT/ OUTPUT

V_IH

High-level input voltage

EN, SELx, DR pins

1.3

0

44

0.8

V

–40°C to +125°C

V_IL

Low-level input voltage

Low-level output voltage

V_OL(FLAG)

POWER SUPPLY

FF and SF pins, I_O= 5 mA

0.35

Rising edge, single supply

Falling edge, single supply

5.1

5

5.8

5.7

6.6

6.4

V

–40°C to +125°C

Undervoltage lockout (UVLO)

threshold voltage (V_DD–V_SS

V_UVLO

)

V_DDUndervoltage lockout

(UVLO) hysteresis

V_HYS

Single supply

0.2

40

V

–40°C to +125°C

Drain resistance to supply rail

during overvoltage event on

selected source pin

Drain resistance to supply rail during

overvoltage event on selected source pin

R_D(OVP)

25°C

kΩ

6

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6.6 ±15 V Dual Supply: Electrical Characteristics

V_DD= +15 V ± 10%, V_SS= –15 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

8.6

11

V_S= –10 V to +10 V

I_D= –10 mA

14

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

Ω

16.5

0.45

0.06

0.01

On-resistance mismatch between V_S= –10 V to +10 V

0.5

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

Ω

channels

I_D= –10 mA

0.6

0.4

V_S= –10 V to +10 V

I_D= –10 mA

0.4

R_FLAT

On-resistance flatness

On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.4

R_{ON_DRIFT}

0.04

0.03

V_S= 0 V, I_S= –10 mA

Ω/°C

0.7

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

V_D= –10 V / + 10 V

–0.7

–2

I_S(OFF)

Input leakage current⁽¹⁾

2

11

1.4

4

nA

–40°C to +85°C

–40°C to +125°C

25°C

–11

–1.4

–4

0.06

0.08

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

V_D= –10 V / + 10 V

I_D(OFF)

Output off leakage current⁽¹⁾

Output on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

24

1.4

4

–24

–1.4

–4

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is on

V_S= V_D= ±10 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

27

–27

FAULT CONDITION

V_S= ± 60 V, GND = 0 V,

V_DD= 16.5 V, V_SS= –16.5 V

Input leakage current

durring overvoltage

I_S(FA)

±100

±125

µA

–40°C to +125°C

Input leakage current

during overvoltage with

grounded supply voltages

V_S= ± 60 V, GND = 0 V

V_DD= V_SS= 0 V

I_{S(FA) Grounded}

Input leakage current

during overvoltage with

floating supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= floating

I_{S(FA) Floating}

±125

±0.1

µA

nA

–40°C to +125°C

25°C

20

30

60

30

50

90

–20

–30

–60

–30

–50

–90

V_S= ± 60 V, GND = 0 V,

V_DD= 16.5 V, V_SS= –16.5 V

Output leakage current

during overvoltage

I_D(FA)

–40°C to +85°C

–40°C to +125°C

25°C

±0.01

Output leakage current

during overvoltage with

grounded supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= 0 V

I_{D(FA) Grounded}

nA

µA

–40°C to +85°C

–40°C to +125°C

25°C

±4

±6

±8

Output leakage current

during overvoltage with

floating supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= floating

I_{D(FA) Floating}

–40°C to +85°C

–40°C to +125°C

25°C

±1.6

±2

I_IH

High-level input current

Low-level input current

V_EN= V_SELx= V_DR= V_DD

µA

–40°C to +125°C

25°C

±1

I_IL

V_EN= V_SELx= V_DR= 0

±1.1

–40°C to +125°C

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6.6 ±15 V Dual Supply: Electrical Characteristics (continued)

V_DD= +15 V ± 10%, V_SS= –15 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

SWITCHING CHARACTERISTICS

25°C

435

515

V_S= 10 V,

R_L= 300 Ω, C_L= 12 pF

530

550

130

140

150

540

555

570

505

515

520

4500

4800

t_{ON (EN)}

Enable turn-on time

Enable turn-off time

Transition time

–40°C to +85°C

–40°C to +125°C

25°C

ns

50

417

V_S= 10 V,

R_L= 300 Ω, C_L= 12 pF

t_{OFF (EN)}

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 10 V,

R_L= 300 Ω, C_L= 12 pF

t_TRAN

–40°C to +85°C

–40°C to +125°C

25°C

110

t_RESPONSE

Fault response time

Fault recovery time

–40°C to +85°C

–40°C to +125°C

25°C

R_L= 300 Ω, C_L= 12 pF

1600

t_RECOVERY

–40°C to +85°C

–40°C to +125°C

R_L= 300 Ω, C_L= 12 pF,

R_PU= 1 kΩ, C_{L_xF}= 12 pF

t_{RESPONSE(FLAG)}Fault flag response time

t_{RECOVERY(FLAG)}Fault flag recovery time

25°C

120

1

ns

µs

R_L= 300 Ω, C_L= 12 pF,

R_PU= 1 kΩ, C_{L_xF}= 12 pF

t_BBM

Q_INJ

Break-before-make time delay

Charge injection

200

380

ns

V_S= 10 V, R_L= 300 Ω, C_L= 12 pF

–40°C to +125°C

V_S= 0 V, C_L= 1 nF

25°C

pC

–300

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V, f = 1 MHz

O_ISO

Off-isolation

25°C

dB

–60

–62

–88

220

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V, f = 1 MHz

Intra-channel crosstalk

Inter-channel crosstalk

–3 dB bandwidth

Insertion loss

X_TALK

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V, f = 1 MHz

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V

BW

MHz

dB

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V, f = 1 MHz

I_LOSS

–0.7

R_S= 50 Ω, R_L= 10 kΩ,

V_S= 15 V_PP, V_BIAS= 0 V,

f = 20 Hz to 20 kHz

Total harmonic distortion plus

noise

THD+N

25°C

0.0007

%

C_S(OFF)

C_D(OFF)

Input off-capacitance

Output off-capacitance

f = 1 MHz, V_S= 0 V

25°C

13

25

pF

C_S(ON)

C_D(ON)

Input/Output on-capacitance

f = 1 MHz, V_S= 0 V

25°C

28

pF

POWER SUPPLY

25°C

0.32

0.5

0.6

0.4

0.5

V_DD= 16.5 V, V_SS= –16.5 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

mA

0.26

0.06

V_DD= 16.5 V, V_SS= –16.5 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_SS

V_SSsupply current

GND current

–40°C to +85°C

–40°C to +125°C

mA

V_DD= 16.5 V, V_SS= –16.5 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_GND

25°C

8

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6.6 ±15 V Dual Supply: Electrical Characteristics (continued)

V_DD= +15 V ± 10%, V_SS= –15 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

0.27

0.7

V_S= ± 60 V,

V_DD= 16.5 V, V_SS= –16.5 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

0.8

0.6

0.8

I_DD(FA)

V_DDsupply current under fault

–40°C to +85°C

–40°C to +125°C

25°C

mA

0.2

V_S= ± 60 V,

V_DD= 16.5 V, V_SS= –16.5 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_SS(FA)

V_SSsupply current under fault

GND current under fault

–40°C to +85°C

–40°C to +125°C

V_S= ± 60 V,

V_DD= 16.5 V, V_SS= –16.5 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_GND(FA)

25°C

0.15

25°C

0.5

0.4

V_DD= 16.5 V, V_SS= –16.5 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 0 V

I_DD(DISABLE)

V_DDsupply current (disable mode)

V_SSsupply current (disable mode)

–40°C to +85°C

–40°C to +125°C

25°C

0.1

V_DD= 16.5 V, V_SS= –16.5 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 0 V

I_SS(DISABLE)

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive,V_Dis negative. And when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating. And when V_Dis at a voltage potential, V_Sis floating.

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6.7 ±20 V Dual Supply: Electrical Characteristics

V_DD= +20 V ± 10%, V_SS= –20 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +20 V, V_SS= –20 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

8.6

11

V_S= –15 V to +15 V

I_D= –10 mA

14

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

Ω

17

0.06

0.35

On-resistance mismatch between V_S= –15 V to +15 V

0.5

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

Ω

channels

I_D= –10 mA

0.5

0.4

0.015

V_S= –15 V to +15 V

I_D= –10 mA

0.5

R_FLAT

On-resistance flatness

On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.5

R_{ON_DRIFT}

0.04

0.03

V_S= 0 V, I_S= –10 mA

Ω/°C

0.7

V_DD= 22 V, V_SS= –22 V

Switch state is off

V_S= +15 V / –15 V

V_D= –15 V / + 15 V

–0.7

–2

I_S(OFF)

Input leakage current⁽¹⁾

2

11

1.4

4

nA

–40°C to +85°C

–40°C to +125°C

25°C

–11

–1.4

–4

0.06

0.08

V_DD= 22 V, V_SS= –22 V

Switch state is off

V_S= +15 V / –15 V

V_D= –15 V / + 15 V

I_D(OFF)

Output off leakage current⁽¹⁾

Output on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

24

1.4

4

–24

–1.4

–4

V_DD= 22 V, V_SS= –22 V

Switch state is on

V_S= V_D= ±15 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

27

–27

FAULT CONDITION

V_S= ± 60 V, GND = 0 V,

V_DD= 22 V, V_SS= –22 V

Input leakage current

durring overvoltage

I_S(FA)

±85

µA

–40°C to +125°C

Input leakage current

during overvoltage with

grounded supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= 0 V

I_{S(FA) Grounded}

±125

Input leakage current

during overvoltage with

floating supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= floating

I_{S(FA) Floating}

±125

±5

µA

nA

–40°C to +125°C

25°C

50

70

90

30

50

90

–50

–70

–90

–30

–50

–90

V_S= ± 60 V, GND = 0 V,

V_DD= 22 V, V_SS= –22 V,

Output leakage current

during overvoltage

I_D(FA)

–40°C to +85°C

–40°C to +125°C

25°C

±10

Output leakage current

during overvoltage with

grounded supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= 0 V

I_{D(FA) Grounded}

nA

µA

–40°C to +85°C

–40°C to +125°C

25°C

±4

±6

±8

Output leakage current

during overvoltage with

floating supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= floating

I_{D(FA) Floating}

–40°C to +85°C

–40°C to +125°C

25°C

±1.8

±2.2

±1

I_IH

High-level input current

Low-level input current

V_EN= V_SELx= V_DR= V_DD

µA

–40°C to +125°C

25°C

I_IL

V_EN= V_SELx= V_DR= 0

±1.1

–40°C to +125°C

10

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6.7 ±20 V Dual Supply: Electrical Characteristics (continued)

V_DD= +20 V ± 10%, V_SS= –20 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +20 V, V_SS= –20 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

SWITCHING CHARACTERISTICS

25°C

430

535

V_S= 10 V,

R_L= 300 Ω, C_L= 12 pF

560

585

120

130

150

555

571

580

505

515

520

4500

4900

t_{ON (EN)}

Enable turn-on time

Enable turn-off time

Transition time

–40°C to +85°C

–40°C to +125°C

25°C

ns

50

433

V_S= 10 V,

R_L= 300 Ω, C_L= 12 pF

t_{OFF (EN)}

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 10 V,

R_L= 300 Ω, C_L= 12 pF

t_TRAN

–40°C to +85°C

–40°C to +125°C

25°C

110

t_RESPONSE

Fault response time

Fault recovery time

–40°C to +85°C

–40°C to +125°C

25°C

R_L= 300 Ω, C_L= 12 pF

1600

t_RECOVERY

–40°C to +85°C

–40°C to +125°C

R_L= 300 Ω, C_L= 12 pF,

R_PU= 1 kΩ, C_{L_xF}= 12 pF

t_{RESPONSE(FLAG)}Fault flag response time

t_{RECOVERY(FLAG)}Fault flag recovery time

25°C

140

1

ns

µs

R_L= 300 Ω, C_L= 12 pF,

R_PU= 1 kΩ, C_{L_xF}= 12 pF

t_BBM

Q_INJ

Break-before-make time delay

Charge injection

210

400

ns

V_S= 10 V, R_L= 300 Ω, C_L= 12 pF

–40°C to +125°C

V_S= 0 V, C_L= 1 nF

25°C

pC

–330

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V, f = 1 MHz

O_ISO

Off-isolation

25°C

dB

–60

–64

–81

230

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V, f = 1 MHz

Intra-channel crosstalk

Inter-channel crosstalk

–3 dB bandwidth

Insertion loss

X_TALK

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V, f = 1 MHz

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V

BW

MHz

dB

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V, f = 1 MHz

I_LOSS

–0.7

R_S= 50 Ω, R_L= 10 kΩ,

V_S= 20 V_PP, V_BIAS= 0 V,

f = 20 Hz to 20 kHz

Total harmonic distortion plus

noise

THD+N

25°C

0.0008

%

C_S(OFF)

C_D(OFF)

Input off-capacitance

Output off-capacitance

f = 1 MHz, V_S= 0 V

25°C

12

24

pF

C_S(ON)

C_D(ON)

Input/Output on-capacitance

f = 1 MHz, V_S= 0 V

25°C

27

pF

POWER SUPPLY

25°C

0.32

0.5

0.6

0.4

0.5

V_DD= 22 V, V_SS= –22 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

mA

0.26

0.06

V_DD= 22 V, V_SS= –22 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_SS

V_SSsupply current

GND current

–40°C to +85°C

–40°C to +125°C

mA

V_DD= 22 V, V_SS= –22 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_GND

25°C

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6.7 ±20 V Dual Supply: Electrical Characteristics (continued)

V_DD= +20 V ± 10%, V_SS= –20 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +20 V, V_SS= –20 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

0.27

0.8

V_S= ± 60 V,

V_DD= 22 V, V_SS= –22 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

1

I_DD(FA)

V_DDsupply current under fault

–40°C to +85°C

–40°C to +125°C

25°C

mA

0.2

0.7

1

V_S= ± 60 V,

V_DD= 22 V, V_SS= –22 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_SS(FA)

V_SSsupply current under fault

GND current under fault

–40°C to +85°C

–40°C to +125°C

1

V_S= ± 60 V,

V_DD= 22 V, V_SS= –22 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_GND(FA)

25°C

0.15

25°C

0.5

0.4

V_DD= 22 V, V_SS= –22 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 0 V

I_DD(DISABLE)

V_DDsupply current (disable mode)

V_SSsupply current (disable mode)

–40°C to +85°C

–40°C to +125°C

25°C

0.1

V_DD= 22 V, V_SS= –22 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 0 V

I_SS(DISABLE)

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive,V_Dis negative. And when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating. And when V_Dis at a voltage potential, V_Sis floating.

12

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6.8 12 V Single Supply: Electrical Characteristics

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

8.6

11

V_S= 0 V to 7.8 V,

I_S= –10 mA

15

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

Ω

18

0.06

0.5

V_S= 0 V to 7.8 V,

I_S= –10 mA

On-resistance mismatch between

channels

0.6

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

Ω

0.7

0.4

V_S= 0 V to 7.8 V,

I_S= –10 mA

0.5

R_FLAT

On-resistance flatness

On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.5

R_{ON_DRIFT}

0.04

0.03

V_S= 6 V, I_S= –10 mA

Ω/°C

0.7

–0.7

–2

V_DD= 13.2 V, V_SS= 0 V

Switch state is off

V_S= 10 V / 1 V

I_S(OFF)

Input leakage current⁽¹⁾

2

11

1.4

4

nA

–40°C to +85°C

–40°C to +125°C

25°C

V_D= 1 V / 10 V

–11

–1.4

–4

0.06

0.08

V_DD= 13.2 V, V_SS= 0 V

Switch state is off

V_S= 10 V / 1 V

I_D(OFF)

Output off leakage current⁽¹⁾

Output on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

V_D= 1 V / 10 V

24

1.4

4

–24

–1.4

–4

V_DD= 13.2 V, V_SS= 0 V

Switch state is on

V_S= V_D= 10 V or 1 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

26

–26

FAULT CONDITION

Input leakage current

durring overvoltage

V_S= ± 60 V, GND = 0 V,

V_DD= 13.2 V, V_SS= 0 V

I_S(FA)

±130

±125

µA

–40°C to +125°C

Input leakage current

during overvoltage with

grounded supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= 0 V

I_{S(FA) Grounded}

Input leakage current

during overvoltage with

floating supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= floating

I_{S(FA) Floating}

±125

±2

µA

nA

–40°C to +125°C

25°C

20

30

50

30

50

90

–20

–30

–50

–30

–50

–90

Output leakage current

during overvoltage

V_S= ± 60 V, GND = 0 V,

V_DD= 13.2 V, V_SS= 0 V

I_D(FA)

–40°C to +85°C

–40°C to +125°C

25°C

±10

Output leakage current

during overvoltage with

grounded supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= 0 V

I_{D(FA) Grounded}

nA

µA

–40°C to +85°C

–40°C to +125°C

25°C

±4

±6

±8

Output leakage current

during overvoltage with

floating supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= floating

I_{D(FA) Floating}

–40°C to +85°C

–40°C to +125°C

25°C

±1.6

±2

I_IH

High-level input current

Low-level input current

V_EN= V_SELx= V_DR= V_DD

µA

–40°C to +125°C

25°C

±1

I_IL

V_EN= V_SELx= V_DR= 0

±1.1

–40°C to +125°C

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6.8 12 V Single Supply: Electrical Characteristics (continued)

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

SWITCHING CHARACTERISTICS

25°C

350

515

V_S= 8 V,

R_L= 300 Ω, C_L= 12 pF

530

550

200

210

520

540

560

765

2400

2900

t_{ON (EN)}

Enable turn-on time

Enable turn-off time

Transition time

–40°C to +85°C

–40°C to +125°C

25°C

ns

85

360

180

950

V_S= 8 V,

R_L= 300 Ω, C_L= 12 pF

t_{OFF (EN)}

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 8 V,

R_L= 300 Ω, C_L= 12 pF

t_TRAN

–40°C to +85°C

–40°C to +125°C

25°C

t_RESPONSE

Fault response time

Fault recovery time

–40°C to +85°C

–40°C to +125°C

25°C

R_L= 300 Ω, C_L= 12 pF

t_RECOVERY

–40°C to +85°C

–40°C to +125°C

R_L= 300 Ω, C_L= 12 pF,

R_PU= 1 kΩ, C_{L_xF}= 12 pF

t_{RESPONSE(FLAG)}Fault flag response time

t_{RECOVERY(FLAG)}Fault flag recovery time

25°C

160

0.7

ns

µs

R_L= 300 Ω, C_L= 12 pF,

R_PU= 1 kΩ, C_{L_xF}= 12 pF

t_BBM

Q_INJ

Break-before-make time delay

Charge injection

25°C

155

250

ns

V_S= 8 V, R_L= 300 Ω, C_L= 12 pF

V_S= 6 V, C_L= 1 nF

pC

–203

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V, f = 1 MHz

O_ISO

Off-isolation

25°C

dB

–56

–58

–81

213

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 6 V, f = 1 MHz

Intra-channel crosstalk

Inter-channel crosstalk

–3 dB bandwidth

Insertion loss

X_TALK

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 6 V, f = 1 MHz

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V

BW

MHz

dB

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 0 V, f = 1 MHz

I_LOSS

–0.7

R_S= 50 Ω, R_L= 10k Ω,

V_S= 6 V_PP, V_BIAS= 6 V,

f = 20 Hz to 20 kHz

Total harmonic distortion plus

noise

THD+N

25°C

0.0009

%

C_S(OFF)

C_D(OFF)

Input off-capacitance

Output off-capacitance

f = 1 MHz, V_S= 6 V

25°C

13

28

pF

C_S(ON)

C_D(ON)

Input/Output on-capacitance

f = 1 MHz, V_S= 6 V

25°C

31

pF

POWER SUPPLY

25°C

0.3

0.5

0.6

0.4

V_DD= 13.2 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

mA

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

0.14

0.06

V_DD= 13.2 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_SS

V_SSsupply current

GND current

–40°C to +85°C

–40°C to +125°C

mA

V_DD= 13.2 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_GND

25°C

14

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6.8 12 V Single Supply: Electrical Characteristics (continued)

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

0.25

0.6

V_S= ± 60 V,

V_DD= 13.2 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

0.7

0.5

I_DD(FA)

V_DDsupply current under fault

–40°C to +85°C

–40°C to +125°C

25°C

mA

0.15

V_S= ± 60 V,

V_DD= 13.2 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_SS(FA)

V_SSsupply current under fault

GND current under fault

–40°C to +85°C

–40°C to +125°C

V_S= ± 60 V,

V_DD= 13.2 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_GND(FA)

25°C

0.15

25°C

0.5

0.4

V_DD= 13.2 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 0 V

I_DD(DISABLE)

V_DDsupply current (disable mode)

V_SSsupply current (disable mode)

–40°C to +85°C

–40°C to +125°C

25°C

0.1

V_DD= 13.2 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 0 V

I_SS(DISABLE)

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis 10 V, V_Dis 1 V. Or when V_Sis 1 V, V_Dis 10 V.

(2) When V_Sis at a voltage potential, V_Dis floating. Or when V_Dis at a voltage potential, V_Sis floating.

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6.9 36 V Single Supply: Electrical Characteristics

V_DD= +36 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +36 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

8.6

11

V_S= 0 V to 30 V,

I_S= –10 mA

14

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

Ω

17

0.06

0.07

0.5

V_S= 0 V to 30 V,

I_S= –10 mA

On-resistance mismatch between

channels

0.6

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

Ω

0.7

0.4

V_S= 0 V to 30 V,

I_S= –10 mA

0.5

R_FLAT

On-resistance flatness

On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.5

R_{ON_DRIFT}

0.04

0.05

V_S= 18 V, I_S= –1 mA

Ω/°C

0.7

–0.7

–2

V_DD= 39.6 V, V_SS= 0 V

Switch state is off

V_S= 30 V / 1 V

I_S(OFF)

Input leakage current⁽¹⁾

2

11

1.4

4

nA

–40°C to +85°C

–40°C to +125°C

25°C

V_D= 1 V / 30 V

–11

–1.4

–4

0.1

V_DD= 39.6 V, V_SS= 0 V

Switch state is off

V_S= 30 V / 1 V

I_D(OFF)

Output off leakage current⁽¹⁾

Output on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

V_D= 1 V / 30 V

24

1.4

4

–24

–1.4

–4

0.15

V_DD= 39.6 V, V_SS= 0 V

Switch state is on

V_S= V_D= 30 V or 1 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

27

–27

FAULT CONDITION

Input leakage current

durring overvoltage

V_S= 60 / –40 V,

V_DD= 39.6 V, V_SS= 0 V, GND = 0 V

I_S(FA)

±90

µA

–40°C to +125°C

Input leakage current

during overvoltage with

grounded supply voltages

V_S= ± 60 V,

V_DD= V_SS= 0 V, GND = 0 V

I_{S(FA) Grounded}

±125

Input leakage current

during overvoltage with

floating supply voltages

V_S= ± 60 V,

V_DD= V_SS= floating, GND = 0 V,

I_{S(FA) Floating}

±125

±2

µA

nA

–40°C to +125°C

25°C

20

30

60

30

50

90

–20

–30

–60

–30

–50

–90

Output leakage current

during overvoltage

V_S= 60 / –40 V,

V_DD= 39.6 V, V_SS= 0, GND = 0V

I_D(FA)

–40°C to +85°C

–40°C to +125°C

25°C

±10

Output leakage current

during overvoltage with

grounded supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= 0 V

I_{D(FA) Grounded}

nA

µA

–40°C to +85°C

–40°C to +125°C

25°C

±4

±6

±8

Output leakage current

during overvoltage with

floating supply voltages

V_S= ± 60 V, GND = 0 V,

V_DD= V_SS= floating

I_{D(FA) Floating}

–40°C to +85°C

–40°C to +125°C

25°C

±2.7

±3.1

±1

I_IH

High-level input current

Low-level input current

V_EN= V_SELx= V_DR= V_DD

µA

–40°C to +125°C

25°C

I_IL

V_EN= V_SELx= V_DR= 0

±1.1

–40°C to +125°C

16

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6.9 36 V Single Supply: Electrical Characteristics (continued)

V_DD= +36 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +36 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

SWITCHING CHARACTERISTICS

25°C

370

520

V_S= 18 V,

R_L= 300 Ω, C_L= 12 pF

550

560

210

230

540

560

570

340

360

385

2350

2850

t_{ON (EN)}

Enable turn-on time

Enable turn-off time

Transition time

–40°C to +85°C

–40°C to +125°C

25°C

ns

100

365

V_S= 18 V,

R_L= 300 Ω, C_L= 12 pF

t_{OFF (EN)}

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 18 V,

R_L= 300 Ω, C_L= 12 pF

t_TRAN

–40°C to +85°C

–40°C to +125°C

25°C

120

t_RESPONSE

Fault response time

Fault recovery time

–40°C to +85°C

–40°C to +125°C

25°C

R_L= 300 Ω, C_L= 12 pF

1250

t_RECOVERY

–40°C to +85°C

–40°C to +125°C

R_L= 300 Ω, C_L= 12 pF,

R_PU= 1 kΩ, C_{L_xF}= 12 pF

t_{RESPONSE(FLAG)}Fault flag response time

t_{RECOVERY(FLAG)}Fault flag recovery time

25°C

100

1

ns

µs

R_L= 300 Ω, C_L= 12 pF,

R_PU= 1 kΩ, C_{L_xF}= 12 pF

t_BBM

Q_INJ

Break-before-make time delay

Charge injection

25°C

160

270

ns

V_S= 18 V, R_L= 300 Ω, C_L= 12 pF

V_S= 18 V, C_L= 1 nF

pC

–300

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 6 V, f = 1 MHz

O_ISO

Off-isolation

25°C

dB

–56

–59

–80

215

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 6 V, f = 1 MHz

Intra-channel crosstalk

Inter-channel crosstalk

–3 dB bandwidth

Insertion loss

X_TALK

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 6 V, f = 1 MHz

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 6 V

BW

MHz

dB

R_S= 50 Ω, R_L= 50 Ω, C_L= 5 pF,

V_S= 200 mV_RMS, V_BIAS= 6 V, f = 1 MHz

I_LOSS

–0.7

R_S= 50 Ω, R_L= 10 kΩ,

V_S= 18 V_PP, V_BIAS= 18 V,

f = 20 Hz to 20 kHz

Total harmonic distortion plus

noise

THD+N

25°C

0.0008

%

C_S(OFF)

C_D(OFF)

Input off-capacitance

Output off-capacitance

f = 1 MHz, V_S= 18 V

25°C

14

28

pF

C_S(ON)

C_D(ON)

Input/Output on-capacitance

f = 1 MHz, V_S= 18 V

25°C

31

pF

POWER SUPPLY

25°C

0.3

0.5

0.6

0.4

V_DD= 39.6 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

mA

0.14

0.06

V_DD= 39.6 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_SS

V_SSsupply current

GND current

–40°C to +85°C

–40°C to +125°C

mA

V_DD= 39.6 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_GND

25°C

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6.9 36 V Single Supply: Electrical Characteristics (continued)

V_DD= +36 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +36 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

0.25

1.2

V_S= 60 / –40 V,

V_DD= 39.6 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

1.6

0.5

I_DD(FA)

V_DDsupply current under fault

–40°C to +85°C

–40°C to +125°C

25°C

mA

0.15

V_S= 60 / –40 V,

V_DD= 39.6 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_SS(FA)

V_SSsupply current under fault

GND current under fault

–40°C to +85°C

–40°C to +125°C

V_S= 60 / –40 V,

V_DD= 39.6 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 5 V

or V_DD

I_GND(FA)

25°C

0.1

25°C

0.15

0.5

0.4

V_DD= 39.6 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 0 V

I_DD(DISABLE)

V_DDsupply current (disable mode)

V_SSsupply current (disable mode)

–40°C to +85°C

–40°C to +125°C

25°C

0.1

V_DD= 39.6 V, V_SS= 0 V,

V_SELx= V_DR= 0 V, 5 V, or V_DD, V_EN= 0 V

I_SS(DISABLE)

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis 30 V, V_Dis 1 V. Or when V_Sis 1 V, V_Dis 30 V.

(2) When V_Sis at a voltage potential, V_Dis floating. Or when V_Dis at a voltage potential, V_Sis floating.

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6.10 Typical Characteristics

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

160

12

11.5

11

V_DD= 13.5 V, V_SS= -13.5 V

V_DD= 15 V, V_SS= -15 V

V_DD= 16.5 V, V_SS= -16.5 V

V_DD= 18 V, V_SS= -18 V

V_DD= 20 V, V_SS= -20 V

V_DD= 22 V, V_SS= -22 V

V_DD= 15 V, V_SS= -15 V

V_DD= 16.5 V, V_SS= -16.5 V

V_DD= 18 V, V_SS= -18 V

V_DD= 20 V, V_SS= -20 V

V_DD= 22 V, V_SS= -22 V

140

120

100

80

10.5

10

9.5

9

60

8.5

8

40

20

7.5

7

0

-22 -18 -14 -10 -6

-2

2

6

10 14 18 22

-22 -18 -14 -10 -6

-2

2

6

10 14 18 22

V_Sor V_D- Source or Drain Voltage (V)

Dual Supply Flat Ron Region

Dual Supply Voltages

图6-2. On-Resistance vs Source or Drain Voltage

图6-1. On-Resistance vs Source or Drain Voltage

9.3

15

14

V_DD= 13.5 V, V_SS= -13.5 V

V_DD= 15 V, V_SS= -15 V

9.2

V_DD= 16.5 V, V_SS= -16.5 V

V_DD= 18 V, V_SS= -18 V

9.1

13

T_A= 125C

V_DD= 20 V, V_SS= -20 V

V_DD= 22 V, V_SS= -22 V

9

8.9

8.8

8.7

8.6

8.5

8.4

8.3

12

11

T_A= 85C

10

9

8

T_A= 25C

T_A= −40C

7

6

5

-10

-8

-6

-4

-2

0

2

4

6

8

10

-15 -12

-9

-6

-3

0

3

6

9

12

V_Sor V_D- Source or Drain Voltage (V)

Flatest R_ONregion for all supply voltages shown

15 V Supply Flatest Ron Region

.

图6-3. On-Resistance vs Source or Drain Voltage

图6-4. On-Resistance vs Source or Drain Voltage

15

14

160

V_DD= 8 V, V_SS= 0 V

NOTE_U_L

V_DD= 8.8 V, V_SS= 0 V

140

120

100

80

NOTE_U_L

V_DD= 10.8 V, V_SS= 0 V

V_DD= 12 V, V_SS= 0 V

V_DD= 13.2 V, V_SS= 0 V

13

T_A= 125C

12

11

T_A= 85C

10

9

60

8

40

T_A= 25C

T_A= −40C

7

20

6

0

5

0

2

4

6

8

10

12

14

-20 -16 -12

-8

-4

0

4

8

12

16 18

V_Sor V_D- Source or Drain Voltage (V)

Single Supply Voltages

20 V Supply Flatest Ron Region

.

图6-5. On-Resistance vs Source or Drain Voltage

图6-6. On-Resistance vs Source or Drain Voltage

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6.10 Typical Characteristics (continued)

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

9.2

9.1

9

15

14

13

12

11

10

9

T_A= 125C

8.9

8.8

8.7

8.6

T_A= 85C

V_DD= 8 V, V_SS= 0 V

V_DD= 8.8 V, V_SS= 0 V

8.5

8

T_A= 25C

8.4

8.3

8.2

V_DD= 10.8 V, V_SS= 0 V

V_DD= 12 V, V_SS= 0 V

V_DD= 13.2 V, V_SS= 0 V

T_A= −40C

7

6

5

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14

0

1

2

3

4

5

6

7

8

9

10

V_Sor V_D- Source or Drain Voltage (V)

Single Supply Flat Ron Region

12 V_DDFlatest Ron Region

.

图6-8. On-Resistance vs Source or Drain Voltage

图6-7. On-Resistance vs Source or Drain Voltage

160

9.3

V_DD= 32.4 V, V_SS= 0 V

NOTE_U_L

V_DD= 32.4 V, V_SS= 0 V

NOTE_U_L

9.2

9.1

9

V_DD= 36 V, V_SS= 0 V

140

120

100

80

NOTE_U_L

V_DD= 39.6 V, V_SS= 0 V

V_DD= 44 V, V_SS= 0 V

V_DD= 39.6 V, V_SS= 0 V

V_DD= 44 V, V_SS= 0 V

8.9

8.8

8.7

8.6

8.5

8.4

8.3

60

40

20

0

4

8

12 16 20 24 28 32 36 40 44

0

4

8

12 16 20 24 28 32 36 40 44

V_Sor V_D- Source or Drain Voltage (V)

Single Supply Voltages

Single Supply Flat Ron Region

.

图6-9. On-Resistance vs Source or Drain Voltage

图6-10. On-Resistance vs Source or Drain Voltage

15

14

15

14

13

12

11

10

9

T_A= 125C

12

11

T_A= 85C

10

9

8

T_A= 25C

T_A= −40C

7

6

5

7

6

5

0

4

8

12

16

20

24

28

32 34

0

4

8

12 16 20 24 28 32 36 40 42

V_Sor V_D- Source or Drain Voltage (V)

36 V_DDFlatest Ron Region

44 V_DDFlatest Ron Region

.

图6-11. On-Resistance vs Source or Drain Voltage

图6-12. On-Resistance vs Source or Drain Voltage

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6.10 Typical Characteristics (continued)

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

15

19

17

15

13

11

9

I_ONV_S= −10 V, V_D= −10 V

I_DOFFV_S= −10 V, V_D= 10 V

I_SOFFV_S= −10 V, V_D= 10 V

I_DOFFV_S= 10 V, V_D= −10 V

I_SOFFV_S= 10 V, V_D= −10 V

I_ONV_S= 10 V, V_D= 10 V

I_ONV_S= 1 V, V_D= 1 V

14

13

12

11

10

9

8

7

6

5

I_DOFFV_S= 1 V, V_D= 10 V

I_SOFFV_S= 1 V, V_D= 10 V

I_DOFFV_S= 10 V, V_D= 1 V

I_SOFFV_S= 10 V, V_D= 1 V

I_ONV_S= 10 V, V_D= 10 V

7

4

3

2

5

3

1

0

-1

1

-1

0

20

40

60

80

100

120

0

20

40

60

80

100

120

Temperature (C)

V_DD= 15 V, V_SS= −15 V

V_DD= 12 V, V_SS= 0 V

.

图6-14. Leakage Current vs Temperature

图6-13. Leakage Current vs Temperature

25

23

21

19

17

15

13

11

9

21

19

17

15

13

11

9

I_ONV_S= 1 V, V_D= 1 V

I_ONV_S= −15 V, V_D= −15 V

I_DOFFV_S= −15 V, V_D= 15 V

I_SOFFV_S= −15 V, V_D= 15 V

I_DOFFV_S= 15 V, V_D= −15 V

I_SOFFV_S= 15 V, V_D= −15 V

I_ONV_S= 15 V, V_D= 15 V

I_DOFFV_S= 1 V, V_D= 30 V

I_SOFFV_S= 1 V, V_D= 30 V

I_DOFFV_S= 30 V, V_D= 1 V

I_SOFFV_S= 30 V, V_D= 1 V

I_ONV_S= 30 V, V_D= 30 V

7

5

3

1

-1

-3

-1

0

20

40

60

80

100

120

0

20

40

60

80

100

120

Temperature (C)

V_DD= 20 V, V_SS= −20 V

V_DD= 36 V, V_SS= 0 V

.

图6-16. Leakage Current vs Temperature

图6-15. Leakage Current vs Temperature

27

24

21

18

15

12

9

32

28

24

20

16

12

8

V_S= -60 V, V_D= 15 V

V_S= -30 V, V_D= 15 V

V_S= 30 V, V_D= -14 V

V_S= 60 V, V_D= -14 V

V_S= -60 V, V_D= 20 V

V_S= -30 V, V_D= 20 V

V_S= 30 V, V_D= -19 V

V_S= 60 V, V_D= -19 V

6

4

3

0

-3

-4

0

20

40

60

80

100

120

0

20

40

60

80

100

120

Temperature (C)

15 V Dual Supply

20 V Dual Supply

.

图6-17. I_D(FA)Overvoltage Leakage Current vs Temperature

图6-18. I_D(FA)Overvoltage Leakage Current vs Temperature

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6.10 Typical Characteristics (continued)

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

25

32

28

24

20

16

12

8

V_S= -60 V, V_D= 12 V

V_S= -30 V, V_D= 12 V

V_S= 30 V, V_D= 1 V

V_S= 60 V, V_D= 1 V

V_S= -40 V, V_D= 36 V

V_S= -30 V, V_D= 36 V

V_S= 30 V, V_D= 1 V

V_S= 60 V, V_D= 1 V

22.5

20

17.5

15

12.5

10

7.5

5

4

2.5

0

-2.5

-4

0

20

40

60

80

100

120

0

20

40

60

80

100

120

Temperature (C)

V_DD= 12 V Single Supply

V_DD= 36 V Single Supply

.

图6-19. I_D(FA)Overvoltage Leakage Current vs Temperature

图6-20. I_D(FA)Overvoltage Leakage Current vs Temperature

0.1

100

60

V_DD= 12 V, V_SS= 0 V

V_DD= 15 V, V_SS= -15 V

V_DD= 20 V, V_SS= -20 V

V_DD= 36 V, V_SS= 0 V

0.05

0.03

0.02

20

0.01

-20

-60

-100

0.005

0.003

0.002

0.001

-140

-180

-220

V_S= -60 V

V_S= -30 V

V_S= 30 V

V_S= 60 V

0.0005

0.0003

0.0002

0.0001

0

20

40

60

80

100

120

0

4k

8k

12k

16k

20k

Temperature (C)

Frequency (Hz)

15 V Dual Supply

.

图6-22. THD+N vs Frequency

图6-21. I_S(FA)Overvoltage Leakage Current vs Temperature

0

-50

0

-50

V_DD= 8 V, V_SS= 0 V

V_DD= 12 V, V_SS= 0 V

V_DD= 36 V, V_SS= 0 V

V_DD= 44 V, V_SS= 0 V

-100

-150

-200

-250

-300

-350

-100

-150

-200

-250

-300

-350

-400

-450

-400

V_DD= 15 V, V_SS= -15 V

V_DD= 20 V, V_SS= -20 V

-450

-500

-20 -16 -12

-8 -4

V_S- Source Voltage (V)

0

4

8

12

16

20

0

4

8

12 16 20 24 28 32 36 40 44

V_S- Source Voltage (V)

.

图6-23. Charge Injection vs Source Voltage –Dual Supply

图6-24. Charge Injection vs Source Voltage –Single Supply

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6.10 Typical Characteristics (continued)

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

400

350

300

250

200

150

100

50

V_DD: 8 V, V_SS: 0 V, Falling Edge

V_DD: 8 V, V_SS: 0 V, Rising Edge

V_DD: 12 V, V_SS: 0 V, Falling Edge

V_DD: 12 V, V_SS: 0 V, Rising Edge

VDD = 36V, VSS = 0 V, Falling Edge

VDD = 36V, VSS = 0 V, Rising Edge

0

-40

-15

10

35

60

85

110 125

Temperature (C)

.

图6-25. Transition Times vs Temperature

图6-26. Transition Times vs Temperature

500

450

400

350

450

400

350

300

250

200

150

100

50

T_OFF15V

300

T_OFF+8V

T_ON+8V

T_OFF+12V

T_ON+12V

T_OFF+36V

T_ON+36V

T_ON15V

T_OFF20V

T_ON20V

250

200

150

100

50

0

-40

-15

10

35

60

85

110 125

-40

-15

10

35

60

85

110 125

Temperature (C)

.

图6-27. Turn-On and Turn-Off Times vs Temperature

图6-28. Turn-On and Turn-Off Times vs Temperature

30

0

CrossTalk: Adjacent Channel

CrossTalk: Nonadjacent Channel

Off-Isolation

10

-10

-1

-2

-3

-4

-5

-6

-30

-50

-70

-90

-110

-130

10k

100k

1M

10M

100M

1G

100k

1M

10M

100M

Frequency(Hz)

Frequency (Hz)

.

图6-29. Crosstalk and Off Isolation vs Frequency

图6-30. Insertion Loss vs Frequency

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6.10 Typical Characteristics (continued)

at T_A= 25°C, V_DD= 15 V, and V_SS= –15 V (unless otherwise noted)

0.9

30

25

20

15

10

5

V_TFalling

V_TRising

0.8

0.7

0.6

0.5

0.4

SOURCE

DRAIN

V_DD

FF/SF

40

0

-5

-40

-15

10

35

60

85

110 125

-20

0

20

60

80

100

120

Temperature (C)

Time (s)

.

图6-31. Threshold Voltage vs Temperature

图6-32. Fault Response and Recovery

70

10

5

65

60

55

50

45

40

35

30

25

20

15

10

5

FF/SF

40V/s Fault Ramp

0

SOURCE

-5

DRAIN

-10

-15

-20

-25

-30

-35

V_SS

V_DD

FF/SF

SOURCE

DRAIN

0

-5

-10

-1.5

30V/s Fault Ramp

-2

-1

0

1

2

3

4

5

6

7

8

-1

-0.5

0

0.5

1

1.5

2

2.5

3

Time (s)

.

图6-34. Drain Output Response –Negative Overvoltage

图6-33. Drain Output Response –Positive Overvoltage

75

70

65

60

55

50

45

40

35

30

25

20

15

10

15

10

5

0

SOURCE

DRAIN

-5

40V/s fault ramp

-10

-15

-20

-25

-30

-35

-40

-45

-50

-55

-60

-65

V_SS

SOURCE

V_DD

400V/s fault ramp

DRAIN

-1

5

0

-5

0.5

1

1.5

2

2.5

3

3.5

4

-2

0

1

2

3

4

5

Time(s)

.

图6-36. Drain Output Recovery –Negative Overvoltage

图6-35. Drain Output Recovery –Positive Overvoltage

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7 Parameter Measurement Information

7.1 On-Resistance

The on-resistance of the TMUX7436F is the ohmic resistance across the source (Sx) and drain (Dx) pins of the

device. The on-resistance varies with input voltage and supply voltage. The symbol R_ONis used to denote on-

resistance. 图 7-1 shows the measurement setup used to measure R_ON. ΔR_ONrepresents the difference

between the R_ONof any two channels, while R_{ON_FLAT}denotes the flatness that is defined as the difference

between the maximum and minimum value of on-resistance measured over the specified analog signal range.

V

V_DD

V_SS

8

4₁₀

=

+

5

V_DD

V_SS

I_S

SW

Sx

Dx

V_S

GND

图7-1. On-Resistance Measurement Setup

7.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state:

1. Source off-leakage current I_S(OFF): the leakage current flowing into or out of the source pin when the switch

is off.

2. Drain off-leakage current I_D(OFF): the leakage current flowing into or out of the drain pin when the switch is

off.

图7-2 shows the setup used to measure both off-leakage currents.

V_DD

V_SS

V_DD

V_SS

I_{s (OFF)}

I_{D (OFF)}

S1A

S1B

S1A

S1B

A

D1

A

V_S

V_D

V_S

V_D

I_{s (OFF)}

I_{D (OFF)}

S2A

S2B

S2A

S2B

D2

A

D2

V_S

GND

V_D

I_S(OFF)

I_D(OFF)

图7-2. Off-Leakage Measurement Setup

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7.3 On-Leakage Current

Source on-leakage current (I_S(ON)) and drain on-leakage current (I_D(ON)) denote the channel leakage currents

when the switch is in the on state. I_S(ON)is measured with the drain floating, while I_D(ON)is measured with the

source floating. 图7-3 shows the circuit used for measuring the on-leakage currents.

V_DD

V_SS

V_DD

V_SS

I_{s (ON)}

A

I_{D (ON)}

S1A

S1B

S1A

S1B

N.C.

D1

A

N.C.

V_S

N.C.

V_D

I_{s (ON)}

A

S2A

S2B

S2A

S2B

N.C.

D2

N.C.

A

V_S

N.C.

V_D

GND

I_S(ON)

I_D(ON)

图7-3. On-Leakage Measurement Setup

7.4 Input and Output Leakage Current Under Overvoltage Fault

If any of the source pin voltage goes above the supplies (V_DDor V_SS) by one threshold voltage (V_T), then the

overvoltage protection feature of the TMUX7436F is triggered to turn off the switch under fault, keeping the fault

channel in a high-impedance state. I_S(FA)and I_D(FA)denotes the input and output leakage current under

overvoltage fault conditions, respectively. When the overvoltage fault occurs, the supply (or supplies) can either

be in normal operating condition (图 7-4) or abnormal operating condition (图 7-5). During abnormal operating

condition, the supply (or supplies) can either be unpowered (V_DD= V_SS= 0 V) or floating (V_DD= V_SS= no

connection), and remains within the leakage performance specifications.

V_DD

V_SS

I_{S (FA)}

I_{D (FA)}

S1A

S1B

A

D1

A

N.C.

V_S

V_D

I_{S (FA)}

I_{D (FA)}

S2A

S2B

A

D2

A

N.C.

V_S

GND

V_D

I_S(FA)/ I_D(FA)

( |V_S| > |V_DD+ V_T| or |V_SS- V_T| )

图7-4. Measurement Setup for Input and Output Leakage Current under Overvoltage Fault With Normal

Supplies

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N.C.

GND

V_DD

V_SS

V_DD

V_SS

I_{S (FA)}

I_{D (FA)}

S1A

S1B

S1A

S1B

A

D1

A

N.C.

V_S

I_{S (FA)}

I_{D (FA)}

S2A

S2B

S2A

S2B

A

D2

A

N.C.

V_S

GND

Unpowered

Floating

(V_DD= V_SS= GND = 0 V)

(V_DD= V_SS= N.C.)

图7-5. Measurement Setup for Input and Output Leakage Current under Overvoltage Fault With

Unpowered or Floating Supplies

7.5 Enable Delay Time

t_ON(EN)is defined as the time taken by the output of the TMUX7436F to rise to a 90% final value after the EN

signal has past the 50% threshold. t_OFF(EN)is defined as the time taken by the output of the TMUX7436F to fall

to a 10% initial value after the EN signal has past the 50% threshold. 图 7-6 shows the setup used to measure

t_ONand t_OFF

.

V_DD

V_SS

0.1 µF

V_DD

S1A

V_SS

3 V

V_S

D1

D2

Output

C_L

t_r< 20 ns

t_f< 20 ns

50%

S1B

V_EN

R_L

0 V

V_S

S2A

S2B

V_S

0.9 V_S

t_ON(EN)

Output

C_L

t_OFF(EN)

0.1 V_S

Output

R_L

EN

GND

V_EN

图7-6. Enable Delay Measurement Setup

7.6 Break-Before-Make Delay

The break-before-make delay is a safety feature of the TMUX7436F switch. The ON switches of the

TMUX7436F first break the connection before the OFF switches make connection. The time delay between the

break and the make is known as break-before-make delay. 图 7-7 shows the setup used to measure break-

before-make delay, denoted by the symbol t_BBM

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V_DD

V_SS

0.1 µF

3 V

V_DD

S1A

V_SS

V_SEL

t_r< 20 ns

t_f< 20 ns

V_S

0 V

V_S

D1

D2

Output

S1B

R_L

C_L

0.8 V_S

Output

0 V

S2A

S2B

V_S

t_BBM

1

t_BBM2

Output

C_L

R_L

t_BBM= min ( t_BBM1, t_BBM2)

SELx

GND

V_SEL

图7-7. Break-Before-Make Delay Measurement Setup

7.7 Transition Time

Transition time is defined as the time taken by the output of the device to rise (to 90% of the transition) or fall (to

10% of the transition) after the select signal (SELx) has fallen or risen to 50% of the transition. 图 7-8 shows the

setup used to measure transition time, denoted by the symbol t_TRAN

.

V_DD

V_SS

0.1 µF

V_S

3 V

0 V

V_DD

S1A

V_SS

V_SEL

t_r< 20 ns

t_f< 20 ns

50%

D1

Output

C_L

S1B

t_TRAN

2

t_TRAN

1

R_L

V_S

Output

0.9 V_S

S2A

S2B

V_S

D2

Output

C_L

0.1 V_S

0 V

R_L

t_TRAN= max ( t_TRAN1, t_TRAN2)

SELx

GND

V_SEL

图7-8. Transition Time Measurement Setup

7.8 Fault Response Time

Fault response time (t_RESPONSE) measures the delay between the source voltage exceeding the supply voltage

(V_DDor V_SS) by 0.5 V and the drain voltage failing to 50% of the maximum output voltage. 图 7-9 shows the

setup used to measure t_RESPONSE

.

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V_DD

V_SS

0.1 µF

Max positive fault

V_DD

S1A

V_SS

0 V

V_DD+ 0.5 V

60V/µs

ramp

60 V/µs

ramp

V_S

D1

Output

C_L

V_SS- 0.5 V

S1B

V_S

0 V

R_L

Max negative fault

t_{RESPONSE (VDD)}

V_DD

t_{RESPONSE (VSS)}

0 V

Output

S2A

S2B

D2

Output

C_L

Output

0 V

Output × 50%

V_S

R_L

V_SS

GND

t_RESPONSE= max ( t_{RESPONSE(VDD)}, t_{RESPONSE(VSS)}

)

图7-9. Fault Response Time Measurement Setup

7.9 Fault Recovery Time

Fault recovery time (t_RECOVERY) measures the delay between the source voltage falling from overvoltage

condition to below supply voltage (V_DDor V_SS) plus 0.5 V and the drain voltage rising from 0 V to 50% of the final

output voltage. 图7-10 shows the setup used to measure t_RECOVERY

.

V_DD

V_SS

0.1 µF

0 V

V_DD

S1A

V_SS

V_DD+ 0.5 V

V_SS- 0.5 V

V_S

t_{RECOVERY (VSS)}

0 V

D1

Output

C_L

0 V

t_{RECOVERY (VDD)}

S1B

V_S

R_L

S2A

S2B

Output

0 V

D2

Output

C_L

Output x 50%

Output × 50%

Output

V_S

R_L

GND

t_RECOVERY= max ( t_{RECOVERY(VDD)}, t_{RECOVERY(VSS)}

)

图7-10. Fault Recovery Time Measurement Setup

7.10 Fault Flag Response Time

Fault flag response time (t_{RESPONSE(FLAG)}) measures the delay between the source voltage exceeding the fault

supply voltage (V_DDor V_SS) by 0.5 V and the general fault flag (FF) pin to go below 10% of its original value. 图

7-11 shows the setup used to measure t_{RESPONSE(FLAG)}

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V_DD

V_SS

0.1 µF

V_DD

S1A

V_SS

0 V

V_DD+ 0.5 V

D1

Output

V_S

S1B

V_FN- 0.5 V

V_S

0 V

t_{RESPONSE(FLAG)_VDD}

5 V

R_L

C_L

t_{RESPONSE(FLAG)_VSS}

S2A

S2B

5 V

0 V

D2

Output

C_L

5 V

V_FF

V_S

R_L

0.5 V

R_PU

0 V

t_{RESPONSE(FLAG)}= max ( t_{RESPONSE(FLAG)_VDD}, t_{RESPONSE(FLAG)_VSS}

)

SF/FF

GND

C_{L_xF}

GND

图7-11. Fault Flag Response Time Measurement Setup

7.11 Fault Flag Recovery Time

Fault flag recovery time (t_{RECOVERY(FLAG)}) measures the delay between the source voltage falling from

overvoltage condition to below fault supply voltage (V_DDor V_SS) plus 0.5 V and the general fault flag (FF) pin to

rise above 3 V with 5 V external pull-up. 图7-12 shows the setup used to measure t_{RECOVERY(FLAG)}

.

V_DD

V_SS

0.1 µF

V_DD

S1A

V_SS

0 V

V_DD+ 0.5 V

V_DD- 0.5 V

D1

Output

C_L

V_S

S1B

V_S

R_L

0 V

t_{RECOVERY(FLAG)_VSS}

t_{RECOVERY(FLAG)_VDD}

S2A

S2B

5 V

V_FF

5 V

V_FF

D2

Output

C_L

5 V

3 V

V_S

R_L

R_PU

0 V

t_{RECOVERY(FLAG)}= max ( t_{RECOVERY(FLAG)_VDD}, t_{RECOVERY(FLAG)_VSS}

)

SF/FF

GND

C_{L_xF}

GND

图7-12. Fault Flag Recovery Time Measurement Setup

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7.12 Charge Injection

Charge injection is a measure of the glitch impulse transferred from the logic input to the signal path during logic

pin switching, and is denoted by the symbol Q_INJ. 图 7-13 shows the setup used to measure charge injection

from the source to drain.

V_DD

V_SS

0.1 µF

V_S

3 V

V_EN

V_DD

S1A

V_SS

t_r< 20 ns

t_f< 20 ns

D1

D2

Output

C_L

0 V

S1B

Output

V_D

V_OUT

Q_INJ= C_L×

V_OUT

S2A

S2B

V_S

Output

C_L

EN

V_EN

GND

图7-13. Charge-Injection Measurement Setup

7.13 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the

source pin (Sx) of an off-channel. 图7-14 shows the setup used to measure off isolation.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Network Analyzer

V_S

S

D

50

V_OUT

V_SIG

50

SxA / SxB / Dx

GND

50

图7-14. Off Isolation Measurement Setup

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7.14 Crosstalk

The following are two types of crosstalk that can be defined for the devices:

1. Intra-channel crosstalk (X_TALK(INTRA)): the voltage at the source pin (Sx) of an off-switch input, when a 1-

_RMSsignal is applied at the source pin of an on-switch input in the same channel, as shown in 图7-15.

V

2. Inter-channel crosstalk (X_TALK(INTER)): the voltage at the source pin (Sx) of an on-switch input, when a 1-

V_RMSsignal is applied at the source pin of an on-switch input in a different channel, as shown in 图7-16.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Network Analyzer

V_S

S1A

D1

50

V_OUT

S1B

S2A

50

V_SIG

50

D2

50

S2B

GND

50

图7-15. Intra-Channel Crosstalk Measurement Setup

V_DD

V_SS

0.1 µF

V_DD

V_SS

Network Analyzer

V_S

S1A

D1

50

V_OUT

50

S1B

S2A

50

V_SIG

50

D2

S2B

GND

50

图7-16. Inter-Channel Crosstalk Measurement Setup

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7.15 Bandwidth

Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to

the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. 图 7-17

shows the setup used to measure bandwidth of the switch.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Network Analyzer

V_S

S

D

50

V_OUT

V_SIG

50

SxA / SxB / Dx

GND

50

图7-17. Bandwidth Measurement Setup

7.16 THD + Noise

The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as

the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the

switch output. The on-resistance of the device varies with the amplitude of the input signal and results in

distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is

denoted as THD+N. 图7-18 shows the setup used to measure THD+N of the devices.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Audio Precision

S

D

40

V_OUT

V_S

R_L

SxA / SxB / Dx

GND

50

图7-18. THD+N Measurement Setup

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8 Detailed Description

8.1 Overview

The TMUX7436F device is a 44-V fault protected multiplexer with latch-up immunity in a 2:1, 2 channel

configuration. The device works well with dual supplies (±5 V to ±22 V), a single supply (8 V to 44 V), or

asymmetric supplies (such as VDD = 15 V, VSS = –5 V). The overvoltage protection feature on the source pins

works under powered and powered-off conditions, allowing for use in harsh industrial environments. The

powered-off condition includes floating power supplies, grounded power supplies, or power supplies at any level

that are below the undervoltage (UV) threshold.

8.2 Functional Block Diagram

V_DD

V_SS

S1A

S1B

D1

D2

S2A

S2B

SEL1

SEL2

EN

Fault Detection/

Switch Driver/

Logic Decoder

FF

SF

DR

TMUX7436F

8.3 Feature Description

8.3.1 Flat ON-Resistance

The TMUX7436F is designed with a special switch architecture to produce ultra-flat on-resistance (R_ON) across

most of the switch input operation region. The flat R_ONresponse allows the device to be used in precision sensor

applications since the R_ONis controlled regardless of the signals sampled. The architecture is implemented

without a charge pump so no unwanted noise is produced from the device to affect sampling accuracy.

8.3.2 Protection Features

The TMUX7436F offers a number of protection features to enable robust system implementations.

8.3.2.1 Input Voltage Tolerance

The maximum voltage that can be applied to any source input pin is +60 V or –60 V, regardless of supply

voltage. This allows the device to handle typical voltage fault condition in industrial applications. Caution: the

device is rated to handle a maximum stress of 85 V across different pins, such as the following:

1. Between source pins and supply rails: 85 V

For example, if the device is powered by V_DDsupply of 25 V, then the maximum negative signal level on any

source pin is –60 V to maintain the 60 V maximum rating on any source pin. If the device is powered by

V

_DDsupply of 40 V, then the maximum negative signal level on any source pin is reduced to –45 V to

maintain the 85 V maximum rating across the source pin and the supply.

2. Between source pins and the drain pin: 85 V

For example, if channel S1A is ON and the voltage on S1A pin is 40 V, then the drain voltage D1 is also 40

V. In this case, the maximum negative voltage allowed on S1B is –45 V to maintain the 85 V maximum

rating across the source pin and the drain pin.

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8.3.2.2 Powered-Off Protection

When the supplies of TMUX7436F are removed (V_DD/ V_SS= 0 V or floating), the source (Sx) pins of the device

remain in high impedance (Hi-Z) state, and the source (Sx) and drain (Dx) pins of the device remain within the

leakage performance mentioned in the Electrical Characteristics. Powered-off protection minimizes system

complexity by removing the need to control power supply sequencing of the system. The feature prevents errant

voltages on the input source pins from reaching the rest of the system and maintains isolation when the system

is powering up. Without powered-off protection, signals on the input source pins can back-power the supply rails

through internal ESD diodes and cause potential damage to the system. For more information on powered-off

protection, refer to the Eliminate Power Sequencing with Powered-Off Protection Signal Switches application

brief.

A GND reference must always be present to ensure proper operation. Source and drain voltage levels of up to

±60 V are blocked in the powered-off condition.

8.3.2.3 Fail-Safe Logic

Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting

the device from potential damage. The switch is specified to be in the OFF state, regardless of the state of the

logic signals. The logic inputs are protected against positive faults of up to +44 V in powered-off condition, but do

not offer protection against negative overvoltage condition.

Fail-safe logic also allows the TMUX7436F device to interface with a voltage greater than V_DDduring normal

operation to add maximum flexibility in system design. For example, with a V_DDof = 15 V, the logic control pins

could be connected to +24 V for a logic high signal which allows different types of signals, such as analog

feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the logic

inputs can be interfaced as high as 44 V.

8.3.2.4 Overvoltage Protection and Detection

The TMUX7436F detects overvoltage inputs by comparing the voltage on a source pin (Sx) with the supplies

(V_DDand V_SS). A signal is considered overvoltage if it exceeds the supply voltages by the threshold voltage (V_T).

The switch automatically turns OFF regardless of the logic controls when an overvoltage is detected. The source

pin becomes high impedance and ensures only small leakage current flows through the switch. The drain pin

(Dx) behavior can be adjusted by controlling the drain response (DR) pin in the following ways:

1. DR pin floating or driven above V_IH:

If the DR pin is driven above VIH level of the pin, then the drain pin becomes high impedance (Hi-Z) upon

overvoltage fault.

2. DR driven below V_IL:

If the DR pin is driven below VIL level of the pin, and the channel expeirencing the overvoltage fault

condition is currently being selected by the logic controls (EN, SELx), then the drain pin (Dx) is pulled to the

supply that was exceeded through a 40 kΩresistor. For example, if the source voltage exceeds V_DD, then

the drain output is pulled to V_DD. If the source voltage exceeds V_SS, then the drain output is pulled to V_SS

.

The pull-up/pull-down impedance is approximately 40 kΩ, and as a result, the drain current is limited during

a shorted load (to GND) condition.

图 8-1 shows a detailed view of the how the DR pin, SELx pin, and EN pin controls the output state of the drain

pin under a fault scenario.

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DR

V_DD

SELx

EN

Logic &

Fault

Detection

40 k

Sx

Dx

ESD

Protection

V_SS

GND

图8-1. Detailed Functional Diagram

8.3.2.5 Adjacent Channel Operation During Fault

When the logic pins are set to a channel under a fault, the overvoltage detection will trigger, the switch will open,

and the drain pin will operate as described in 节 8.3.2.4. During such an event, all other channels not under a

fault can continue to operate as normal. For example, if S1A voltage exceeds V_DD, and the logic pins are set to

S1A, and the DR pin is set to logic low, then the drain output is pulled to V_DD. Afterwards if the logic pins are

changed to set S1B, which is not in overvoltage or undervoltage, then the drain will disconnect from the pullup to

V_DDand the S1B switch will be enabled and connected to the drain, operating as normal, although there is still

an overvoltage condition present on S1A. If the logic pins are switched back to S1A, then the S1B switch will be

disabled, the drain pin will be pulled up to V_DDagain, and the switch from S1A to drain will be disabled until the

overvoltage fault is removed.

8.3.2.6 ESD Protection

All pins on the TMUX7436F support HBM ESD protection level up to ±6 kV, which helps prevent the device from

being damaged by ESD events during the manufacturing process.

The drain pins (Dx) have internal ESD protection diodes to the supplies V_DDand V_SS; therefore the voltage at

the drain pins must not exceed the supply voltages to prevent excessive diode current. The source pins have

specialized ESD protection that allows the signal voltage to reach ±60 V regardless of supply voltage level.

Exceeding ±60 V on any source input may damage the ESD protection circuitry on the device and cause the

device to malfunction if the damage is excessive.

8.3.2.7 Latch-Up Immunity

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the

low impedance path.

The TMUX7436F device is constructed on silicon on insulator (SOI) based process where an oxide layer is

added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from

forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due to

overvoltage or current injections. The latch-up immunity feature allows the TMUX7436F to be used in harsh

environments. For more information on latch-up immunity, refer to Using Latch Up Immune Multiplexers to Help

Improve System Reliability.

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8.3.2.8 EMC Protection

The TMUX7436F is not intended for standalone electromagnetic compatibility (EMC) protection in industrial

applications. There are three common high voltage transient specifications that govern industrial high voltage

transient specification: IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and IEC61000-4-5 (surge immunity). A

transient voltage suppressor (TVS), along with some low-value series current limiting resistor, are required to

prevent source input voltages from going above the rated ±60 V limits.

When selecting a TVS protection device, it is critical to ensure that the maximum working voltage is greater than

both the normal operating range of the input source pins to be protected and any known system common-mode

overvoltage that may be present due to miswiring, loss of power, or short circuit. 图8-2 shows an example of the

proper design window when selecting a TVS device.

Region 1 denotes normal operation region of TMUX7436F, where the input source voltages stay below the

supplies V_DDand V_SS. Region 2 represents the range of possible persistent DC (or long duration AC overvoltage

fault) presented on the source input pins. Region 3 represents the margin between any known DC overvoltage

level and the absolute maximum rating of the TMUX7436F. The TVS breakdown voltage must be selected to be

less than the absolute maximum rating of the TMUX7436F, but greater than any known possible persistent DC

or long duration AC overvoltage fault to avoid triggering the TVS inadvertently. Region 4 represents the margin

system designers must impose when selecting the TVS protection device to prevent accidental triggering of ESD

cells of the TMUX7436F device.

Internal ESD

Trigger Voltage

4

Device Absolute

Max Rating

TVS

Breakdown

Voltage

3

2

System

Overvoltage

Protection Window

Positive Supply

V_DD

0 V

1

Normal Operation

Negative Supply

V_SS

2

3

4

System

Overvoltage

Protection Window

TVS

Breakdown

Voltage

Device Absolute

Max Rating

Internal ESD

Trigger Voltage

图8-2. System Operation Regions and Proper Region of Selecting a TVS Protection Device

8.3.3 Overvoltage Fault Flags

The voltages on the source input pins of the TMUX7436F are continuously monitored, and the status of whether

an overvoltage condition occurs is indicated by an active low general fault flag (FF). The voltage on the FF pin

indicates if any of the source input pins are experiencing an overvoltage condition. If any source pin voltage

exceeds the fault supply voltages by a V_T, then the FF output is pulled-down to below V_OL

.

The specific fault (SF) output pins, on the other hand, can be used to decode which inputs are experiencing an

overvoltage condition. As provided in the 表 8-1, the SF pin is pulled-down to below V_OLwhen an overvoltage

condition is detected on a specific source input pin, depending on the state of the SEL1, SEL2, and EN logic

pins.

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Both the FF pin and the SF pin are an open-drain output and an external pull-up resistor of 1 kΩ is

recommended. The pull-up voltage can be in the range of 1.8 V to 5.5 V, depending on the controller voltage the

device interfaces with.

8.3.4 Bidirectional Operation

The TMUX7436F conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx).

However, it is noted that the overvoltage protection is implemented only on the source (Sx) side. The voltage on

the drain is only allowed to swing between V_DDand V_SSand no overvotlage protection is available on the drain

side.

The flatest on-resistance region extends from V_SSto roughly 3 V below V_DD. Once the signal is within 3 V of V_DD

the on-resistance will expoentially increase and may impact desired signal transmission.

8.3.5 1.8 V Logic Compatible Inputs

The TMUX7436F device has 1.8 V logic compatible control for all logic control inputs. 1.8 V logic level inputs

allows the TMUX7436F to interface with processors that have lower logic I/O rails and eliminates the need for an

external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations,

refer to Simplifying Design with 1.8 V logic Muxes and Switches.

8.3.6 Integrated Pull-Down Resistor on Logic Pins

The TMUX7436F has internal weak pull-down resistors to GND to ensure the logic pins are not left floating. The

value of this pull-down resistor is approximately 4 MΩ, but is clamped to about 1 µA at higher voltages. This

feature integrates up to four external components and reduces system size and cost.

8.4 Device Functional Modes

The TMUX7436F offers two modes of operation (normal mode and fault mode) depending on whether any of the

input pins experience an overvoltage condition.

8.4.1 Normal Mode

In Normal mode operation, signals of up to V_DDand V_SScan be passed through the switch from source (Sx) to

drain (Dx) or from drain (Dx) to source (Sx). As provided in 表 8-1, the select pins (SELx) and enable pin (EN)

determines which switch path to turn on. The following conditions must be satisfied for the switch to stay in the

ON condition:

• The difference between the supples (V_DD–V_SS) must be greater than or equal to 8 V, with a minimum V_DD

of 5 V.

• The input signals on the source (Sx) or the drain (Dx) must be be between V_DD+ V_Tand V_SS–V_T.

• The logic control (SELx and EN) must have selected the switch.

8.4.2 Fault Mode

The TMUX7436F enters into Fault mode when any of the input signals on the source (Sx) pins exceed V_DDor

V_SSby a threshold voltage V_T. Under the overvoltage condition, the switch input experiencing the fault

automatically turns off regardless of the logic status, and the source pin becomes high impedance with negligible

amount of leakage current flowing through the switch. For more information about how the drain pain (Dx)

behavior under the Fault mode can be programmed, see 节8.3.2.4.

In the Fault mode, the general fault flag (FF) is asserted low. 表 8-1 provides how the specific flag (SF) is

asserted low depending on the status of the logic control pins SELx and EN.

The overvoltage protection is provided only for the source (Sx) input pins. The drain (Dx) pin, if used as signal

input, must stay in between V_DDand V_SSat all times since no overvoltage protection is implemented on the drain

pin.

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8.4.3 Truth Tables

表8-1 and 表8-2 provides the truth tables for the TMUX7436F under normal and fault conditions.

表8-1. TMUX7436F Truth Table

Fault Condition

Normal Condition

EN

SEL2

SEL1

State of Specific Flag (SF) when fault occurs on

On Switch

None

S1A

0

S1B

1

S2A

1

S2B

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

None

1

0

1

None

1

0

None

1

0

1

S1B, S2B

S1A, S2B

S1B, S2A

S1A, S2A

0

1

0

1

0

1

0

1

Take note, more than one source pin can be in fault at a given time. As 表8-1 provides, the SF pin will assert low

even when multiple source pins are under fault.

表8-2. TMUX7436F DR Truth Table

Dx State During Fault

DR PIN STATE

Condition

0

1

Pulled up to V_DDor V_SS

Open (HI-Z)

If unused, then SELx pins must be tied to GND to ensure the device does not consume additional current (for

more information, refer to Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx or Dx)

should be connected to GND.

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The TMUX7436F is a part of the fault protected switches and multiplexers family of devices. The abilty to protect

downstream components from overvoltage events up to ±60 V and latch-up immunity features makes these

switches and multiplexers suitable for harsh environments.

9.2 Typical Application

The need to monitor remote sensors is common among factory automation control systems. For example, an

analog input module or mixed module (AI, AO, DI, and DO) of a programmable logic controller (PLC) will

interface to a field transmitter to monitor various process sensors at remote locations around the factory. A

switch or multiplexer is often used to connect multiple inputs from the system and reduce the number of

downstream channels.

There are a number of fault cases that may occur that can be damaging to many of the integrated circuits. Such

fault conditions may include, but are not limited to, human error from wiring the connections incorrectly,

component failure, wire shorts, electromagnetic interference (EMI), transient distrubances, and more.

Supply

Power Module

GND

Local Control Side

TMUX7436F

+15V -15V

V_DDV_SS

+

-

+24V

+60V

Field Side

Di eren al

Output

S1A

S1B

+15V

D1

D2

Sensors

Fault

Protected

Mux Inputs

+

–

Control

& Processing

DAC

ADC

RG

S2A

S2B

+

-

Di eren al

Output

-15V

Logic Select Pins

SEL2

SEL1

1.8V Logic

Signals

图9-1. Typical Application

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9.2.1 Design Requirements

表9-1. Design Parameters

PARAMETER

VALUE

+15 V

Positive supply (V_DD) mux

Negative supply (V_SS) mux

Power board supply voltage

Input or output signal range non-faulted

Overvoltage protection levels

Control logic thresholds

−15 V

24 V

−15 V to 15 V

−60 V to 60 V

1.8 V compatible, up to 44 V

−40°C to +125°C

Temperature range

9.2.2 Detailed Design Procedure

The normal operation of the application is to take multiple differential inputs and use a 2:1 multiplexer to pass the

signal to the downstream instrumentation amplifier. A fault protected switch can add extra robustness to the

sytem against fault conditions while also reducing the number of components required to interface with the

systems physical input channels.

The 图 9-1 shows the case where a human wired the condition incorrectly and one of the input connectors

shorted to the power board supply voltage. If the board supply voltage is higher than the power supply of the

multiplexer, then the TMUX7436F device will disconnect the source input from passing the signal to protect the

downstream components. The drain pin of the channels can either be pulled up to the supply voltage (V_DDand

V

_SS) through a 40 kΩ resistor or be left floating depending on the state of the DR pin. This can be configured to

match the system requirements on how to handle a fault condition.

9.2.3 Application Curves

The previous example shows how the fault protection of the TMUX7436F is utilized to protect downstream

components from damage due to wiring the connections incorrectly from the power module. 图 9-2 shows an

example of positive overvoltage fault response with a fast fault ramp rate of 40 V/µs. 图9-3 shows the extremely

flat on-resistance across source voltage while operating within a common signal range of ±10 V. These features

make the TMUX7436F an ideal solution for factory automation applications that can face various fault conditions

but also require excellent linearity and low distortion.

70

65

60

55

50

45

40

35

30

25

20

15

10

5

9.3

9.2

9.1

9

V_DD= 13.5 V, V_SS= -13.5 V

V_DD= 15 V, V_SS= -15 V

V_DD= 16.5 V, V_SS= -16.5 V

V_DD= 18 V, V_SS= -18 V

V_DD= 20 V, V_SS= -20 V

V_DD= 22 V, V_SS= -22 V

40V/s Fault Ramp

SOURCE

8.9

8.8

8.7

8.6

8.5

8.4

8.3

V_DD

FF/SF

DRAIN

0

-5

-10

-1.5

-10

-8

-6

-4

-2

0

2

4

6

8

10

-1

-0.5

0

0.5

1

1.5

2

2.5

3

V_Sor V_D- Source or Drain Voltage (V)

Time (s)

图9-3. R_ONFlatness in Non-Fault Region

图9-2. Positive Overvoltage Response

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10 Power Supply Recommendations

The TMUX7436F operates across a wide supply range of ±5 V to ±22 V (8 V to 44 V in single-supply mode). It

also performs well with asymmetrical supplies such as V_DD= 12 V and V_SS= –5 V. Use a supply decoupling

capacitor ranging from 1 µF to 10 µF at the V_DDand V_SSpins to ground for improved supply noise immunity.

Always ensure the ground (GND) connection is established before supplies are ramped.

11 Layout

11.1 Layout Guidelines

图 11-1 and 图 11-2 shows an example of a PCB layout with the TMUX7436F. The following are some key

considerations:

• Decouple the V_DDand V_SSpins with a 1-µF capacitor, placed as close to the pin as possible. Make sure that

the capacitor voltage rating is sufficient for the V_DDand V_SSsupplies.

• Multiple decoupling capacitors can be used if their is a lot of noise in the system. For example, a 0.1-µF and

1-µF can be placed on the supply pins. If multiple capacitors are used, placing the lowest value capacitor

closest to the supply pin is recommended.

• Keep the input lines as short as possible.

• Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

11.2 Layout Example

Wide (low inductance)

trace for power

Via to power plane

1k

1kΩ

Via to

ground plane

1k

SEL1

SF

FF

C

Wide (low inductance)

trace for power

S1A

EN

D1

S1B

V_SS

EN

VDD

S2B

D2

D1

V_DD

S2B

D2

TMUX7436F

S1B

VSS

GND

NC

C

S2A

SEL2

Wide (low inductance)

trace for power

DR

Via to ground plane

Via to

ground plane

图11-2. WQFN Layout Example

图11-1. TSSOP Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

• Texas Instruments, Implications of Slow or Floating CMOS Inputs application note

• Texas Instruments, Improving Analog Input Modules Reliability Using Fault Protected Multiplexers application

report

• Texas Instruments, Multiplexers and Signal Switches Glossary application report

• Texas Instruments, Protection Against Overvoltage Events, Miswiring, and Common Mode Voltages

application report

• Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability application

report

• Texas Instruments, Using Latch Up Immune Multiplexers to Help Improve System Reliability

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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型号：	TMUX7436FPWR
厂家：	TEXAS INSTRUMENTS
描述：	具有故障保护功能、闩锁效应抑制和 1.8V 逻辑电平的 ±60V 双路 2:1 多路复用器 \| PW \| 16 \| -40 to 125 复用器
文件：	总46页 (文件大小：3001K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMUX7436FPWR [TI]

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