TMUXHS4212RKSR [TI]
2 通道 16Gbps 2:1/1:2 差分多路复用器/多路信号分离器 | RKS | 20 | 0 to 70;
| 型号： | TMUXHS4212RKSR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2 通道 16Gbps 2:1/1:2 差分多路复用器/多路信号分离器 | RKS | 20 | 0 to 70 输出元件 复用器 |
| 文件： | 总29页 (文件大小：2796K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUXHS4212
ZHCSKO2A –MAY 2020 –REVISED MAY 2022
TMUXHS4212 双通道差分2:1 多路复用器或1:2 多路信号分离器
1 特性
3 说明
• 提供双向2:1 多路复用器或1:2 多路信号分离器
• 支持USB 3.2，速率高达10Gbps (Gen 2.0)；支持
PCI Express，速率高达16Gbps (Gen 4.0)
• 还支持SATA、SAS、Mipi® DSI/CSI、FPD-Link
III、LVDS、SFI 和以太网®接口
• 13GHz 的-3dB 差分带宽
• 动态特性：
– 插入损耗= −1.3/−1.8dB（5/8GHz 时）
– 回损= −13/−12dB（5/8GHz 时）
– 关断隔离= −22/−20dB（5/8GHz 时）
• 自适应共模电压跟踪
• 支持高达0V 至1.8V 的共模电压
• 单电源电压VCC 为3.3 或1.8V
• 超低有效(180μA) 和待机功耗(< 2μA)
• -40° 至105°C 的工业温度选项
• 采用2.5mm x 4.5mm QFN 封装
TMUXHS4212 是一款采用多路复用器或多路信号分离
器配置的高速双向无源开关。此开关适用于多种应用，
包括 USB Type-C™ 和 PCI Express。TMUXHS4212
是一款通用模拟差分无源多路复用器或多路信号分离
器， 适用于许多高速差分接口， 其数据速率高达
16Gbps。该器件可用于电气通道具有信号完整性裕度
的更高数据速率。TMUXHS4212 支持差分信号，其共
模电压范围 (CMV) 高达 0V 至 1.8V，差分振幅高达
1800mVpp。自适应 CMV 跟踪可确保通过器件的通道
在整个共模电压范围内保持不变。
TMUXHS4212 的动态特性允许进行高速开关，使信号
眼图具有最小的衰减，并且几乎不会增加抖动。该器件
的芯片设计经过优化，可在较高信号频谱上实现出色的
频率响应。其芯片信号布线和开关网络相匹配，以实现
最佳的差分对内延迟差性能。
TMUXHS4212 具有扩展的工业温度范围，适合多种严
苛应用，包括工业和高可靠性用例。
2 应用
器件信息(1)
• PC 和笔记本电脑
• 智能手机、平板电脑和电视
• 游戏、家庭影院和娱乐
• 数据中心和企业级计算
• 医疗应用
• 测试和测量
• 工厂自动化和控制
• 航天和国防
封装尺寸（标称
器件型号
封装
值）
TMUXHS4212
TMUXHS4212I
2.50mm × 4.50mm
× 0.5mm 间距
VQFN (20)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 电子销售终端(EPOS)
• 无线基础设施
USB Type-C
USB Type-C
PCIe Card
RX1
TX1
x16
Slot
x8
RX
Connector-B
TX
x8
TX2
RX1
RX2
RX2
TX1
TX2
h
c
-
8
ch
-
RXB
XB
8
TMUXHS4212
T
RX 8-ch
TX 8-ch
CPU
TX
RX
USB
Host
USB
Device
CC1 CC2
h
CC2
CC1
c
-
8
h
c
PCIe Card
SEL
SEL
-
8
XA
T
RXA
CC/PD
Controller
CC/PD
Controller
x8
Slot
Connector-A
x8
USB-C DFP Port with USB 3.2
USB-C UFP Port with USB 3.2
PCIe 3.0/4.0 Lane Switching
应用用例
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEP7
TMUXHS4212
ZHCSKO2A –MAY 2020 –REVISED MAY 2022
www.ti.com.cn
Table of Contents
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Applications.................................................. 13
9.3 Systems Examples................................................... 18
10 Power Supply Recommendations..............................18
11 Layout...........................................................................19
11.1 Layout Guidelines................................................... 19
11.2 Layout Example...................................................... 19
12 Device and Documentation Support..........................20
12.1 接收文档更新通知................................................... 20
12.2 支持资源..................................................................20
12.3 Trademarks.............................................................20
12.4 Electrostatic Discharge Caution..............................20
12.5 术语表..................................................................... 20
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 High-Speed Performance Parameters........................5
6.7 Switching Characteristics............................................6
6.8 Typical Characteristics................................................7
7 Parameter Measurement Information............................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
Information.................................................................... 20
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (May 2020) to Revision A (May 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 更新了“特性”部分中的单电源电压VCC ..........................................................................................................1
• Updated the RSVD1 and RSVD2 description.....................................................................................................3
• Changed single supply voltage VCC from: 3.3 V to: 3.3 or 1.8 V ....................................................................... 3
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5 Pin Configuration and Functions
OEn
A0p
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
B0p
B0n
B1p
B1n
C0p
C0n
C1p
C1n
A0n
Thermal
Pad
GND
VCC
A1p
A1n
SEL
Not to scale
图5-1. RKS Package, 20-Pin VQFN (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
A0n
NO.
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G
Port A, channel 0, high-speed negative signal
Port A, channel 0, high-speed positive signal
Port A, channel 1, high-speed negative signal
Port A, channel 1, high-speed positive signal
Port B, channel 0, high-speed negative signal (connector side)
Port B, channel 0, high-speed positive signal (connector side)
Port B, channel 1, high-speed negative signal
Port B, channel 1, high-speed positive signal
Port C, channel 0, high-speed negative signal
Port C, channel 0, high-speed positive signal
Port C, channel 1, high-speed negative signal
Port C, channel 1, high-speed positive signal
Ground
A0p
A1n
A1p
B0n
B0p
B1n
B1p
C0n
C0p
C1n
C1p
GND
3
8
7
18
19
16
17
14
15
12
13
5, 11, 20
Active-low chip enable. The pin can be connected to GND if always on functional
behavior is desired.
L: Normal operation, H: Shutdown. If always ON, behavior of the device is desired.
The pin can be permanently connected to GND.
OEn
2
I
RSVD1
RSVD2
1
NA
NA
Reserved pins. Connect both pins to VCC
10
Port select pin.
L: Port A to Port B, H: Port A to Port C
SEL
VCC
9
6
I
P
3.3 V or 1.8 V power
(1) I = input, O = output, G = ground, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCC-
Supply voltage
4
V
–0.5
ABSMAX
VHS-
Voltage
Differential I/O
Control pins
2.4
V
–0.5
ABSMAX
VCTR-
Voltage
VCC+0.4
150
V
–0.5
–65
ABSMAX
TSTG
Storage temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under
Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
VESD
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.71
TYP
1.8
MAX
1.98
3.6
UNIT
V
1.8 V mode
3.3 V mode
VCC
Supply Voltage
3.0
3.3
V
VCC-RAMP Supply voltage ramp time
0.1
100
ms
V
VIH
Input high voltage
SEL, OEn pins
SEL, OEn pins
0.75 VCC
VIL
Input low voltage
0.25 VCC
1.8
V
VDIFF
High-speed signal pins differential voltage
0
0
Vpp
V
VCC 1.8 V mode
VCC 3.3 V mode
TMUXHS4212
TMUXHS4212I
1.2
VCM
High speed signal pins common mode voltage
Operating free-air/ambient temperature
0
1.8
V
0
70
°C
°C
TA
-40
105
6.4 Thermal Information
TMUXHS4212
RKS (VQFN)
20 PINS
53.0
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance - High K
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
52.3
27.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.9
ψJT
26.9
ψJB
RθJC(bot)
11.1
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and IC Package ThermalMetrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature and supply voltage range (unless otherwise noted)
PARAMETER
Device active current
TEST CONDITIONS
MIN
TYP
180
2
MAX
UNIT
OEn = 0; 0 V ≤VCM ≤1.8; SEL = 0 or
ICC
250
µA
VCC
ISTDN
CON
RON
Device shutdown current
Output ON capacitance to GND
Output ON resistance
OEn = VCC
5
0.6
8.4
µA
pF
OEn = 0
5
0 V ≤VCM ≤1.8 V; IO = –8 mA
Ω
Ω
On-resistance match between pairs for the same
channel at same VCM, VCC and TA
0.5
ΔRON
On-resistance flatness RON(MAX) –RON(MIN)
over VCM range for the same channel at
same VCC and TA
RFLAT_ON
0.75
Ω
IIH,CTRL
IIL,CTRL
RCM,HS
Input high current, control pins (SEL, OEn)
Input low current, control pins (SEL, OEn)
Common mode resistance to ground on Ax pins
VIN = VCC
2
1
µA
µA
VIN = 0 V
Each pin to GND
1.0
1.6
MΩ
VIN = 1.8 V for selected port - A and B with
SEL = 0, and A and C with SEL = VCC
IIH,HS,SEL
Input high current, high-speed pins [Ax/Bx/Cx][p/n]
8
µA
VIN = 1.8 V for non-selected port - C with
SEL = 0, and B with SEL = VCC
IIH,HS,NSEL
IIL,HS
IHIZ,HS
RA,p2n
Input high current, high-speed pins [Ax/Bx/Cx][p/n]
Input low current, high-speed pins [Ax/Bx/Cx][p/n]
150
1
µA
µA
(1)
VIN = 0 V
OEn = VCC; Ax[p/n] = 1.8 V, [B and
C]x[p/n] = 0 V and Ax[p/n] = 0 V, [B and
C]x[p/n] = 1.8 V
Leakage current through turned off switch between
Ax[p/n] to [B]x[p/n] and [C]x[p/n]
5
µA
DC Impedance between p and n for Ax pins
OEn = 0 and VCC
20
KΩ
(1) There is a 20-kΩpull-down in non-selected port.
6.6 High-Speed Performance Parameters
PARAMETER
ƒ= 10 MHz
ƒ= 2.5 GHz
ƒ= 4 GHz
TEST CONDITION
MIN
TYP
MAX
UNIT
-0.5
-0.8
-1.1
-1.3
-1.8
-2.1
13
IL
Differential insertion loss
–3-dB bandwidth
dB
GHz
dB
ƒ= 5 GHz
ƒ= 8 GHz
ƒ= 10 GHz
BW
RL
-28
-17
-13
-13
-12
-12
-55
-27
-24
-22
-20
-18
ƒ= 10 MHz
ƒ= 2.5 GHz
ƒ= 4 GHz
ƒ= 5 GHz
ƒ= 8 GHz
ƒ= 10 GHz
ƒ= 10 MHz
ƒ= 2.5 GHz
ƒ= 4 GHz
ƒ= 5 GHz
ƒ= 8 GHz
ƒ= 10 GHz
Differential return loss
OIRR
Differential OFF isolation
dB
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MAX UNIT
6.6 High-Speed Performance Parameters (continued)
PARAMETER
TEST CONDITION
ƒ= 10 MHz
MIN
TYP
-65
-40
-35
-32
-30
-27
ƒ= 2.5 GHz
ƒ= 4 GHz
ƒ= 5 GHz
ƒ= 8 GHz
ƒ= 10 GHz
XTALK
Differential crosstalk
dB
Mode conversion - differential to
common mode
SCD11,22
SCD21,12
SDC11,22
SDC21,12
-29
-27
-29
-26
dB
dB
dB
dB
ƒ= 5 GHz
ƒ= 5 GHz
ƒ= 5 GHz
ƒ= 5 GHz
Mode conversion - differential to
common mode
Mode conversion - common mode
to differential
Mode conversion - common mode
to differential
6.7 Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
tPD
Switch propagation delay
f = 1 Ghz
70
ps
tSW_ON_CM_SHIF
Switching time SEL-to-Switch ON
Switching time SEL-to-Switch ON
For different CMV
For same CMV
For different CMV
For same CMV
f = 1 Ghz
5
100
1
us
ns
us
ns
ps
ps
T
tSW_ON
tSW_OFF_CM_SHI
Switching time SEL-to-Switch OFF
Switching time SEL-to-Switch OFF
FT
tSW_OFF
100
8
Intra-pair output skew between P and N pins for same
channel
tSK_INTRA
tSK_INTER
Inter-pair output skew between channels
f = 1 Ghz
10
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6.8 Typical Characteristics
图6-2. Jitter Decomposition of 10 Gbps PRBS-7
Signals Through a Typical TMUXHS4212 Channel
in TI Evaluation Board
图6-1. Jitter Decomposition of 10 Gbps PRBS-7
Signals Through Calibration Traces in TI
Evaluation Board
图6-3. Jitter Decomposition of 16 Gbps PRBS-7
Signals Through Calibration Traces in TI
Evaluation Board
图6-4. Jitter Decomposition of 16 Gbps PRBS-7
Signals Through a Typical TMUXHS4212 Channel
in TI Evaluation Board
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7 Parameter Measurement Information
VCC
RSC = 50 Ω
Bxp/Cxp
Bxn/Cxn
Axp
RL = 50 Ω
RL = 50 Ω
RSC = 50 Ω
Axn
SEL
图7-1. Test Setup
50%
50%
SEL
90%
10%
VOUT
tSW_ON
tSW_OFF
图7-2. Switch On and Off Timing Diagram
2.6-V Max
50%
50%
VIN
0 V
2.6-V Max
50%
50%
VOUT
0 V
tPD
VOUTp
50%
TSK_INTRA
VOUTn
B0/C0
VOUT
50%
50%
50%
50%
B1/C1
VOUT
tSK_INTER
图7-3. Timing Diagrams and Test Setup
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8 Detailed Description
8.1 Overview
The TMUXHS4212 is a generic analog differential passive mux or demux that can work for any high-speed
interface with differential signaling where common mode voltage (CMV) and differential amplitude up to 1800
mVpp. It employs adaptive input voltage tracking that ensures the channel remains unchanged for the entire
common mode voltage range. Two channels of the device can be used for electrical signals that have different
CMV between them. Two channels can also be used in such a way that the device switches two different
interface signals with different data and electrical characteristics.
Excellent dynamic characteristics of the device allow high speed switching with minimum attenuation to the
signal eye diagram with very little added jitter. While the device is recommended for the interfaces up to 16
Gbps, actual data rate where the device can be used highly depends on the electrical channels. For low loss
channels where adequate margin is maintained, the device can potentially be used for higher data rates.
The TMUXHS4212 is only recommended for differential signaling. However, certain low voltage single ended
signaling (such as, Mipi DPHY LP signaling) can pass through the device. It is recommended to analyze the data
line biasing of the device for such single ended use cases.
The TMUXHS4212 comes in two different pinout options that provide layout implementation choices.
8.2 Functional Block Diagram
B0p
B0n
A0p
A0n
B1p
VCC
B1n
Switch
OEn
Regula on
SEL_int
and Bias
SEL
Circuits
C0p
C0n
GND
A1p
A1n
C1p
C1n
8.3 Feature Description
8.3.1 Output Enable and Power Savings
The TMUXHS4212 has two power modes, active/normal operating mode and standby/shutdown mode. During
standby mode, the device consumes very-little current to achieve ultra low power in systems where power
saving is critical. To enter standby mode, the OEn control pin is pulled high through a resistor and must remain
high. For active/normal operation, the OEn control pin should be pulled low to GND or dynamically controlled to
switch between H or L.
The TMUXHS4212 consumes 180 μA of power when operational and has a shutdown mode exercisable by the
OEn pin resulting < 2 µA.
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8.3.2 Data Line Biasing
The TMUXHS4212 has a weak pull-down of 1 MΩ from A[0/1][p/n] pins to GND. While these resistors biases
the device data channels to common mode voltage (CMV) of 0 V with very weak strength, it is recommended
that the device is biased by a stronger impedance from either side of the device to a valid value in the range of 0
– 1.8 V. To avoid double biasing, ensure that the appropriate ac coupling capacitors are on either side of the
device.
In certain use cases, if both sides of the TMUXHS4212 are ac coupled, then it is recommended to use
appropriate CMV biasing for the device. 10 kΩ to GND or any other bias voltage in the CMV range for each
A[0/1][p/n] pin will suffice for most use cases.
The high-speed data ports incorporate 20 kΩpull-down resistors that are switched in when a port is not selected
and switched out when the port is selected. For example, when SEL = L, the C[0/1][p/n] pins have 20 kΩ
resistors to GND. The feature ensures that the unselected port is always biased to a known voltage for long term
reliability of the device and the electrical channel.
The positive and negative terminals of data pins A[0/1] have a weak (20 kΩ) differential resistor for device
switch regulation operation. This does not impact signal integrity or functionality of high speed differential
signaling that typically has much stronger differential impedance (such as 100 Ω).
8.4 Device Functional Modes
表8-1. Port Select Control Logic(1)
PORT B OR PORT C CHANNEL CONNECTED TO PORT A CHANNEL
PORT A CHANNEL
SEL = L
SEL = H
A0p
A0n
A1p
A1n
B0p
C0p
B0n
C0n
B1p
C1p
B1n
C1n
(1) The TMUXHS4212 can tolerate polarity inversions for all differential signals on Ports A, B, and C.
Ensure that the same polarity is maintained on Port A versus Ports B or C in such flexible
implementation.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TMUXHS4212 is a generic 2-channel high-speed mux or demux type of switch that can be used for routing
high-speed signals between two different locations on a circuit board. The TMUXHS4212 supports many high-
speed data protocols, provided the signals' differential amplitude and common mode voltage are within <1800
mVpp and a common mode voltage is <1.8 V. The TMUXHS4212 can be used for many high speed interfaces
including the following:
• Universal Serial Bus (USB) 3.2 Gen 1.0 and 2.0
• USB Type-C
• Peripheral Component Interconnect Express (PCIe™) Gen 1.0, 2.0, 3.0, and 4.0
• Serial ATA (SATA/eSATA)
• Serial Attached SCSI (SAS)
• DisplayPort (DP) 1.4 and 2.0
• Thunderbolt™ (TBT) 3.0
• Mipi Camera Serial Interface (CSI-2), Display Serial Interface (DSI)
• Low Voltage Differential Signalling (LVDS)
• Serdes Framer Interface (SFI)
• Ethernet Interfaces
The device’s mux or demux selection pin SEL can easily be controlled by an available GPIO pin of a controller
or hard tie to voltage level H or L as an application requires.
The TMUXHS4212 with adaptive voltage tracking technology can support applications where the common mode
is different between the RX and TX pair. The switch paths of the TMUXHS4212 have internal weak pull-down
resistors of 1 MΩ on the A port pins. While these resistors bias the device data channels to common mode
voltage (CMV) of 0 V with a weak strength, it is recommended that the device is biased from either side of the
device to a valid value in the range of 0 – 1.8 V. It is expected that the system/host controller and Device/End
point common mode bias impedances are much stronger (smaller) than the TMUXHS4212 internal pull-down
resistors; therefore, they are not impacted.
Many interfaces require ac coupling between the transmitter and receiver. The 0201 or 0402 capacitors are the
preferred option to provide ac coupling. Avoid the 0603 and 0805 size capacitors and C-packs. When placing ac
coupling capacitors, symmetric placement is best. The capacitor value must be chosen according to the specific
interface the device is being used. The value of the capacitor should match for the positive and negative signal
pair. For many interfaces (such as, USB 3.2 and PCIe) the designer should place them along the TX pairs on the
system board, which are usually routed on the top layer of the board. Depending upon the application and
interface specifications, use the appropriate value for ac coupling capacitors.
The ac coupling capacitors have several placement options. Typical use cases warrant that the capacitors are
placed on one side of the TMUXHS4212. In certain use cases, if both sides of the TMUXHS4212 are ac coupled,
then it is recommended to use appropriate CMV biasing for the device. 10 kΩ to GND or any other bias voltage
in the range of 0 – 1.8 V for each A[0/1][p/n] pin will suffice for most use cases. 图 9-1 shows a few placement
options. Some interfaces such as USB SS and PCIe recommends ac coupling capacitors on the TX signals
before it goes to a connector. Option (a) features TX ac coupling capacitors on the connector side of the
TMUXHS4212. Option (b) illustrates the capacitors on the host of the TMUXHS4212. Option (c) showcases
where the TMUXHS4212 is ac coupled on both sides. Range for VBIAS is range of 0 –1.8 V.
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Device/EndPoint Board
Device/EndPoint Board
B0p
B0n
B0p
B0n
RX
RX
RX
RX
TX
Device/
EndPoint
Device/
EndPoint
B0p
B0p
B0n
B1p
B1p
B1n
TX
RX
TX
TX
TX
TX
TX
TX
B0n
B1n
Host
Host
RX
B1p
B1p
B1n
RX
RX
B1n
C0p
C0p
C0n
RX
RX
RX
TX
RX
TX
C0n
Device/
EndPoint
Device/
EndPoint
C1p
C1p
C1n
TX
TX
C1n
Host Board
Host Board
Device/EndPoint Board
Device/EndPoint Board
(a)
(b)
Device/EndPoint Board
RX
VBIAS
B0p
B0n
Device/
EndPoint
B0p
B0n
B1p
B1n
TX
TX
Host
RX
B1p
B1n
C0p
C0n
RX
Device/
EndPoint
C1p
C1n
VBIAS
TX
Host Board
Device/EndPoint Board
(c)
图9-1. AC Coupling Capacitors Placement Options Between Host and Device/Endpoint Through
TMUXHS4212
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9.2 Typical Applications
9.2.1 USB 3.2 Implementation for USB Type-C
The TMUXHS4212 can be used in USB Type-C implementation to mux USB 3.2 superspeed signals (TX1 and
RX1 pairs versus TX2 and RX2 pairs) to accommodate plug flips. In typical use cases, the mux selection is done
by a USB Type-C Channel Configuration (CC) or Power Delivery (PD) controller. The device can used on a USB
Type-C DFP, UFP, or DRP port. 图 9-2 shows two USB Type-C connector applications with both a host and
device side. The cable between the two connectors swivels the pairs to properly route the signals to the correct
pin. The other applications are more generic because different connectors can be used.
TXp1
Device/Hub
Board
A2
A3
TXp1
TXn1
Host Board
B0p
B0n
A2
A3
B0p
B0n
TXn1
TXp
TXn
TXp2
TXn2
TXp
A0p
A0n
B2
B3
TXp2
TXn2
C0p
C0n
A0p
A0n
TX
C0p
C0n
B2
B3
TX
TXn
Device
/Hub
Host
RXp
RXn
RXp
RXn
A1p
A1n
A1p
A1n
RX
RXP1
RXn1
RX
B1p
B1n
B11
B10
RXP1
RXn1
B1p
B1n
B11
B10
OEn
RXp2
RXn2
OEn
A11
A10
RXp2
RXn2
Optional
C1p
C1n
A11
A10
C1p
C1n
Optional
Controller
Controller
10 kW
GND
10 kW
GND
VCC
VCC
0.1 µF
0.1 µF
VCC
CC/PD
Controller
VCC
CC1
A5
B5
CC1
A5
B5
CC/PD
Controller
CC2
CC2
Down Facing Port (DFP)
Up Facing Port (UFP)
图9-2. USB 3.2 Implementation for USB Type-C Connector
9.2.1.1 Design Requirements
The TMUXHS4212 can be designed into many different applications. All the applications have certain
requirements for the system to work properly. The TMUXHS4212 requires 3.3 V ±10% VCC rail. The OEn pin
must be low for the device to work; otherwise, it disables the outputs. A processor can drive the OEn pin. The
expectation is that one side of the device has ac coupling capacitors. 表 9-1 provides information on expected
values to perform properly.
表9-1. Design Parameters
DESIGN PARAMETER
VALUE
VCC
3.3 V
AXp/n, BXp/n, CXp/n CM input voltage
Control/OEn pin max voltage for low
Control/OEn pin min voltage for high
ac coupling capacitor
0 V to 1.8 V
0.5 V
1.42 V
75 nF to 265 nF
1 kΩto 100 kΩ
RBIAS (图9-2) when needed
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9.2.1.2 Detailed Design Procedure
The TMUXHS4212 is a high-speed passive switch device that can behave as a mux or demux. Because this is a
passive switch, signal integrity is important because the device provides no signal conditioning capability. The
device can support 2 to 3 inches of board trace and a connector on either end.
To design in the TMUXHS4212, the designer needs to understand the following:
• Determine the loss profile between circuits that are to be muxed or demuxed.
• Provide clean impedance and electrical length matched board traces.
• Provide a control signal for the SEL and OEn pins.
• The thermal pad must be connected to ground.
• See the application schematics on recommended decouple capacitors from VCC pins to ground.
9.2.1.3 Application Curves
图9-3. 5 Gbps PRBS-7 Signals Through Calibration
图9-4. 5 Gbps PRBS-7 Signals Through a Typical
TMUXHS4212 Channel in TI Evaluation Board
Traces in TI Evaluation Board
图9-5. 10 Gbps PRBS-7 Signals Through
图9-6. 10 Gbps PRBS-7 Signals Through a Typical
Calibration Traces in TI Evaluation Board
TMUXHS4212 Channel in TI Evaluation Board
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9.2.2 PCIe Lane Muxing
The TMUXHS4212 can be used to switch PCIe lanes between two slots. In many PC and server motherboards,
the CPU does not have enough PCIe lanes to provide desired system flexibility for end customers. In such
applications, the TMUXHS4212 can be used to switch PCIe TX and RX lanes between two slots. 图9-7 provides
a schematic where eight TMUXHS4212 devices are used to switch eight PCIe TX and eight RX lanes. Note: the
common mode voltage (CMV) bias for the TMUXHS4212 must be within the range of 0 – 1.8 V. In
implementations where receiver CMV bias of a PCIe root complex or an end point can not be ensured within the
CMV range, additional DC blocking capacitors and appropriate CMV biasing must be implemented.
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A0p
A0n
A1p
A1n
B0p
B0n
C0p
C0n
B1p
B1n
C1p
C1n
TX0_1
TX1_1
TX0
TX1
TX0_2
TX1_2
VCC
0.1 µF
SEL
OEn
A0p
A0n
A1p
A1n
B0p
B0n
C0p
C0n
B1p
B1n
C1p
C1n
TX2_1
TX3_1
TX2
TX3
TX2_2
TX3_2
SEL
OEn
A0p
A0n
A1p
A1n
B0p
B0n
C0p
C0n
B1p
B1n
C1p
C1n
TX4_1
TX5_1
TX4
TX5
TX4_2
TX5_2
SEL
OEn
A0p
A0n
A1p
A1n
B0p
B0n
C0p
C0n
B1p
B1n
C1p
C1n
TX6_1
TX7_1
TX6
TX7
TX6_2
TX7_2
SEL
OEn
B0p
B0n
C0p
C0n
B1p
B1n
C1p
C1n
A0p
A0n
A1p
A1n
RX0_1
RX1_1
RX0
RX1
RX0_2
RX1_2
SEL
OEn
A0p
A0n
A1p
A1n
B0p
B0n
C0p
C0n
B1p
B1n
C1p
C1n
RX2
RX3
RX2_1
RX3_1
RX2_2
RX3_2
SEL
OEn
A0p
A0n
A1p
A1n
B0p
B0n
C0p
C0n
B1p
B1n
C1p
C1n
RX4
RX5
RX4_1
RX5_1
RX4_2
RX5_2
SEL
OEn
A0p
A0n
A1p
A1n
B0p
B0n
C0p
C0n
B1p
B1n
C1p
C1n
RX6
RX7
RX6_1
RX7_1
RX6_2
RX7_2
SEL
OEn
Optional
Controller
10 kW
GND
图9-7. PCIe Lane Muxing
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9.2.2.1 Application Curves
图9-8. 8 Gbps PRBS-7 Signals Through Calibration
图9-9. 8 Gbps PRBS-7 Signals Through a Typical
TMUXHS4212 Channel in TI Evaluation Board
Traces in TI Evaluation Board
图9-10. 16 Gbps PRBS-7 Signals Through
Calibration Traces in TI Evaluation Board
图9-11. 16 Gbps PRBS-7 Signals Through a
Typical TMUXHS4212 Channel in TI Evaluation
Board
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9.3 Systems Examples
9.3.1 USB/eSATA
SSRXP1
SSRXn1
B0p
B0n
A0p
A0n
TXp
TXn
B1p
B1n
SSTXp1
SSTXn1
A1p
A1n
OEn
SEL
RXp
RXn
SSRXp2
SSRXn2
C0p
C0n
Optional
SSTXp2
SSTXn2
C1p
C1n
Controller
10 kW
VCC
0.1 µF
GND
GND
VCC
图9-12. eSATA and USB 3.2 Combo Connector
9.3.2 MIPI Camera Serial Interface
B0+
B0t
B1+
B1t
D0p
D0n
CSI Camera
Module-1
D0p
A0+
CLKp
CLKn
D0n
A0t
CLKp
A1+
C0+
D0p
CLKn
A1t
OEn
SEL
CSI Camera
Module-2
C0t
C1+
C1t
D0n
CSI RX Chipset
CLKp
CLKn
Optional
Controller
10 lQ
VCC
GND
0.1 µF
GND
VCC
图9-13. CSI Camera Selection
10 Power Supply Recommendations
The TMUXHS4212 does not require a power supply sequence. TI, however, recommends that OEn is asserted
low after the device supply VCC is stable and in specification. TI also recommends to place ample decoupling
capacitors at the device VCC near the pin.
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11 Layout
11.1 Layout Guidelines
On a high-K board, TI always recommends to solder the Power-pad™ onto the thermal land. A thermal land is
the area of solder-tinned-copper underneath the Power-pad package. On a high-K board, the TMUXHS4212 can
operate over the full temperature range by soldering the Power-pad onto the thermal land without vias.
For high speed layout guidelines, refer to High-Speed Layout Guidelines for Signal Conditioners and USB Hubs.
The designer must use a 1-oz Cu trace connecting the GND pins to the thermal land for the device to operate
across the temperature range on a low-K board. A general PCB design guide for Power-pad packages is
provided in Power-pad Thermally-Enhanced Package.
11.2 Layout Example
图11-1 shows a basic layout example for the application shown in 节9.2.1
OEn and SEL can be controlled
Match high-speed traces
by the microcontroller. OEn can
length as close as possible
also be tied to GND with resistor
to minimize skew
for always On operation.
OEn
A0p
A0n
B0p
B0n
2
B1p
B1n
C0p
C0n
GND
VCC
A1p
A1n
SEL
C1p
C1n
Match high-speed traces
length as close as possible
to minimize skew
Place VCC decoupling capacitors as
close to VCC pins as possible.
图11-1. TMUXHS4212 Layout Example
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
USB Type-C™ is a trademark of USB Implementation Forum.
PCIe™ is a trademark of PCI-SIG.
Thunderbolt™ is a trademark of Intel Corporation.
Power-pad™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
Mipi® is a registered trademark of MIPI Alliance, Inc..
以太网® is a registered trademark of Fuji Xerox Co., Ltd.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUXHS4212IRKSR
TMUXHS4212IRKST
TMUXHS4212RKSR
TMUXHS4212RKST
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
RKS
RKS
RKS
RKS
20
20
20
20
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
0 to 70
HS4212
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
HS4212
HS4212
HS4212
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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11-Apr-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUXHS4212IRKSR
TMUXHS4212IRKST
TMUXHS4212RKSR
TMUXHS4212RKST
VQFN
VQFN
VQFN
VQFN
RKS
RKS
RKS
RKS
20
20
20
20
3000
250
180.0
180.0
180.0
180.0
12.4
12.4
12.4
12.4
2.8
2.8
2.8
2.8
4.8
4.8
4.8
4.8
1.2
1.2
1.2
1.2
4.0
4.0
4.0
4.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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25-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUXHS4212IRKSR
TMUXHS4212IRKST
TMUXHS4212RKSR
TMUXHS4212RKST
VQFN
VQFN
VQFN
VQFN
RKS
RKS
RKS
RKS
20
20
20
20
3000
250
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RKS 20
2.5 x 4.5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226872/A
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PACKAGE OUTLINE
RKS0020A
VQFN - 1 mm max height
S
C
A
L
E
3
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.6
2.4
B
A
PIN 1 INDEX AREA
4.6
4.4
0.1 C
C
1.0
0.8
SEATING PLANE
0.08 C
0.05
0.00
1
0.1
2X 0.5
(0.2) TYP
11
10
14X 0.5
EXPOSED
THERMAL PAD
9
12
2X
3.5
3
0.1
2
19
0.30
0.18
20X
1
20
PIN 1 ID
(OPTIONAL)
0.1
C A B
0.5
0.3
20X
0.05
4222490/B 02/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RKS0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1)
SYMM
1
20
20X (0.6)
2
19
20X (0.24)
(1.25)
SYMM
(3)
(4.3)
16X (0.5)
(R0.05) TYP
12
9
(
0.2) VIA
TYP
10
11
(2.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222490/B 02/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
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EXAMPLE STENCIL DESIGN
RKS0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.95)
20
1
20X (0.6)
2
19
20X (0.24)
2X (1.31)
16X (0.5)
SYMM
(4.3)
(0.76)
METAL
TYP
9
12
(R0.05) TYP
11
10
SYMM
(2.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
83% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222490/B 02/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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