TMX320C6455ZTZ1 [TI]
64-BIT, 66.67MHz, OTHER DSP, PBGA697, 24 X 24 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, BGA-697;
| 型号： | TMX320C6455ZTZ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 64-BIT, 66.67MHz, OTHER DSP, PBGA697, 24 X 24 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, BGA-697 时钟 外围集成电路 |
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TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
1 TMS320C6455 Fixed-Point Digital Signal Processor
1.1 Features
•
Four 1x Serial RapidIO® Links (or One 4x),
v1.2 Compliant
•
High-Performance Fixed-Point DSP (C6455)
–
–
–
–
–
–
1.39-, 1.17-, 1-ns Instruction Cycle Time
720-, 850-MHz and 1-GHz Clock Rate
Eight 32-Bit Instructions/Cycle
5760, 6800, 8000 MIPS
5760, 6800, 8000 MMACS (16 Bits)
Commercial Temperature [0°C to 90°C]
–
1.25-, 2.5-, 3.125-Gbps Link Rates
–
Message Passing, DirectIO Support, Error
Management Extensions, and Congestion
Control
–
IEEE 1149.6 Compliant I/Os
•
•
32-/16-Bit Host-Port Interface (HPI)
•
•
TMS320C64x+™ DSP Core
32-Bit/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.3
One Inter-Integrated Circuit (I2C) Bus
–
–
–
–
Dedicated SPLOOP Instruction
Compact Instructions (32-/16-Bit)
Instruction Set Enhancements
Exception Handling
•
•
Two Multichannel Buffered Serial Ports
(McBSPs)
TMS320C64x+ Megamodule L1/L2 Memory
Architecture:
•
10/100/1000 Mb/s Ethernet MAC (EMAC)
–
–
–
–
256K-Bit (32K-Byte) L1P Program Cache
[Direct Mapped]
256K-Bit (32K-Byte) L1D Data Cache
[2-Way Set-Associative]
16M-Bit (2048K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
Time Stamp Counter
–
–
IEEE 802.3 Compliant
Supports Multiple Media Independent
Interfaces (MII, GMII, RMII, and RGMII)
–
8 Independent Transmit (TX) and
8 Independent Received (RX) Channels
•
•
Two 64-Bit General-Purpose Timers,
Configurable as Four 32-Bit Timers
•
•
Enhanced Viterbi Decoder Coprocessor (VCP2)
–
–
Supports Over 694 7.95-Kbps AMR
Programmable Code Parameters
Universal Test and Operations PHY Interface
for ATM (UTOPIA)
–
–
UTOPIA Level 2 Slave ATM Controller
8-Bit Transmit and Receive Operations up
to 50 MHz per Direction
Enhanced Turbo Decoder Coprocessor (TCP2)
–
Supports up to Eight 2-Mbps 3GPP
(6 Iterations)
–
User-Defined Cell Format up to 64 Bytes
–
Programmable Turbo Code and Decoding
Parameters
•
•
•
16 General-Purpose I/O (GPIO) Pins
System PLL and PLL Controller
•
•
Endianess: Little Endian, Big Endian
64-Bit/133-MHz External Memory Interface
Secondary PLL and PLL Controller, Dedicated
to EMAC and DDR2 Memory Controller
–
Glueless I/F to Async Memories (SRAM,
Flash, and EEPROM) and Sync
•
•
IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
Memories (SBSRAM and ZBT SRAM)
–
–
Supports I/F to Standard Sync Devices
and Custom Logic (FPGA, CPLD, ASICs)
32M-Byte Total Addressable External
Memory Space
697-Pin Ball Grid Array (BGA) Package
(ZTZ Suffix), 0.8-mm Ball Pitch
•
•
0.09-µm/7-Level Cu Metal Process (CMOS)
3.3-, 1.8-, 1.5-, 1.2-V I/Os, 1.2-V Internal
•
•
32-Bit DDR2 Memory Controller (DDR2-500
SDRAM)
EDMA Controller (64 Independent Channels)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the forma-
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
Copyright © 2005–2005, Texas Instruments Incorporated
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
1.1.1 ZTZ BGA Package (Bottom View)
The TMS320C6455 devices are designed for a package temperature range of 0°C to +90°C (commercial
temperature range).
ZTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE
(BOTTOM VIEW)
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29
10 12 14 16 18 20 22 24 26 28
2
4
6
8
NOTE: The ZTZ mechanical package designator represents the version of the GTZ package with lead-free balls. For more detailed information,
see the Mechanical Data section of this document.
Figure 1-1. ZTZ BGA Package (Bottom View)
1.2 Description
The TMS320C64x+™ DSPs (including the TMS320C6455 device) are the highest-performance fixed-point
DSP generation in the TMS320C6000™ DSP platform. The C6455 device is based on the third-generation
high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by
Texas Instruments (TI), making these DSPs an excellent choice for applications including video and
telecom infrastructure, imaging/medical, and video conferencing. The C64x+™ devices are upward
code-compatible from previous devices that are part of the C6000™ DSP platform.
Based on 90-nm process technology and with performance of up to 8000 million instructions per second
(MIPS) [or 8000 16-bit MMACs per cycle] at a clock rate of 1 GHz, the C6455 device offers cost-effective
solutions to high-performance DSP programming challenges. The C6455 DSP possesses the operational
flexibility of high-speed controllers and the numerical capability of array processors.
The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier
C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles
the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates
(MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+
core. At a 1-GHz clock rate, this means 8000 16-bit MMACs can occur every second. Moreover, each
multiplier on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock
cycle.
The C6455 device includes Serial RapidIO®. This high bandwidth peripheral dramatically improves
system performance and reduces system cost for applications that include multiple DSPs on a board,
such as video and telecom infrastructures and medical/imaging.
2
TMS320C6455 Fixed-Point Digital Signal Processor
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
The C6455 DSP integrates a large amount of on-chip memory organized as a two-level memory system.
The level-1 (L1) program and data memories on the C6455 device are 32KB each. This memory can be
configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1
program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The
level 2 (L2) memory is shared between program and data space and is 2MB in size. L2 memory can also
be configured as mapped RAM, cache, or some combination of the two. The C64x+ Megamodule also has
a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with
reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for
time stamp.
The peripheral set also includes: an inter-integrated circuit bus module (I2C); two multichannel buffered
serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer
Mode (ATM) Slave [UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four
32-bit timers); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral
component interconnect (PCI); a 16-pin general-purpose input/output port (GPIO) with programmable
interrupt/event generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which
provides an efficient interface between the C6455 DSP core processor and the network; a management
data input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in
order to enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA),
which is capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAM
interface.
The I2C ports on the C6455 allow the DSP to easily control peripheral devices and communicate with a
host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to
communicate with serial peripheral interface (SPI) mode peripheral devices.
The C6455 device has two high-performance embedded coprocessors [enhanced Viterbi Decoder
Coprocessor (VCP2) and enhanced Turbo Decoder Coprocessor (TCP2)] that significantly speed up
channel-decoding operations on-chip. The VCP2 operating at CPU clock divided-by-3 can decode over
694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint
lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5 and flexible polynomials, while
generating hard decisions or soft decisions. The TCP2 operating at CPU clock divided-by-3 can decode
up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP2
implements the max*log-map algorithm and is designed to support all polynomials and rates required by
Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and
turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also
programmable. Communications between the VCP2/TCP2 and the CPU are carried out through the
EDMA controller.
The C6455 has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into
source code execution.
TMS320C6455 Fixed-Point Digital Signal Processor
3
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
1.3 Functional Block Diagram
Figure 1-2 shows the functional block diagram of the C6455 device.
32
C6455
DDR2 SDRAM
DDR2
Mem Ctlr
SBSRAM
(E)
PLL2
ZBT SRAM
L2 ROM
32K
Bytes
L1P Cache Direct-Mapped
32K Bytes
64
EMIFA
SRAM
TCP2
VCP2
ROM/FLASH
I/O Devices
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
C64x+ DSP Core
(A)
McBSP0
Control Registers
SPLOOP Buffer
Instruction Fetch
(B)(C)
McBSP1
16-/32-bit
Instruction Dispatch
L2
Cache
Memory
2048K
Bytes
Serial Rapid
I/O
Instruction
Decode
In-Circuit Emulation
Data Path B
M
e
g
a
m
o
d
u
l
Data Path A
(C)
HPI (32/16)
A Register File
A31−A16
B Register File
B31−B16
(C)
PCI66
A15−A0
B15−B0
e
(C)
UTOPIA
.M1
xx
xx
.M2
xx
xx
.L1 .S1
.D1
.D2
.S2 .L2
EMAC
10/100/1000
MII
RMII
GMII
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
(E)
RMGII
MDIO
L1D Cache 2-Way
Set-Associative
32K Bytes Total
16
(C)
GPIO16
I2C
(D)
Timer1
HI
LO
EDMA 3.0
PLL1 and
PLL1
Controller
Power-Down
(D)
Timer0
Logic
HI
LO
Boot Configuration
A. McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
B. System consists of Test, Emulation, Power Down, and Interrupt Controller.
C. The PCI peripheral pins are MUXED with some of the HPI, UTOPIA, McBSP1, and GPIO peripheral pins.
D. Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as either two 64-bit general-purpose timer or two 32-bit general-purpose
timers or a watchdog timer.
E. The PLL2 peripheral is also used for the RGMII mode of the EMAC.
Figure 1-2. Functional Block Diagram
4
TMS320C6455 Fixed-Point Digital Signal Processor
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Contents
1
2
TMS320C6455 Fixed-Point Digital Signal Pro-
6
C6455 Peripheral Information and Electrical
cessor ...................................................... 1
1.1 Features .............................................. 1
1.1.1 ZTZ BGA Package (Bottom View)................... 2
1.2 Description............................................ 2
1.3 Functional Block Diagram ............................ 4
Device Overview ......................................... 6
2.1 Device Characteristics................................ 6
2.2 CPU (DSP Core) Description......................... 7
2.3 Memory Map Summary ............................. 10
2.4 Bootmode Sequence................................ 12
2.5 Pin Assignments .................................... 13
2.6 Signal Groups Description .......................... 14
2.7 Terminal Functions.................................. 21
2.8 Development ........................................ 46
2.9 Device Silicon Revision ............................. 49
Device Configurations................................. 49
3.1 Device Configuration at Device Reset .............. 49
3.2 Priority Allocation.................................... 51
Specifications ........................................... 72
6.1 Parameter Information .............................. 72
6.2
Recommended Clock and Control Signals Tran-
sition Behavior....................................... 74
6.3 Power-Down Modes Logic .......................... 74
6.4 Power-Supply Sequencing .......................... 74
6.5 Power-Supply Decoupling........................... 74
6.6 Power-Down Operation ............................. 74
6.7 Powersaver.......................................... 75
6.8
Enhanced Direct Memory Access (EDMA) Control-
ler.................................................... 75
6.9 Interrupts ............................................ 84
6.10 Reset................................................ 87
6.11 PLL1 and PLL1 Controller - TBD ................... 91
6.12 PLL2 and PLL2 Controller .......................... 97
6.13 DDR2 Memory Controller ........................... 98
6.14 External Memory Interface A (EMIFA).............. 99
6.15 I2C Peripheral ..................................... 109
6.16 Host-Port Interface (HPI) Peripheral............... 114
6.17 Multichannel Buffered Serial Port (McBSP) ....... 124
6.18 Ethernet MAC (EMAC) ............................ 133
6.19 Timers ............................................. 149
6.20 Enhanced Viterbi-Decoder Coprocessor (VCP2).. 150
6.21 Enhanced Turbo Decoder Coprocessor (TCP2) .. 152
6.22 Peripheral Component Interconnect (PCI) ........ 153
6.23 UTOPIA............................................ 159
6.24 Serial Rapid I/O (RIO) Port ........................ 162
6.25 General-Purpose Input/Output (GPIO) ............ 175
6.26 IEEE 1149.1 JTAG ................................ 178
Revision History............................................ 179
3
3.3
Peripheral Configuration at Device Reset........... 51
Peripheral Selection After Device Reset ............ 53
3.4
3.5 Device Status Register Description ................. 53
3.6 JTAG ID Register Description....................... 56
3.8 Debugging Considerations - TBD ................... 56
3.9 Configuration Examples - TBD...................... 57
Device Operating Conditions ........................ 59
4
5
4.1
Absolute Maximum Ratings Over Operating Case
Temperature Range (Unless Otherwise Noted)..... 59
4.2 Recommended Operating Conditions............... 59
4.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) ............ 60
7
Mechanical Data....................................... 180
7.1 Thermal Data ...................................... 180
7.2 Packaging Information ............................. 180
C64x+ Megamodule.................................... 62
5.1 Memory Architecture ................................ 62
5.2
C64+ Megamodule Device-Specific Information .... 62
C64x+ Megamodule Register Description(s)........ 63
5.3
Contents
5
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
2 Device Overview
2.1 Device Characteristics
Table 2-1, provides an overview of the C6455 DSP. The tables show significant features of the C6455
device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type
with pin count.
Table 2-1. Characteristics of the C6455 Processor
HARDWARE FEATURES
C6455
EMIFA (64-bit bus width) [133 MHz]
(clock source = AECLKIN or SYSCLK3)
1
DDR2 Memory Controller (32-bit bus width) [1.8 V I/O]
(clock source = CLKIN2)
1
1
1
EDMA (64 independent channels) [CPU/3 clock rate]
High-speed 1x/4x Serial Rapid IO Port
(RIOCLK and RIOCLK)
Peripherals
I2C
1
Not all peripherals pins
are available at the same
time (For more detail, see
the Device Configuration
section).
HPI (32- or 16-bit user selectable)
PCI (32-bit), [66-MHz or 33-MHz]
1 (HPI16 or HPI32)
1 (PCI66 or PCI33)
McBSPs (internal CPU/12 or external clock source up
to 100 Mbps)
2
UTOPIA (8-bit mode, 50-MHz, Slave-only)
10/100/1000 Ethernet MAC (EMAC)
Management Data Input/Output (MDIO)
1
1
1
64-Bit Timers (Configurable)
(internal clock source = CPU/6 clock frequency)
2 64-bit or 4 32-bit
General-Purpose Input/Output Port (GPIO)
VCP2 (clock source = CPU/3 clock frequency)
TCP2 (clock source = CPU/3 clock frequency)
Size (Bytes)
16
1
1
Decoder Coprocessors
On-Chip Memory
2128K
32K-Byte (32KB) L1 Program Memory Controller
[SRAM/Cache]
32KB Data Memory Controller [SRAM/Cache]
2048KB L2 Unified Memory/Cache
32KB L2 ROM
Organization
CPU MegaModule
Revision ID
Revision ID Register (MM_REVID.[15:0])
0x0181 2000
0x0
JTAG BSDL_ID
Frequency
JTAGID register (address location: 0x02A80008)
MHz
0x0008 A02F
720, 850, and 1000 (1-GHz)
1.39 ns (C6455-720), 1.17 ns (C6455-850),
1 ns (C6455-1000) [1 GHz CPU]
Cycle Time
ns
Core (V)
1.2 V (-720, -850, -1000)
1.2 [RapidIO],
1.5/1.8 [EMAC RGMII], and
1.8 and 3.3 V [I/O Supply Voltage]
Voltage
I/O (V)
PLL1 and PLL1
Controller Options
CLKIN frequency multiplier
Bypass (x1), x20, x25, x30, x32
x10
CLKIN frequency multiplier
[DDR2 Memory Controller and EMAC support only]
PLL2
BGA Package
24 x 24 mm
µm
697-Pin Flip-Chip Plastic BGA (ZTZ)
0.09 µm
Process Technology
6
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-1. Characteristics of the C6455 Processor (continued)
HARDWARE FEATURES
C6455
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
Product Status(1)
PP
TMX320C6455ZTZ720,
TMX320C6455ZTZ850,
TMX320C6455ZTZ1
(For more details on the C64x+™ DSP part num-
bering, see Figure 2-9)
Device Part Numbers
(1) PRODUCT PREVIEW information concerns experimental products (designated as TMX) that are in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
2.2 CPU (DSP Core) Description
The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain
32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be
data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit
data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are
stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or
32 MSBs in the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C64x+ CPU extends the performance of the C64x core through enhancements and new features.
Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, two
16 x 16 bit multiplies, two 16 x 32 bit multiplies, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add
operations, and four 16 x 16 multiplies with add/subtract capabilites (including a complex multiply). There
is also support for Galois field mutiplication for 8-bit and 32-bit data. Many communications algorithms
such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes
for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex
multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and
16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for
audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
•
SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Futhermore, loops in the SPLOOP buffer are fully interruptible.
•
Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 obits if the C64x+
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
Device Overview
7
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
•
•
•
•
Instruction Set Enhancements - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
Exception Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a
free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following
documents:
•
•
•
•
•
C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRUTBD)
C64x+ DSP Cache User's Guide (literature number SPRUTBD)
C64x+ Megamodule Peripherals Reference Guide (literature number SPRUTBD)
C64x+ DSP Technical Overview (literature number SPRU965)
C64x to C64x+ CPU Migration Guide (literature number SPRAATBD)
8
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Even
Odd
src1
src2
register
register
file A
file A
(A0, A2,
(A1, A3,
A4...A30)
A5...A31)
.L1
odd dst
even dst
long src
(D)
8
32 MSB
32 LSB
ST1b
ST1a
8
long src
even dst
odd dst
src1
(D)
Data path A
.S1
src2
32
32
(A)
(B)
dst2
dst1
src1
.M1
src2
(C)
32 MSB
32 LSB
LD1b
LD1a
dst
src1
src2
.D1
.D2
DA1
2x
Even
register
file B
(B0, B2,
B4...B30)
1x
Odd
register
file B
(B1, B3,
B5...B31)
src2
DA2
src1
dst
32 LSB
LD2a
LD2b
32 MSB
src2
(C)
.M2
src1
dst2
32
32
(B)
(A)
dst1
src2
src1
.S2
odd dst
even dst
long src
(D)
Data path B
8
8
32 MSB
32 LSB
ST2a
ST2b
long src
even dst
(D)
odd dst
.L2
src2
src1
Control Register
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths
Device Overview
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TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
2.3 Memory Map Summary
Table 2-2 shows the memory map address ranges of the C6455 device. The external memory
configuration register address ranges in the C6455 device begin at the hex address location 0x7000 0000
for EMIFA and hex address location 0x7800 0000 for DDR2 Memory Controller.
Table 2-2. C6455 Memory Map Summary
MEMORY BLOCK DESCRIPTION
BLOCK SIZE (BYTES)
HEX ADDRESS RANGE
0000 0000 - 000F FFFF
0010 0000 - 0010 7FFF
0010 8000 - 007F FFFF
0080 0000 - 009F FFFF
00A0 0000 - 00DF FFFF
00E0 0000 - 00E0 7FFF
00E0 8000 - 00EF FFFF
00F0 0000 - 00F0 7FFF
00F0 8000 - 00FF FFFF
0100 0000 - 017F FFFF
0180 0000 - 0180 FFFF
0181 0000 - 0181 FFFF
0182 0000 - 0182 01FF
Reserved
1024K
32K
Internal ROM
Reserved
7M - 32K
2M
Internal RAM (L2) [L2 SRAM]
Reserved
4M
L1P SRAM
32K
Reserved
1M - 32K
32K
L1D SRAM
Reserved
1M - 32K
8M
Reserved
CPU MegaModule Interrupt Controller
CPU MegaModule Powerdown Status
CPU MegaModule IDMA Registers
64K
64K
64K
CPU MegaModule BandWidth Management Control
Registers
768
0182 0200 - 0182 02FF
CPU MegaModule Configuration Registers
130K
3.5K
0182 0300 - 0183 FFFF
0184 0000 - 0184 0DFF
CPU MegaModule Cache Configuration Registers
CPU MegaModule BandWidth Management L1D and
L2 Registers
12.8K
0184 0E00 - 0184 3FFF
CPU MegaModule Cache Status and Control Registers
8K
8K
0184 4000 - 0184 5FFF
0184 6000 - 0184 7FFF
0184 8000 - 0184 9FFF
0184 A000 - 0184 BFFF
0184 0000 - 0185 FFFF
0186 0000 - 0187 FFF0
0187 FFFC - 01BB FFFF
01BC 0000 - 01BF FFFF
01C0 0000 - 0287 FFFF
0288 0000 - 028B FFFF
028C 0000 - 028F FFFF
0290 0000 - 0293 FFFF
0294 0000 - 0297 FFFF
0298 0000 - 0299 FFFF
029A 0000 - 029A 01FF
029C 0200 - 029C 02FF
02A0 0000 - 02A0 7FFF
02A0 8000 - 02A1 FFFF
02A2 0000 - 02A2 7FFF
02A2 8000 - 02A2 FFFF
02A3 0000 - 02A3 7FFF
02A3 8000 - 02A3 FFFF
Reserved
CPU MegaModule Cache MAR Registers
8K
CPU MegaModule Memory Protection Registers
CPU MegaModule L1/L2 Control Registers
Reserved
8K
128K
128K - 16
3.4M
256K
12.5M
256K
256K
256K
256K
128K
512
Reserved
Emulation
Reserved
HPI Control Registers
McBSP 0 Registers
McBSP 1 Registers
Timer 0 Registers
Timer 1 Registers
PLL1 Controller
Reserved
512K - 512
32K
EDMA3.0 - CC Registers
Reserved
96K
Reserved
32K
Reserved
32K
Reserved
32K
Reserved
32K
10
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-2. C6455 Memory Map Summary (continued)
MEMORY BLOCK DESCRIPTION
BLOCK SIZE (BYTES)
256K
HEX ADDRESS RANGE
02A4 0000 - 02A7 FFFF
02A8 0000 - 02AB FFFF
02AC 0000 - 02AF FFFF
02B0 0000 - 02B0 3FFF
02B0 4000 - 02B3 FFFF
02B4 0000 - 02B4 01FF
02B4 0200 - 02B7 FFFF
02B8 0000 - 02B9 FFFF
02BA 0000 - 02BB FFFF
02BC 0000 - 02BF FFFF
02C0 0000 - 02C3 FFFF
02C4 0000 - 02C7 FFFF
02C8 0000 - 02C8 0FFF
02C8 1000 - 02C8 17FF
02C8 1800 - 02C8 1FFF
02C8 2000 - 02C8 3FFF
02C8 4000 - 02CF FFFF
02D0 0000 - 02D3 FFFF
02D4 0000 - 02DF FFFF
02E0 0000 - 02E0 3FFF
02E0 4000 - 02FF FFFF
0300 0000 - 03FF FFFF
0400 0000 - 0FFF FFFF
1000 0000 - 1FFF FFFF
2000 0000 - 2FFF FFFF
3000 0000 - 3000 00FF
3000 0100 - 33FF FFFF
3400 0000 - 3400 00FF
3400 0100 - 37FF FFFF
3800 0000 - 3BFF FFFF
3C00 0000 - 3C00 03FF
3C00 0400 - 3C00 07FF
3C00 0800 - 3CFF FFFF
3D00 0000 - 3FFF FFFF
4000 0000 - 4FFF FFFF
5000 0000 - 57FF FFFF
5800 0000 - 5FFF FFFF
6000 0000 - 6FFF FFFF
7000 0000 - 77FF FFFF
7800 0000 - 7FFF FFFF
8000 0000 - 8FFF FFFF
9000 0000 - 9FFF FFFF
A000 0000 - AFFF FFFF
A080 0000 - A07F FFFF
B000 0000 - B07F FFFF
B080 0000 - BFFF FFFF
Reserved
Chip-Level Registers
Powersaver Registers
GPIO Registers
256K
256K
16K
I2C Data and Control Registers
UTOPIA Control Registers
Reserved
256K
512
256K - 512
128K
VCP2 Control Registers
TCP2 Control Registers
Reserved
128K
256K
PCI Control Registers
Reserved
256K
256K
EMAC Control
4K
EMAC Wrapper Control
MDIO Control Registers
EMAC CPPI RAM
Reserved
2K
2K
8K
496K
RapidIO Control Registers
Reserved
256K
768K
RapidIO CPPI RAM
Reserved
16K
2M - 16K
16M
Reserved
Reserved
192M
256M
256M
256
Reserved
Reserved
McBSP 0 Data
Reserved
64M - 256
256
McBSP 1 Data
Reserved
64M - 256
64M
Reserved
UTOPIA Rx Data Registers
UTOPIA Tx Data Registers
Reserved
1K
1K
16M - 2K
48M
Reserved
Reserved
256M
128M
128M
256M
128M
128M
256M
256M
8M
TCP2 Data Registers
VCP2 Data Registers
Reserved
EMIFA (EMIF64) Configuration Registers
DDR2 Memory Controller Configuration Registers
Reserved
Reserved
EMIFA CE2 - SBSRAM/Async(1)
Reserved
256M - 8M
8M
EMIFA CE3 - SBSRAM/Async(1)
Reserved
256M - 8M
(1) The EMIFA CE0 and CE1 are not functionally supported on the C6455 device, and therefore, are not pinned out.
Device Overview
11
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-2. C6455 Memory Map Summary (continued)
MEMORY BLOCK DESCRIPTION
EMIFA CE4 - SBSRAM/Async(1)
BLOCK SIZE (BYTES)
HEX ADDRESS RANGE
8M
256M - 8M
8M
C000 0000 - C07F FFFF
C080 0000 - CFFF FFFF
D000 0000 - D07F FFFF
D080 0000 - DFFF FFFF
E000 0000 - EFFF FFFF
F000 0000 - FFFF FFFF
Reserved
EMIFA CE5 - SBSRAM/Async(1)
Reserved
256M - 8M
256M
DDR2 Memory Controller CE0 - DDR2 SDRAM
Reserved
256M
2.4 Bootmode Sequence
The boot sequence is a process by which the DSP's internal memory is loaded with program and data
sections and the DSP's internal registers are programmed with predetermined values. The boot sequence
is started automatically after each power-on, warm, max, and system reset (For more details on the
initiators of these resets, see the Reset section of this document, Section 6.10).
There are several methods by which the memory and register initialization can take place. Each of these
methods is referred to as a boot mode. The boot mode to be used is selected at reset through the
BOOTMODE[3:0] pins.
2.4.1 Bootmodes Supported
The C6455 has six types of boot modes:
•
No boot (BOOTMODE[3:0] = 0000b)
With no boot, the CPU executes directly from the internal L2 SRAM located at address 0x80 0000.
Note: device operations is undefined if invalid code is located at address 0x80 0000.
•
Host boot (BOOTMODE[3:0] = 0001b)
If host boot is selected, after reset, the CPU is internally "stalled" while the remainder of the device is
released. During this period, an external host can initialize the CPU's memory space as necessary
through a host interface, including internal configuration registers, such as those that control the EMIF
or other peripherals. Once the host is finished with all necessary initialization, it must generate a DSP
interrupt (DSPINT) to complete the boot process. This transition causes the boot configuration logic to
bring the CPU out of the "stalled" state. The CPU then begins execution from the internal L2 SRAM
located at 0x80 0000. The DSPINT condition is not latched by the CPU, because it occurs while the
CPU is still internally "stalled". Also, DSPINT brings the CPU out of the "stalled" state only if the host
boot process is selected. All memory may be written to and read by the host. This allows for the host
to verify what it sends to the DSP if required. After the CPU is out of the "stalled" state, the CPU needs
to clear the DSPINT, otherwise, no more DSPINTs can be received.
For the TCI6482 device, the Host Port Interface (HPI) peripheral or the Peripheral Component
Interconnect (PCI) interface can be used for host boot. To use the HPI for host boot, the PCI_EN pin
(Y29) must be low [default]; enabling the HPI peripheral. Conversely, to use the PCI interface for host
boot, the PCI_EN pin (Y29) must be high; enabling the PCI peripheral. The DSP interrupt can be
generated through the use of the DSPINT bit in the HPI Control (HPIC) register and the PCI TBD
(TBD) register.
•
•
EMIFA 8-bit ROM boot (BOOTMODE[3:0] = 0100b)
After reset, the device will begin executing software out of an Asynchronous 8-bit ROM located in
EMIFA CE3 space using the default settings in the EMIFA registers.
Master I2C boot (BOOTMODE[3:0] = 0101b)
After reset, the DSP can act as a master to the I2C bus and copy data from an I2C EEPROM or a
device acting as an I2C slave to the DSP using a predefined boot table format. The destination
address and length are contained within the boot table.
12
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
•
Slave I2C boot (BOOTMODE[3:0] = 0110b)
A Slave I2C boot is also implemented, which programs the DSP as an I2C Slave and simply waits for a
Master to send data using a standard boot table format.
Using the Slave I2C boot, a single DSP or a device acting as an I2C Master can simultaneously boot
multiple slave DSPs connected to the same I2C bus. Note that the Master DSP may require booting
via an I2C EEPROM before acting as a Master and booting other DSPs.
•
Serial RapidIO boot (BOOTMODE[3:0] = 1000b through 1111b)
Upon reset, the following sequence of events occur:
–
–
–
–
–
–
–
–
–
Internal boot ROM is used to configure device registers, including SerDes, and EDMA
The peripheral's state machines and registers are reset
RapidIO ports send idle control symbols to initialize SerDes ports
Host enabled to explore system with RapidIO maintenance packets
Host identifies, enumerates, and initializes the RapidIO device
Host controller configures DSP peripherals through maintenance packets
Application S/W sent from Host controller to DSP memory
DSP CPU is awakened by interrupt such as a RapidIO DOORBELL packet
Application S/W is executed and normal operation follows
For Serial RapidIO boot, BOOTMODE2 (L26 pin) is used in conjunction with the CFGGP[2:0] (T26,
U26, and U25 pins, respectively) to determine the device address within the RapidIO network.
BOOTMODE2 is the MSB of the address, while CFGGP[2:0] are used as the three LSBs–giving the
user the opportunity to have up to 16 unique device IDs.
BOOTMODE[1:0] (L25 and P26, respectively) denote the configuration of the RapidIO peripheral; i.e.,
"00b" refers to RapidIO Configuration 0. For exact device RapidIO Configurations, see the TBD
Application Report (Literature Number TBD).
2.4.2 2nd-Level Bootloaders
Any of the boot modes can be used to download a 2nd-level bootloader. A 2nd-level bootloader allows for
any level of customization to current boot methods as well as definition of a completely customized boot.
TI offers a few 2nd-level bootloaders, such as an EMAC bootloader and a UTOPIA bootloader, which can
be loaded using the Master I2C boot.
2.5 Pin Assignments
2.5.1 Pin Map
TBD through TBD show the C6455 pin assignments in four quadrants (A, B, C, and D).
Device Overview
13
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
2.6 Signal Groups Description
RESETSTAT
RESET
NMI
CLKIN1
Clock/PLL1
and
PLL Controller
(A)
SYSCLK3/GP[1]
Reset and
Interrupts
PLLV1
POR
CLKIN2
PLLV2
Clock/PLL2
RSV00
RSV01
RSV02
RSV03
RSV04
RSV05
•
TMS
TDO
TDI
TCK
TRST
Reserved
•
•
IEEE Standard
1149.1
(JTAG)
Emulation
EMU0
EMU1
•
•
RSV42
RSV43
RSV44
•
EMU14
EMU15
EMU16
EMU17
EMU18
Peripheral
Enable/Disable
PCI_EN
Control/Status
A. This pin is muxed with the GP[1] pin and by default these signals function as SYSCLK3. For more details, see the Device
Configurationssection of this data sheet.
Figure 2-2. CPU and Peripheral Signals
14
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
TOUTL0
TINPL0
TINPL1
Timer 1
Timer 0
TOUTL1
Timers (64-Bit)
(C)
(C)
(C)
GP[7]
GP[6]
GP[5]
GP[4]
URADDR3/PREQ/GP[15]
URADDR2/PINTA/GP[14]
URADDR1/PRST/GP[13]
URADDR0/PGNT/GP[12]
(C)
GPIO
(B)
(B)
(B)
FSX1/GP[11]
FSR1/GP[10]
CLKX1/GP[3]
URADDR4/PCBE0/GP[2]
SYSCLK3/GP[1]
CLKR1/GP[0]
(C)
(B)
(A)
DX1/GP[9]
(B)
(B)
DR1/GP[8]
General-Purpose Input/Output 0 (GPIO) Port
4
4
RIOTX[3:0]
RIOCLK
RIOCLK
Transmit
Clock
RIOTX[3:0]
4
RIORX[3:0]
RIORX[3:0]
Receive
4
RAPID IO
A. This pin is muxed with the GP[1] pin and by default this signal functions as SYSCLK3. For more details, see the Device Configurations
section of this data sheet.
B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins.
For more details, see the Device Configurations section of this data sheet.
C. These UTOPIA and PCI peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO
peripheralpins. For more details, see the Device Configurations section of this data sheet.
Figure 2-3. Timers/GPIO/RapidIO Peripheral Signals
Device Overview
15
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
64
Data
AED[63:0]
AECLKIN
(A)
ACE5
AECLKOUT
(A)
ACE4
ACE3
ACE2
Memory Map
Space Select
(A)
(A)
External
Memory I/F
Control
20
Address
AEA[19:0]
ASWE/AAWE
AARDY
ABE7
ABE6
AR/W
AAOE/ASOE
ASADS/ASRE
ABE5
ABE4
ABE3
ABE2
Byte Enables
ABE1
ABE0
AHOLD
Bus
AHOLDA
ABUSREQ
Arbitration
Bank Address
ABA[1:0]
EMIFA (64-bit Data Bus)
32
Data
DED[31:0]
DDR2CLKOUT
DDR2CLKOUT
DSDCKE
Memory Map
Space Select
DCE0
DSDCAS
External
Memory I/F
Control
DSDRAS
DSDWE
14
Address
DEA[13:0]
DSDDQS[3:0]
DSDDQS[3:0]
DSDDQGATE[3:0]
DEODT[1:0]
DSDDQM3
DSDDQM2
DSDDQM1
DSDDQM0
Byte Enables
Bank Address
DBA[2:0]
DDR2 Memoty Controller (32-bit Data Bus)
A. The EMIFA ACE0 and ACE1 are not functionally supported on the C6455 device.
Figure 2-4. EMIFA/DDR2 Memory Controller Peripheral Signals
16
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
(A)
HPI
(Host-Port Interface)
32
HD[15:0]/AD[15:0]
Data
HD[31:16]/AD[31:16]
HAS/PPAR
HR/W/PCBE2
HCS/PPERR
HDS1/PSERR
HDS2/PCBE1
HRDY/PIRDY
HCNTL0/PSTOP
HCNTL1/PDEVSEL
Register Select
Control
Half-Word
Select
HHWIL/PCLK
(HPI16 ONLY)
HINT/PFRAME
McBSP1
Transmit
McBSP0
Transmit
CLKX0
CLKX1/GP[3]
FSX0
DX0
FSX1/GP[11]
DX1/GP[9]
CLKR0
FSR0
CLKR1/GP[0]
FSR1/GP[10]
DR1/GP[8]
Receive
Clock
Receive
Clock
DR0
CLKS
(SHARED)
McBSPs
(Multichannel Buffered Serial Ports)
(B)
SCL
SDA
I2C
A. These HPI pins are muxed with the PCI peripheral. By default, these pins function as HPI. When the HPI is enabled, the number of HPI pins
used depends on the HPI configuration (HPI16 or HPI32). For more details on these muxed pins, see the Device Configurations section of
this data sheet.
B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins. For
more details, see the Device Configurations section of this data sheet.
Figure 2-5. HPI/McBSP/I2C Peripheral Signals
Device Overview
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TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
Ethernet MAC
(EMAC)
Transmit
MII
UXDATA[7:2]/MTXD[7:2],
RMII
UXDATA[1:0]/MTXD[1:0]/RMTXD[1:0]
GMII
MDIO
(A)
RGTXD[3:0]
RGMII
Input/Output
MII
Receive
UXADDR3/MDIO
RMII
GMII
MII
URDATA[7:2]/MRXD[7:2],
URDATA[1:0]/MRXD[1:0]/RMRXD[1:0]
RMII
GMII
(A)
RGMII
RGMDIO
(A)
RGMII
RGRXD[3:0]
Clock
MII
Error Detect
and Control
UXADDR4/MDCLK
RGMDCLK
RMII
GMII
MII
URSOC/MRXER/RMRXER,
URENB/MRXDV,
URCLAV/MCRS/RMCRSDV,
UXSOC/MCOL,
RMII
GMII
(A)
RGMII
UXENB/MTXEN/RMTXEN
(A)
RGMII
RGTXCTL, RGRXCTL
Clocks
MII
UXCLK/MTCLK/RMREFCLK,
URCLK/MRCLK,
RMII
GMII
UXCLAV/GMTCLK
(A)
RGTXC,
RGRXC,
RGMII
RGREFCLK
(B)
Ethernet MAC (EMAC) and MDIO
A. RGMII signals are mutually exclusive to all other EMAC signals.
B. These EMAC pins are muxed with the UTOPIA peripheral. By default, these signals function as EMAC. For more details on these
muxed pins, see the Device Configurations section of this data sheet.
Figure 2-6. EMAC/MDIO [MII/RMII/GMII/RGMII Peripheral Signals
18
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TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
(A)
UTOPIA (SLAVE)
URDATA7/MRXD7
UXDATA7/MTXD7
URDATA6/MRXD6
URDATA5/MRXD5
UXDATA6/MTXD6
UXDATA5/MTXD5
URDATA4/MRXD4
URDATA3/MRXD3
UXDATA4/MTXD4
UXDATA3/MTXD3
Receive
Transmit
URDATA2/MRXD2
UXDATA2/MTXD2
URDATA1/MRXD1/RMRXD1
URDATA0/MRXD0/RMRXD0
UXDATA1/MTXD1/RMTXD1
UXDATA0/MTXD0/RMTXD0
UXENB/MTXEN/RMTXEN
UXADDR4/GMDCLK
UXADDR3/GMDIO
UXADDR2/PCBE3
UXADDR1/PIDSEL
UXADDR0/PTRDY
UXCLAV/GMTCLK
UXSOC/MCOL/TCLKRISE
URENB/MRXDV
URADDR4/PCLK/GP[2]
URADDR3/PREQ/GP[15]
URADDR2/PINTA/GP[14]
URADDR1/PRST/GP[13]
URADDR0/PGNT/GP[12]
URCLAV/MCRS/RMCRSDV
URSOC/MRXER/RMRXER
Control/Status
Control/Status
Clock
Clock
URCLK/MRCLK
UXCLK/MTCLK/REFCLK
A. These UTOPIA pins are muxed with the PCI or EMAC or GPIO peripherals. By default, these signals function as GPIO or EMAC peripheral
pins or have no function. For more details on these muxed pins, see the Device Configurations section of this data sheet.
Figure 2-7. UTOPIA Peripheral Signals
Device Overview
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Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
32
HD[15:0]/AD[15:0]
Data/Address
Clock
HHWIL/PCLK
HD[31:16]/AD[31:16]
UXADDR1/PIDSEL
HCNTL1/PDEVSEL
HINT/PFRAME
URADDR2/PINTA/GP[14]
HAS/PPAR
UXADDR2/PCBE3
HR/W/PCBE2
Command
Byte Enable
HDS2/PCBE1
Control
UXADDR4/PCBE0/GP[2]
URADDR1/PRST/GP[13]
HRDY/PIRDY
HCNTL0/PSTOP
UXADDR0/PTRDY
URADDR0/PGNT/GP[12]
URADDR3/PREQ/GP[15]
Arbitration
HDS1/PSERR
HCS/PPERR
Error
Serial
EEPROM
Software Controllable
(A)
PCI Interface
A. These PCI pins are muxed with the HPI or UTOPIA or GPIO peripherals. By default, these signals function as HPI or GPIO or EMAC. For more
details on these muxed pins, see the Device Configurations section of this data sheet.
Figure 2-8. PCI Peripheral Signals
20
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Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
2.7 Terminal Functions
The terminal functions table (Table 2-3) identifies the external signal names, the associated pin (ball)
numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin
has any internal pullup/pulldown resistors and a functional pin description. For more detailed information
on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see
the Device Configurations section of this data sheet.
Table 2-3. Terminal Functions TBD
SIGNAL
TYPE(1) IPD/IPU(2)
CLOCK/PLL CONFIGURATIONS
DESCRIPTION
NAME
NO.
CLKIN1
CLKIN2
PLLV1
PLLV2
N28
G3
I
I
IPD
IPD
Clock Input for PLL1.
Clock Input for PLL2.
T29
A5
A
A
1.8-V I/O supply voltage for PLL1
1.8-V I/O supply voltage for PLL2
SYSCLK3 is the clock output at 1/8 of the device speed (O/Z) or this pin can be
programmed as the GP1 pin (I/O/Z) [default].
SYSCLK3/GP[1](3)
AJ13
I/O/Z
IPD
JTAG EMULATION
TMS
TDO
TDI
AJ10
AH8
AH9
AJ9
I
IPU
IPU
IPU
IPU
JTAG test-port mode select
JTAG test-port data out
JTAG test-port data in
JTAG test-port clock
O/Z
I
I
TCK
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE
1149.1 JTAG compatibility statement portion of this data sheet.
TRST
AH7
I
IPD
EMU0
EMU1
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
EMU12
EMU13
EMU14
EMU15
EMU16
EMU17
EMU18
AF7
AE11
AG9
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
Emulation pin 0
Emulation pin 1
Emulation pin 2
Emulation pin 3
Emulation pin 4
Emulation pin 5
Emulation pin 6
Emulation pin 7
Emulation pin 8
Emulation pin 9
Emulation pin 10
Emulation pin 11
Emulation pin 12
Emulation pin 13
Emulation pin 14
Emulation pin 15
Emulation pin 16
Emulation pin 17
Emulation pin 18
AF10
AF9
AE12
AG8
AF12
AF11
AH13
AD10
AD12
AE10
AD8
AF13
AE9
AH12
AH10
AE13
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
RESET
NMI
AG14
AH4
I
I
Device reset
IPD
Nonmaskable interrupt, edge-driven (rising edge)
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the
opposite supply rail, a 1-kΩ resistor should be used.)
(3) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
Device Overview
21
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
RESETSTAT
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
AE14
AF14
AG2
AG3
AJ2
O
I
Reset Status pin. The RESETSTAT pin indicates when the device is in reset
Power on reset.
POR
GP[7]
GP[6]
GP[5]
GP[4]
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPD
General-purpose input/output (GPIO) pins (I/O/Z).
AH2
URADDR3/PREQ/
GP[15]
P2
P3
R5
R4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
URADDR2/PINTA/
GP[14]
UTOPIA received address pins or PCI peripheral pins or General-purpose
input/output (GPIO) [15:12, 2] pins (I/O/Z) [default]
URADDR1/PRST/
GP[13]
PCI bus request (O/Z) or GP[15] (I/O/Z) [default]
PCI interrupt A (O/Z) or GP[14] (I/O/Z) [default]
PCI reset (I) or GP[13] (I/O/Z) [default]
URADDR0/PGNT/
GP[12]
PCI bus grant (I) or GP[12] (I/O/Z) [default]
PCI command/byte enable 0 (I/O/Z) or GP[2] (I/O/Z) [default]
FSX1/GP[11]
FSR1/GP[10]
DX1/GP[9]
AG4
AE5
AG5
AH5
AF5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPD
IPD
McBSP1 pins or GP[11:8] pins (I/O/Z) [default]
McBSP1 transmit clock (I/O/Z) or GP[3] (I/O/Z) [default]
McBSP1 receive clock (I/O/Z) or GP[0] (I/O/Z) [default]
DR1/GP[8]
CLKX1/GP[3]
GP[1] pin (I/O/Z). SYSCLK3 is the clock output at 1/8 of the device speed (O/Z)
or this pin can be programmed as a GP[1] pin (I/O/Z) [default].
URADDR4/PCBE0/
GP[2]
P1
I/O/Z
SYSCLK3/GP[1](3)
AJ13
AF4
O/Z
IPD
IPD
CLKR1/GP[0]
I/O/Z
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI)
PCI enable pin. This pin controls the selection (enable/disable) of the HPI and
GP[15:8], or PCI peripherals. This pin works in conjunction with the
MCBSP1_EN (AEA5 pin) to enable/disable other peripherals (for more details,
see the Device Configurations section of this data sheet).
PCI_EN
Y29
I
IPD
HINT/PFRAME
U3
U4
I/O/Z
I/O/Z
Host interrupt from DSP to host (O/Z) or PCI frame (I/O/Z)
Host control - selects between control, address, or data registers (I) [default] or
PCI device select (I/O/Z)
HCNTL1/PDEVSEL
Host control - selects between control, address, or data registers (I) [default] or
PCI stop (I/O/Z)
HCNTL0/PSTOP
HHWIL/PCLK
U5
V3
I/O/Z
I/O/Z
Host half-word select - first or second half-word (not necessarily high or low
order)
[For HPI16 bus width selection only] (I) [default] or PCI clock (I)
HR/W/PCBE2
HAS/PPAR
T5
T3
U6
U2
U1
T4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)
Host address strobe (I) [default] or PCI parity (I/O/Z)
HCS/PPERR
HDS1/PSERR
HDS2/PCBE1
HRDY/PIRDY
Host chip select (I) [default] or PCI parity error (I/O/Z)
Host data strobe 1 (I) [default] or PCI system error (I/O/Z)
Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z)
Host ready from DSP to host (O/Z) [default] or PCI initiator ready (I/O/Z)
URADDR3/PREQ/
GP[15]
UTOPIA received address pin 3 (URADDR3) or PCI bus request (O/Z) or
GP[15] (I/O/Z) [default]
P2
P3
R5
R4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
URADDR2/PINTA/
GP[14]
UTOPIA received address pin 2 or PCI interrupt A (O/Z) or
GP[14] (I/O/Z) [default]
URADDR1/PRST/
GP[13]
UTOPIA received address pin 1 (URADDR1) or PCI reset (I) or
GP[13] (I/O/Z) [default]
URADDR0/PGNT/
GP[12]
UTOPIA received address pin 0 (URADDR0) or PCI bus grant (I) or
GP[12] (I/O/Z) [default]
22
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
TYPE(1) IPD/IPU(2)
DESCRIPTION
NAME
NO.
URADDR4/PCBE0/
GP[2]
UTOPIA received address pin 4 (URADDR4) or PCI command/byte enable 0
(I/O/Z) or GP[2] (I/O/Z) [default]
P1
I/O/Z
I/O/Z
UTOPIA transmit address pin 2 (UXADDR2) (I) or PCI command/byte enable 3
(I/O/Z)
UXADDR2/PCBE3
UXADDR1/PIDSEL
P5
R3
UTOPIA transmit address pin 1 (UXADDR1) (I) or PCI initialization device
select (I)
I
UXADDR0/PIRDY
HD31/AD31
HD30/AD30
HD29/AD29
HD28/AD28
HD27/AD27
HD26/AD26
HD25/AD25
HD24/AD24
HD23/AD23
HD22/AD22
HD21/AD21
HD20/AD20
HD19/AD19
HD18/AD18
HD17/AD17
HD16/AD16
HD15/AD15
HD14/AD14
HD13/AD13
HD12/AD12
HD11/AD11
HD10/AD10
HD9/AD9
P4
AA3
AA5
AC4
AA4
AC5
Y1
I/O/Z
UTOPIA transmit address pin 0 (UXADDR0) (I) or PCI initiator ready (I/O/Z)
AD2
W1
Host-port data [31:16] pin (I/O/Z) [default] or PCI data-address bus [31:16]
(I/O/Z)
I/O/Z
AC3
AE1
AD1
W2
AC1
Y2
AB1
Y3
AB2
W4
AC2
V4
AF3
AE3
AB3
W5
HD8/AD8
I/O/Z
Host-port data [15:0] pin (I/O/Z) [default] or PCI data-address bus [15:0] (I/O/Z)
HD7/AD7
AB4
Y4
HD6/AD6
HD5/AD5
AD3
Y5
HD4/AD4
HD3/AD3
AD4
W6
HD2/AD2
HD1/AD1
AB5
AE2
HD0/AD0
Device Overview
23
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
EMIFA (64-BIT) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
ABA1/EMIFA_EN
ABA0/DDR2_EN
V25
O/Z
O/Z
IPD
IPD
EMIFA bank address control (ABA[1:0])
Active-low bank selects for the 64-bit EMIFA.
•
When interfacing to 16-bit Asynchronous devices, ABA1 carries bit 1 of the
byte address.
For an 8-bit Asynchronous interface, ABA[1:0] are used to carry bits 1 and
0 of the byte address
V26
DDR2 EMIF enable (DDR2_EN) [ABA0]
0 - DDR2 EMIF peripheral pins are disabled (default)
1 - DDR2 EMIF peripheral pins are enabled
EMIFA enable (EMIFA_EN) [ABA1]
0 - EMIFA peripheral pins are disabled (default)
1 - EMIFA peripheral pins are enabled
ACE5
ACE4
ACE3
ACE2
ABE7
ABE6
ABE5
ABE4
ABE3
ABE2
ABE1
ABE0
V27
V28
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
EMIFA memory space enables
•
Enabled by bits 28 through 31 of the word address
W26
W27
W29
K26
•
Only one pin is asserted during any external data access
Note: The C6455 device does not have ACE0 and ACE1 pins
L29
EMIFA byte-enable control
L28
•
Decoded from the low-order address bits. The number of address bits or
byte enables used depends on the width of external memory.
AA29
AA28
AA25
AA26
•
Byte-write enables for most types of memory.
EMIFA (64-BIT) - BUS ARBITRATION
AHOLDA
AHOLD
N26
R29
L27
O
I
IPU
IPU
IPU
EMIFA hold-request-acknowledge to the host
EMIFA hold request from the host
EMIFA bus request output
ABUSREQ
O
EMIFA (64-BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
EMIFA external input clock. The EMIFA input clock (AECLKIN or SYSCLK3
AECLKIN
N29
I
IPD
clock) is selected at reset via the pullup/pulldown resistor on the AEA[15] pin.
Note: AECLKIN is the default for the EMIFA input clock.
AECLKOUT
V29
O/Z
O/Z
IPD
IPU
EMIFA output clock [at EMIFA input clock (AECLKIN or SYSCLK3) frequency]
Asynchronous memory write-enable/Programmable synchronous interface
write-enable
AAWE/ASWE
AB25
AARDY
K29
W25
Y28
I
IPU
IPU
IPU
Asynchronous memory ready input
AR/W
O/Z
O/Z
Asynchronous/Programmable synchronous memory read/write
Asynchronous/Programmable synchronous memory output-enable
Programmable synchronous address strobe or read-enable
AAOE/ASOE
•
For programmable synchronous interface, the r_enable fileld in the Chip
Select x Configuration Register selects between ASADS and ASRE:
ASADS/ASRE
R26
O/Z
IPU
–
If r_enable = 0, then the ASADS/ASRE signal functions as the ASADS
signal.
–
If r_enable = 1, then the ASADS/ASRE signal functions as the ASRE
signal.
24
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
TYPE(1) IPD/IPU(2)
DESCRIPTION
NAME
NO.
EMIFA (64-BIT) - ADDRESS
AEA19/BOOTMODE3
AEA18/BOOTMODE2
AEA17/BOOTMODE1
AEA16/BOOTMODE0
AEA15/AECLKIN_SEL
AEA14/HPI_WIDTH
AEA13/LENDIAN
N25
L26
L25
P26
P27
R25
R27
R28
EMIFA external address (word address) (O/Z)
Controls initialization of the DSP modes at reset (I) via pullup/pulldown resistors
[For more detailed information, see the Device Configurations section of this
datasheet.]
O/Z
O/Z
IPD
IPU
•
Bootmode - device bootmode configurations (BOOTMODE[3:0]) [Note: the
peripheral must be enabled to use the particular bootmode.]
AEA[19:16]:
0000 - No boot (default mode)
0001 - HostHPI/PCI boot
0010 -Reserved
0011 - Reserved
AEA12/UTOPIA_EN
0100 - EMIFA 8-bit ROM boot
0101 - Master I2C boot
0110 - Slave I2C boot
0111 - Reserved
1000 thru 1111 - Serial Rapid I/O boot configurations
For more detailed information on the bootmodes, see Section 2.4,
Bootmode Sequence of this document.
•
•
EMIFA input clock source select
Clock mode select for EMIFA (AECLKIN_SEL)
AEA15:
0 - AECLKIN (default mode)
1 - SYSCLK3 (CPU/x) Clock Rate. The SYSCLK3 clock rate is software
selectable via the Software PLL1 Controller. By default, SYSCLK3 is
selected as CPU/8 clock rate.
HPI peripheral bus width (HPI_WIDTH) select
[Applies only when HPI is enabled; PCI_EN pin = 0]
AEA14:
0 - HPI operates as an HPI16 (default). (HPI bus is 16 bits wide. HD[15:0]
pins are used and the remaining HD[31:16] pins are reserved pins in the
Hi-Z state.)
AEA11
T25
1 - HPI operates as an HPI32.
•
•
Device Endian mode (LENDIAN)
AEA13:
0 - System operates in Big Endian mode
1 - System operates in Little Endian mode(default)
O/Z
IPD
UTOPIA Enable bit (UTOPIA_EN)
AEA12: UTOPIA peripheral enable(functional)
0 - UTOPIA disabled; Ethernet MAC (EMAC) and MDIO enable(default).
This means all multiplexed EMAC/UTOPIA and MDIO/UTOPIA pins func-
tion as EMAC and MDIO. Which EMAC/MDIO configuration (interface) [MII,
RMII, GMII or the standalone RGMII] is controlled by the MACSEL[1:0] bits.
1 - UTOPIA enabled; EMAC and MDIO disabled [except when the
MACSEL[1:0] bits = 11 then, the EMAC/MDIO RGMII interface is still
functional].
This means all multiplexed EMAC/UTOPIA and MDIO/UTOPIA pins now
function as UTOPIA. And if MACSEL[1:0] = 11, the RGMII standalone pin
functions can be used.
AEA10/MACSEL1
AEA9/MACSEL0
M25
M27
•
EMAC/MDIO interface select bits (MACSEL[1:0])
If the EMAC and MDIO peripherals are enabled, AEA12 pin (UTOPIA_EN
= 0) , there are two additional configuration pins — MACSEL[1:0] — to
select the EMAC/MDIO interface.
AEA[10:9]: MACSEL[1:0] with AEA12 =0.
00 - 10/100 EMAC/MDIO MII Mode Interface (default)
01 - 10/100 EMAC/MDIO RMII Mode Interface
10 - 10/100/1000 EMAC/MDIO GMII Mode Interface
11 - 10/100/1000 with RGMII Mode Interface
[RGMII interface requires a 1.8 V or 1.5 V I/O supply]
When UTOPIA is enabled (AEA12 = 1), if the MACSEL[1:0] bits = 11 then,
the EMAC/MDIO RGMII interface is still functional. For more detailed
information, see the Device Configuraiton section of this data sheet.
Device Overview
25
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
P25
N27
U27
U28
AEA8/PCI_EEAI
AEA7
•
•
PCI EEPROM Auto-Initialization (PCI_EEAI)
AEA8: PCI auto-initialization via external EEPROM
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be
pulled up.
0 - PCI auto-initialization through EEPROM is disabled (default).
1 - PCI auto-initialization through EEPROM is enabled.
AEA6/PCI66
AEA5/MCBSP1_EN
AEA4/SYSCLKOUT_
EN
T28
PCI Frequency Selection (PCI66)
[The PCI peripheral needs be enabled (PCI_EN = 1) to use this function]
Selects the PCI operating frequency of 66 MHz or 33 MHz PCI operating
frequency is selected at reset via the pullup/pulldown resistor on the PCI66
pin:
AEA3
T27
T26
U26
AEA2/CFGGP2
AEA1/CFGGP1
AEA6:
0 - PCI operates at 33 MHz (default).
1 - PCI operates at 66 MHz.
Note: If the PCI peripheral is disabled (PCI_EN = 0), this pin must not be
pulled up.
•
•
•
McBSP1 Enable bit (MCBSP1_EN)
Selects which function is enabled on the McBSP1/GPIO muxed pins
O/Z
IPD
AEA5:
0 - GPIO pin functions enabled (default).
1 - McBSP1 pin functions enabled.
SYSCLKOUT Enable bit (SYSCLKOUT_EN)
Selects which function is enabled on the SYSCLK3/GP[1] muxed pin
AEA0/CFGGP0
U25
AEA4:
0 - GP[1] pin function of the SYSCLK3/GP[1] pin enabled (default).
1 - SYSCLK3 pin function of the SYSCLK3/GP[1] pin enabled.
Configuration GPI (CFGGP[2:0]) (AEA[2:0])
These pins are latched during reset and their values are shown in the
DEVSTAT register. These values can be used by S/W routines for boot
operations.
Note: For proper C6455 device operation, the AEA11 and AEA3 pins must be
externally pulled up with a 1-kΩ resistor during Power-On Reset, Warm Reset,
and Max Reset.
Also for proper C6455 device operation, do not oppose the IPD on the AEA7
pin during Power-On Reset, Warm Reset, and Max Reset.
26
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
EMIFA (64-BIT) - DATA
AED63
AED62
AED61
AED60
AED59
AED58
AED57
AED56
AED55
AED54
AED53
AED52
AED51
AED50
AED49
AED48
AED47
AED46
AED45
AED44
AED43
AED42
AED41
AED40
AED39
AED38
AED37
AED36
AED35
AED34
AED33
AED32
AED31
AED30
AED29
AED28
AED27
AED26
AED25
AED24
AED23
AED22
F25
A27
C27
C28
E27
D28
D27
F27
G25
G26
A28
F28
B28
G27
B27
G28
H25
J26
H26
J27
H27
J28
I/O/Z
IPU
EMIFA external data
C29
J29
D29
J25
F29
F26
G29
K28
K25
K27
AA27
AG29
AB29
AC27
AB28
AC26
AB27
AC25
AB26
AD28
Device Overview
27
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
AED21
AED20
AED19
AED18
AED17
AED16
AED15
AED14
AED13
AED12
AED11
AED10
AED9
AD29
AJ28
AF29
AH28
AE29
AG28
AF28
AH26
AE28
AE26
AD26
AF27
AG27
AD27
AE25
AJ27
AJ26
AE27
AG25
AH27
AF25
AD25
I/O/Z
IPU
EMIFA external data
AED8
AED7
AED6
AED5
AED4
AED3
AED2
AED1
AED0
DDR2 Memory Controller (32-BIT) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
DDR2 Memory Controller memory space enables
DCE0
E14
O/Z
•
•
Enabled by bits 28 through 31 of the word address
Only one pin is asserted during any external data access
DBA2
DBA1
DBA0
E15
D15
C15
B14
A14
D13
C13
B13
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
DDR2 Memory Controller bank address control
•
DDR2CLKOUT
DDR2CLKOUT
DSDCAS
DDR2 Memory Controller output clock (CPU/4 frequency)
Negative DDR2 Memory Controller output clock (CPU/4 frequency)
DDR2 Memory Controller SDRAM column-address strobe
DDR2 Memory Controller SDRAM row-address strobe
DSDRAS
DSDWE
DDR2 Memory Controller SDRAM write-enable
DDR2 Memory Controller SDRAM clock-enable (used for self-refresh mode).
DSDCKE
D14
O/Z
•
If SDRAM is not in system, SDCKE can be used as a general-purpose
output.
DEODT1
DEODT0
A17
E16
O/Z
O/Z
On-die termination signals to external DDR2 SDRAM.
Note: There are no on-die termination resistors implemented on the C6455
DSP die.
DSDDQGATE3
DSDDQGATE2
DSDDQGATE1
DSDDQGATE0
F21
E21
B9
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DDR2 Memory Controller data strobe gate [3:0]
For hookup of these signals, please refer to the Implementing DDR2 PCB
Layout on a TMS320C6455 Hardware Design Application Report (Literature
Number SPRAAA7) [Document Release Pending].
A9
28
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
DSDDQM3
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
C23
C20
C8
O/Z
O/Z
O/Z
DDR2 Memory Controller byte-enable controls
•
Decoded from the low-order address bits. The number of address bits or
byte enables used depends on the width of external memory.
DSDDQM2
DSDDQM1
•
•
Byte-write enables for most types of memory.
DSDDQM0
C11
O/Z
Can be directly connected to SDRAM read and write mask signal (SDQM).
DSDDQS3
DSDDQS2
DSDDQS1
DSDDQS0
DSDDQS3
DSDDQS2
DSDDQS1
DSDDQS0
E23
E20
E8
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DDR2 Memory Controller data strobe [3:0] positive
DDR2 Memory Controller data strobe [3:0] negative
E11
D23
D20
D8
D11
DDR2 MEMORY CONTROLLER (32-BIT) - ADDRESS
DEA13
DEA12
DEA11
DEA10
DEA9
DEA8
DEA7
DEA6
DEA5
DEA4
DEA3
DEA2
DEA1
DEA0
B15
A15
A16
B16
C16
D16
B17
C17
D17
E17
A18
B18
C18
D18
O/Z
DDR2 Memory Controller external address (word address)
Device Overview
29
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
DDR2 MEMORY CONTROLLER (32-BIT) - DATA
DED31
DED30
DED29
DED28
DED27
DED26
DED25
DED24
DED23
DED22
DED21
DED20
DED19
DED18
DED17
DED16
DED15
DED14
DED13
DED12
DED11
DED10
DED9
B25
A25
B24
A24
D22
C22
B22
A22
D21
C21
B21
A21
D19
C19
A19
B19
C7
I/O/Z
DDR2 Memory Controller external data
D7
A7
B7
F9
E9
D9
DED8
C9
DED7
D10
C10
B10
A10
D12
C12
B12
A12
DED6
DED5
DED4
DED3
DED2
DED1
DED0
TIMER 1
TOUTL1L
TINPL1
AG7
AJ6
O/Z
I
IPD
IPD
Timer 1 output pin for lower 32-bit counter
Timer 1 input pin for lower 32-bit counter
TIMER 0
TOUTL0
TINPL0
AF8
AH6
O/Z
I
IPD
IPD
Timer 0 output pin for lower 32-bit counter
Timer 0 input pin for lower 32-bit counter
INTER-INTEGRATED CIRCUIT (I2C)
SCL
SDA
AG26
AF26
I/O/Z
I/O/Z
—
—
I2C clock. When the I2C module is used, use an external pullup resistor.
I2C data. When I2C is used, ensure there is an external pullup resistor.
MULTICHANNEL BUFFERED SERIAL PORT 1 AND MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP1 and McBSP0)
McBSP external clock source (as opposed to internal) (I/O/Z)
[shared by McBSP1 and McBSP0]
CLKS
AJ4
I/O/Z
IPD
30
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKR1/GP[0]
AF4
AE5
AH5
AG5
AG4
AF5
I/O/Z
IPD
IPD
IPD
IPD
IPD
IPD
McBSP1 receive clock (I/O/Z) or GP[1] (I/O/Z) [default]
FSR1/GP[10]
DR1/GP[8]
I/O/Z
I
McBSP1 receive frame sync (I/O/Z) or GP[10] (I/O/Z) [default]
McBSP1 receive data (I) or GP[8] (I/O/Z) [default]
DX1/GP[9]
O/Z
I/O/Z
I/O/Z
McBSP1 transmit data (O/Z) or GP[9] (I/O/Z) [default]
McBSP1 transmit frame sync (I/O/Z) or GP[11] (I/O/Z) [default]
McBSP1 transmit clock (I/O/Z) or GP[3] (I/O/Z) [default]
FSX1/GP[11]
CLKX1/GP[3]
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKR0
FSR0
DR0
AG1
AH3
AJ5
AF6
AJ3
AG6
I/O/Z
I/O/Z
I
IPU
IPD
IPD
IPD
IPD
IPU
McBSP0 receive clock (I/O/Z)
McBSP0 receive frame sync (I/O/Z)
McBSP0 receive data (I)
DX0
O/Z
I/O/Z
I/O/Z
McBSP0 transmit data (O/Z)
McBSP0 transmit frame sync (I/O/Z)
McBSP0 transmit clock (I/O/Z)
FSX0
CLKX0
UNIVERSAL TEST AND OPERATIONS PHY INTERFACE for ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA SLAVE]
UTOPIA SLAVE (ATM CONTROLLER) - TRANSMIT INTERFACE
Source clock for UTOPIA transmit driven by Master ATM Controller.
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
UXCLK/MTCLK/
RMREFCLK
pin is either EMAC MII transmit clock (MTCLK) or the EMAC RMII reference
clock. The EMAC function is controlled by the MACSEL[1:0] (AEA[10:9] pins).
For more detailed information, see the Device Configuration section of this
datasheet.
N4
K5
I/O/Z
I/O/Z
Transmit cell available status output signal from UTOPIA Slave.
0 indicates a complete cell is NOT available for transmit
1 indicates a complete cell is available for transmit
UXCLAV/GMTCLK
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC GMII transmit clock. MACSEL[1:0] dependent.
UTOPIA transmit interface enable input signal. Asserted by the Master ATM
Controller to indicate that the UTOPIA Slave should put out on the Transmit
Data Bus the first byte of valid data and the UXSOC signal in the next clock
cycle.
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is either the EMAC MII transmit enable [default] or EMAC RMII transmit
enable or EMAC GMII transmit enable. MACSEL[1:0] dependent.
UXENB/MTXEN/
RMTXEN
J5
I/O/Z
Transmit Start-of-Cell signal. This signal is output by the UTOPIA Slave on the
rising edge of the UXCLK, indicating that the first valid byte of the cell is
available on the 8-bit Transmit Data Bus (UXDATA[7:0]).
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is either the EMAC MII collision sense or EMAC GMII collision sense.
MACSEL[1:0] dependent.
UXSOC/MCOL
K3
I/O/Z
UXADDR4/MDCLK
UXADDR3/MDIO
UXADDR2/PCBE3
UXADDR1/PIDSEL
M5
N3
P5
R3
I
I
I
I
UTOPIA transmit address pins (UXADDR[4:0]) (I)
As UTOPIA transmit address pins, UTOPIA_EN (AEA12 pin) = 1:
•
5-bit Slave transmit address input pins driven by the Master ATM Controller
to identify and select one of the Slave devices (up to 31 possible) in the
ATM System.
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0) and if
the PCI_EN pin (TBD) = 1, these pins are PCI peripheral pins -
PCI command/byte enable 3(PCBE3) [I/O/Z],
PCI initialization device select (PIDSEL) [I], and
PCI initiator ready (PIRDY) [I/O/Z].
UXADDR0/PIRDY
P4
I
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
pins are MDIO MII or GMII serial data input/output (MDIO or GMDIO).
MACSEL[1:0] dependent.
Device Overview
31
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
N5
M3
L5
UXDATA7/MTXD7
UXDATA6/MTXD6
UXDATA5/MTXD5
UXDATA4/MTXD4
UXDATA3/MTXD3
UXDATA2/MTXD2
UTOPIA 8-bit transmit data bus (I/O/Z) or EMAC MII 4-bit transmit data bus
(I/O/Z) [default] or EMAC GMII 8-bit transmit data bus or EMAC RMII 2-bit
transmit data bus (I/O/Z)
Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the
UXCLK) transmits the 8-bit ATM cells to the Master ATM Controller.
L3
K4
M4
I/O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
pins function as EMAC pins and are controlled by the MACSEL[1:0] (AEA[10:9]
pins) to select the MII, RMII, GMII or RGMII EMAC interface. (For more details,
see the Device Configurations section of this datasheet).
UXDATA1/MTXD1/
RMTXD1
L4
UXDATA0/MTXD0/
RMTXD0
M1
UTOPIA SLAVE (ATM CONTROLLER) - RECEIVE INTERFACE
Source clock for UTOPIA receive driven by Master ATM Controller.
URCLK/MRCLK
H1
J4
I/O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or GMII receive clock. MACSEL[1:0] dependent.
Receive cell available status output signal from UTOPIA Slave.
0 indicates NO space is available to receive a cell from Master ATM Controller
1 indicates space is available to receive a cell from Master ATM Controller
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII carrier sense [deafult] or RMII carrier sense/data valid or GMII
carrier sense. MACSEL[1:0] dependent. MACSEL[1:0] dependent.
URCLAV/MCRS/
RMCRSDV
I/O/Z
UTOPIA receive interface enable input signal. Asserted by the Master ATM
Controller to indicate to the UTOPIA Slave to sample the Receive Data Bus
(URDATA[7:0]) and URSOC signal in the next clock cycle or thereafter.
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or GMII receive data valid. MACSEL[1:0] dependent.
URENB/MRXDV
H5
H4
I/O/Z
I/O/Z
Receive Start-of-Cell signal. This signal is output by the Master ATM Controller
to indicate to the UTOPIA Slave that the first valid byte of the cell is available to
sample on the 8-bit Receive Data Bus (URDATA[7:0]).
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or RMII or GMII receive error. MACSEL[1:0]
dependent.
URSOC/MRXER/
RMRXER
URADDR4/PCBE0/
GP[2]
UTOPIA receive address pins [URADDR[4:0] (I)]:
As UTOPIA receive address pins, UTOPIA_EN (AEA12 pin) = 1:
P1
P2
P3
R5
I
I
I
I
•
5-bit Slave receive address input pins driven by the Master ATM Controller
to identify and select one of the Slave devices (up to 31 possible) in the
ATM System.
URADDR3/PREQ/
GP[15]
URADDR2/PINTA/
GP[14]
•
When the UTOPIA peripheral is disabled [UTOPIA_EN (AEA12 pin) = 0],
these pins are PCI (if PCI_EN = 1) or GPIO (if PCI_EN = 0) pins
(GP[15:12, 2]).
URADDR1/PRST/
GP[13]
As PCI peripheral pins -
PCI command/byte enable 0 (PCBE0) [I/O/Z]
PCI bus request (PREQ) [O/Z],
PCI interrupt A (PINTA) [O/Z],
PCI reset (PRST) [I] and
URADDR0/PGNT/
GP[12]
R4
I
PCI bus grant (PGNT) [I/O/Z].
URDATA7/MRXD7
URDATA6/MRXD6
URDATA5/MRXD5
URDATA4/MRXD4
URDATA3/MRXD3
URDATA2/MRXD2
M2
H2
L2
L1
J3
UTOPIA 8-bit Receive Data Bus (I/O/Z) or EMAC receive data bus [MII] (I/O/Z)
[default] or [GMII] (I/O/Z) or [RMII] (I/O/Z)
Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the
URCLK) can receive the 8-bit ATM cell data from the Master ATM Controller.
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
pins function as EMAC pins and are controlled by the MACSEL[1:0] (AEA[10:9]
pins) to select the MII, RMII, GMII, or RGMII EMAC interface. (For more details,
see the Device Configurations section of this data sheet).
I/O/Z
J1
URDATA1/MRXD1/
RMRXD1
H3
J2
URDATA0/MRXD0/
RMRXD0
32
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
RAPID I/O SERIAL PORT
RIOCLK
RIOCLK
RIOTX3
RIOTX2
RIOTX1
RIOTX0
RIOTX3
RIOTX2
RIOTX1
RIOTX0
RIORX3
RIORX2
RIORX1
RIORX0
RIORX3
RIORX2
RIORX1
RIORX0
AF15
AG15
AF17
AG18
AG22
AF23
AF18
AG19
AG21
AF22
AH18
AJ18
AJ22
AH22
AH17
AJ19
AJ21
AH23
I
I
Rapid I/O serial port source (reference) clock
Negative Rapid I/O serial port source (reference) clock
O
Rapid IO transmit data bus bits [3:0]
O/Z
Rapid IO negative transmit data bus bits [3:0] (differential)
Rapid IO receive data bus bits [3:0]
I
I
Rapid IO negative receive data bus bits [3:0] (differential)
MANAGEMENT DATA INPUT/OUTPUT (MDIO) FOR MII/RMII/GMII
UXADDR4/MDCLK
UXADDR3/MDIO
M5
N3
I/O/Z
I/O/Z
IPD
IPU
UTOPIA transmit address pin 4 or MDIO serial clock input/output
UTOPIA transmit address pin 3 or MDIO serial data input/output
MANAGEMENT DATA INPUT/OUTPUT (MDIO) FOR RGMII
RGMDCLK
RGMDIO
B4
A4
O/Z
I/O/Z
MDIO serial clock input/output (RGMII mode)
MDIO serial data input/output (RGMII mode)
ETHERNET MAC (EMAC) [MII/RMII/GMII]
If the Ethernet MAC (EMAC) and MDIO peripherals are enabled (AEA12 pin driven low [UTOPIA_EN = 0]), there are two additional
configuration pins — the MAC_SEL[1:0] (AEA[10:9] pins) — that select one of the four interface modes (MII, RMII, GMII, or RGMII) for the
EMAC/MDIO interface. For more detailed information on the EMAC select pins, see the Device Configuration section of this document.
UTOPIA receive clock (URCLK) driven by Master ATM Controller(TBD) or
URCLK/MRCLK
H1
I/O/Z
I/O/Z
I/O/Z
when the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or GMII receive clock. MACSEL[1:0] dependent.
UTOPIA receive cell available status output signal from UTOPIA Slave(TBD) or
when the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII carrier sense [default] or RMII carrier sense/data valid or GMII
carrier sense. MACSEL[1:0] dependent.
URCLAV/MCRS/
RMCRSDV
J4
UTOPIA receive Start-of-Cell signal (TBD) or when the UTOPIA peripheral is
disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is EMAC MII [default] or RMII
or GMII receive error. MACSEL[1:0] dependent.
URSOC/MRXER/
RMRXER
H4
UTOPIA receive interface enable input signal. Asserted by the Master ATM
Controller to indicate to the UTOPIA Slave to sample the Receive Data Bus
(URDATA[7:0]) and URSOC signal in the next clock cycle or thereafter.
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or GMII receive data valid. MACSEL[1:0] dependent.
URENB/MRXDV
H5
I/O/Z
Device Overview
33
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
M2
H2
L2
URDATA7/MRXD7
URDATA6/MRXD6
URDATA5/MRXD5
URDATA4/MRXD4
URDATA3/MRXD3
URDATA2/MRXD2
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
UTOPIA 8-bit Receive Data Bus (I/O/Z) [default] or EMAC receive data bus
[MII] (I/O/Z) [default] or [GMII] (I/O/Z) or [RMII] (I/O/Z)
L1
Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the
URCLK) can receive the 8-bit ATM cell data from the Master ATM Controller.
J3
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
pins function as EMAC pins and are controlled by the MACSEL[1:0] (AEA[10:9]
pins) to select the MII, RMII, GMII or RGMII EMAC interface. (For more details,
see the Device Configurations section of this datasheet).
J1
URDATA1/MRXD1/
RMTXD1
H3
J2
I/O/Z
I/O/Z
URDATA0/MRXD0/
RMTXD0
Transmit cell available status output signal from UTOPIA Slave.
0 indicates a complete cell is NOT available for transmit
1 indicates a complete cell is available for transmit
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC GMII transmit clock. MACSEL[1:0] dependent.
UXCLAV/GMTCLK
K5
N4
I/O/Z
I/O/Z
UTOPIA transmit source clock (UXCLK) driven by Master ATM Controller
(TBD) or when the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] =
0), this pin is either EMAC MII transmit clock (MTCLK) [default] or the EMAC
RMII reference clock. The EMAC function is controlled by the MACSEL[1:0]
(AEA[10:9] pins). For more detailed information, see the Device Configuration
section of this datasheet.
UXCLK/MTCLK/
RMREFCLK
UTOPIA transmit Start-of-Cell signal. This signal is output by the UTOPIA Slave
on the rising edge of the UXCLK, indicating that the first valid byte of the cell is
available on the 8-bit Transmit Data Bus (UXDATA[7:0]).
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is either the EMAC MII collision sense [default] or EMAC GMII collision
sense. MACSEL[1:0] dependent.
UXSOC/MCOL
K3
J5
O/Z
UTOPIA transmit interface enable input signal (TBD) or when the UTOPIA
peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is either the
EMAC MII transmit enable [default] or EMAC RMII transmit enable or EMAC
GMII transmit enable. MACSEL[1:0] dependent.
UXENB/MTXEN/
RMTXEN
I/O/Z
UXDATA7/MTXD7
UXDATA6/MTXD6
UXDATA5/MTXD5
UXDATA4/MTXD4
UXDATA3/MTXD3
UXDATA2/MTXD2
N5
M3
L5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
UTOPIA 8-bit transmit data bus (I/O/Z) or EMAC MII 4-bit transmit data bus
(I/O/Z) [default] or EMAC GMII 8-bit transmit data bus or EMAC RMII 2-bit
transmit data bus (I/O/Z)
L3
Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the
UXCLK) transmits the 8-bit ATM cells to the Master ATM Controller.
K4
M4
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
pins function as EMAC pins and are controlled by the MACSEL[1:0] (AEA[10:9]
pins) to select the MII, RMII, GMII or RGMII EMAC interface. (For more details,
see the Device Configurations section of this datasheet).
UXDATA1/MTXD1/
RMTXD1
L4
I/O/Z
I/O/Z
UXDATA0/MTXD0/
RMTXD0
M1
ETHERNET MAC (EMAC) [RGMII]
If the Ethernet MAC (EMAC) and MDIO peripherals are enabled (AEA12 pin driven low [UTOPIA_EN = 0]), there are two additional
configuration pins — the MAC_SEL[1:0] (AEA[10:9] pins) — that select one of the four interface modes (MII, RMII, GMII, or RGMII) for the
EMAC/MDIO interface. For more detailed information on the EMAC select pins, see the Device Configuration section of this document.
RGREFCLK
RGTXC
C4
D4
A2
C3
B3
A3
D3
E3
O/Z
O/Z
RGMII reference clock. MACSEL[1:0] =11
RGMII transmit clock. MACSEL[1:0] =11
RGTXD3
RGTXD2
RGTXD1
RGTXD0
RGTXCTL
RGRXC
O/Z
RGMII transmit data [3:0]. MACSEL[1:0] =11
O/Z
I
RGMII transmit enable. MACSEL[1:0] =11
RGMII receive clock. MACSEL[1:0] =11
34
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
RGRXD3
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
C1
E4
E2
E1
C2
I
I
I
I
I
RGRXD2
RGRXD1
RGRXD0
RGRXCTL
RGMII receive data [3:0] TBD. MACSEL[1:0] =11
RGMII receive control [for error detection and data valid]. MACSEL[1:0] =11
RESERVED FOR TEST
RSV01
RSV02
RSV03
RSV04
RSV05
N1
V5
Reserved. These pins must be connected directly to Core Supply (CVDD) for
proper device operation
W3
N11
P11
Reserved. This pin must be connected directly to 3.3-V I/O Supply (DVDD33) for
proper device operation.
RSV06
RSV07
L6
G4
I
I
I
Reserved. This pin must be connected directly to 1.5-/1.8-V I/O Supply
(DVDD15) for proper device operation.
Note: If the EMAC RMII is not used, these pins can be connected directly to
ground (VSS) .
RSV08
F3
RSV09
RSV10
D26
A26
Reserved. This pin must be connected directly to 1.8-V I/O Supply (DVDD18) for
proper device operation.
Reserved. This pin must be connected via a 200-Ω resistor directly to ground
(VSS) for proper device operation.
Note: If the DDR2 Memory Controller is not used, this pin can be connected
directly to ground (VSS) .
RSV11
RSV12
RSV13
RSV14
D24
C24
F2
Reserved. This pin must be connected via a 200-Ω resistor directly to 1.8-V I/O
Supply (DVDD18) for proper device operation.
Note: If the DDR2 Memory Controller is not used, this pin can be connected
directly to ground (VSS) .
Reserved. If EMAC RGMII is used, this pin must be connected via a 200-Ω
resistor directly to ground (VSS) for proper device operation.
If EMAC RGMII is not used, this pin can be connected directly to ground (VSS
for proper device operation.
)
)
Reserved. If EMAC RGMII is used, this pin must be connected via a 200-Ω
resistor directly to 1.5/1.8-V I/O Supply (DVDD15) for proper device operation.
If EMAC RGMII is not used, this pin can be connected directly to ground (VSS
for proper device operation.
F1
Reserved. This pin must be connected via a 40-Ω resistor directly to ground
(VSS) for proper device operation.
RSV15
RSV16
T1
T2
Reserved. This pin must be connected via a 20-Ω resistor directly to 3.3-V I/O
Supply (DVDD33) for proper device operation.
Device Overview
35
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
AE21
E13
F18
U29
A6
RSV17
RSV18
RSV19
RSV20
RSV21
RSV22
RSV23
RSV24
RSV25
RSV26
RSV27
RSV36
RSV37
RSV38
RSV39
RSV40
RSV41
RSV42
RSV43
RSV44
RSV28
RSV29
RSV30
RSV31
RSV32
RSV33
RSV34
RSV35
A
A
A
A
A
O
O
O
O
A
A
B26
C26
B6
C6
AJ11
AH11
AD11
AD9
AG10
AG11
AJ12
W28
Y26
Y25
Y27
N7
Reserved (leave unconnected, do not connect to power or ground)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
O/Z
O/Z
O/Z
O/Z
A
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
N6
A
P23
P24
D25
C25
E6
A
A
Reserved. This pin must be connected directly to VSS for proper device
operation.
I
IPD
IPD
IPD
IPD
I
I
D6
I
SUPPLY VOLTAGE PINS
NOTE: The number of blank rows in each respecitve supply voltage and ground (GND) sections to follow indicates the actual number of
supply voltage pins or GND pins required on the C6455 device.
1.8/2-V reference for SSTL buffer [DDR2 Memory Controller peripheral].
VREFSSTL
VREFHSTL
DVDDR
C14
B2
A
A
S
NOTE: If the DDR2 Memory Controller peripheral is not used, connect this pin
to VSS
.
1.8/2-V or 1.5/2-V reference for HSTL buffer [EMAC RGMII peripheral].
NOTE: If the EMAC RGMII peripheral is not used, connect this pin to VSS
.
1.8-V I/O supply voltage (RapidIO I/O Voltage for Rapid I/O regulator supply).
AD20
NOTE: If Rapid I/O is not used, these pins must be connected directly to VSS
for proper device operation.
VDDA– 1.2-V I/O supply voltage (RapidIO I/O Voltage for Rapid I/O analog
supply)
AC15
AC17
AD16
ADVDD12
A
A
Do not use the core supply.
NOTE: If Rapid I/O is not used, these pins must be connected directly to VSS
for proper device operation.
A13
E18
AVDD18
1.8-V I/O supply voltage (DDR2 Memory Controller)
36
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
U16
V15
V17
W16
W18
AE17
AE19
AE23
AF20
AH20
AJ17
AJ23
A1
1.2-V I/O supply voltage
(RapidIO I/O Voltage for Rapid I/O termination supply),
(RapidIO I/O Voltage for Rapid I/O digital supply)
(RapidIO I/O MAC/PHY supply)
DVDD12
S
Do not use the core supply.
NOTE: If Rapid I/O is not used, these pins must be connected directly to VSS
for proper device operation.
B5
D2
1.8-V or 1.5-V I/O supply voltage (EMAC RGMII I/O Voltage)
NOTE: If EMAC RGMII is not used, these pins must be connected directly to
VSS for proper device operation.
DVDD15
D5
S
F5
G6
H7
B8
B11
B20
B23
E10
E12
E22
E24
F7
F11
F13
F15
F17
F19
F23
G8
DVDD18
S
1.8-V I/O supply voltage (DDR2 EMIF I/O Voltage)
G10
G12
G14
G16
G18
G20
G22
G24
Device Overview
37
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
A29
E26
E28
G2
H23
H28
J6
DVDD33
S
3.3-V I/O supply voltage
J24
K1
K7
K23
L24
38
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
M7
M23
M28
N24
P6
P28
R1
R6
R23
T7
T24
U23
V1
V7
V24
W23
Y7
Y24
AA1
AA6
AA23
AB7
AB24
AC6
AC9
AC11
AC13
AC19
AC21
AC23
AC29
AD5
AD7
AD14
AD18
AD22
AD24
AE6
AE8
DVDD33
S
3.3-V I/O supply voltage
Device Overview
39
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
AE15
AF1
AF16
AF24
AG12
AG17
AG23
AH14
AH16
AH24
AJ1
DVDD33
S
3.3-V I/O supply voltage
AJ7
AJ15
AJ25
AJ29
L12
L14
L16
L18
M11
M13
M15
M17
M19
N12
CVDD
N14
S
1.2-V core supply voltage
N16
N18
P13
P15
P17
P19
R12
R14
R16
R18
40
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
T11
T13
T15
T17
T19
U12
U14
U18
V11
V13
V19
W12
W14
CVDD
S
1.2-V core supply voltage
GROUND PINS
A8
A11
A20
A23
B1
B29
C5
D1
E5
E7
VSS
GND
Ground pins
E19
E25
E29
F4
F6
F8
F10
F12
F14
F16
Device Overview
41
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
F20
F22
F24
G1
G5
G7
G9
G11
G13
G15
G17
G19
G21
G23
H6
H24
H29
J7
VSS
GND
Ground pins
J23
K2
K6
K24
L7
L11
L13
L15
L17
L19
L23
M6
M12
M14
42
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
M16
M18
M24
M26
M29
N2
N13
N15
N17
N19
N23
P7
P12
P14
P16
P18
P29
R2
VSS
GND
Ground pins
R7
R11
R13
R15
R17
R19
R24
T6
T12
T14
T16
T18
T23
U7
U11
U13
Device Overview
43
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
U15
U17
U19
U24
V2
V6
V12
V14
V16
V18
V23
W7
W11
W13
W15
W17
W19
W24
Y6
VSS
GND
Ground pins
Y23
AA2
AA7
AA24
AB6
AB23
AC7
AC8
AC10
AC12
AC14
AC16
AC18
44
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 2-3. Terminal Functions TBD (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
AC20
AC22
AC24
AC28
AD6
AD13
AD15
AD17
AD19
AD21
AD23
AE4
AE7
AE16
AE18
AE20
AE22
AE24
AF2
VSS
GND
Ground pins
AF19
AF21
AG13
AG16
AG20
AG24
AH1
AH15
AH19
AH21
AH25
AH29
AJ8
AJ14
AJ16
AJ20
AJ24
Device Overview
45
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
2.8 Development
2.8.1 Development Support
In case the customer would like to develop their own features and software on the C6455 device, TI offers
an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate
the performance of the processors, generate code, develop algorithm implementations, and fully integrate
and debug software and hardware modules. The tool's support documentation is electronically available
within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of C6000™ DSP-based applications:
Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any DSP application.
Hardware Development Tools:Extended Development System (XDS™) Emulator (supports C6000™
DSP multiprocessor system debug) EVM (Evaluation Module)
46
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
2.8.2 Device Support
2.8.2.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., TMX320C6455ZTZ1). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZTZ), the temperature range (for example, blank is the default commercial
temperature range), and the device speed range in megahertz (for example, 1 is 1 GHz). Figure 2-9
provides a legend for reading the complete device name for any TMS320C64x+™ DSP generation
member.
For device part numbers and further ordering information for TMS320C6455 in the ZTZ package type, see
the TI website ( http://www.ti.com) or contact your TI sales representative.
Device Overview
47
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
TMX
320
C6455
ZTZ
1
DEVICE SPEED RANGE
7 = 720 MHz
PREFIX
TMX = Experimental device
TMS = Qualified device
8 = 850 MHz
1 = 1 GHz
(A)
PACKAGE TYPE
ZTZ = 697-pin plastic BGA, with Pb-Free soldered balls
DEVICE FAMILY
320 = TMS320t DSP family
DEVICE
C64x+tDSP:
C6455
A. BGA = Ball Grid Array
Figure 2-9. TMS320C64x+™ DSP Device Nomenclature (including the TMS320C6455 DSP)
48
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
2.8.2.2 Documentation Support - TBD
2.9 Device Silicon Revision
The data manual supports the initial release of the C6455 device; therefore, no device-specific silicon
errata document is currently available.
3 Device Configurations
On the C6455 device, bootmode and certain device configurations/peripheral selections are determined at
device reset, while peripheral usage (on/off) is determined by the Power Saver registers after device reset.
By default, the peripherals on the C6455 device are "off" and need to be "turned on". For more
details, see the Power Saver section of this document.
RESERVED (AEA[3] pin), for proper device operation this pin must be externally PULLED UP
RESERVED (AEA[11] pin), for proper device operation this pin must be externally PULLED UP
The C6455 has no hardware CLKMODE selection, the PLL1 multiply factor is set in software during boot.
3.1 Device Configuration at Device Reset
Table 3-1 describes the C6455 device configuration pins. The logic level of the AEA[19:0], ABA[1:0], and
PCI_EN pins is latched at reset to determine the device configuration. The logic level on the device
configuration pins can be set by using external pullup/pulldown resistors or by using some control device
(e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to
ensure there is no contention on the lines when the device is out of reset. The device configuration pins
are sampled during reset and are driven after the reset is removed. At this time, the control device should
ensure it has stopped driving the device configuration pins of the DSP to again avoid contention.
Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN)
CONFIGURATION
PIN
IPD/
NO.
FUNCTIONAL DESCRIPTION
Bootmode Selections (Bootmode [3:0]):
IPU(1)
[Note: the peripheral must be enabled to use the particular bootmode.]
0000 - No boot (default mode)
0001 - Host boot (HPI/PCI)
0010 - Reserved
0011 - Reserved
0100 - EMIFA 8-bit ROM boot
0101 - Master I2C boot
[N25,
L26,
L25,
P26]
AEA[19:16]
IPD
0110 - Slave I2C boot
0111 - Reserved
1000 thru 1111 - Serial Rapid I/O boot configurations
For more detailed information on the bootmodes, see Section 2.4, Bootmode Sequence of
this document.
EMIFA input clock source select
Clock mode select for EMIFA (AECLKIN_SEL)
AEA15
AEA14
P27
R25
IPD
IPD
0 - AECLKIN (default mode)
1 - SYSCLK3 (CPU/x) Clock Rate. The SYSCLK3 clock rate is software selectable via the
Software PLL1 Controller. By default, SYSCLK3 is selected as CPU/8 clock rate.
HPI peripheral bus width (HPI_WIDTH) select [Applies only when HPI is enabled; PCI_EN
pin = 0]
0 - HPI operates as an HPI16 (default).
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the Hi-Z state.)
1 - HPI operates as an HPI32.
(1) IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the
opposite supply rail, a 1-kΩ resistor should be used.)
Device Configurations
49
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued)
CONFIGURATION
IPD/
NO.
FUNCTIONAL DESCRIPTION
PIN
IPU(1)
Device Endian mode (LENDIAN)
AEA13
R27
IPU
0 - System operates in Big Endian mode
1 - System operates in Little Endian mode (default)
UTOPIA enable bit (UTOPIA_EN)
0 - UTOPIA disabled; Ethernet MAC (EMAC) and MDIO enabled (default)
This means all multiplexed EMAC/UTOPIA and MDIO/UTOPIA pins function as EMAC and
MDIO. Which EMAC/MDIO configuration (interface) [MII, RMII, GMII or the standalone
RGMII] is controlled by the MACSEL[1:0] bits (AEA[10:9] pins).
1 - UTOPIA enabled; EMAC and MDIO disabled [except when the MACSEL[1:0] bits = 11
then, the EMAC/MDIO RGMII interface is still functional]
AEA12
AEA11
R28
T25
IPD
IPD
This means all multiplexed EMAC/UTOPIA and MDIO/UTOPIA pins now function as
UTOPIA. And if MACSEL[1:0] = 11, the RGMII standalone pin functions can be used.
Reserved. For proper C6455 device operation, this pin must be externally pulled up with a
1-kΩ resistor at device reset.
If the EMAC/MDIO peripherals are enabled, [AEA12 pin driven low (UTOPIA_EN = 0)], there
are two additional configuration pins — the MACSEL[1:0] (AEA[10:9] pins) — that select one
of the four interface modes (MII, RMII, GMII, or RGMII) for the EMAC.
EMAC Interface Selects (MACSEL[1:0]) [EMAC/DMIO enabled; UTOPIA disabled
(UTOPIA_EN (AEA12 pin) = 0)]
00 - 10/100 EMAC/MDIO with MII Interface [default]
01 - 10/100 EMAC/MDIO with RMII Interface
10 - 10/100/1000 EMAC/MDIO with GMII Interface
11 - 10/100/1000 EMAC/MDIO with RGMII Interface
[RGMII interface requires a 1.8 V or 1.5 V I/O supply]
[M25,
M27]
AEA[10:9]
IPD
If the UTOPIA peripheral is enabled, [UTOPIA_EN (AEA12 pin) = 1] the UTOPIA interface is
dependent on the PCI_EN pin [Y29] and the EMAC/MDIO interface is dependent on
MAC_SEL[1:0] (AEA10:9):
0 11 - UTOPIA Slave with Full Functionality
0 11 - UTOPIA Slave with Full Functionality plus 10/100/1000 EMAC/MDIO with RGMII
Interface
1 11 - UTOPIA Slave with Single PHY Mode only Plus PCI
1 11 - UTOPIA Slave with Single PHY Mode only Plus 10/100/1000 EMAC/MDIO with RGMII
Interface Plus PCI
For more detailed information on the UTOPIA_EN, PCI_EN, and the MAC_SEL[1:0] control
pin selections, see Table 3-3.
PCI EEPROM Auto-Initialization (PCI_EEAI)
PCI auto-initialization via external EEPROM
0 - PCI auto-initialization through external EEPROM is disabled; the PCI peripheral uses the
specified PCI default values (default).
1 - PCI auto-initialization through external EEPROM is enabled; the PCI peripheral is
configured through external I2C EEPROM provided the PCI peripheral is enabled
(PCI_EN = 1).
AEA8
P25
IPD
Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
For proper C6455 device operation, do not oppose the IPD on this pin.
AEA7
AEA6
N27
U27
IPD
IPD
PCI Frequency Selection (PCI66)
[PCI peripheral needs be enabled (PCI_EN pin = 1) to use this function]
Selects the PCI operating frequency of 66 MHz or 33 MHz PCI operating frequency is
selected at reset via the pullup/pulldown resistor on the PCI66 pin:
0 - PCI operates at 33 MHz (default).
1 - PCI operates at 66 MHz.
Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
McBSP1 Enable bit (MCBSP1_EN)
Selects which function is enabled on the McBSP1/GPIO muxed pins
0 - GPIO pin functions enabled (default).
AEA5
U28
IPD
1 - McBSP1 pin functions enabled.
SYSCLKOUT Enable bit (SYSCLKOUT_EN)
Selects which function is enabled on the SYSCLK3/GP[1] muxed pin
0 - GP[1] pin function of the SYSCLK3/GP[1] pin enabled (default).
1 - SYSCLK3 pin function of the SYSCLK3/GP[1] pin enabled.
AEA4
AEA3
T28
T27
IPD
IPD
Reserved. For proper C6455 device operation, this pin must be externally pulled up with a
1-kΩ resistor at device reset.
50
Device Configurations
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Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued)
CONFIGURATION
IPD/
NO.
FUNCTIONAL DESCRIPTION
PIN
IPU(1)
[T26,
U26,
U25]
Configuration GPI (General-Purpose Inputs for Configuration purposes (CFGGP[2:0])
These pins are used in S/W routines located in internal ROM for boot operations.
AEA[2:0]
IPD
IPD
PCI Enable bit (PCI_EN)
Controls whether the HPI peripheral or PCI peripheral is enabled/disabled.
0 - HPI peripheral pins are enabled; PCI peripheral pins are disabled (default)
1 - PCI peripheral pins are enabled; HPI peripheral pins are disabled
PCI_EN
Y29
DDR2 Memory Controller enable (DDR2_EN)
ABA0
ABA1
V26
V25
IPD
IPD
0 - DDR2 Memory Controller peripheral pins are disabled (default)
1 - DDR2 Memory Controller peripheral pins are enabled
EMIFA enable (EMIFA_EN)
0 - EMIFA peripheral pins are disabled (default)
1 - EMIFA peripheral pins are enabled
3.2 Priority Allocation
On the C6455 device, each of the master ports (excluding the C64x+ Megamodule) should be assigned a
priority via the Priority Allocation (PRI_ALLOC) register (see Figure 3-1). A value of 000b has the highest
priority, while 111b has the lowest priority. Other Master peripherals are not present in the PRI_ALLOC
register as they have their own registers to program their priorities (For more information on the default
priority values in these peripheral registers, see the device-compatible Peripheral Reference Guide(s). TI
recommends that these priority registers be reprogrammed upon initial use.
31
15
16
Reserved
R-0000 0000 0000 0000
12
11
9
8
6
5
3
2
0
Reserved
R-000 0
SRIO_CPPI
R/W-001
Reserved
R/W-100
HPI/PCI
R/W-010
EMAC_CPPI
R/W-001
LEGEND: R/W = Read/Write; R = Read only; -n = value at reset
Figure 3-1. Priority Allocation Register (PRI_ALLOC)
3.3 Peripheral Configuration at Device Reset
Some C6455 peripherals share the same pins (internally muxed) and are mutually exclusive.
On the C6455 device, the PCI peripheral is muxed with the HPI peripheral and partially muxed with
UTOPIA.
Device Configurations
51
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Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 3-2. PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH Peripheral Selection (HPI16/32, PCI, and PCI
EEPROM)
PERIPHERAL SELECTION(1)
PERIPHERALS SELECTED
PCI66
AEA6 Pin
[U27]
PCI_EEAI
AEA8 Pin
[P25](1)
HPI_WIDTH
AEA14 Pin
[R25]
PCI_EN pin
[Y29]
HPI Data
Lower
HPI Data
Upper
32-Bit PCI
(66-/33-MHz)
PCI
Auto-Init
0
0
0
0
0
0
0
1
Enabled
Enabled
Hi-Z
Disabled
Disabled
N/A
N/A
Enabled
Enabled
(via External
EEPROM)
1
1
1
X
Disabled
Enabled
(66 MHz)
1
1
1
0
0
0
X
X
Disabled
Disabled
Disabled
Disabled
(default values)
Enabled
(33 MHz)
Enabled
(via External
EEPROM)
1
0
1
X
Disabled
(1) PCI_EEAI is latched at reset as a configuration input. If PCI_EEAI is set as one, then default values are loaded from an external I2C
EEPROM.
The UTOPIA_EN function (AEA12 pin) controls whether or not the peripheral module is used and the
MAC_SEL[1:0] functions (AEA[10:9) control which interface and features are used.
52
Device Configurations
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Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 3-3. UTOPIA_EN, and MAC_SEL[1:0] Peripheral Selection (UTOPIA and EMAC)
PERIPHERAL SELECTION
MAC_SEL[1:0]
AEA[10:9] Pins
[M25, M27]
HOST FUNCTION SELECTED
UTOPIA_EN
AEA12 Pin [R28]
PCI_EN Pin
[Y29]
0
0
0
0
1
x
x
x
x
0
00b
01b
10b
11b
!11b
10/100 EMAC/MDIO with MII Interface [default]
10/100 EMAC/MDIO with RMII Interface
10/100/1000 EMAC/MDIO with GMII Interface
10/100/1000 EMAC/MDIO with RGMII Interface(1)
UTOPIA Slave with Full Functionality
UTOPIA Slave with Full Functionality plus 10/100/1000 EMAC/MDIO with
RGMII Interface(1)
1
1
1
0
1
1
11b
!11b
11b
UTOPIA Slave with Single PHY Mode Only Plus PCI
UTOPIA Slave with Single PHY Mode only Plus 10/100/1000 EMAC/MDIO with
RGMII Interface Plus PCI(1)
(1) RGMII interface requires a 1.5-/1.8-V I/O supply.
3.4 Peripheral Selection After Device Reset
The C6455 device has a powersaver module that manages the power down of specific peripheral
modules. For more detailed information on the powersaver module and its associated registers, see the
Powersaver section of this document.
3.5 Device Status Register Description
The device status register depicts the status of the device peripheral selection. Once set, these bits will
remain set until a device reset; therefore, these bits should be masked when reading the DEVSTAT
register since their values can change. For the actual register bit names and their associated bit field
descriptions, see Figure 3-2 and Table 3-4.
31
24
Reserved
R-0000 0000
23
22
21
20
19
18
17
16
Reserved
EMIFA_EN
DDR2_EN
PCI_EN
CFGGP2
CFGGP1
CFGGP0
Reserved
R-0
15
R-x
14
R-x
13
R-x
R-x
11
R-x
10
R-x
9
R-1
8
12
SYSCLKOUT_
EN
MCBSP1_EN
PCI66
RESERVED
PCI_EEAI
MAC_SEL1
MAC_SEL0
Reserved
R-x
R-x
R-x
R-0
R-x
3
R-x
2
R-x
1
R-1
0
7
6
5
4
UTOPIA_EN
LENDIAN
HPI_WIDTH
AECLKINSEL
BOOTMODE3 BOOTMODE2 BOOTMODE1 BOOTMODE0
R-x
R-x
R-x
R-x
R-x R-x R-x R-x
LEGEND: R/W = Read/Write; R = Read only; -x = value after reset
Figure 3-2. Device Status Register (DEVSTAT) - 0x02A8 0000
Device Configurations
53
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 3-4. Device Status Register (DEVSTAT) Field Descriptions
Bit
Field
Value Description
31:30 Reserved
29:23 Reserved
Reserved. For proper device operation, write only zeroes to these bits.
Reserved. Read-only, writes have no effect.
22
21
20
EMIFA_EN
DDR2_EN
PCI_EN
EMIFA Enable (EMIFA_EN) status bit
Shows the status of whether the EMIFA peripheral is enabled/disabled.
0
1
EMIFA peripheral pins are disabled (default)
EMIFA peripheral pins are enabled
DDR2 Memory Controller Enable (DDR2_EN) status bit
Shows the status of whether the DDR2 Memory Controller peripheral is enabled/disabled.
DDR2 Memory Controller peripheral pins are disabled (default)
DDR2 Memory Controller peripheral pins are enabled
0
1
PCI Enable (PCI_EN) status bit
Shows the status of whether the HPI peripheral or PCI peripheral is enabled/disabled.
0
1
HPI peripheral pins are enabled; PCI peripheral pins are disabled (default)
PCI peripheral pins are enabled; HPI peripheral pins are disabled
19:17 CFGGP[2:0]
Used as General-Purpose inputs for configuration purposes.
These pins are latched at reset. These values can be used by S/W routines for boot operations.
16
15
Reserved
Reserved. Read-only, writes have no effect.
SYSCLKOUT_EN
SYSCLKOUT Enable (SYSCLKOUT_EN) status bit
Shows the status of which function is enabled on the SYSCLK3/GP[1] muxed pin.
0
1
GP[1] pin function of the SYSCLK3/GP[1] pin enabled (default).
SYSCLK3 pin function of the SYSCLK3/GP[1] pin enabled.
14
13
MCBSP1_EN
PCI66
McBSP1 Enable (MCBSP1_EN) status bit
Shows the status of which function is enabled on the McBSP1/GPIO muxed pins.
0
1
GPIO pin functions enabled (default).
McBSP1 pin functions enabled.
PCI Frequency Selection (PCI66) status bit
Shows the status of the PCI operating frequency of either 66 MHz or 33 MHz.
0
1
PCI operates at 33 MHz (default).
PCI operates at 66 MHz.
12
11
Reserved
PCI_EEAI
Reserved. Read-only, writes have no effect.
PCI EEPROM Auto-Initialization (PCI_EEAI) status bit
Shows whether the PCI auto-initialization via external EEPROM is enabled/disabled.
0
1
PCI auto-initialization through external EEPROM is disabled; the PCI peripheral uses the specified
PCI default values (default).
PCI auto-initialization through external EEPROM is enabled; the PCI peripheral is configured
through external I2C EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1).
10:9
MACSEL[1:0]
EMAC Interface Select (MACSEL[1:0]) status bits
Shows which EMAC interface mode has been selected.
00
01
10
11
10/100 EMAC/MDIO with MII Interface (default)
10/100 EMAC/MDIO with RMII Interface
10/100/1000 EMAC/MDIO with GMII Interface
10/100/1000 EMAC/MDIO with RGMII Mode Interface
[RGMII interface requires a 1.8 V or 1.5 V I/O supply]
Reserved. Read-only, writes have no effect.
8
7
Reserved
UTOPIA_EN
UTOPIA enable (UTOPIA_EN) status bit
Shows the status of whether the UTOPIA peripheral or the EMAC/MDIO peripherals are enabled.
0
1
UTOPIA disabled; Ethernet MAC (EMAC) and MDIO enabled (default)
UTOPIA enabled; EMAC and MDIO disabled
54
Device Configurations
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 3-4. Device Status Register (DEVSTAT) Field Descriptions (continued)
Bit
Field
Value Description
6
LENDIAN
Device Endian mode (LENDIAN)
Shows the status of whether the system is operating in Big Endian mode or Little Endian mode
(default).
0
1
System is operating in Big Endian mode.
System is operating in Little Endian mode (default)
5
4
HPI_WIDTH
HPI bus width control bit.
Shows the status of whether the HPI bus operates in 32-bit mode or in 16-bit mode (default).
0
1
HPI operates in 16-bit mode. (default).
HPI operates in 32-bit mode.
AECLKINSEL
EMIFA input clock select
Shows the status of what clock mode is enabled or disabled for EMIFA.
0
1
AECLKIN (default mode)
SYSCLK3 (CPU/x) Clock Rate. The SYSCLK3 clock rate is software selectable via the Software
PLL1 Controller. By default, SYSCLK3 is selected as CPU/8 clock rate.
3
BOOTMODE[3:0]
Bootmode configuration bits
Shows the status of what device bootmode configuration is operational.
Bootmode [3:0]
[Note: the peripheral must be enabled to use the particular boomode.]
0000 No boot (default mode)
0001 Host boot (HPI/PCI)
0010 Reserved
0011 Reserved
0100 EMIFA 8-bit ROM boot
0101 Master I2C boot
0110 Slave I2C boot
0111 Reserved
1000
thru
1111
Serial Rapid I/O boot For more detailed information on the bootmodes, see Section 2.4, Bootmode
Sequence of this document.
Device Configurations
55
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
3.6 JTAG ID Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
C6455 device, the JTAG ID register resides at address location 0x02A8 0008. The register hex value for
the C6455 device is: 0x0008 A02F. For the actual register bit names and their associated bit field
descriptions, see Figure 3-3 and Table 3-5.
31
28 27
12 11
1
0
VARIANT
(4-bit)
PART NUMBER (16-bit)
R-0000 0000 1000 1010
MANUFACTURER (11-bit)
R-0000 0010 111
LSB
R-0000
R-1
LEGEND: R = Read only; -n = value after reset
Figure 3-3. JTAG ID Register - C6455 Register Value - 0x0008 A02F
Table 3-5. JTAG ID Register Field Descriptions
Bit
Field
Value
Description
31:28 VARIANT
Variant (4-Bit) value. C6455 value: 0000.
Note: the VARIANT field may be invalid if no CLKIN1 signal is applied. If the
CLKIN1 signal is applied, for proper device boundary-scan operation, do not
oppose the internal pullup (IPU) on the EMU1 pin and the EMU0 pin must be
externally pulled down via a 1-kΩ resistor. For normal operation, do not oppose
the IPU on the EMU0 pin.
27:12 PART NUMBER
11:1 MANUFACTURER
Part Number (16-Bit) value. C6455 value: 0000 0000 1000 1010.
Manufacturer (11-Bit) value. C6455 value: 0000 0010 111.
LSB. This bit is read as a "1" for C6455.
0
LSB
3.8 Debugging Considerations - TBD
It is recommended that external connections be provided to device configuration pins, including AEA[19:0],
ABA[1:0], and PCI_EN. Although internal pullup/pulldown resistors exist on these pins, providing external
connectivity adds convenience to the user in debugging and flexibility in switching operating modes.
For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.
56
Device Configurations
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
3.9 Configuration Examples - TBD
Figure 3-4 and Figure 3-5 illustrate examples of peripheral selections/options that are configurable on the
C6455 device.
32
HD[31:0]
HPI
HRDY, HINT
(32-Bit)
VCP2
HCNTL0, HCNTL1, HHWIL,
HAS, HR/W, HCS, HDS1, HDS2
TCP2
PCI
64
AED[63:0]
UTOPIA
GPIO
EMIFA
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[7:0],
AECLKOUT, ASDCKE,
AHOLDA, ABUSREQ,
ASADS/ASRE, AAOE/ASOE,
AAWE/ASWE
GP[15:12,2,1]
32
ED[31:0]
DDR2
EMIF
DEA[21:2], DCE[1:0], DBE[3:0], DDRCLK, DDRCLK,
DSDCKE, DDQS, DDQS, DSDCAS, DSDRAS,
DSDWE
PLL1
and PLL1
Controller
CLKIN1, PLLV1
SYSCLKINT4
CLKIN2, PLLV2
PLL2
TINP1L
McBSP1
McBSP0
EMAC
TIMER1
TOUT1L
TINP0
CLKR0, FSR0, DR0, CLKS0,
DX0, FSX0, CLKX0
TIMER0
RapidIO
TOUT0
MRXD[7:0], MRXER, MRXDV, MCOL,
MCRS, MTCLK, MRCLK
RIOCLK, RIOCLK, RIOTX[3:0],
RIOTX[3:0], RIORX[3:0], RIORX[3:0]
SCL
SDA
MTXD[7:0], MTXEN,
MDIO, MDCLK
MDIO
I2C
Shading denotes a peripheral module not available for this configuration.
Power Saver Register Value: TBD
DEVSTAT Register: 0x0061 8161
PCI_EN [Y29 pin] = 0 (PCI disabled, default)
ABA1 (EMIFA_EN) [V25 pin] = 1(EMIFA enabled)
ABA0 (DDR2_EN) [V26 pin] = 1 (DDR2 Memory Controller enabled)
AEA[19:16] (BOOTMODE[3:0]) = 0001, (HPI Boot)
AEA[15] (AECLKIN_SEL) = 0, (AECLKIN, default)
AEA[14] (HPI_WIDTH) = 1, (HPI, 32-bit Operation)
AEA[13] (LENDIAN) = IPU, (Little Endian Mode, default)
AEA[12] (UTOPIA_EN) = 0, (UTOPIA disabled, default)
AEA[10:9] (MACSEL[1:0]) = 00, (10/100 MII Mode)
AEA[8] (PCI_EEAI) = 0, (PCI EEPROM Auto-Init disabled, default)
AEA[7] = 0, (do not oppose IPD)
AEA[6] (PCI66) = 0, (PCI 33 MHz [default, don’t care])
AEA[5] (MCBSP1_EN) = 0, (McBSP1 disabled, default)
AEA[4] (SYSCLKOUT_EN) = 1, (SYSCLK3 pin function)
AEA[2:0] (CFGGP[2:0]) = 000 (default)
Figure 3-4. Configuration Example A (McBSP + HPI32 + I2C + EMIFA + DDR2 Memory Controller +
TIMERS + RapidIO + EMAC (MII) + MDIO)
Device Configurations
57
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
32
HD[31:0]
HPI
(32-Bit)
VCP2
TCP2
HRDY, HINT
HCNTL0, HCNTL1, HHWIL,
HAS, HR/W, HCS, HDS1, HDS2
PCI
64
AED[63:0]
UTOPIA
GPIO
EMIFA
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[7:0],
AECLKOUT, ASDCKE,
AHOLDA, ABUSREQ,
ASADS/ASRE, AAOE/ASOE,
AAWE/ASWE
GP[15:12,2,1]
32
ED[31:0]
DDR2
EMIF
DEA[21:2], DCE[1:0], DBE[3:0], DDRCLK, DDRCLK,
DSDCKE, DDQS, DDQS, DSDCAS, DSDRAS,
DSDWE
PLL1
and PLL1
Controller
CLKIN1, PLLV1
SYSCLKINT4
CLKIN2, PLLV2
PLL2
TINP1L
CLKR1, FSR1, DR1, CLKS1,
DX1, FSX1, CLKX1
McBSP1
McBSP0
EMAC
TIMER1
TOUT1L
TINP0
CLKR0, FSR0, DR0, CLKS0,
DX0, FSX0, CLKX0
TIMER0
RapidIO
TOUT0
MRXD[7:0], MRXER, MRXDV, MCOL,
MCRS, MTCLK, MRCLK
RIOCLK, RIOCLK, RIOTX[3:0],
RIOTX[3:0], RIORX[3:0], RIORX[3:0]
SCL
SDA
MTXD[7:0], MTXEN,
MDIO, MDCLK
MDIO
I2C
Shading denotes a peripheral module not available for this configuration.
Power Saver Register Value: TBD
DEVSTAT Register: 0x0061 C161
PCI_EN [Y29 pin] = 0 (PCI disabled, default)
ABA1 (EMIFA_EN) [V25 pin] = 1(EMIFA enabled)
ABA0 (DDR2_EN) [V26 pin] = 1 (DDR2 Memory Controller enabled)
AEA[19:16] (BOOTMODE[3:0]) = 0001, (HPI Boot)
AEA[15] (AECLKIN_SEL) = 0, (AECLKIN, default)
AEA[14] (HPI_WIDTH) = 1, (HPI, 32-bit Operation)
AEA[13] (LENDIAN) = IPU, (Little Endian Mode, default)
AEA[12] (UTOPIA_EN) = 0, (UTOPIA disabled, default)
AEA[10:9] (MACSEL[1:0]) = 00, (10/100 MII Mode)
AEA[8] (PCI_EEAI) = 0, (PCI EEPROM Auto-Init disabled, default)
AEA[7] = 0, (do not oppose IPD)
AEA[6] (PCI66) = 0, (PCI 33 MHz [default, don’t care])
AEA[5] (MCBSP1_EN) = 1, (McBSP1 enabled)
AEA[4] (SYSCLKOUT_EN) = 1, (SYSCLK3 pin function)
AEA[2:0] (CFGGP[2:0]) = 000 (default)
Figure 3-5. Configuration Example B (2 McBSPs + HPI32 + I2C + EMIFA + DDR2 Memory Controller +
TIMERS + RapidIO + EMAC (GMII) + MDIO
58
Device Configurations
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
4 Device Operating Conditions
4.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise
Noted)(1)
Supply voltage ranges:
(2)
CVDD
TBD
TBD
(2)
DVDD33, DVDD18, DVDD15, DVDD12
(except PCI), VI
(PCI), VIP
TBD
Input voltage range:
Output voltage range:
TBD
(except PCI), VO
(PCI), VOP
TBD
TBD
Operating case temperature range, TC: (default)
Storage temperature range, Tstg
0°C to 90°C
–65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
4.2 Recommended Operating Conditions
MIN NOM
MAX UNIT
CVDD
Supply voltage, Core
1.17
3.14
1.71
1.71
1.43
1.14
1.2
3.3
1.8
1.8
1.5
1.2
1.24
3.47
1.89
1.89
1.57
1.26
V
V
V
V
V
V
DVDD33
DVDD18
Supply voltage, I/O
Supply voltage, I/O
Supply voltage, I/O [required only for EMAC RGMII (1.8 V operation)]
Supply voltage, I/O [required only for EMAC RGMII (1.5 V operation)]
Supply voltage, I/O [required only for RapidIO (RIO)]
DVDD15
DVDD12
Reference voltage, I/O
[required only for EMAC RGMII (1.8 V operation)]
0.855
0.713
0.9
0.945
0.787
V
V
VREFHSTL
Reference voltage, I/O
[required only for EMAC RGMII (1.5 V operation)]
0.75
VREFSSTL Reference voltage, I/O [required only for DDR2 I/F]
0.833
0.9
0
0.969
0
V
V
V
V
V
V
V
V
V
V
V
V
V
VSS
VIH
Supply ground
0
2
High-level input voltage (3.3 V except PCI and I2C)
Input voltage (PCI)
VIP
–0.5
DVDD33 + 0.5 V
DVDD33 + 0.5
VIHP
VIHI
VIHR
High-level input voltage (PCI)
High-level input voltage (I2C)
High-level input voltage (RGMII)
0.5DVDD33
0.7DVDD33
VREFHSTL + 0.10
VREFSSTL + 0.125
–0.3
DVDD15 + 0.30
DVDD18 + 0.3
VREFSSTL– 0.125
0.8
VIHD (dc) High-level input voltage (DDR2 I/F)
VILD (dc)
VIL
Low-level input voltage (DDR2 I/F)
Low-level input voltage (3.3 V except PCI and I2C)
Low-level input voltage (PCI)
VILP
VILI
–0.5
0
0.3DVDD33
Low-level input voltage (I2C)
0.3DVDD33
VILR
TC
Low-level input voltage (RGMII)
Operating case temperature
–0.3
0
VREFHSTL– 0.1
90 °C
Device Operating Conditions
59
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS(1)
DVDD33 = MIN, IOH = MAX
IOHP = –0.5 mA, DVDD = 3.3 V
MIN
TYP
MAX UNIT
High-level output voltage
(except PCI and I2C)
VOH
0.8DVDD33
V
V
(2)
VOHP
VOHI
High-level output voltage (PCI)
High-level output voltage (I2C)
0.9DVDD33
TBD
V
High-level output voltage
(RGMII)
VOHR
VOL
DVDD15– 0.3
V
Low-level output voltage
(except PCI and I2C)
DVDD33 = MIN, IOL = MAX
0.4
V
(2)
VOLP
VOLI
Low-level output voltage (PCI)
Low-level output voltage (I2C)
IOLP = 1.5 mA, DVDD = 3.3 V
0.2DVDD33
V
V
0
0.4
Low-level output voltage
(RGMII)
VOLR
0.4
V
V
High-level input voltage (DDR2
I/F)
VIHD (ac)
VIHL (ac)
VOLD
VREFSSTL + 0.25
Low-level input voltage (DDR2
I/F)
VREFSSTL– 0.25
VREFSSTL– 0.643
V
Low-level output voltage (DDR2
I/F)
V
High-level output voltage
(DDR2 I/F)
VOHD
VREFSSTL + 0.643
V
VI = VSS to DVDD33 no opposing
internal resistor
±1
uA
uA
uA
Input current (except PCI and
I2C)
VI = VSS to DVDD33 opposing
internal pullup resistor(3)
II
TBD
TBD
VI = VSS to DVDD33 opposing
internal pulldown resistor(3)
IIP
IIR
IID
Input leakage current (PCI)(4)
Input current (RGMII)
0 < VIP < DVDD33 = 3.3 V
±20
±1
uA
uA
Input current (DDR2 I/F)
TBD
AECLKOUT, CLKR1/GP[0],
CLKX1/GP[3], SYSCLK3/GP[1],
EMU[18:0], CLKR0, CLKX0
–8
mA
EMIF pins (except AECLKOUT),
NMI, Timer pins, PCI_EN, all
pins with UTOPIA capability
(except URADDR[4:0] and
UXADDR[2:1]), RESETSTAT,
McBSP pins (except CLKR1,
CLKR0, CLKX1, CLKX0),
GP[7:4], and TDO
–4
mA
mA
IOH
High-level output current
All pins with HPI and PCI capa-
bility
–0.5
RGMII pins (except RGMDIO
and RGMDCLK)
–8
TBD
mA
mA
mA
RGMDIO, RGMDCLK
DDR2 Memory Controller bus
pins
–13.4
I2C
TBD
TBD
mA
mA
SRIO
(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
(2) These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Table TBD
and Table TBD, respectively.
(3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(4) PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
60
Device Operating Conditions
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Tempera-
ture (Unless Otherwise Noted) (continued)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX UNIT
AECLKOUT, CLKR1/GP[0],
CLKX1/GP[3], SYSCLK3/GP[1],
EMU[18:0], CLKR0, CLKX0
8
mA
EMIF pins (except AECLKOUT),
NMI, Timer pins, PCI_EN, all
pins with UTOPIA capability
(except URADDR[4:0] and
UXADDR[2:1]), RESETSTAT,
McBSP pins (except CLKR1,
CLKR0, CLKX1, CLKX0),
GP[7:4], and TDO
4
mA
mA
IOL
Low-level output current
All pins with HPI and PCI capa-
bility
0.5
RGMII pins (except RGMDIO
and RGMDCLK)
8
TBD
13.4
mA
mA
mA
RGMDIO, RGMDCLK
DDR2 Memory Controller bus
pins
I2C
TBD
TBD
±20
±10
mA
mA
uA
SRIO
IOZ
Off-state output current
VO = DVDD33 or 0 V
IOZR
RGMII off-state output current
uA
DDR2 I/F off-state output cur-
rent
IOZD
TBD
CVDD = 1.2 V, CPU clock =
1000 MHz
TBD
TBD
mA
mA
mA
CVDD = 1.2 V, CPU clock = 850
MHz
ICDD
Core supply current(5)
CVDD = 1.2 V, CPU clock = 720
MHz
TBD
TBD
IDDD
Ci
I/O supply current(5)
Input capacitance
Output capacitance
TBD
mA
pF
pF
10
10
Co
(5) TBD
Device Operating Conditions
61
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276A–MAY 2005–REVISED JULY 2005
5 C64x+ Megamodule
The C64x+ Megamodule consists of several components — the C64x+ CPU Core, the L1 memory and
cache controllers, the L2 memory and cache controller, the external memory controller with an internal
DMA (IDMA), and the system components.
For more detailed information on the TMS320C64x+ Megamodule on the C6455 device, see the
TMS320C64x+ Megamodule Applications Report (Literature Number SPRAA68).
5.1 Memory Architecture
All memory on the C6455 has a unique location in the memory map (see C6455 Memory Map Summary,
Table 2-2).
For more detailed information on the new C64x+ CPU architecture, see the TMS320C64x/C64x+ DSP
CPU and Instruction Set Reference Guide (Literature Number SPRU732)
5.2 C64+ Megamodule Device-Specific Information
Table 5-1 shows the reset types supported on the C6455 device and they affect the resetting of the
Megamodule, either both globally and locally or just locally.
Table 5-1. Megamodule Reset (Global or Local)
GLOBAL
MEGAMODULE
RESET
LOCAL
MEGAMODULE
RESET
RESET TYPE
Power-On Reset
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Warm Reset
Max Reset
System Reset
CPU Reset
For more detailed information on the global and local Megamodule resets, see the Megamodule
Reference Guide (Literuature Number TBD). And for more detailed information on device resets, see
Section 6.10, Reset of this document.
62
C64x+ Megamodule
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
5.3 C64x+ Megamodule Register Description(s)
Table 5-2. CPU MegaModule Powerdown Control Registers
HEX ADDRESS RANGE
0181 0000
ACRONYM
REGISTER NAME
Powerdown control command register
TBD
CMD
-
0184 0004 - 0184
Table 5-3. CPU MegaModule Memory Protection Registers (L1/L2 Control)
HEX ADDRESS RANGE
0184 A000
ACRONYM
L2MPFAR
L2MPFSR
L2MPFCR
-
REGISTER NAME
L2 memory protection fault address register
0184 A004
L2 memory protection fault status register
L2 memory protection fault command register
Reserved
0184 A008
0184 A00C - 0184 A0FF
0184 A100
L2MPLK0
L2MPLK1
L2MPLK2
L2MPLK3
L2MPLKCMD
L2MPLKSTAT
-
L2 memory protection lock key bits [31:0]
L2 memory protection lock key bits [63:32]
L2 memory protection lock key bits [95:64]
L2 memory protection lock key bits [127:96]
L2 memory protection lock key command register
L2 memory protection lock key status register
Reserved
0184 A104
0184 A108
0184 A10C
0184 A110
0184 A114
0184 A118 - 0184 A1FF
0184 A200
L2MPPA0
L2MPPA1
L2MPPA2
L2MPPA3
L2MPPA4
L2MPPA5
L2MPPA6
L2MPPA7
L2MPPA8
L2MPPA9
L2MPPA10
L2MPPA11
L2MPPA12
L2MPPA13
L2MPPA14
L2MPPA15
L2MPPA16
L2MPPA17
L2MPPA18
L2MPPA19
L2MPPA20
L2MPPA21
L2MPPA22
L2MPPA23
L2MPPA24
L2 memory protection page attribute register 0
L2 memory protection page attribute register 1
L2 memory protection page attribute register 2
L2 memory protection page attribute register 3
L2 memory protection page attribute register 4
L2 memory protection page attribute register 5
L2 memory protection page attribute register 6
L2 memory protection page attribute register 7
L2 memory protection page attribute register 8
L2 memory protection page attribute register 9
L2 memory protection page attribute register 10
L2 memory protection page attribute register 11
L2 memory protection page attribute register 12
L2 memory protection page attribute register 13
L2 memory protection page attribute register 14
L2 memory protection page attribute register 15
L2 memory protection page attribute register 16
L2 memory protection page attribute register 17
L2 memory protection page attribute register 18
L2 memory protection page attribute register 19
L2 memory protection page attribute register 20
L2 memory protection page attribute register 21
L2 memory protection page attribute register 22
L2 memory protection page attribute register 23
L2 memory protection page attribute register 24
0184 A204
0184 A208
0184 A20C
0184 A210
0184 A214
0184 A218
0184 A21C
0184 A220
0184 A224
0184 A228
0184 A22C
0184 A230
0184 A234
0184 A238
0184 A23C
0184 A240
0184 A244
0184 A248
0184 A24C
0184 A250
0184 A254
0184 A258
0184 A25C
0184 A260
C64x+ Megamodule
63
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 5-3. CPU MegaModule Memory Protection Registers (L1/L2 Control) (continued)
HEX ADDRESS RANGE
0184 A264
0184 A268
0184 A26C
0184 A270
0184 A274
0184 A278
0184 A27C
0184 A280
0184 A284
0184 A288
0184 A28C
0184 A290
0184 A294
0184 A298
0184 A29C
0184 A2A0
0184 A2A4
0184 A2A8
0184 A2AC
0184 A2B0
0184 A2B4
0184 A2B8
0184 A2BC
0184 A2C0
0184 A2C4
0184 A2C8
0184 A2CC
0184 A2D0
0184 A2D4
0184 A2D8
0184 A2DC
0184 A2E0
0184 A2E4
0184 A2E8
0184 A2EC
0184 A2F0
0184 A2F4
0184 A2F8
0184 A2FC
0184 A300 - 0184 A3FF
0184 A400
0184 A404
0184 A408
0184 A40C - 0184 A4FF
0184 A500
0184 A504
0184 A508
ACRONYM
L2MPPA25
L2MPPA26
L2MPPA27
L2MPPA28
L2MPPA29
L2MPPA30
L2MPPA31
L2MPPA32
L2MPPA33
L2MPPA34
L2MPPA35
L2MPPA36
L2MPPA37
L2MPPA38
L2MPPA39
L2MPPA40
L2MPPA41
L2MPPA42
L2MPPA43
L2MPPA44
L2MPPA45
L2MPPA46
L2MPPA47
L2MPPA48
L2MPPA49
L2MPPA50
L2MPPA51
L2MPPA52
L2MPPA53
L2MPPA54
L2MPPA55
L2MPPA56
L2MPPA57
L2MPPA58
L2MPPA59
L2MPPA60
L2MPPA61
L2MPPA62
L2MPPA63
-
REGISTER NAME
L2 memory protection page attribute register 25
L2 memory protection page attribute register 26
L2 memory protection page attribute register 27
L2 memory protection page attribute register 28
L2 memory protection page attribute register 29
L2 memory protection page attribute register 30
L2 memory protection page attribute register 31
L2 memory protection page attribute register 32
L2 memory protection page attribute register 33
L2 memory protection page attribute register 34
L2 memory protection page attribute register 35
L2 memory protection page attribute register 36
L2 memory protection page attribute register 37
L2 memory protection page attribute register 38
L2 memory protection page attribute register 39
L2 memory protection page attribute register 40
L2 memory protection page attribute register 41
L2 memory protection page attribute register 42
L2 memory protection page attribute register 43
L2 memory protection page attribute register 44
L2 memory protection page attribute register 45
L2 memory protection page attribute register 46
L2 memory protection page attribute register 47
L2 memory protection page attribute register 48
L2 memory protection page attribute register 49
L2 memory protection page attribute register 50
L2 memory protection page attribute register 51
L2 memory protection page attribute register 52
L2 memory protection page attribute register 53
L2 memory protection page attribute register 54
L2 memory protection page attribute register 55
L2 memory protection page attribute register 56
L2 memory protection page attribute register 57
L2 memory protection page attribute register 58
L2 memory protection page attribute register 59
L2 memory protection page attribute register 60
L2 memory protection page attribute register 61
L2 memory protection page attribute register 62
L2 memory protection page attribute register 63
Reserved
L1PMPFAR
L1PMPFSR
L1PMPFCR
-
L1 program (L1P) memory protection fault address register
L1P memory protection fault status register
L1P memory protection fault command register
Reserved
L1PMPLK0
L1PMPLK1
L1PMPLK2
L1P memory protection lock key bits [31:0]
L1P memory protection lock key bits [63:32]
L1P memory protection lock key bits [95:64]
64
C64x+ Megamodule
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 5-3. CPU MegaModule Memory Protection Registers (L1/L2 Control) (continued)
HEX ADDRESS RANGE
0184 A50C
0184 A510
ACRONYM
REGISTER NAME
L1PMPLK3
L1P memory protection lock key bits [127:96]
L1PMPLKCMD L1P memory protection lock key command register
L1PMPLKSTAT L1P memory protection lock key status register
0184 A514
0184 A518 - 0184 A5FF
0184 A600
-
Reserved
L1PMPPA0
L1PMPPA1
L1PMPPA2
L1PMPPA3
L1PMPPA4
L1PMPPA5
L1PMPPA6
L1PMPPA7
L1PMPPA8
L1PMPPA9
L1PMPPA10
L1PMPPA11
L1PMPPA12
L1PMPPA13
L1PMPPA14
L1PMPPA15
L1PMPPA16
L1PMPPA17
L1PMPPA18
L1PMPPA19
L1PMPPA20
L1PMPPA21
L1PMPPA22
L1PMPPA23
L1PMPPA24
L1PMPPA25
L1PMPPA26
L1PMPPA27
L1PMPPA28
L1PMPPA29
L1PMPPA30
L1PMPPA31
-
L1P memory protection page attribute register 0
L1P memory protection page attribute register 1
L1P memory protection page attribute register 2
L1P memory protection page attribute register 3
L1P memory protection page attribute register 4
L1P memory protection page attribute register 5
L1P memory protection page attribute register 6
L1P memory protection page attribute register 7
L1P memory protection page attribute register 8
L1P memory protection page attribute register 9
L1P memory protection page attribute register 10
L1P memory protection page attribute register 11
L1P memory protection page attribute register 12
L1P memory protection page attribute register 13
L1P memory protection page attribute register 14
L1P memory protection page attribute register 15
L1P memory protection page attribute register 16
L1P memory protection page attribute register 17
L1P memory protection page attribute register 18
L1P memory protection page attribute register 19
L1P memory protection page attribute register 20
L1P memory protection page attribute register 21
L1P memory protection page attribute register 22
L1P memory protection page attribute register 23
L1P memory protection page attribute register 24
L1P memory protection page attribute register 25
L1P memory protection page attribute register 26
L1P memory protection page attribute register 27
L1P memory protection page attribute register 28
L1P memory protection page attribute register 29
L1P memory protection page attribute register 30
L1P memory protection page attribute register 31
Reserved
0184 A604
0184 A608
0184 A60C
0184 A610
0184 A614
0184 A618
0184 A61C
0184 A620
0184 A624
0184 A628
0184 A62C
0184 A630
0184 A634
0184 A638
0184 A63C
0184 A640
0184 A644
0184 A648
0184 A64C
0184 A650
0184 A654
0184 A658
0184 A65C
0184 A660
0184 A664
0184 A668
0184 A66C
0184 A670
0184 A674
0184 A678
0184 A67C
0184 A680 - 0184 ABFF
0184 AC00
0184 AC04
0184 AC08
0184 AC0C - 0184 ACFF
0184 AD00
0184 AD04
0184 AD08
0184 AD0C
0184 AD10
0184 AD14
L1DMPFAR
L1DMPFSR
L1DMPFCR
-
L1 data (L1D) memory protection fault address register
L1D memory protection fault status register
L1D memory protection fault command register
Reserved
L1DMPLK0
L1DMPLK1
L1DMPLK2
L1DMPLK3
L1D memory protection lock key bits [31:0]
L1D memory protection lock key bits [63:32]
L1D memory protection lock key bits [95:64]
L1D memory protection lock key bits [127:96]
L1DMPLKCMD L1D memory protection lock key command register
L1DMPLKSTAT L1D memory protection lock key status register
C64x+ Megamodule
65
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 5-3. CPU MegaModule Memory Protection Registers (L1/L2 Control) (continued)
HEX ADDRESS RANGE
0184 AD18 - 0184 ADFF
0184 AE00
ACRONYM
-
REGISTER NAME
Reserved
L1DMPPA0
L1DMPPA1
L1DMPPA2
L1DMPPA3
L1DMPPA4
L1DMPPA5
L1DMPPA6
L1DMPPA7
L1DMPPA8
L1DMPPA9
L1DMPPA10
L1DMPPA11
L1DMPPA12
L1DMPPA13
L1DMPPA14
L1DMPPA15
L1DMPPA16
L1DMPPA17
L1DMPPA18
L1DMPPA19
L1DMPPA20
L1DMPPA21
L1DMPPA22
L1DMPPA23
L1DMPPA24
L1DMPPA25
L1DMPPA26
L1DMPPA27
L1DMPPA28
L1DMPPA29
L1DMPPA30
L1DMPPA31
-
L1D memory protection page attribute register 0
L1D memory protection page attribute register 1
L1D memory protection page attribute register 2
L1D memory protection page attribute register 3
L1D memory protection page attribute register 4
L1D memory protection page attribute register 5
L1D memory protection page attribute register 6
L1D memory protection page attribute register 7
L1D memory protection page attribute register 8
L1D memory protection page attribute register 9
L1D memory protection page attribute register 10
L1D memory protection page attribute register 11
L1D memory protection page attribute register 12
L1D memory protection page attribute register 13
L1D memory protection page attribute register 14
L1D memory protection page attribute register 15
L1D memory protection page attribute register 16
L1D memory protection page attribute register 17
L1D memory protection page attribute register 18
L1D memory protection page attribute register 19
L1D memory protection page attribute register 20
L1D memory protection page attribute register 21
L1D memory protection page attribute register 22
L1D memory protection page attribute register 23
L1D memory protection page attribute register 24
L1D memory protection page attribute register 25
L1D memory protection page attribute register 26
L1D memory protection page attribute register 27
L1D memory protection page attribute register 28
L1D memory protection page attribute register 29
L1D memory protection page attribute register 30
L1D memory protection page attribute register 31
Reserved
0184 AE04
0184 AE08
0184 AE0C
0184 AE10
0184 AE14
0184 AE18
0184 AE1C
0184 AE20
0184 AE24
0184 AE28
0184 AE2C
0184 AE30
0184 AE34
0184 AE38
0184 AE3C
0184 AE40
0184 AE44
0184 AE48
0184 AE4C
0184 AE50
0184 AE54
0184 AE58
0184 AE5C
0184 AE60
0184 AE64
0184 AE68
0184 AE6C
0184 AE70
0184 AE74
0184 AE78
0184 AE7C
0184 AE80 - 0185 FFFF
Table 5-4. CPU MegaModule Interrupt Registers
HEX ADDRESS RANGE
0180 0000
ACRONYM
EVTFLAG0
EVTFLAG1
EVTFLAG2
EVTFLAG3
-
REGISTER NAME
Event flag register 0 (Events [31:0])
0180 0004
0180 0008
0180 000C
0180 0010 - 0180 001C
0180 0020
Reserved
EVTSET0
EVTSET1
EVTSET2
Event set register 0 (Events [31:0])
0180 0024
0180 0028
66
C64x+ Megamodule
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 5-4. CPU MegaModule Interrupt Registers (continued)
HEX ADDRESS RANGE
0180 002C
ACRONYM
EVTSET3
-
REGISTER NAME
0180 0030 - 0180 003C
0180 0040
Reserved
EVTCLR0
EVTCLR1
EVTCLR2
EVTCLR3
-
Event clear register 0 (Events [31:0])
0180 0044
0180 0048
0180 004C
0180 0050 - 0180 007C
0180 0080
Reserved
EVTMASK0
EVTMASK1
EVTMASK2
EVTMASK3
-
Event mask register 0 (Events [31:0])
0180 0084
0180 0088
0180 008C
0180 0090 - 0180 009C
0180 00A0
Reserved
MEVTFLAG0
MEVTFLAG1
MEVTFLAG2
MEVTFLAG3
-
Masked event flag status register 0 (Events [31:0])
0180 00A4
0180 00A8
0180 00AC
0180 00B0 - 0180 00BC
0180 00C0
Reserved
EXCMASK0
EXCMASK1
EXCMASK2
EXCMASK3
-
Exception mask register 0 (Events [31:0])
0180 00C4
0180 00C8
0180 00CC
0180 00D0 - 0180 00DC
0180 00E0
Reserved
MEXCFLAG0
MEXCFLAG1
MEXCFLAG2
MEXCFLAG3
-
Masked exception flag status register 0 (Events [31:0])
0180 00E4
0180 00E8
0180 00EC
0180 00F0 - 0180 00FC
0180 0100
Reserved
-
Reserved
0180 0104
INTMUX1
INTMUX2
INTMUX3
-
Interrupt multiplexor register 0
0180 0108
0180 010C
0180 0110 - 0180 013C
0180 0140
Reserved
AEGMUX0
AEGMUX1
-
Advanced event generator mux regsiter 0
0180 0144
0180 0148 - 0180 017C
0180 0180
Reserved
INTXSTAT
INTXCLR
INTDMASK
-
Interrupt exception status register
Interrupt exception clear register
Dropped interrupt mask register
Reserved
0180 0184
0180 0188
0180 0188 - 0180 01BC
0180 01C0
EVTASRT
Event asserting register
C64x+ Megamodule
67
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 5-5. CPU MegaModule IDMA Registers
HEX ADDRESS RANGE
0182 0000
ACRONYM
IDMA0STAT
IDMA0MASK
IMDA0SRC
IDMA0DST
IDMA0CNT
-
REGISTER NAME
IDMA Channel 0 Status Register
0182 0004
IDMA Channel 0 Mask Register
IDMA Channel 0 Source Address Register
IDMA Channel 0 Destination Address Register
IDMA Channel 0 Count Register
Reserved
0182 0008
0182 000C
0182 0010
0182 0014 - 0182 00FC
0182 0100
IDMA1STAT
-
IDMA Channel 1 Status Register
Reserved
0182 0104
0182 0108
IMDA1SRC
IDMA1DST
IDMA1CNT
-
IDMA Channel 1 Source Address Register
IDMA Channel 1 Destination Address Register
IDMA Channel 1 Count Register
Reserved
0182 010C
0182 0110
0182 0114 - 0182 017C
0182 0180
-
Reserved
0182 0184 - 0182 01FF
-
Reserved
Table 5-6. CPU MegaModule Configuration Registers
HEX ADDRESS RANGE
0182 0300
ACRONYM
MPFAR
REGISTER NAME
Memory Protection Fault Address Register
0182 0304
MPFSR
Memory Protection Fault Status Register
Memory Protection Fault Command Register
0182 0308
MPFCR
Table 5-7. CPU MegaModule Cache Registers
HEX ADDRESS RANGE
0184 0000
ACRONYM
L2CFG
-
REGISTER NAME
L2 Cache Configuration Register
Reserved
0184 0004 - 0184 001C
0184 0020
L1PCFG
L1PCC
-
L1P Configuration Register
L1P Cache Control Register
Reserved
0184 0024
0184 0028 - 0184 003C
0184 0040
L1DCFG
L1DCC
-
L1D Configuration Register
L1D Cache Control Register
Reserved
0184 0044
0184 0048 - 0184 3FFC
0184 4000
L2WBAR
L2WWC
-
L2 Writeback Base Address Register - for Block Writebacks
L2 Writeback Word Count Register
Reserved
0184 4004
0184 4008 - 0184 400C
0184 4010
L2WIBAR
L2WIWC
L2IBAR
L2IWC
L1PIBAR
L1PIWC
L1DWIBAR
L1DWIWC
L2 Writeback and Invalidate Base Address Register - for Block Writebacks
L2 Writeback and Invalidate word count register
L2 Invalidate Base Address Register
0184 4014
0184 4018
0184 401C
L2 Invalidate Word Count Register
0184 4020
L1P Invalidate Base Address Register
0184 4024
L1P Invalidate Word Count Register
0184 4030
L1D Writeback and Invalidate Base Address Register
L1D Writeback and Invalidate Word Count Register
0184 4034
68
C64x+ Megamodule
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 5-7. CPU MegaModule Cache Registers (continued)
HEX ADDRESS RANGE
0184 4038
ACRONYM
-
REGISTER NAME
Reserved
0184 4040
L1DWBAR
L1DWWC
L1DIBAR
L1DIWC
-
L1D Writeback Base Address Register - for Block Writebacks
L1D Writeback Word Count Register
L1D Invalidate Base Address Register
L1D Invalidate Word Count Register
Reserved
0184 4044
0184 4048
0184 404C
0184 5000
0184 5004
L2WB
L2WBINV
L2INV
-
L2 Global Writeback Register
L2 Global Writeback and Invalidate Register
L2 Global Invalidate Register
Reserved
0184 5008
0184 500C - 0184 5024
0184 5028
L1PINV
-
L1P Global Invalidate Register
Reserved
0184 502C - 0184 503C
0184 5040
L1DWB
L1DWBINV
L1DINV
-
L1D Global Writeback Register
L1D Global Writeback and Invalidate Register
L1D Global Invalidate Register
Reserved
0184 5044
0184 5048
0184 504C - 0184 7FFC
MAR0 to
MAR127
0184 8000 - 0184 81FC
0184 8200 - 0184 823C
0184 8240 - 0184 827C
Reserved
Reserved
Reserved
MAR128 to
MAR143
MAR144 to
MAR159
0184 8280
0184 8284
0184 8288
0184 828C
0184 8290
0184 8294
0184 8298
0184 829C
0184 82A0
0184 82A4
0184 82A8
0184 82AC
0184 82B0
0184 82B4
0184 82B8
0184 82BC
0184 82C0
0184 82C4
0184 82C8
0184 82CC
0184 82D0
0184 82D4
0184 82D8
0184 82DC
0184 82E0
0184 82E4
MAR160
MAR161
MAR162
MAR163
MAR164
MAR165
MAR166
MAR167
MAR168
MAR169
MAR170
MAR171
MAR172
MAR173
MAR174
MAR175
MAR176
MAR177
MAR178
MAR179
MAR180
MAR181
MAR182
MAR183
MAR184
MAR185
Controls EMIFA CE2 Range A000 0000 - A0FF FFFF
Controls EMIFA CE2 Range A100 0000 - A1FF FFFF
Controls EMIFA CE2 Range A200 0000 - A2FF FFFF
Controls EMIFA CE2 Range A300 0000 - A3FF FFFF
Controls EMIFA CE2 Range A400 0000 - A4FF FFFF
Controls EMIFA CE2 Range A500 0000 - A5FF FFFF
Controls EMIFA CE2 Range A600 0000 - A6FF FFFF
Controls EMIFA CE2 Range A700 0000 - A7FF FFFF
Controls EMIFA CE2 Range A800 0000 - A8FF FFFF
Controls EMIFA CE2 Range A900 0000 - A9FF FFFF
Controls EMIFA CE2 Range AA00 0000 - AAFF FFFF
Controls EMIFA CE2 Range AB00 0000 - ABFF FFFF
Controls EMIFA CE2 Range AC00 0000 - ACFF FFFF
Controls EMIFA CE2 Range AD00 0000 - ADFF FFFF
Controls EMIFA CE2 Range AE00 0000 - AEFF FFFF
Controls EMIFA CE2 Range AF00 0000 - AFFF FFFF
Controls EMIFA CE3 Range B000 0000 - B0FF FFFF
Controls EMIFA CE3 Range B100 0000 - B1FF FFFF
Controls EMIFA CE3 Range B200 0000 - B2FF FFFF
Controls EMIFA CE3 Range B300 0000 - B3FF FFFF
Controls EMIFA CE3 Range B400 0000 - B4FF FFFF
Controls EMIFA CE3 Range B500 0000 - B5FF FFFF
Controls EMIFA CE3 Range B600 0000 - B6FF FFFF
Controls EMIFA CE3 Range B700 0000 - B7FF FFFF
Controls EMIFA CE3 Range B800 0000 - B8FF FFFF
Controls EMIFA CE3 Range B900 0000 - B9FF FFFF
C64x+ Megamodule
69
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 5-7. CPU MegaModule Cache Registers (continued)
HEX ADDRESS RANGE
0184 82E8
0184 82EC
0184 82F0
0184 82F4
0184 82F8
0184 82FC
0184 8300
0184 8304
0184 8308
0184 830C
0184 8310
0184 8314
0184 8318
0184 831C
0184 8320
0184 8324
0184 8328
0184 832C
0184 8330
0184 8334
0184 8338
0184 833C
0184 8340
0184 8344
0184 8348
0184 834C
0184 8350
0184 8354
0184 8358
0184 835C
0184 8360
0184 8364
0184 8368
0184 836C
0184 8370
0184 8374
0184 8378
0184 837C
0184 8380
0184 8384
0184 8388
0184 838C
0184 8390
0184 8394
0184 8398
0184 839C
0184 83A0
ACRONYM
MAR186
MAR187
MAR188
MAR189
MAR190
MAR191
MAR192
MAR193
MAR194
MAR195
MAR196
MAR197
MAR198
MAR199
MAR200
MAR201
MAR202
MAR203
MAR204
MAR205
MAR206
MAR207
MAR208
MAR209
MAR210
MAR211
MAR212
MAR213
MAR214
MAR215
MAR216
MAR217
MAR218
MAR219
MAR220
MAR221
MAR222
MAR223
MAR224
MAR225
MAR226
MAR227
MAR228
MAR229
MAR230
MAR231
MAR232
REGISTER NAME
Controls EMIFA CE3 Range BA00 0000 - BAFF FFFF
Controls EMIFA CE3 Range BB00 0000 - BBFF FFFF
Controls EMIFA CE3 Range BC00 0000 - BCFF FFFF
Controls EMIFA CE3 Range BD00 0000 - BDFF FFFF
Controls EMIFA CE3 Range BE00 0000 - BEFF FFFF
Controls EMIFA CE3 Range BF00 0000 - BFFF FFFF
Controls EMIFA CE4 Range C000 0000 - C0FF FFFF
Controls EMIFA CE4 Range C100 0000 - C1FF FFFF
Controls EMIFA CE4 Range C200 0000 - C2FF FFFF
Controls EMIFA CE4 Range C300 0000 - C3FF FFFF
Controls EMIFA CE4 Range C400 0000 - C4FF FFFF
Controls EMIFA CE4 Range C500 0000 - C5FF FFFF
Controls EMIFA CE4 Range C600 0000 - C6FF FFFF
Controls EMIFA CE4 Range C700 0000 - C7FF FFFF
Controls EMIFA CE4 Range C800 0000 - C8FF FFFF
Controls EMIFA CE4 Range C900 0000 - C9FF FFFF
Controls EMIFA CE4 Range CA00 0000 - CAFF FFFF
Controls EMIFA CE4 Range CB00 0000 - CBFF FFFF
Controls EMIFA CE4 Range CC00 0000 - CCFF FFFF
Controls EMIFA CE4 Range CD00 0000 - CDFF FFFF
Controls EMIFA CE4 Range CE00 0000 - CEFF FFFF
Controls EMIFA CE4 Range CF00 0000 - CFFF FFFF
Controls EMIFA CE5 Range D000 0000 - D0FF FFFF
Controls EMIFA CE5 Range D100 0000 - D1FF FFFF
Controls EMIFA CE5 Range D200 0000 - D2FF FFFF
Controls EMIFA CE5 Range D300 0000 - D3FF FFFF
Controls EMIFA CE5 Range D400 0000 - D4FF FFFF
Controls EMIFA CE5 Range D500 0000 - D5FF FFFF
Controls EMIFA CE5 Range D600 0000 - D6FF FFFF
Controls EMIFA CE5 Range D700 0000 - D7FF FFFF
Controls EMIFA CE5 Range D800 0000 - D8FF FFFF
Controls EMIFA CE5 Range D900 0000 - D9FF FFFF
Controls EMIFA CE5 Range DA00 0000 - DAFF FFFF
Controls EMIFA CE5 Range DB00 0000 - DBFF FFFF
Controls EMIFA CE5 Range DC00 0000 - DCFF FFFF
Controls EMIFA CE5 Range DD00 0000 - DDFF FFFF
Controls EMIFA CE5 Range DE00 0000 - DEFF FFFF
Controls EMIFA CE5 Range DF00 0000 - DFFF FFFF
Controls DDR2 CE0 Range E000 0000 - E0FF FFFF
Controls DDR2 CE0 Range E100 0000 - E1FF FFFF
Controls DDR2 CE0 Range E200 0000 - E2FF FFFF
Controls DDR2 CE0 Range E300 0000 - E3FF FFFF
Controls DDR2 CE0 Range E400 0000 - E4FF FFFF
Controls DDR2 CE0 Range E500 0000 - E5FF FFFF
Controls DDR2 CE0 Range E600 0000 - E6FF FFFF
Controls DDR2 CE0 Range E700 0000 - E7FF FFFF
Controls DDR2 CE0 Range E800 0000 - E8FF FFFF
70
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Table 5-7. CPU MegaModule Cache Registers (continued)
HEX ADDRESS RANGE
0184 83A4
ACRONYM
MAR233
MAR234
MAR235
MAR236
MAR237
MAR238
MAR239
REGISTER NAME
Controls DDR2 CE0 Range E900 0000 - E9FF FFFF
Controls DDR2 CE0 Range EA00 0000 - EAFF FFFF
Controls DDR2 CE0 Range EB00 0000 - EBFF FFFF
Controls DDR2 CE0 Range EC00 0000 - ECFF FFFF
Controls DDR2 CE0 Range ED00 0000 - EDFF FFFF
Controls DDR2 CE0 Range EE00 0000 - EEFF FFFF
Controls DDR2 CE0 Range EF00 0000 - EFFF FFFF
0184 83A8
0184 83AC
0184 83B0
0184 83B4
0184 83B8
0184 83BC
MAR240 to
MAR255
0184 83C0 -0184 83FC
Reserved
Table 5-8. CPU MegaModule BandWidth Management Registers
HEX ADDRESS RANGE
0182 0200
ACRONYM
CPUARBE
IDMAARBE
SDMAARBE
MAMARBE
-
REGISTER NAME
CPU Arbitration Register
IDMA Arbitration Register
0182 0204
0182 0208
Slave DMA Arbitration Register
Master DMA Arbitration Register
Reserved
0182 020C
0182 0210 - 0182 02FF
Table 5-9. Device Configuration Registers (Chip-Level Registers)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Device Status Register
COMMENTS
Read-only. Provides
status of the User's device
configuration on reset.
02A8 0000
DEVSTAT
Sets priority for Master
peripherals.
02A8 0004
PRI_ALLOC
Priority Allocation Register
Read-only. Provides 32-bit
JTAG ID of the device.
02A8 0008
JTAGID
-
JTAG and BSDL Identification Register
Reserved
02A8 000C - 02AB FFFF
C64x+ Megamodule
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6 C6455 Peripheral Information and Electrical Specifications
6.1 Parameter Information
6.1.1 Parameter Information Device-Specific Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must
be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The
transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data
sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 6-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1.1 3.3-V Signal Transition Levels
All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.
V
ref
= 1.5 V
Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAXand VIH MINfor input clocks,
VOLMAXand VOH MINfor output clocks, VILP MAXand VIHP MINfor PCI input clocks, and VOLP MAXand
VOHP MINfor PCI output clocks.
V
ref
= V MIN (or V MIN or
IH OH
V
IHP
MIN or V
MIN)
OHP
V
ref
= V MAX (or V MAX or
IL OL
V
ILP
MAX or V
MAX)
OLP
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
72
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6.1.1.2 Signal Transition Rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
6.1.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (literature number SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external
device and from the external device to the DSP. This round-trip delay tends to negatively impact the input
setup time margin, but also tends to improve the input hold time margins (see Table 6-1 and Figure 6-4).
Figure 6-4 represents a general transfer between the DSP and an external device. The figure also
represents board route delays and how they are perceived by the DSP and the external device.
Table 6-1. Board-Level Timing Example
(see Figure 6-4)
NO.
1
DESCRIPTION
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
External device hold time requirement
External device setup time requirement
Control signal route delay
External device hold time
4
5
6
7
8
External device access time
DSP hold time requirement
DSP setup time requirement
Data route delay
9
10
11
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AECLKOUT
(Output from DSP)
1
AECLKOUT
(Input to External Device)
2
3
(A)
Control Signals
(Output from DSP)
4
5
6
Control Signals
(Input to External Device)
7
8
(B)
Data Signals
(Output from External Device)
9
10
11
(B)
Data Signals
(Input to DSP)
A. Control signals include data for Writes.
B. Data signals are generated during Reads from an external device.
Figure 6-4. Board-Level Input/Output Timings
6.2 Recommended Clock and Control Signals Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
6.3 Power-Down Modes Logic
6.4 Power-Supply Sequencing
TI recommends that the power-supply sequencing specified in the Reset Electrical/Data Timing section
(Section 6.10.6) of this document be followed.
6.5 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum
distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capaci-
tors, therefore physically smaller capacitors should be used while maintaining the largest available
capacitance value. As with the selection of any component, verification of capacitor availability over the
product's production lifetime should be considered.
6.6 Power-Down Operation
One of the power goals for the C6455 is to reduce power dissipation due to inactive/unused peripherals. A
provision to turn off clocks to unused peripherals is included. The gating of these clocks is derived from
boot mode settings, device configuration registers within the C64x+ Megamodule power-down controller,
and/or power-down settings within the peripheral.
Any module that is not being used at all (indicated by configuration settings at reset) will have its clock
disabled in order to minimize power consumption. For C6455 device, modules that may be completely
disabled at reset are I2C, McBSP, UTOPIA, EMAC, RapidIO, TCP2, and VCP2.
74
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The C6455 device allows any peripheral to be powered down through software. This, too, results in gating
of the clock(s) to the powered-down peripheral. Once a peripheral is powered-down, it must remain
powered down until the next device reset.
6.7 Powersaver
TBD
6.7.1 Powersaver Device-Specific Information
TBD
6.7.2 Powersaver Perpheral Register Description(s)
Table 6-2. Powersaver Registers
HEX ADDRESS RANGE
02AC 0000
ACRONYM
REGISTER NAME
-
Reserved
02AC 0004
LCK
Lock register
02AC 0008
MDCTL0
Module state control register 0
Reserved
02AC 000C
-
02AC 0010
-
Reserved
02AC 0014
MDSTAT0
Module status register 0
Module status register 1
Reserved
02AC 0018
MDSTAT1
02AC 001C
-
02AC 0020
-
Reserved
02AC 0024
-
Reserved
02AC 0028
-
Reserved
02AC 002C
EMIFCLKGAT
-
Clock gating for EMIFA, DDR2
Reserved
02AC 0030 - 02AF FFFF
6.8 Enhanced Direct Memory Access (EDMA) Controller
The EDMA controller handles all data transfers between the level-two (L2) cache/memory controller and
the device peripherals on the C6455 DSP. These data transfers include cache servicing, non-cacheable
memory accesses, user-programmed data transfers, and host accesses.
6.8.1 EDMA Device-Specific Information
The EDMA on the C6455 device is further enhanced from any other C64x generation DSP device. The
C6455 device separates out the functional components of the EDMA into several distinct components.
•
•
•
Switched Central Resource (SCR)
Channel Controller (CC)
Transfer Controller (TC)
Switched Central Resource (SCR): The SCR is an n-port to m-port switched central resource that allows
N master peripherals to connect to M slave peripherals. The SCR allows seamless arbitration between the
N masters to each slave.
EDMA: The EDMA is the engine that performs slave-to-slave data transfers. Since all connections through
the SCR are master/slave, the EDMA must exist to allow transfers off of global (i.e.,
non-peripheral-specific) system events or software-driven transfers. The EDMA consists of two
subcomponents:
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•
Channel Controller (CC): The CC contains 64 channels synchronized to system events. The CC
contains a parameterizeable RAM that holds transfer parameters for the 64 channels, plus reload
space. Llinking and chaining are used to allow synchronization between transfers and auto-reload
capabilities for each channel. Enhancements include:
–
Orthogonal completion codes - the OCCs are now more exclusive when selecting whether to
interrupt the CPU or chain to another channel. This simplifies the EDMA driver.
–
Quick DMA support (QDMA) - Formerly performed by the C64x Megamodule, the CC allows for
software-driven transfers. Rather than requiring a system event, a transfer is started as soon as the
parameters are written.
•
Transfer Controller (TC): The TC is the EDMA engine that actually performs the reads and writes, and
buffers the data being transferred in an intermediate FIFO. The TC contains 4 DMA channels, and is
programmed by the CC.
For the C6455 EDMA block diagram, see Figure 6-5.
Chip Events
UREVT
UXEVT
MCBSPREVT2
MCBSPXEVT2
MCBSPREVT1
MCBSPXEVT1
MCBSPREVT0
MCBSPXEVT0
eVCPREVT
CC
(64-Channel
QDMA)
eVCPXEVT
eTCPREVT
eTCPXEVT
SLAVE
MASTER
S
S
S
S
S
S
TCP2
VCP2
M0
M1
M2
M3
S0
S1
S2
S3
M
TC
4 Channels
CFG
McBSPs
EMAC
MDIO
M
M
M
M
M
CLK /2
128-bit
CPU/3 MHz
Utopia
PCI
S
HPI
PCI
CLK x2
S
Reserved
Reserved
M
M
M
S
S
S
DDR2 EMIF
M
M
S
S
Serial RapidIO
Megamodule
EMIFA
Megamodule
Figure 6-5. EDMA Block Diagram
76
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6.8.1.1 EDMA Channel Synchronization Events
The C64x+ EDMA3 supports up to 64 EDMA channels which service peripheral devices and external
memory. Table 6-3 lists the source of C64x+ EDMA3 synchronization events associated with each of the
programmable EDMA channels. For the C6455 device, the association of an event to a channel is fixed;
each of the EDMA channels has one specific event associated with it. These specific events are captured
in the EDMA3 event registers (ERL, ERH) even if the events are disabled by the EDMA event enable
registers (EERL, EERH). The priority of each event can be specified independently in the transfer
parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and
how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the
TMS320C64x+ DSP EDMA3 Controller Reference Guide (literature number SPRUTBD).
Table 6-3. C6455 EDMA Channel Synchronization Events(1)
EDMA
CHANNEL
BINARY
EVENT NAME
EVENT DESCRIPTION
0
1
000 0000
000 0001
000 0010
000 0011
000 0100
000 0101
000 0110
000 0111
000 1000
000 1001
000 1010
000 1011
000 1100
000 1101
000 1110
000 1111
001 0000
001 0001
-
DSP_EVT
HPI/PCI-to-DSP event
TEVTLO0
Timer 0 lower counter event
Timer 0 high counter event
None
2
TEVTHI0
3
-
4
-
None
5
-
None
6
-
None
7
-
None
8
-
None
9
-
-
None
10
11
12
13
14
15
16
17
18-19
20
21-27
28
29
30
31
32
33-39
40
41-43
44
45
46-47
None
-
None
XEVT0
REVT0
XEVT1
REVT1
TEVTLO1
TEVTHI1
-
McBSP0 transmit event
McBSP0 receive event
McBSP1 transmit event
McBSP1 receive event
Timer 1 lower counter event
Timer 1 high counter event
None
001 0100
-
RIOINT1
-
Rapid IO Interrupt 1
None
001 1100
001 1101
001 1110
001 1111
010 0000
-
VCPREVT
VCPXEVT
TCPREVT
TCPXEVT
UREVT
-
VCP2 receive event
VCP2 transmit event
TCP2 receive event
TCP2 transmit event
UTOPIA receive event
None
010 1000
-
UXEVT
-
UTOPIA transmit event
None
010 1100
010 1101
-
ICREVT
ICXEVT
-
I2C receive event
I2C transmit event
None
(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate
transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TBD Reference Guide (Literature
Number SPRUTBD).
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Table 6-3. C6455 EDMA Channel Synchronization Events (continued)
EDMA
CHANNEL
BINARY
EVENT NAME
EVENT DESCRIPTION
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
011 0000
011 0001
011 0010
011 0011
011 0100
011 0101
011 0110
011 0111
011 1000
011 1001
011 1010
011 1011
011 1100
011 1101
011 1110
011 1111
GPINT0
GPINT1
GPINT2
GPINT3
GPINT4
GPINT5
GPINT6
GPINT7
GPINT8
GPINT9
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
GPIO event 0
GPIO event 1
GPIO event 2
GPIO event 3
GPIO event 4
GPIO event 5
GPIO event 6
GPIO event 7
GPIO event 8
GPIO event 9
GPIO event 10
GPIO event 11
GPIO event 12
GPIO event 13
GPIO event 14
GPIO event 15
6.8.2 EDMA Peripheral Register Description(s)
Table 6-4. EDMA Registers
HEX ADDRESS RANGE
02A0 0000 - 02A0 00FC
02A0 0100
ACRONYM
REGISTER NAME
-
Reserved
DCHMAP0
DCHMAP1
DCHMAP2
DCHMAP3
DCHMAP4
DCHMAP5
DCHMAP6
DCHMAP7
DCHMAP8
DCHMAP9
DCHMAP10
DCHMAP11
DCHMAP12
DCHMAP13
DCHMAP14
DCHMAP15
DCHMAP16
DCHMAP17
DCHMAP18
DCHMAP19
DCHMAP20
DCHMAP21
EDMA Channel 0 Mapping to PaRAM
EDMA Channel 1 Mapping to PaRAM
EDMA Channel 2 Mapping to PaRAM
EDMA Channel 3 Mapping to PaRAM
EDMA Channel 4 Mapping to PaRAM
EDMA Channel 5 Mapping to PaRAM
EDMA Channel 6 Mapping to PaRAM
EDMA Channel 7 Mapping to PaRAM
EDMA Channel 8 Mapping to PaRAM
EDMA Channel 9 Mapping to PaRAM
EDMA Channel 10 Mapping to PaRAM
EDMA Channel 11 Mapping to PaRAM
EDMA Channel 12 Mapping to PaRAM
EDMA Channel 13 Mapping to PaRAM
EDMA Channel 14 Mapping to PaRAM
EDMA Channel 15 Mapping to PaRAM
EDMA Channel 16 Mapping to PaRAM
EDMA Channel 17 Mapping to PaRAM
EDMA Channel 18 Mapping to PaRAM
EDMA Channel 19 Mapping to PaRAM
EDMA Channel 20 Mapping to PaRAM
EDMA Channel 21 Mapping to PaRAM
02A0 0104
02A0 0108
02A0 010C
02A0 0110
02A0 0114
02A0 0118
02A0 011C
02A0 0120
02A0 0124
02A0 0128
02A0 012C
02A0 0130
02A0 0134
02A0 0138
02A0 013C
02A0 0140
02A0 0144
02A0 0148
02A0 014C
02A0 0150
02A0 0154
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Table 6-4. EDMA Registers (continued)
HEX ADDRESS RANGE
02A0 0158
02A0 015C
02A0 0160
02A0 0164
02A0 0168
02A0 016C
02A0 0170
02A0 0174
02A0 0178
02A0 017C
02A0 0180
02A0 0184
02A0 0188
02A0 018C
02A0 0190
02A0 0194
02A0 0198
02A0 019C
02A0 01A0
02A0 01A4
02A0 01A8
02A0 01AC
02A0 01B0
02A0 01B4
02A0 01B8
02A0 01BC
02A0 01C0
02A0 01C4
02A0 01C8
02A0 01CC
02A0 01D0
02A0 01D4
02A0 01D8
02A0 01DC
02A0 01E0
02A0 01E4
02A0 01E8
02A0 01EC
02A0 01F0
02A0 01F4
02A0 01F8
02A0 01FC
02A0 0200
02A0 0204
02A0 0208
02A0 020C
02A0 0210 - 02A0 021C
ACRONYM
DCHMAP22
DCHMAP23
DCHMAP24
DCHMAP25
DCHMAP26
DCHMAP27
DCHMAP28
DCHMAP29
DCHMAP30
DCHMAP31
DCHMAP32
DCHMAP33
DCHMAP34
DCHMAP35
DCHMAP36
DCHMAP37
DCHMAP38
DCHMAP39
DCHMAP40
DCHMAP41
DCHMAP42
DCHMAP43
DCHMAP44
DCHMAP45
DCHMAP46
DCHMAP47
DCHMAP48
DCHMAP49
DCHMAP50
DCHMAP51
DCHMAP52
DCHMAP53
DCHMAP54
DCHMAP55
DCHMAP56
DCHMAP57
DCHMAP58
DCHMAP59
DCHMAP60
DCHMAP61
DCHMAP62
DCHMAP63
QCHMAP0
QCHMAP1
QCHMAP2
QCHMAP3
-
REGISTER NAME
EDMA Channel 22 Mapping to PaRAM
EDMA Channel 23 Mapping to PaRAM
EDMA Channel 24 Mapping to PaRAM
EDMA Channel 25 Mapping to PaRAM
EDMA Channel 26 Mapping to PaRAM
EDMA Channel 27 Mapping to PaRAM
EDMA Channel 28 Mapping to PaRAM
EDMA Channel 29 Mapping to PaRAM
EDMA Channel 30 Mapping to PaRAM
EDMA Channel 31 Mapping to PaRAM
EDMA Channel 32 Mapping to PaRAM
EDMA Channel 33 Mapping to PaRAM
EDMA Channel 34 Mapping to PaRAM
EDMA Channel 35 Mapping to PaRAM
EDMA Channel 36 Mapping to PaRAM
EDMA Channel 37 Mapping to PaRAM
EDMA Channel 38 Mapping to PaRAM
EDMA Channel 39 Mapping to PaRAM
EDMA Channel 40 Mapping to PaRAM
EDMA Channel 41 Mapping to PaRAM
EDMA Channel 42 Mapping to PaRAM
EDMA Channel 43 Mapping to PaRAM
EDMA Channel 44 Mapping to PaRAM
EDMA Channel 45 Mapping to PaRAM
EDMA Channel 46 Mapping to PaRAM
EDMA Channel 47 Mapping to PaRAM
EDMA Channel 48 Mapping to PaRAM
EDMA Channel 49 Mapping to PaRAM
EDMA Channel 50 Mapping to PaRAM
EDMA Channel 51 Mapping to PaRAM
EDMA Channel 52 Mapping to PaRAM
EDMA Channel 53 Mapping to PaRAM
EDMA Channel 54 Mapping to PaRAM
EDMA Channel 55 Mapping to PaRAM
EDMA Channel 56 Mapping to PaRAM
EDMA Channel 57 Mapping to PaRAM
EDMA Channel 58 Mapping to PaRAM
EDMA Channel 59 Mapping to PaRAM
EDMA Channel 60 Mapping to PaRAM
EDMA Channel 61 Mapping to PaRAM
EDMA Channel 62 Mapping to PaRAM
EDMA Channel 63 Mapping to PaRAM
EDMA QDMA Channel 0 Mapping to PaRAM
EDMA QDMA Channel 1 Mapping to PaRAM
EDMA QDMA Channel 2 Mapping to PaRAM
EDMA QDMA Channel 3 Mapping to PaRAM
Reserved
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Table 6-4. EDMA Registers (continued)
HEX ADDRESS RANGE
02A0 0220 - 02A0 023C
02A0 0240
ACRONYM
-
REGISTER NAME
Reserved
DMAQNUM0
DMAQNUM1
DMAQNUM2
DMAQNUM3
-
EDMA Que Number 0; Channels 00 thru 07
EDMA Que Number 1; Channels 08 thru 15
EDMA Que Number 2; Channels 16 thru 23
EDMA Que Number 3; Channels 24 thru 31
Reserved
02A0 0244
02A0 0248
02A0 024C
02A0 0250 - 02A0 025C
02A0 0260
QDMAQNUM
-
EDMA QDMA Que Number
02A0 0264 - 02A0 027C
02A0 0280
Reserved
QUETCMAP
QUEPRI
-
EDMA Queue to TC Mapping
02A0 0284
EDMA Queue Priority
02A0 0288 - 02A0 02FC
02A0 0300
Reserved
EMR
EDMA Event MIssed Register
02A0 0304
EMRH
EDMA Event MIssed High Register
EDMA Event Missed Clear Register
EDMA Event Missed Clear High Register
EDMA QDMA Event MIssed Register
EDMA QDMA Event MIssed Clear Register
EDMA CC Error Register
02A0 0308
EMCR
02A0 030C
EMCRH
QEMR
02A0 0310
02A0 0314
QEMCR
CCERR
CCERRCLR
EEVAL
-
02A0 0318
02A0 031C
EDMA CC Error Clear Register
02A0 0320
EDMA
02A0 0324 - 02A0 033C
02A0 0340
Reserved
DRAE0
DRAEH0
DRAE1
DRAEH1
DRAE2
DRAEH2
DRAE3
DRAEH3
DRAE4
DRAEH4
DRAE5
DRAEH5
DRAE6
DRAEH6
DRAE7
DRAEH7
QRAE0
QRAE1
QRAE2
QRAE3
-
EDMA Region Access Enable 0 Register
EDMA Region Access High Enable 0 Register
EDMA Region Access Enable 1 Register
EDMA Region Access High Enable 1 Register
EDMA Region Access Enable 2 Register
EDMA Region Access High Enable 2 Register
EDMA Region Access Enable 3 Register
EDMA Region Access High Enable 3 Register
EDMA Region Access Enable 4 Register
EDMA Region Access High Enable 4 Register
EDMA Region Access Enable 5 Register
EDMA Region Access High Enable 5 Register
EDMA Region Access Enable 6 Register
EDMA Region Access High Enable 6 Register
EDMA Region Access Enable 7 Register
EDMA Region Access High Enable 7 Register
EDMA QDMA Region Access Enable 0
EDMA QDMA Region Access Enable 1
EDMA QDMA Region Access Enable 2
EDMA QDMA Region Access Enable 3
Reserved
02A0 0344
02A0 0348
02A0 034C
02A0 0350
02A0 0354
02A0 0358
02A0 035C
02A0 0360
02A0 0364
02A0 0368
02A0 036C
02A0 0370
02A0 0374
02A0 0378
02A0 0380
02A0 0384
02A0 0388
02A0 038C
02A0 0390
02A0 0394 - 02A0 039C
02A0 0400
Q0E0
EDMA Event Q0 Entry 0 / Event Q0 Base
EDMA Event Q0 Entry 1 / Event Q0 Base
EDMA Event Q0 Entry 2 / Event Q0 Base
EDMA Event Q0 Entry 3 / Event Q0 Base
EDMA Event Q0 Entry 4 / Event Q0 Base
02A0 0404
Q0E1
02A0 0408
Q0E2
02A0 040C
Q0E3
02A0 0410
Q0E4
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Table 6-4. EDMA Registers (continued)
HEX ADDRESS RANGE
02A0 0414
02A0 0418
02A0 041C
02A0 0420
02A0 0424
02A0 0428
02A0 042C
02A0 0430
02A0 0434
02A0 0438
02A0 043C
02A0 0440
02A0 0444
02A0 0448
02A0 044C
02A0 0450
02A0 0454
02A0 0458
02A0 045C
02A0 0460
02A0 0464
02A0 0468
02A0 046C
02A0 0470
02A0 0474
02A0 0478
02A0 047C
02A0 0480
02A0 0484
02A0 0488
02A0 048C
02A0 0490
02A0 0494
02A0 0498
02A0 049C
02A0 04A0
02A0 04A4
02A0 04A8
02A0 04AC
02A0 04B0
02A0 04B4
02A0 04B8
02A0 04BC
02A0 04C0 - 02A0 04CC
02A0 04D0
02A0 04D4
02A0 04D8
ACRONYM
Q0E5
Q0E6
Q0E7
Q0E8
Q0E9
Q0E10
Q0E11
Q0E12
Q0E13
Q0E14
Q0E15
Q1E0
Q1E1
Q1E2
Q1E3
Q1E4
Q1E5
Q1E6
Q1E7
Q1E8
Q1E9
Q1E10
Q1E11
Q1E12
Q1E13
Q1E14
Q1E15
Q2E0
Q2E1
Q2E2
Q2E3
Q2E4
Q2E5
Q2E6
Q2E7
Q2E8
Q2E9
Q2E10
Q2E11
Q2E12
Q2E13
Q2E14
Q2E15
-
REGISTER NAME
EDMA Event Q0 Entry 5 / Event Q0 Base
EDMA Event Q0 Entry 6 / Event Q0 Base
EDMA Event Q0 Entry 7 / Event Q0 Base
EDMA Event Q0 Entry 8 / Event Q0 Base
EDMA Event Q0 Entry 9 / Event Q0 Base
EDMA Event Q0 Entry 10 / Event Q0 Base
EDMA Event Q0 Entry 11 / Event Q0 Base
EDMA Event Q0 Entry 12 / Event Q0 Base
EDMA Event Q0 Entry 13 / Event Q0 Base
EDMA Event Q0 Entry 14 / Event Q0 Base
EDMA Event Q0 Entry 15 / Event Q0 Base
EDMA Event Q1 Entry 0 / Event Q1 Base
EDMA Event Q1 Entry 1 / Event Q1 Base
EDMA Event Q1 Entry 2 / Event Q1 Base
EDMA Event Q1 Entry 3 / Event Q1 Base
EDMA Event Q1 Entry 4 / Event Q1 Base
EDMA Event Q1 Entry 5 / Event Q1 Base
EDMA Event Q1 Entry 6 / Event Q1 Base
EDMA Event Q1 Entry 7 / Event Q1 Base
EDMA Event Q1 Entry 8 / Event Q1 Base
EDMA Event Q1 Entry 9 / Event Q1 Base
EDMA Event Q1 Entry 10 / Event Q1 Base
EDMA Event Q1 Entry 11 / Event Q1 Base
EDMA Event Q1 Entry 12 / Event Q1 Base
EDMA Event Q1 Entry 13 / Event Q1 Base
EDMA Event Q1 Entry 14 / Event Q1 Base
EDMA Event Q1 Entry 15 / Event Q1 Base
EDMA Event Q2 Entry 0 / Event Q2 Base
EDMA Event Q2 Entry 1 / Event Q2 Base
EDMA Event Q2 Entry 2 / Event Q2 Base
EDMA Event Q2 Entry 3 / Event Q2 Base
EDMA Event Q2 Entry 4 / Event Q2 Base
EDMA Event Q2 Entry 5 / Event Q2 Base
EDMA Event Q2 Entry 6 / Event Q2 Base
EDMA Event Q2 Entry 7 / Event Q2 Base
EDMA Event Q2 Entry 8 / Event Q2 Base
EDMA Event Q2 Entry 9 / Event Q2 Base
EDMA Event Q2 Entry 10 / Event Q2 Base
EDMA Event Q2 Entry 11 / Event Q2 Base
EDMA Event Q2 Entry 12 / Event Q2 Base
EDMA Event Q2 Entry 13 / Event Q2 Base
EDMA Event Q2 Entry 14 / Event Q2 Base
EDMA Event Q2 Entry 15 / Event Q2 Base
Reserved
Q3E0
Q3E1
Q3E2
EDMA Event Q3 Entry 0 / Event Q3 Base
EDMA Event Q3 Entry 1 / Event Q3 Base
EDMA Event Q3 Entry 2 / Event Q3 Base
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Table 6-4. EDMA Registers (continued)
HEX ADDRESS RANGE
02A0 04DC
ACRONYM
REGISTER NAME
EDMA Event Q3 Entry 3 / Event Q3 Base
Q3E3
02A0 04E0
Q3E4
EDMA Event Q3 Entry 4 / Event Q3 Base
EDMA Event Q3 Entry 5 / Event Q3 Base
EDMA Event Q3 Entry 6 / Event Q3 Base
EDMA Event Q3 Entry 7 / Event Q3 Base
EDMA Event Q3 Entry 8 / Event Q3 Base
EDMA Event Q3 Entry 9 / Event Q3 Base
EDMA Event Q3 Entry 10 / Event Q3 Base
EDMA Event Q3 Entry 11 / Event Q3 Base
EDMA Event Q3 Entry 12 / Event Q3 Base
EDMA Event Q3 Entry 13 / Event Q3 Base
EDMA Event Q3 Entry 14 / Event Q3 Base
EDMA Event Q3 Entry 15 / Event Q3 Base
Reserved
02A0 04E4
Q3E5
02A0 04E8
Q3E6
02A0 04EC
Q3E7
02A0 04F0
Q3E8
02A0 04F4
Q3E9
02A0 04F8
Q3E10
02A0 04FC
Q3E11
02A0 0500
Q3E12
02A0 0504
Q3E13
02A0 0508
Q3E14
02A0 050C
Q3E15
02A0 0510 - 02A0 051C
02A0 0520 - 02A0 05FC
02A0 0600
-
-
Reserved
QSTAT0
EDMA Queue 0 Status
EDMA Queue 1 Status
EDMA Queue 2 Status
EDMA Queue 3 Status
Reserved
02A0 0604
QSTAT1
02A0 0608
QSTAT2
02A0 060C
QSTAT3
02A0 0610 - 02A0 061C
02A0 0620
-
QWMTHRA
EDMA Queue Threshold A, for Q[3:0]
Reserved
02A0 0624
-
02A0 0628
QWMCLR
EDMA Queue Watermark Clear Command
Reserved
02A0 062C - 02A0 063C
02A0 0640
-
CCSTAT
CC Status
02A0 0644 - 02A0 06FC
02A0 0700
-
Reserved
-
Reserved
02A0 0704
-
Reserved
02A0 0708
-
Reserved
02A0 070C - 02A0 07FC
02A0 0800
-
Reserved
-
Reserved
02A0 0804
-
Reserved
02A0 0808
-
Reserved
02A0 080C
-
Reserved
02A0 0810
-
-
Reserved
02A0 0814
Reserved
02A0 0818
-
Reserved
02A0 081C
-
Reserved
02A0 0820 - 02A0 0FFC
02A0 1000
-
Reserved
ER (ERL)
ERH
ECR
ECRH
ESR
ESRH
CER
CERH
EDMA Event Register
EDMA Event High Register
EDMA Event Clear Register
EDMA Event Clear High Register
EDMA Event Set Register
EDMA Event Set High Register
EDMA Chained Event Register
EDMA Chained Event High Register
02A0 1004
02A0 1008
02A0 100C
02A0 1010
02A0 1014
02A0 1018
02A0 101C
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Table 6-4. EDMA Registers (continued)
HEX ADDRESS RANGE
02A0 1020
ACRONYM
EER
REGISTER NAME
EDMA Event Enable Register
02A0 1024
EERH
EECR
EECRH
EESR
EESRH
SER
EDMA Event Enable High Register
EDMA Event Enable Clear Register
EDMA Event Enable Clear High Register
EDMA Event Enable Set Register
EDMA Event Enable Set High Register
EDMA Secondary Event Register
EDMA Secondary Event High Register
EDMA Secondary Event Clear Register
EDMA Secondary Event Clear High Register
Reserved
02A0 1028
02A0 102C
02A0 1030
02A0 1034
02A0 1038
02A0 103C
02A0 1040
SERH
SECR
SECRH
-
02A0 1044
02A0 1048 - 02A0 104C
02A0 1050
IER
EDMA Interrupt Enable Register
EDMA Interrupt Enable High Register
EDMA Interrupt Enable Clear Register
EDMA Interrupt Enable Clear High Register
EDMA Interrupt Enable Set Register
EDMA Interrupt Enable Set High Register
EDMA Interrupt Pending Register
EDMA Interrupt Pending High Register
EDMA Interrupt Clear Register
EDMA Interrupt Clear High Register
EDMA Interrupt Evaluation Register (Set/Eval)
Reserved
02A0 1054
IERH
IECR
IECRH
IESR
IESRH
IPR
02A0 1058
02A0 105C
02A0 1060
02A0 1064
02A0 1068
02A0 106C
02A0 1070
IPRH
ICR
02A0 1074
ICRH
IEVAL
-
02A0 1078
02A0 107C
02A0 1080
QER
EDMA QDMA Event Register
EDMA QDMA Event Enable Register
EDMA QDMA Event Enable Clear Register
EDMA QDMA Event Enable Set Register
EDMA QDMA Secondary Event Register
EDMA QDMA Secondary Event Clear Register
Reserved
02A0 1084
QEER
QEECR
QEESR
QSER
QSECR
-
02A0 1088
02A0 108C
02A0 1090
02A0 1094
02A0 1098 - 02A0 3FFF
EDMA Parameter (PaRAM)
Parameter Set 0
02A0 4000
02A0 4020
Parameter Set 1
02A0 4040
Parameter Set 2
02A0 4060
Parameter Set 3
02A0 4080
Parameter Set 4
02A0 40A0
Parameter Set 5
02A0 40C0
Parameter Set 6
02A0 40E0
Parameter Set 7
02A0 4110
Parameter Set 8
02A0 4130
Parameter Set 9
02A0 4150
Parameter Set 10
02A0 4154 - 02A0 5FEC
02A0 5FF0
... Parameter Set 11 thru Parameter Set 254
Parameter Set 255
02A0 5FF4 - 02A0 7FE0
02A0 7FE4 - 02A0 7FFF
-
-
Reserved
Reserved
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6.9 Interrupts
6.9.1 Interrupt Sources and Interrupt Selector
The CPU interrupts on the C6455 device are configured through the enhanced interrupt selector. The
interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU
interrupt inputs, the CPU exception input, or the advanced emulation logic. Table 6-5 shows the mapping
of system events to the interrupt controller inputs. Event numbers 0-31 correspond to the default interrupt
mapping of the device. The remaining events must be mapped using software.
Table 6-5. C6455 DSP Interrupts
EVENT NUMBER
INT_00(1)
INTERRUPT EVENT
EVT0
INTERRUPT SOURCE
Interrupt Controller output of event combiner 0, for events 1 - 31.
Interrupt Controller output of event combiner 1, for events 32 - 63.
Interrupt Controller output of event combiner 2, for events 64 - 95.
Interrupt Controller output of event combiner 3, for events 96 - 127.
Reserved. Do not use.
INT_01(1)
INT_02(1)
INT_03(1)
EVT1
EVT2
EVT3
INT_04 - INT_08(2)
Reserved
EMU interrupt for:
1. Host scan access
2. DTDMA transfer complete
3. AET interrupt
INT_09(2)
EMU_DTDMA
INT_10(2)
INT_11(2)
INT_12(2)
INT_13(2)
INT_14(2)
INT_15(2)
INT_16
Reserved
EMU_RTDXRX
EMU_RTDXTX
IDMA0
Reserved. Do not use.
EMU real-time data exchange (RTDX) receive complete
EMU RTDX transmit complete
IDMA channel 0 interrupt
IDMA channel 1 interrupt
HPI/PCI host interrupt
I2C interrupt
IDMA1
HINT
I2CINT
INT_17
MACINT
Ethernet MAC interrupt
EMIFA error interrupt
INT_18
AEASYNCERR
Reserved
RIOINT0
INT_19
Reserved. Do not use.
RapidIO interrupt 0
INT_20
INT_21
RIOINT1
RapidIO interrupt 1
INT_22
RIOINT4
RapidIO interrupt 4
INT_23
Reserved
CC_GINT
Reserved
L2PDWAKE0
L2PDWAKE1
VCP2_INT
TCP2_INT
Reserved
UINT
Reserved. Do not use.
EDMA3 channel global completion interrupt
Reserved. Do not use.
L2 wakeup interrupt 0
INT_24
INT_25 - INT_29
INT_30
INT_31
L2 wakeup interrupt 1
INT_32
VCP2 error interrupt
INT_33
TCP2 error interrupt
INT_34 - INT_35
INT_36
Reserved. Do not use.
UTOPIA interrupt
INT_37 - INT_39
INT_40
Reserved
RINT0
Reserved. Do not use.
McBSP0 receive interrupt
(1) Interrupts INT_00 through INT_03 are non-maskable and fixed.
(2) Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers
fields. Table 6-5 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt
sources and selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).
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Table 6-5. C6455 DSP Interrupts (continued)
EVENT NUMBER
INT_41
INT_42
INT_43
INT_44 - INT_49
INT_50
INT_51
INT_52
INT_53
INT_54
INT_55
INT_56
INT_57
INT_58
INT_59
INT_60
INT_61
INT_62
INT_63
INT_64
INT_65
INT_66
INT_67
INT_68
INT_69
INT_70
INT_71
INT_72
INT_73
INT_74
INT_75
INT_76
INT_77
INT_78
INT_79
INT_80
INT_81
INT_82
INT_83
INT_84
INT_85
INT_86 - INT_95
INT_96
INT_97
INT_98
INT_99
INT_100
INT_101
INTERRUPT EVENT
XINT0
INTERRUPT SOURCE
McBSP0 transmit interrupt
RINT1
McBSP1 receive interrupt
McBSP1 transmit interrupt
Reserved. Do not use.
Reserved. Do not use.
GPIO interrupt
XINT1
Reserved
Reserved
GPINT0
GPINT1
GPIO interrupt
GPINT2
GPIO interrupt
GPINT3
GPIO interrupt
GPINT4
GPIO interrupt
GPINT5
GPIO interrupt
GPINT6
GPIO interrupt
GPINT7
GPIO interrupt
GPINT8
GPIO interrupt
GPINT9
GPIO interrupt
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
TINTLO0
TINTHI0
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Timer 0 lower counter interrupt
Timer 0 higher counter interrupt
Timer 1 lower counter interrupt
Timer 1 higher counter interrupt
CC completion interrupt - Mask0
CC completion interrupt - Mask1
CC completion interrupt - Mask2
CC completion interrupt - Mask3
CC completion interrupt - Mask4
CC completion interrupt - Mask5
CC completion interrupt - Mask6
CC completion interrupt - Mask7
CC error interrupt
TINTLO1
TINTHI1
CC_INT0
CC_INT1
CC_INT2
CC_INT3
CC_INT4
CC_INT5
CC_INT6
CC_INT7
CC_ERRINT
CC_MPINT
TC_ERRINT0
TC_ERRINT1
TC_ERRINT2
TC_ERRINT3
CC_AETEVT
Reserved
INTERR
CC memory protection interrupt
TC0 error interrupt
TC1 error interrupt
TC2 error interrupt
TC3 error interrupt
CC AET event
Reserved. Do not use.
Interrupt Controller dropped CPU interrupt event
EMC invalid IDMA parameters
Reserved. Do not use.
Reserved. Do not use.
EFI interrupt from side A
EFI interrupt from side B
EMC_IDMAERR
Reserved
Reserved
EFIINTA
EFIINTB
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Table 6-5. C6455 DSP Interrupts (continued)
EVENT NUMBER
INT_102 - INT_111
INT_112
INTERRUPT EVENT
Reserved
INTERRUPT SOURCE
Reserved. Do not use.
Reserved. Do not use.
Reserved
INT_113
L1P_ED1
L1P single bit error detected during DMA read
Reserved. Do not use.
INT_114 - INT_115
INT_116
Reserved
L2_ED1
L2 single bit error detected
INT_117
L2_ED2
L2 two bit error detected
INT_118
PDC_INT
Powerdown sleep interrupt
INT_119
Reserved
Reserved. Do not use.
INT_120
L1P_CMPA
L1P_DMPA
L1D_CMPA
L1D_DMPA
L2_CMPA
L1P CPU memory protection fault
L1P DMA memory protection fault
L1D CPU memory protection fault
L1D DMA memory protection fault
L2 CPU memory protection fault
L2 DMA memory protection fault
IDMA CPU memory protection fault
IDMA bus error interrupt
INT_121
INT_122
INT_123
INT_124
INT_125
L2_DMPA
INT_126
IDMA_CMPA
IDMA_BUSERR
INT_127
6.9.2 External Interrupts Electrical Data/Timing
Table 6-6. Timing Requirements for External Interrupts(1) (see Figure 6-6)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
tw(NMIL)
tw(NMIH)
Width of the NMI interrupt pulse low
Width of the NMI interrupt pulse high
6P
6P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
2
1
NMI
Figure 6-6. NMI Interrupt Timing
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6.10 Reset
The C6455 device has several types of resets – Power-on Reset, Warm Reset, Max Reset, System
Reset, and CPU Reset. Table 6-7 explains further the types of reset, the reset initiator, and the effects on
the chip.
Table 6-7. Reset Types(1)
TYPE
INITIATOR
EFFECT(s)
Hardware circuit detects power on condition. Resets the entire chip including reset of the test/emulation logic.
POR (power-on-reset)
POR pin active low.
Total reset of chip (cold reset). Activates the POR signal on-chip.
Resets everything except for test/emulation logic. Emulator stays
alive during Warm Reset.
Warm Reset
Max Reset
RESET pin active low
RapidIO [through RIOINT5(2)
Emulator
Same as a Warm Reset.
Soft Reset. A soft reset maintains memory contents and does not
affect or reset the Device Configuration pins, the PLL1 and PLL2
peripherals, the PLL1 Controller, the PowerSaver module, or the
Test/Emulation circuitry.
System Reset
CPU Reset
Emulator
HPI
Resets the CPU.
(1) For more detailed information on the C6455 device Reset Types, see the TBD Reference Guide (Literature Number SPRUTBD).
(2) RIOINT5 is used generate a MAXreset only. It is not connected to the device interrupt controller. For more detailed information on the
RIOINT5, see the Serial Rapid I/O (SRIO) Peripheral Reference Guide (Literature Number TBD).
6.10.1 Power-on Reset (POR Pin)
Note: The reset (RESET) pin must be held inactive (High) throughout the Power-On Reset.
1. During Power up, the power-on reset (POR) pin must be low [active].
2. Once the power supplies are within valid operating conditions, the POR pin must be held low for a
minimum of 256 CLKIN1 cycles before being pulled high. Within the minimum 256 CLKIN1 cycles, the
following happens:
a. The reset signals flow to the entire chip (including the test and emulation logic), resetting anything
that uses reset asynchronously, and sends a Hi-z signal to all the I/O pads to prevent off-chip
contention.
b. The clocks are reset and are propagated throughout the chip to reset any logic that was using
reset synchronously.
The RESETSTAT pin is active (low), indicating the device is in reset.
3. When the POR pin is released (driven inactive high), the configuration pin values are latched and
device initialization begins.
4. After device initialization is complete, all system clocks are paused for 8 CLKIN1 cycles and then
restarted.
5. The device is now out of reset, the RESETSTAT pin goes inactive (high), and the device execution
begins as dictated by the selected boot mode (see Section 2.4, Bootmode Sequence).
6.10.2 Warm Reset
Note: The power-on reset (POR) pin must be held inactive (high) throughout the Warm Reset.
1. The reset (RESET) pin must be high [inactive].
2. Once the power supplies are within valid operating conditions, the RESET pin must be held low for a
minimum of 24 CLKIN1 cycles before being pulled high. Within the minimum 24 CLKIN1 cycles, the
following happens:
a. The reset signals flow to the entire chip (excluding the PLL2 module and the test and emulation
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logic), resetting anything that uses reset asynchronously, and sends a Hi-z signal to all the I/O
pads to prevent off-chip contention.
b. The clocks are reset and are propagated throughout the chip to reset any logic that was using
reset synchronously.
The RESETSTAT pin is active (low), indicating the device is in reset.
3. When the RESET pin is released (driven inactive high), the configuration pin values are latched and
device initialization begins.
4. After device initialization is complete, all system clocks are paused for 8 CLKIN1 cycles and then
restarted.
5. The device is now out of reset, the RESETSTAT pin goes inactive (high), and the device execution
begins as dictated by the selected boot mode (see Section 2.4, Bootmode Sequence).
RESET should not be tied together with POR.
6.10.3 Max Reset
A Max Reset is initiated by the RapidIO peripheral or by the emulator and has the same affect as a Warm
Reset.
6.10.4 System Reset
A System Reset is initiated by the emulator. The System Reset is considered a "soft reset" — meaning
the internal memory contents are maintained and neither the clock logic or the power control logic are
afffected.
A System (Soft) Reset does not reset the PLL1 and PLL2 peripherals, the PLL1 Controller, and the
Powersaver modules or the Test/Emulation circuitry.
The boot sequence is initiated after a system reset. Since the configuration pins (including the
BOOTMODE[3:0] pins) are not latched with a system reset, the previous values, as shown in the
DEVSTAT register, are used to select the bootmode.
6.10.5 CPU Reset
A CPU Reset is initiated by the HPI peripheral. This reset only affects the CPU.
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6.10.6 Reset Electrical Data/Timing
Table 6-8. Timing Requirements for Reset(1) (see Figure 6-7 and Figure 6-8)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
tsu(DVDD33-CVDD12) Setup time, DVDD33 supply stable before CVDD12 supply stable
0.5
200
ms
ms
Setup time, CVDD12 supply stable before DVDD18 supply and VREFSSTL
reference voltage stable
tsu(CVDD12-DVDD18)
0.5
200
200
200
Setup time, DVDD18 supply and VREFSSTL reference voltage stable before
tsu(DVDD18-DVDD15)
3
4
0.5
0.5
ms
ms
DVDD15 supply and VREFHSTL reference voltage stable
Setup time, DVDD15 supply and VREFHSTL reference voltage stable before
DVDD12 supply stable
tsu(DVDD15-DVDD12)
5
6
th(DVDD12-POR)
tw(POR)
Hold time, POR low after DVDD12 supply stable
Pulse duration, RESET low
256*C
24C
ns
ns
Setup time, bootmode and configuration bits valid before POR high or
RESET high
7
8
tsu(boot)
th(boot)
6P
6P
ns
ns
Hold time, bootmode and configuration bits valid after POR high or RESET
high(2)
(1) C = 1/CLKIN clock frequency in ns.
(2) AEA[19:0], ABA[1:0], and PCI_EN are the boot configuration pins during device reset.
Table 6-9. Switching Characteristics Over Recommended Operating Conditions During Reset
(see Figure 6-8)
–1000
NO.
PARAMETER
UNIT
MIN
MAX
TBD
TBD
8
9
td(PORH-RSTATH)
Delay time, POR high to RESETSTAT high
ns
ns
td(RESETH-RSTATH) Delay time, RESET high to RESETSTAT high
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CLKIN1
CLKIN2
DV
DD33
DD12
1
CV
2
DV
DD18
VREFSSTL (DDR2)
DV
3
DD15
VREFHSTL (RMII)
4
DV
DD12
5
POR
RESET
9
RESETSTAT
7
8
Boot and
(A)
Device Configuration Pins
A. Boot and Device Configurations Inputs (during reset) include: AEA[19:0], ABA[1:0], andPCI_EN.
Figure 6-7. Power-Up Timing
CLKIN1
CLKIN2
POR
6
(B)
RESET
9
RESETSTAT
7
8
Boot and
(A)
Device Configuration Pins
A. Boot and Device Configurations Inputs (during reset) include: AEA[19:0], ABA[1:0], and PCI_EN.
B. RESET should only be used after device has been powered-up. See Reset section for more details on the use of the
RESET pin.
Figure 6-8. Reset Timing - TBD
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6.11 PLL1 and PLL1 Controller - TBD
The C6455 device includes a PLL1 and a software programmable PLL1 Controller. The PLL1 controller is
able to generate different clocks for different parts of the system (i.e., Megamodule, DSP core, Peripheral
Data Bus, EMIFA , and other peripherals). Figure 6-9 illustrates the PLL1, the PLL1 controller, and the
clock generator logic.
There is no hardware CLKMODE selection on the C6455 device. The PLL multiply factor is set in software
after reset.
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6.11.1 PLL1 and PLL1 Controller Device-Specific Information
+1.8 V
PLLV1
C2
C1
EMI filter
560 pF 0.1 µF
(See NOTES)
PLLOUT
PLLEN (TBD BIT)
SYSREFCLK1
PLLREF
(C64x+ MegaModule)
PLL1
x1,x20,x25,
x30,x32
CLKIN1
PREDIV
DIVIDER1
/3
1
0
(A)
SYSCLK1
DIVIDER2
/6
(B)
SYSCLK2
(D)
DIVIDER3
/x
(C)
SYSCLK3
(Internal EMIF Clock
Input)
(D)
DIVIDER4
/y
SYSCLK4
(Emulation and Trace)
PLL1 Controller
AECLKIN (External EMIF Clock Input)
1
0
AECLKINSEL
(AEA[15] pin)
EMIFA
(EMIF Input Clock)
TMD320C6455 DSP
AECLKOUT
A. EDMA, Chip infrastructure, CFG, and VCP2, TCP2, EMIFA, DDR2 Memory Controller, and RapidIO Peripherals
B. PCI, EMAC/MDIO, HPI, UTOPIA, McBSP, GPIO, TIMER, I2C, PLL1 Controller, and Powersaver
C. EMIFA
D. “/x” and ”/y” are variable divide ratio rates.
(For the PLL Multiply Options, PLL Lock Time, and PLL Clock Frequency Ranges, see the “TMS320C6455 PLL Multiply Factor Options,
Clock Frequency Ranges, and Typical Lock Time” table.)
NOTES: Place all PLL external components (C1, C2, and the EMI Filter) as close to the C64x+ DSP device as possible. For the best
performance,TI recommends that all the PLL external components be on a single side of the board without jumpers, swirches, or
components other than the ones shown.
For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI Filter).
The 1.8-V supply for the EMI filter must be from the same 1.8-V power plane supplying the I/O voltage, D
EMI filter manufacturer Murata part number NFM18CC222R1C3.
.
VDD18
Figure 6-9. External PLL1 Circuitry for Either PLL1 Multiply Modes or x1 (Bypass) Mode
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6.11.3 PLL1 Controller Peripheral Register Description(s)
Table 6-10. PLL1 Controller
HEX ADDRESS RANGE
029A 0000
029A 0004
029A 0008
029A 000C
029A 0010
029A 0014
029A 0018 - 029A 00DC
029A 00E0
029A 00E4
029A 00E8
029A 00EC
029A 00F0
029A 00F4
029A 00F8
029A 00FC
029A 0100
029A 0104
029A 0108
029A 010C
029A 0110
029A 0114
029A 0118
029A 011C
029A 0120
029A 0124
029A 0128
029A 012C
029A 0130
029A 0134
029A 0138
029A 013C
029A 0140
029A 0144
029A 0148
029A 014C
029A 0150
029A 0154
029A 0158
029A 015C
029A 0160
029A 0164
029A 0168
029A 016C
ACRONYM
REGISTER NAME
PLLPID
Peripheral identification register [value: 0x0001 0802]
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
FUSERR
Fusefarm error register
Reset type status register
Reserved
RSTYPE
-
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
PLLM
PLL multiplier control register
PLL pre-divider control register
Reserved
PREDIV
-
-
Reserved
PLLDIV3
PLL controller divider 3 register
Reserved
-
-
Reserved
-
Reserved
-
Reserved
-
Reserved
PLLCMD
PLL controller command register
PLL controller status register
Reserved
PLLSTAT
-
DCHANGE
PLLDIV ratio change status register
Reserved
-
-
Reserved
SYSTAT
SYSCLK status register
Reserved
-
-
Reserved
-
Reserved
PLLDIV4
PLL controller divider 4 register
Reserved
-
-
-
Reserved
Reserved
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Table 6-10. PLL1 Controller (continued)
HEX ADDRESS RANGE
029A 0170
ACRONYM
REGISTER NAME
-
-
-
-
Reserved
Reserved
Reserved
Reserved
029A 0174 - 029A 01EF
029A 01F0 - 029A 01FF
029A 0200 - 029B FFFF
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6.11.4 PLL1 Controller Registers
PLLPID
FUSERR
RSTYPE
PLLM
31
16
Reserved
R-0
15
6
5
0
Reserved
PLLM
R/W-1
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 6-10. PLL1 Multiply Control Register (PLLM) [Hex Address: 029A 0110]
Table 6-11. PLL1 Multiply Control Register (PLLM) Field Descriptions
Bit
31:6
5:0
Field
Value Description
Reserved
PLLM
-
Reserved. Read-only, writes have no effect.
PLL1 Multiplier Select Bits
Defines the frequency multiplier of the input reference clock in conjunction with the TBD.
Note: The TCI6482 device only supports the x1 (BYPASS), x20, x25, x30 and x32 multiply
options.
00000 x1 (BYPASS)
10011 x20
11000 x25
11101 x30
11111 x32
PLLM select values 00001 through 10010, 10100 through 10111, 11101 through 11100, and 11110
are Reserved and not supported on this device.
PREDIV
PLLDIV1 and PLLDIV2 - have fixed values PLLDIV3, PLLDIV4 - PLL1 Controller Divider n Registers for
SYSCLKn (PLLDIVn)
These registers control the value of the divider Dn for SYSCLKn. Each divider divides down
SYSREFCLK1 (SYSCLK reference clock from either the BYPASS or PLL1 path).
PLLCMD
The PLL1 Controller Command Register contains the command bits for various PLLCTRL operations. The
register bits always read back what was previously written. These bits are not self-modified by the
PLLCTRL except through a reset where the bits are returned to default. The status of the command
register can be viewed in the PLLSTAT register.
PLLSTAT
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The fields in this register show the PLL1 Controller status (status of the PLLCMD register). TBD
DCHANGE
SYSTAT
6.11.5 PLL1 Controller Input and Output Clock Electrical Data/Timing
Table 6-12. Timing Requirements for CLKIN1 for –1000 Devices(1)(2)(3) (see Figure 6-11)
-720
-850
-1000
NO.
PLL MODES
x1 (Bypass),
UNIT
x20, x25, x30, x32
MIN
15
MAX
1
2
3
4
5
tc(CLKIN1)
tw(CLKIN1H)
tw(CLKIN1L)
tt(CLKIN1)
Cycle time, CLKIN1(4)
30
ns
ns
ns
ns
ps
Pulse duration, CLKIN1 high
Pulse duration, CLKIN1 low
Transition time, CLKIN1
Period Jitter, CLKIN1
0.4C
0.4C
5
tJ(CLKIN1)
50
(1) The reference points for the rise and fall transitions are measured at VIL MAXand VIH MIN.
(2) For more details on the PLL multiplier factors (x1 [BYPASS], x20, x25, x30, x32), see the Clock PLL1 section of this data sheet.
(3) C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.
(4) The PLL1 multiplier factors (x1 [BYPASS], x20, x25, x30, x32) further limit the MINand MAXvalues for tc(CLKIN1). For more detailed
information on these limitations, see the PLL1 Lock and Reset Times table (TBD).
1
5
4
2
CLKIN1
3
4
Figure 6-11. CLKIN1 Timing
Table 6-13. Switching Characteristics Over Recommended Operating Conditions for SYSCLK3
[CPU/8 - CPU/12](1)(2)
(see Figure 6-12)
-720
-850
NO.
PARAMETER
-1000
UNIT
MIN
MAX
6P + 0.7
6P + 0.7
1
2
3
4
tw(CKO3H)
tw(CKO3L)
tt(CKO3)
Pulse duration, SYSCLK3 high
Pulse duration, SYSCLK3 low
Transition time, SYSCLK3
4P – 0.7
4P – 0.7
ns
ns
ns
(1) The reference points for the rise and fall transitions are measured at VOL MAXand VOH MIN.
(2) P = 1/CPU clock frequency in nanoseconds (ns)
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3
SYSCLK3
2
3
Figure 6-12. SYSCLK3 Timing
6.12 PLL2 and PLL2 Controller
TMS320C6455 DSP
(25 MHz)
(250 MHz)
DDR2
PLL2
x 10
CLKIN2
Memory Controller
+1.8 V
PLLV2
RGMII and GMII
/x
RMII
C162
C161
EMI filter
560 pF 0.1 µF
PLL2 Controller
(See NOTES)
NOTES: Place all PLL external components (C161, C162, and the EMI Filter) as close to the C64x+ DSP device as possible.
For the best performance, TI recommends that all the PLL external components be on a single side of the board without
jumpers, swirches, or components other than the ones shown.
For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C161,
C162, and the EMI Filter).
The 1.8-V supply for the EMI filter must be from the same 1.8-V power plane supplying the I/O voltage, D
EMI filter manufacturer Murata part number NFM18CC222R1C3.
.
VDD18
A. /x must be programmed to /2 for GMII (default) and to /5 for RGMII or RMII
B. If EMAC is enabled, CLKIN2 frequency must be 25 MHz.
Figure 6-13. PLL2 Block Diagram(A)(B)
6.12.1 PLL2 Controller Input Clock Electrical Data/Timing
Table 6-14. Timing Requirements for CLKIN2(1)(2)(3) (see Figure 6-14)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
3
4
5
tc(CLKIN2)
tw(CLKIN2H)
tw(CLKIN2L)
tt(CLKIN2)
Cycle time, CLKIN2
37.5
0.4C
0.4C
80
ns
ns
ns
ns
ps
Pulse duration, CLKIN2 high
Pulse duration, CLKIN2 low
Transition time, CLKIN2
Period jitter, CLKIN2
5
tJ(CLKIN2)
50
(1) The reference points for the rise and fall transitions are measured at VIL MAXand VIH MIN.
(2) C = CLKIN2 cycle time in ns. For example, when CLKIN2 frequency is 50 MHz, use C = 20 ns.
(3) If EMAC is enabled, CLKIN2 cycle time must be 40 ns (25 MHz).
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1
5
4
2
CLKIN2
3
4
Figure 6-14. CLKIN2 Timing
6.13 DDR2 Memory Controller
The 32-bit DDR2 Memory Controller bus of the C6455 is used to interface to JEDEC DDR2 devices. The
DDR2 bus is designed to sustain a throughput of up to 2.0 GBps at a 500-MHz data rate (250-MHz clock
rate) as long as data requests are pending in the DDR2 Memory Controller.
The DDR2 external bus only interfaces to DDR2 devices; it does not share the bus with any other types of
peripherals. The decoupling of DDR2 memories from other devices both simplifies board design and
provides I/O concurrency from a second external memory interface, EMIFA.
6.13.1 DDR2 Memory Controller Device-Specific Information
The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces
such as EMIF, HPI, and McBSP. For these other interfaces the device timing was specified in terms of
data manual specifications and I/O buffer information specification (IBIS) models.
For the C6455 DDR2 memory bus, the approach is to specify compatible DDR2 devices and provide the
printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has
performed the simulation and system characterization to ensure all DDR2 interface timings in this solution
are met. The complete DDR2 system solution is documented in the Implementing DDR2 PCB Layout on a
TMS320C6455 Hardware Design Application Report (Literature Number SPRAAA7) [Document Release
Pending].
TI only supports designs that follow the board design guidelines outlined in the SPRAAA7
Application Report.
6.13.2 DDR2 Memory Controller Peripheral Register Description(s)
Table 6-15. DDR2 Memory Controller Registers
HEX ADDRESS RANGE
7800 0000
ACRONYM
REGISTER NAME
-
Reserved
7800 0004
SDSTS
DDR2 Memory Controller SDRAM Status Register
7800 0008
SDCFG
DDR2 Memory Controller SDRAM Configuration Register
7800 000C
SDCTL
DDR2 Memory Controller SDRAM Refresh Control Register
7800 0010
SDTIM
DDR2 Memory Controller SDRAM Timing Register
7800 0014 - 7800 004C
7800 0050 - 7800 0078
7800 007C - 7800 00BC
7800 00C0 - 7800 00E0
7800 00E4
-
Reserved
-
Reserved
-
Reserved
-
Reserved
DDRCTL
DDR2 Memory Controller PHY Control Register
7800 00E8
DDRSTS
DDR2 Memory Controller PHY Status Register
7800 00EC - 7800 00FC
7800 0100 - 7FFF FFFF
-
-
Reserved
Reserved
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6.13.3 DDR2 Memory Controller Electrical Data/Timing
The Implementing DDR2 PCB Layout on a TMS320C6455 Hardware Design Application Report (Literature
Number SPRAAA7) specifies a complete DDR2 interface solution for the C6455 as well as a list of
compatible DDR2 devices. TI has performed the simulation and system characterization to ensure all
DDR2 interface timings in this solution are met; therefore, no electrical data/timing information is supplied
here for this interface.
TI only supports designs that follow the board design guidelines outlined in the SPRAAA7
Application Report [Document Release Pending].
6.14 External Memory Interface A (EMIFA)
The EMIFA can interface to a variety of external devices or ASICs, including:
•
•
•
•
Pipelined and flow-through Synchronous-Burst SRAM (SBSRAM)
ZBT (Zero Bus Turnaround) SRAM and Late Write SRAM
Synchronous FIFOs
Asynchronous memory, including SRAM, ROM, and Flash
6.14.1 EMIFA Device-Specific Information
Timing analysis must be done to verify all AC timings are met. TI recommends utilizing I/O buffer
information specification (IBIS) to analyze all AC timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS
Models for Timing Analysis application report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines
(see the Terminal Functions table for the EMIF output signals).
6.14.2 EMIFA Peripheral Register Description(s)
Table 6-16. EMIFA Registers
HEX ADDRESS RANGE
7000 0000
ACRONYM
REGISTER NAME
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7000 0004
-
7000 0008
-
7000 000C
-
7000 0010
-
7000 0014 - 7000 004C
7000 0050 - 7000 007C
7000 0080
-
-
CESEC2
CESEC3
CESEC4
CESEC5
-
EMIFA Chip Select 2 Configuration Register
EMIFA Chip Select 3 Configuration Register
EMIFA Chip Select 4 Configuration Register
EMIFA Chip Select 5 Configuration Register
Reserved
7000 0084
7000 0088
7000 008C
7000 0090 - 7000 009C
7000 00A0
ASYNCWAITCFG EMIFA Async Wait Cycle Configuration Register
7000 00A4 - 7000 00BC
7000 00C0
-
Reserved
INTRAW
INTMSK
EMIFA Interrupt RAW Register
EMIFA Interrupt Masked Register
7000 00C4
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Table 6-16. EMIFA Registers (continued)
HEX ADDRESS RANGE
7000 00C8
ACRONYM
REGISTER NAME
EMIFA Interrupt Mask Set Register
INTMSKSET
7000 00CC
INTMSKCLR
EMIFA Interrupt Mask Clear Register
7000 00D0 - 7000 00DC
7000 00E0 - 77FF FFFF
-
-
Reserved
Reserved
100
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6.14.3 EMIFA Electrical Data/Timing
Table 6-17. Timing Requirements for AECLKIN for EMIFA(1)(2)(3) (see Figure 6-15)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
3
4
5
tc(EKI)
tw(EKIH)
tw(EKIL)
tt(EKI)
Cycle time, AECLKIN
6(4)
2.7
2.7
16P
ns
ns
ns
ns
ns
Pulse duration, AECLKIN high
Pulse duration, AECLKIN low
Transition time, AECLKIN
Period Jitter, AECLKIN
2
tJ(EKI)
0.02E(5)
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) The reference points for the rise and fall transitions are measured at VIL MAXand VIH MIN.
(3) E = the EMIF input clock (AECLKIN or SYSCLK3) period in ns for EMIFA.
(4) Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times
are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the -1000
devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met.
(5) This timing only applies when AECLKIN is used for EMIFA.
1
5
4
2
AECLKIN
3
4
Figure 6-15. AECLKIN Timing for EMIFA
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Table 6-18. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the
EMIFA Module(1)(2)(3) (see Figure 6-16)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
5
6
tc(EKO)
Cycle time, AECLKOUT
E – 0.7
EH – 0.7
EL – 0.7
E + 0.7
ns
ns
ns
ns
ns
ns
tw(EKOH)
tw(EKOL)
Pulse duration, AECLKOUT high
EH + 0.7
Pulse duration, AECLKOUT low
EL + 0.7
tt(EKO)
Transition time, AECLKOUT
1
8
8
td(EKIH-EKOH)
td(EKIL-EKOL)
Delay time, AECLKIN high to AECLKOUT high
Delay time, AECLKIN low to AECLKOUT low
1
1
(1) E = the EMIF input clock (AECLKIN or SYSCLK3) period in ns for EMIFA.
(2) The reference points for the rise and fall transitions are measured at VOL MAXand VOH MIN.
(3) EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
AECLKIN
5
2
3
3
1
4
AECLKOUT1
Figure 6-16. AECLKOUT Timing for the EMIFA Module
6.14.3.1 Asynchronous Memory Timing
Table 6-19. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1)(2)(3)
(see Figure 6-17 and Figure 6-18)
-720
-850
-1000
NO.
UNIT
MIN
MAX
3
4
5
6
7
tsu(EDV-AOEH)
th(AOEH-EDV)
tsu(ARDY-EKOH)
th(EKOH-ARDY)
tw(ARDY)
Setup time, AEDx valid before AAOE high
Hold time, AEDx valid after AAOE high
6.5
ns
ns
ns
ns
ns
3
Setup time, AARDY valid before AECLKOUT high
Hold time, AARDY valid after AECLKOUT high
Pulse width, AARDY assertion and deassertion
1
2
2E + 5
Delay time, from AARDY sampled deasserted on AECLKOUT rising to
beginning of programmed hold period
8
9
td(ARDY-HOLD)
tsu(ARDY-HOLD)
4E
ns
ns
Setup time, before end of programmed strobe period by which AARDY
should be asserted in order to insert extended strobe wait states.
2E
(1) E = AECLKOUT period in ns for EMIFA
(2) To ensure data setup time, simply program the strobe width wide enough.
(3) AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E
to ensure setup and hold time is met.
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Table 6-20. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module(1)(2)(3) (see Figure 6-17 and Figure 6-18)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
7
1
tosu(SELV-AOEL)
toh(AOEH-SELIV)
td(EKOH-AOEV)
tosu(SELV-AWEL)
toh(AWEH-SELIV)
td(EKOH-AWEV)
Output setup time, select signals valid to AAOE low
Output hold time, AAOE high to select signals invalid
Delay time, AECLKOUT high to AAOE valid
RS * E – 1.5
RS * E – 1.9
1
ns
ns
ns
ns
ns
ns
2
10
11
12
13
Output setup time, select signals valid to AAWE low
Output hold time, AAWE high to select signals invalid
Delay time, AECLKOUT high to AAWE valid
WS * E – 1.7
WH * E – 1.8
1.3
7.1
(1) E = AECLKOUT period in ns for EMIFA
(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters
are programmed via the EMIFA chip select configuration registers.
(3) Select signals for EMIFA include: ACEx, ABE[7:0], AEA[19:0], ABA[1:0]; and for EMIFA writes, also include AR/W, AED[63:0].
Strobe = 4
Setup = 1
Hold = 1
2
AECLKOUT
ACEx
1
1
2
2
Byte Enables
Address
ABE[7:0]
1
AEA[19:0]/
ABA[1:0]
3
4
Read Data
AED[63:0]
10
10
(A)
AAOE/ASOE
(A)
AAWE/ASWE
AR/W
(B)
DEASSERTED
AARDY
A
B
AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous
memory accesses.
Polarity of the AARDY signal is programmable through the “wp” field of the EMIFA Async Wait Cycle Configuration Register
(ASYNCWAITCFG).
Figure 6-17. Asynchronous Memory Read Timing for EMIFA
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Strobe = 4
Hold = 1
Setup = 1
AECLKOUT
ACEx
12
12
12
11
11
Byte Enables
Address
ABE[7:0]
11
AEA[19:0]/
ABA[1:0]
11
12
Write Data
AED[63:0]
(A)
AAOE/ASOE
13
13
(A)
AAWE/ASWE
11
12
AR/W
(B)
AARDY
A
B
AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous memory
accesses.
Polarity of the AARDY signal is programmable through the “wp” field of the EMIFA Async Wait Cycle Configuration Register
(ASYNCWAITCFG).
Figure 6-18. Asynchronous Memory Write Timing for EMIFA
Strobe
Strobe
Hold = 2
Setup = 2
Extended Strobe
9
8
AECLKOUT
6
5
7
7
(A)
ASSERTED
DEASSERTED
AARDY
A
Polarity of the AARDY signal is programmable through the “wp” field of the EMIFA Async Wait Cycle Configuration Register
(ASYNCWAITCFG).
Figure 6-19. AARDY Timing
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6.14.3.2 Programmable Synchronous Interface Timing
Table 6-21. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module
(see Figure 6-20)
-720
-850
-1000
NO.
UNIT
MIN
MAX
6
7
tsu(EDV-EKOH)
th(EKOH-EDV)
Setup time, read AEDx valid before AECLKOUT high
Hold time, read AEDx valid after AECLKOUT high
2
ns
ns
1.5
Table 6-22. Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module(1) (see Figure 6-20–Figure 6-22)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
4.9
1
2
td(EKOH-CEV)
td(EKOH-BEV)
td(EKOH-BEIV)
td(EKOH-EAV)
td(EKOH-EAIV)
td(EKOH-ADSV)
td(EKOH-OEV)
td(EKOH-EDV)
td(EKOH-EDIV)
td(EKOH-WEV)
Delay time, AECLKOUT high to ACEx valid
Delay time, AECLKOUT high to ABEx valid
Delay time, AECLKOUT high to ABEx invalid
Delay time, AECLKOUT high to AEAx valid
Delay time, AECLKOUT high to AEAx invalid
Delay time, AECLKOUT high to ASADS/ASRE valid
Delay time, AECLKOUT high to ASOE valid
Delay time, AECLKOUT high to AEDx valid
Delay time, AECLKOUT high to AEDx invalid
Delay time, AECLKOUT high to ASWE valid
1.3
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.9
3
4
4.9
5
1.3
1.3
1.3
8
4.9
4.9
4.9
9
10
11
12
1.3
1.3
4.9
(1) The following parameters are programmable via the EMIF CE Space Secondary Control register (CESECx):
•
•
•
Read latency (r_ltncy): 0-, 1-, 2-, or 3-cycle read latency
Write latency (w_ltncy): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (cs_ext): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has
been issued (cs_ext = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (cs_ext = 1).
•
Function of ASADS/ASRE (r_enable): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (r_enable = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (r_enable = 1).
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READ latency = 2
AECLKOUT
1
1
3
5
ACEx
2
BE1
ABE[7:0]
AEA[19:0]/ABA[1:0]
AED[63:0]
BE2
BE3
BE4
4
EA1
EA2
EA3
EA4
7
6
Q1
Q2
Q3
Q4
8
9
8
(B)
ASADS/ASRE
9
(B)
AAOE/ASOE
(B)
AAWE/ASWE
A
B
The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):
−Read latency (r_ltncy): 1-, 2-, or 3-cycle read latency
−Write latency (w_ltncy): 0-, 1-, 2-, or 3-cycle read latency
−ACEx assertion length (cs_ext): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been
issued (cs_ext = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (cs_ext = 1).
−Function of ASADS/ASRE (r_enable): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (r_enable = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (r_enable = 1).
−In this figure r_ltncy = 2, cs_ext = 0, and r_enable = 0.
AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
Figure 6-20. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)(A)
AECLKOUT
1
2
1
3
ACEx
ABE[7:0]
BE1
BE2
EA2
Q2
BE3
EA3
Q3
BE4
EA4
Q4
5
4
AEA[19:0]/ABA[1:0]
AED[63:0]
EA1
10
Q1
10
11
8
8
(B)
ASADS/ASRE
(B)
AAOE/ASOE
12
12
(B)
AAWE/ASWE
A
The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):
− Read latency (r_ltncy): 1-, 2-, or 3-cycle read latency
− Write latency (w_ltncy): 0-, 1-, 2-, or 3-cycle read latency
− ACEx assertion length (cs_ext): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been
issued (cs_ext = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (cs_ext = 1).
− Function of ASADS/ASRE (r_enable): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (r_enable = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (r_enable = 1).
− In this figure r_ltncy = 2, cs_ext = 0, and r_enable = 0.
B
AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
Figure 6-21. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)(A)
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Write
Latency =
(B)
1
AECLKOUTx
1
1
ACEx
3
2
ABE[7:0]
BE1
BE2
BE3
EA3
Q2
BE4
5
4
AEA[19:0]/ABA[1:0]
AED[63:0]
EA1
10
EA2
10
EA4
11
Q1
Q3
Q4
8
8
(B)
ASADS/ASRE
(B)
AAOE/ASOE
12
12
(B)
AAWE/ASWE
A
B
The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):
− Read latency (r_ltncy): 1-, 2-, or 3-cycle read latency
− Write latency (w_ltncy): 0-, 1-, 2-, or 3-cycle read latency
− ACEx assertion length (cs_ext): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been
issued (cs_ext = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (cs_ext = 1).
− Function of ASADS/ASRE (r_enable): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (r_enable = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (r_enable = 1).
− In this figure r_ltncy = TBD, cs_ext = TBD, and r_enable = TBD.
AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
Figure 6-22. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) (A)
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6.14.4 HOLD/HOLDA Timing
Table 6-23. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module(1) (see Figure 6-23)
-720
-850
-1000
NO.
UNIT
MIN
MAX
3
th(HOLDAL-HOLDL)
Hold time, HOLD low after HOLDA low
E
ns
(1) E = the EMIF input clock (ECLKIN) period in ns for EMIFA.
Table 6-24. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module(1)(2) (see Figure 6-23)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
(3)
1
2
4
5
td(HOLDL-EMHZ)
td(EMHZ-HOLDAL)
td(HOLDH-EMLZ)
td(EMLZ-HOLDAH)
Delay time, HOLD low to EMIFA Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIFA Bus low impedance to HOLDA high
2E
0
ns
ns
ns
ns
2E
7E
2E
2E
0
(1) E = the EMIF input clock (ECLKIN) period in ns for EMIFA.
(2) EMIFA Bus consists of: ACE[5:2], ABE[7:0], AED[63:0], AEA[19:0], ABA[1:0], AR/W, ASADS/ASRE, AAOE/ASOE, and AAWE/ASWE.
(3) All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the
minimum delay time can be achieved.
External Requestor
DSP Owns Bus
DSP Owns Bus
Owns Bus
3
HOLD
2
5
HOLDA
(A)
1
4
EMIF Bus
DSP
DSP
AECLKOUT
A. EMIFA Bus consists of: ACE[5:2], ABE[7:0], AED[63:0], AEA[19:0], ABA[1:0], AR/W, ASADS/ASRE, AAOE/ASOE,
and AAWE/ASWE.
Figure 6-23. HOLD/HOLDA Timing for EMIFA
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6.14.5 BUSREQ Timing
Table 6-25. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles
for EMIFA Module (see Figure 6-24)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
1
td(AEKOH-ABUSRV)
Delay time, AECLKOUT high to ABUSREQ valid
1
5.5
ns
AECLKOUTx
1
1
ABUSREQ
Figure 6-24. BUSREQ Timing for EMIFA
6.15 I2C Peripheral
The inter-integrated circuit (I2C) module provides an interface between a C64x+ DSP and other devices
compliant with Philips Semiconductors Inter-IC bus (I2C bus) specification version 2.1 and connected by
way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit
data to/from the DSP through the I2C module.
6.15.1 I2C Device-Specific Information
The C6455 device includes an I2C peripheral module (I2C). NOTE: when using the I2C module, ensure
there are external pullup resistors on the SDA and SCL pins.
The I2C modules on the C6455 may be used by the DSP to control local peripherals ICs (DACs, ADCs,
etc.) or may be used to communicate with other controllers in a system or to implement a user interface.
The I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to remove noise 50 ns or less
7- and 10-Bit Device Addressing Modes
Multi-Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
Slew-Rate Limited Open-Drain Output Buffers
Figure 6-25 is a block diagram of the I2C module.
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I2C Module
Clock
Prescale
Peripheral Clock
(CPU/6)
I2CPSC
Control
Bit Clock
Own
I2COAR
I2CSAR
I2CMDR
I2CCNT
I2CEMDR
Generator
Address
SCL
Noise
I2C Clock
Filter
Slave
Address
I2CCLKH
I2CCLKL
Mode
Data
Count
Transmit
I2CXSR
Transmit
Shift
Extended
Mode
Transmit
Buffer
I2CDXR
SDA
Interrupt/DMA
I2CIMR
Noise
I2C Data
Filter
Interrupt
Mask/Status
Receive
I2CDRR
Receive
Buffer
Interrupt
Status
I2CSTR
Interrupt
Vector
Receive
Shift
I2CRSR
I2CIVR
Shading denotes control/status registers.
Figure 6-25. I2C Module Block Diagram
6.15.2 I2C Peripheral Register Description(s)
Table 6-26. I2C Registers
HEX ADDRESS RANGE
02B0 4000
02B0 4004
02B0 4008
02B0 400C
02B0 4010
02B0 4014
02B0 4018
02B0 401C
02B0 4020
02B0 4024
02B0 4028
02B0 402C
02B0 4030
ACRONYM
REGISTER NAME
I2COAR
I2CIMR
I2C own address register
I2C interrupt mask/status register
I2C interrupt status register
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CIVR
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt vector register
I2C Extended mode register
I2C prescaler register
I2CEMDR
I2CPSC
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Table 6-26. I2C Registers (continued)
HEX ADDRESS RANGE
02B0 4034
ACRONYM
REGISTER NAME
I2CPID1
I2C Peripheral Identification register 1 [Value: 0x0000 0105]
02B0 4038
I2CPID2
I2C Peripheral Identification register 2 [Value: 0x0000 0005]
02B0 403C - 02B0 405C
02B0 4060 - 02B3 407F
02B0 4080 - 02B3 FFFF
-
-
-
Reserved
Reserved
Reserved
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6.15.3 I2C Electrical Data/Timing
6.15.3.1 Inter-Integrated Circuits (I2C) Timing
Table 6-27. Timing Requirements for I2C Timings(1) (see Figure 6-26)
-720
-850
-1000
NO.
UNIT
STANDARD MODE
FAST MODE
MIN
MIN
MAX
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for
a repeated START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
3
th(SCLL-SDAL)
0.6
µs
4
5
6
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SDLH)
Setup time, SDA valid before SCL high
250
Hold time, SDA valid after SCL low (For
I2C bus™ devices)
7
th(SDA-SDLL)
0(3)
0(3)
0.9(4)
µs
Pulse duration, SDA high between STOP
8
tw(SDAH)
and START
conditions
4.7
1.3
µs
(5)
9
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
(5)
(5)
(5)
10
11
12
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
300
Setup time, SCL high before SDA high (for
STOP condition)
13
tsu(SCLH-SDAH)
tw(SP)
4
0.6
0
µs
Pulse duration, spike (must be sup-
pressed)
14
15
50
ns
(5)
Cb
Capacitive load for each bus line
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus™ system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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11
9
SDA
6
8
14
13
4
5
10
SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 6-26. I2C Receive Timings
Table 6-28. Switching Characteristics for I2C Timings(1) (see Figure 6-27)
-720
-850
-1000
NO.
PARAMETER
UNIT
STANDARD MODE
FAST MODE
MIN
MIN
MAX
MAX
16
17
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Delay time, SCL high to SDA low (for a
repeated START condition)
td(SCLH-SDAL)
4.7
4
0.6
Delay time, SDA low to SCL low (for a
START and a repeated START condition)
18
td(SDAL-SCLL)
0.6
µs
19
20
21
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
td(SDAV-SDLH)
Delay time, SDA valid to SCL high
250
100
Valid time, SDA valid after SCL low (For
I2C bus™ devices)
22
23
tv(SDLL-SDAV)
tw(SDAH)
0
0
0.9
µs
µs
Pulse duration, SDA high between STOP
and START conditions
4.7
1.3
(1)
24
25
26
27
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
(1)
(1)
(1)
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
300
Delay time, SCL high to SDA high (for
STOP condition)
28
29
td(SCLH-SDAH)
Cp
4
0.6
µs
Capacitance for each I2C pin
10
10
pF
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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26
24
SDA
21
23
19
28
20
25
SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 6-27. I2C Transmit Timings
6.16 Host-Port Interface (HPI) Peripheral
6.16.1 HPI Device-Specific Information
The C6455 device includes a user-configurable 16-bit or 32-bit Host-port interface (HPI16/HPI32).
The AEA14 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16-bit or 32-bit
peripheral.
The C6455 device uses the HPI data pins for peripheral configuration and bootmode set up. For more
details on HPI peripheral configuration and the associated pins, see the Device Configurations section of
this data sheet.
6.16.2 HPI Peripheral Register Description(s)
Table 6-29. HPI Control Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
0288 0000
-
Reserved
PWREMU_MGMT has both
Host/CPU read/write access
0288 0004
PWREMU_MGMT
HPI power and emulation management register
0288 0008 - 0288 0024
0288 0028
-
-
-
Reserved
Reserved
Reserved
0288 002C
HPIC has both Host/CPU
read/write access
0288 0030
0288 0034
0288 0008
HPIC
HPI control register
HPIA
HPI address register
(Write)
(HPIAW)(1)
HPIA has both Host/CPU
read/write access
HPIA
HPI address register
(Read)
(HPIAR)(1)
0288 000C - 028B 007F
0288 0080 - 028B FFFF
-
-
Reserved
Reserved
(1) Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR
independently.
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6.16.3 HPI Electrical Data/Timing
Table 6-30. Timing Requirements for Host-Port Interface Cycles(1)(2) (see Table 6-31 through Figure 6-35)
-720
-850
-1000
NO.
UNIT
MIN
MAX
9
tsu(HASL-HSTBL)
th(HSTBL-HASL)
tsu(SELV-HASL)
th(HASL-SELV)
tw(HSTBL)
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
Setup time, select signals(3) valid before HAS low
Hold time, select signals(3) valid after HAS low
Pulse duration, HSTROBE low
5
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
18
37
5
5
15
2
tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals(3) valid before HSTROBE low
Hold time, select signals(3) valid after HSTROBE low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Setup time, HCS low before HSTROBE low
tsu(SELV-HSTBL)
th(HSTBL-SELV)
tsu(HDV-HSTBH)
th(HSTBH-HDV)
tsu(HCSL-HSTBL)
5
5
5
0
0
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
38
th(HRDYL-HSTBL)
0
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(3) Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
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Table 6-31. Switching Characteristics for Host-Port Interface Cycles(1)(2)
(see Table 6-31 through Figure 6-35)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
Case 1. HPIC or HPIA read
5
15
Case 2. HPID read with no
auto-increment
9 * 2H + 20
Case 3. HPID read with
auto-increment and read FIFO in-
itially empty
Delay time, HSTROBE low to
DSP data valid
1
td(HSTBL-HDV)
ns
9 * 2H + 20
Case 4. HPID read with
auto-increment and data previously
prefetched into the read FIFO
5
15
2
3
4
5
tdis(HSTBH-HDV)
ten(HSTBL-HD)
td(HSTBL-HRDYH)
td(HSTBH-HRDYH)
Disable time, HD high-impedance from HSTROBE high
Enable time, HD driven from HSTROBE low
Delay time, HSTROBE low to HRDY high
Delay time, HSTROBE high to HRDY high
Case 1. HPID read with no
1
3
4
15
12
12
ns
ns
ns
ns
10 * 2H + 20
auto-increment
Delay time, HSTROBE low to
6
td(HSTBL-HRDYL)
ns
Case 2. HPID read with
HRDY low
auto-increment and read FIFO in-
itially empty
10 * 2H + 20
7
td(HDV-HRDYL)
Delay time, HD valid to HRDY low
Case 1. HPIA write
0
ns
ns
5 * 2H + 20
5 * 2H + 20
Delay time, HSTROBE high to
HRDY low
Case 2. HPID read with
auto-increment and read FIFO
initially empty
34
td(DSH-HRDYL)
Delay time, HSTROBE low to HRDY low for HPIA write and FIFO
not empty
35
36
td(HSTBL-HRDYL)
td(HASL-HRDYH)
40 * 2H + 20
12
ns
ns
Delay time, HAS low to HRDY high
(1) H = 0.5 * SYSCLK2 period
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
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HCS
HAS
HCNTL[1:0]
HR/W
HHWIL
13
16
15
16
15
37
37
14
13
(A)
HSTROBE
3
3
1
1
2
2
HD[15:0]
38
4
7
6
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing)and the state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 6-28. HPI16 Read Timing (HAS Not Used, Tied High)
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HCS
HAS
12
11
12
11
HCNTL[1:0]
12
11
12
11
HR/W
12
11
12
11
HHWIL
10
9
10
9
37
13
13
37
14
(A)
HSTROBE
1
3
1
3
2
2
HD[15:0]
7
38
36
6
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing)and the state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 6-29. HPI16 Read Timing (HAS Used)
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HCS
HAS
HCNTL[1:0]
HR/W
HHWIL
16
13
16
15
37
15
37
13
14
(A)
HSTROBE
18
18
17
17
HD[15:0]
34
38
4
34
5
35
5
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing)and the state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 6-30. HPI16 Write Timing (HAS Not Used, Tied High)
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HCS
HAS
12
11
12
11
HCNTL[1:0]
12
12
11
11
HR/W
12
11
12
11
14
HHWIL
9
10
10
9
37
37
13
(A)
HSTROBE
13
18
18
17
17
HD[15:0]
34
35
34
5
36
5
38
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing)and the state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 6-31. HPI16 Write Timing (HAS Used)
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HAS
(input)
16
15
HCNTL[1:0]
(input)
HR/W
(input)
13
(A)
HSTROBE
(input)
37
HCS
(input)
1
2
3
HD[31:0]
(output)
38
7
6
4
†(B)
HRDY
(output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2:
[NOT(HDS1 XOR HDS2)] OR HCS.
B. Dependingon the type of write operation (HPID, HPIA, HPIC, HPID) and the state of
the FIFO, transitions on HRDY may or may not occur (see the TBD section for more
details).
For more detailed information on the HPI peripheral, see the TBD Reference Guide
(literaturenumber TBD).
Figure 6-32. HPI32 Read Timing (HAS Not Used, Tied High)
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10
HAS
(input)
12
11
HCNTL[1:0]
(input)
HR/W
(input)
9
13
(A)
HSTROBE
(input)
37
HCS
(input)
1
2
3
HD[31:0]
(output)
7
38
6
36
(B)
HRDY
(output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2:
[NOT(HDS1 XOR HDS2)] OR HCS.
B. Dependingon the type of write operation (HPID, HPIA, HPIC, HPID) and the state
of the FIFO, transitions on HRDY may or may not occur (see the TBD section for
more details).
For more detailed information on the HPI peripheral, see the TBD Reference
Guide (literature number TBD).
Figure 6-33. HPI32 Read Timing (HAS Used)
122
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HAS
(input)
16
15
HCNTL[1:0]
(input)
HR/W
(input)
13
(A)
HSTROBE
(input)
37
HCS
(input)
18
17
HD[31:0]
(input)
38
34
35
5
4
(B)
HRDY
(output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Dependingon the type of write operation (HPID, HPIA, HPIC, HPID) and the state of the FIFO, transitions on HRDY may
or may not occur (see the TBD section for more details).
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 6-34. HPI32 Write Timing (HAS Not Used, Tied High)
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10
HAS
(input)
12
11
HCNTL[1:0]
(input)
HR/W
(input)
9
13
(A)
HSTROBE
(input)
37
HCS
(input)
18
17
HD[31:0]
(input)
35
34
TBD
36
5
(B)
HRDY
(output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)]
OR HCS.
B. Dependingon the type of write operation (HPID, HPIA, HPIC, HPID) and the state of the FIFO, transitions
on HRDY may or may not occur (see the TBD section for more details).
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number
TBD).
Figure 6-35. HPI32 Write Timing (HAS Used)
6.17 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
•
•
•
•
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
•
External shift clock or an internal, programmable frequency shift clock for data transfer
For more detailed information on the McBSP peripheral, see the TBD Reference Guide (Literature Number
SPRUTBD).
124
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6.17.1 McBSP Device-Specific Information
The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
6.17.1.1 McBSP Peripheral Register Description(s)
Table 6-32. McBSP 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and EDMA con-
troller can only read this
register; they cannot write
to it.
028C 0000
DRR0
McBSP0 data receive register via Configuration Bus
3000 0000
028C 0004
DRR0
DXR0
McBSP0 data receive register via EDMA Bus
McBSP0 data transmit register via Configuration Bus
McBSP0 data transmit register via EDMA Bus
McBSP0 serial port control register
3000 0010
DXR0
028C 0008
SPCR0
RCR0
028C 000C
028C 0010
McBSP0 receive control register
XCR0
McBSP0 transmit control register
028C 0014
SRGR0
MCR0
McBSP0 sample rate generator register
028C 0018
McBSP0 multichannel control register
028C 001C
028C 0020
RCERE00
XCERE00
PCR0
McBSP0 enhanced receive channel enable register 0
McBSP0 enhanced transmit channel enable register 0
McBSP0 pin control register
028C 0024
028C 0028
RCERE10
XCERE10
RCERE20
XCERE20
RCERE30
XCERE30
-
McBSP0 enhanced receive channel enable register 1
McBSP0 enhanced transmit channel enable register 1
McBSP0 enhanced receive channel enable register 2
McBSP0 enhanced transmit channel enable register 2
McBSP0 enhanced receive channel enable register 3
McBSP0 enhanced transmit channel enable register 3
Reserved
028C 002C
028C 0030
028C 0034
028C 0038
028C 003C
028C 0040 - 028F FFFF
Table 6-33. McBSP 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and EDMA con-
troller can only read this
register; they cannot write
to it.
0290 0000
DRR1
McBSP1 data receive register via Configuration Bus
3400 0000
0290 0004
3400 0010
0290 0008
0290 000C
0290 0010
0290 0014
0290 0018
0290 001C
0290 0020
DRR1
DXR1
McBSP1 data receive register via EDMA bus
McBSP1 data transmit register via configuration bus
McBSP1 data transmit register via EDMA bus
McBSP1 serial port control register
DXR1
SPCR1
RCR1
McBSP1 receive control register
XCR1
McBSP1 transmit control register
SRGR1
MCR1
McBSP1 sample rate generator register
McBSP1 multichannel control register
RCERE01
XCERE01
McBSP1 enhanced receive channel enable register 0
McBSP1 enhanced transmit channel enable register 0
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Table 6-33. McBSP 1 Registers (continued)
HEX ADDRESS RANGE
0290 0024
ACRONYM
PCR1
REGISTER NAME
McBSP1 pin control register
COMMENTS
0290 0028
RCERE11
XCERE11
RCERE21
XCERE21
RCERE31
XCERE31
-
McBSP1 enhanced receive channel enable register 1
McBSP1 enhanced transmit channel enable register 1
McBSP1 enhanced receive channel enable register 2
McBSP1 enhanced transmit channel enable register 2
McBSP1 enhanced receive channel enable register 3
McBSP1 enhanced transmit channel enable register 3
Reserved
0290 002C
0290 0030
0290 0034
0290 0038
0290 003C
0290 0040 - 0293 FFFF
6.17.2 McBSP Electrical Data/Timing
6.17.2.1 Multichannel Buffered Serial Port (McBSP) Timing
Table 6-34. Timing Requirements for McBSP(1) (see Figure 6-36)
-720
-850
-1000
NO.
UNIT
MIN
MAX
2
3
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
6P or 10(2)(3)
0.5tc(CKRX)– 1(4)
ns
ns
Pulse duration, CLKR/X high or CLKR/X low
9
1.3
6
5
6
tsu(FRH-CKRL)
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
3
8
7
0.9
3
8
Hold time, DR valid after CLKR low
3.1
9
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
1.3
6
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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Table 6-35. Switching Characteristics Over Recommended Operating Conditions for McBSP(1)(2)
(see Figure 6-36)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, CLKS high to CLKR/X high for internal CLKR/X
generated from CLKS input(3)
1
td(CKSH-CKRXH)
1.4
10
ns
2
3
4
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
6P or 10(4)(5)(6)
C – 1(7)
–2.1
ns
ns
ns
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
C + 1(7)
td(CKRH-FRV)
3
–1.7
3
9
td(CKXH-FXV)
tdis(CKXH-DXHZ)
td(CKXH-DXV)
Delay time, CLKX high to internal FSX valid
ns
ns
ns
1.7
9
4
–3.9
Disable time, DX high impedance following
last data bit from CLKX high
12
13
2.1
9
–3.9 + D1(8)
2.1 + D1(8)
–2.3 + D1(9)
4 + D2(8)
9 + D2(8)
5.6 + D2(9)
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
14
td(FXH-DXV)
ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
1.9 + D1(9)
9 + D2(9)
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
(4) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(5) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(6) Use whichever value is greater.
(7) C = H or L
S = sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(8) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(9) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
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CLKS
1
2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
DR
7
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
(A)
13
14
13
(A)
12
DX
Bit 0
Bit(n-1)
(n-2)
(n-3)
A. Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.
B. The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
Figure 6-36. McBSP Timing(B)
Table 6-36. Timing Requirements for FSR When GSYNC = 1 (see Figure 6-37)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
tsu(FRH-CKSH)
th(CKSH-FRH)
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
4
4
ns
ns
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 6-37. FSR Timing When GSYNC = 1
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Table 6-37. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0(1)(2)
(see Figure 6-38)
-720
-850
-1000
NO.
UNIT
MASTER
SLAVE
MIN
MIN
12
4
MAX
MAX
4
5
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 – 18P
5 + 36P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 6-38. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 0(1)(2) (see Figure 6-38)
-720
-850
-1000
NO.
PARAMETER
UNIT
MASTER(3)
MIN
SLAVE
MIN
MAX
T + 3
L + 3
4
MAX
1
2
3
th(CKXL-FXL)
td(FXL-CKXH)
td(CKXH-DXV)
Hold time, FSX low after CLKX low(4)
Delay time, FSX low to CLKX high(5)
Delay time, CLKX high to DX valid
T – 2
ns
ns
ns
L – 2
–2
18P + 2.8
30P + 17
Disable time, DX high impedance following
last data bit from CLKX low
6
tdis(CKXL-DXHZ)
L – 2
L + 3
ns
Disable time, DX high impedance following
last data bit from FSX high
7
8
tdis(FXH-DXHZ)
td(FXL-DXV)
6P + 3
18P + 17
24P + 17
ns
ns
Delay time, FSX low to DX valid
12P + 2
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
8
FSX
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-4)
Figure 6-38. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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Table 6-39. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0(1)(2)
(see Figure 6-39)
-720
-850
-1000
NO.
UNIT
MASTER
SLAVE
MIN
MIN
12
4
MAX
MAX
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 – 18P
5 + 36P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 6-40. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 0(1)(2) (see Figure 6-39)
-720
-850
-1000
NO.
PARAMETER
UNIT
MASTER(3)
MIN
SLAVE
MIN
MAX
L + 3
T + 3
4
MAX
1
2
3
th(CKXL-FXL)
td(FXL-CKXH)
td(CKXL-DXV)
Hold time, FSX low after CLKX low(4)
Delay time, FSX low to CLKX high(5)
Delay time, CLKX low to DX valid
L – 2
ns
ns
ns
T – 2
–2
18P + 2.8
18P + 3
12P + 2
30P + 17
30P + 17
24P + 17
Disable time, DX high impedance following
last data bit from CLKX low
6
7
tdis(CKXL-DXHZ)
td(FXL-DXV)
–2
4
ns
ns
Delay time, FSX low to DX valid
H – 2
H + 4
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
7
FSX
DX
6
3
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-3)
(n-4)
4
5
DR
Bit 0
(n-2)
(n-4)
Figure 6-39. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
130
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Table 6-41. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1(1)(2)
(see Figure 6-40)
-720
-850
-1000
NO.
UNIT
MASTER
SLAVE
MIN
MIN
12
4
MAX
MAX
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 – 18P
5 + 36P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 6-42. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 1(1)(2) (see Figure 6-40)
-720
-850
-1000
NO.
PARAMETER
UNIT
MASTER(3)
MIN
SLAVE
MIN
MAX
T + 3
H + 3
4
MAX
1
2
3
th(CKXH-FXL)
td(FXL-CKXL)
td(CKXL-DXV)
Hold time, FSX low after CLKX high(4)
Delay time, FSX low to CLKX low(5)
Delay time, CLKX low to DX valid
T – 2
ns
ns
ns
H – 2
–2
18P + 2.8
30P + 17
Disable time, DX high impedance following
last data bit from CLKX high
6
tdis(CKXH-DXHZ)
H – 2
H + 3
ns
Disable time, DX high impedance following
last data bit from FSX high
7
8
tdis(FXH-DXHZ)
td(FXL-DXV)
6P + 3
18P + 17
24P + 17
ns
ns
Delay time, FSX low to DX valid
12P + 2
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
8
FSX
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 6-40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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Table 6-43. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1(1)(2)
(see Figure 6-41)
-720
-850
-1000
NO.
UNIT
MASTER
SLAVE
MIN
MIN
12
4
MAX
MAX
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 – 18P
5 + 36P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 6-44. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 1(1)(2) (see Figure 6-41)
-720
-850
-1000
NO.
PARAMETER
UNIT
MASTER(3)
MIN
SLAVE
MIN
MAX
H + 3
T + 1
4
MAX
1
2
3
th(CKXH-FXL)
td(FXL-CKXL)
td(CKXH-DXV)
Hold time, FSX low after CLKX high(4)
Delay time, FSX low to CLKX low(5)
Delay time, CLKX high to DX valid
H – 2
T – 2
ns
ns
ns
–2
18P + 2.8
18P + 3
12P + 2
30P + 17
30P + 17
24P + 17
Disable time, DX high impedance following
last data bit from CLKX high
6
7
tdis(CKXH-DXHZ)
td(FXL-DXV)
–2
4
ns
ns
Delay time, FSX low to DX valid
L – 2
L + 4
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
FSX
DX
7
6
3
Bit 0
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
DR
(n-2)
(n-3)
(n-4)
Figure 6-41. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
132
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6.18 Ethernet MAC (EMAC)
The Ethernet Media Access Controller (EMAC) module provides an efficient interface between the C6455
DSP core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/second
[Mbps]), and 100BaseTX (100 Mbps), in either half- or full-duplex mode, and 1000BaseT (1000 Mbps) in
full-duplex mode, with hardware flow control and quality-of-service (QOS) support.
The EMAC module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE
802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER.
Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will
intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame
will be detected as an error by the network.
The EMAC control module is the main interface between the device core processor, the MDIO module,
and the EMAC module. The relationship between these three components is shown in Figure 6-42. The
EMAC control module contains the necessary components to allow the EMAC to make efficient use of
device memory, plus it controls device interrupts. The EMAC control module incorporates 8K-bytes of
internal RAM to hold EMAC buffer descriptors. The relationship between these three components is
shown in Figure 6-42.
Interrupt
controller
DMA memory
transfer controller
Configuration bus
Peripheral bus
EMAC control module
MDIO module
EMAC/MDIO
interrupt
EMAC module
MDIO bus
Ethernet Bus
Figure 6-42. EMAC, MDIO, and EMAC Control Modules
For more detailed information on the EMAC/MDIO, see the TBD User Guide (Literature Number
SPRUTBD).
6.18.1 EMAC Device-Specific Information
Interface Modes
The EMAC module on the TMS320C6455 supports four interface modes: Media Independent Interface
(MII), Reduced Media Independent Interface (RMII), Gigabit Media Independent Interface (GMII), and
Reduced Gigabit Media Independent Interface (RGMII). The MII and GMII interface modes are defined in
the IEEE 802.3-2002 standard.
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The RGMII mode of the EMAC conforms to the Reduced Gigabit Media Independent Interface (RGMII)
Specification (version 2.0). The RGMII mode implements the same functionality as the GMII mode, but
with a reduced number of pins. Data and control information is transmitted and received using both edges
of the transmit and receive clocks (TXC and RXC).
Note: The EMAC internally delays the transmit clock (TXC) with respect to the transmit data and control
pins. Therefore, the EMAC conforms to the RGMII-ID operation of the RGMII specification. However, the
EMAC does not delay the receive clock (RXC); this signal must be delayed with respect to the receive
data and control pins outside of the DSP.
The RMII mode of the EMAC conforms to the RMII Specification (revision 1.2), as written by the RMII
Consortium. As the name implies, the Reduced Media Independent Interface (RMII) mode is a reduced
pin count version of the MII mode.
Interface Mode Select
The EMAC uses the same pins for the MII, GMII, and RMII modes. Standalone pins are included for the
RGMII mode due to specific voltage requirements. Only one mode can be used at a time. The mode used
is selected at device reset based on the MACSEL[1:0] configuration pins (for more detailed information,
see the Device Configurations section of this document). Table 6-45 shows which multiplexed pins are
used in the MII, GMII, and RMII modes on the EMAC. For a detailed description of these pin functions,
see the Terminal Functions Table.
134
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Table 6-45. EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes)
BALL NUMBER
DEVICE PIN NAME
URDATA0/MRXD0/RMRXD0
URDATA1/MRXD1/RMRXD1
URDATA2/MRXD2
MII
MRXD0
RMII
RMRXD0
RMRXD1
GMII
MRXD0
J2
H3
J1
MRXD1
MRXD2
MRXD3
MRXD1
MRXD2
MRXD3
MRXD4
MRXD5
MRXD6
MRXD7
J3
URDATA3/MRXD3
L1
L2
H2
M2
URDATA4/MRXD4
URDATA5/MRXD5
URDATA6/MRXD6
URDATA7/MRXD7
M1
L4
UXDATA0/MTXD0/RMTXD0
UXDATA1/MTXD1/RMTXD1
UXDATA2/MTXD2
MTXD0
MTXD1
MTXD2
MTXD3
RMTXD0
RMTXD1
MTXD0
MTXD1
MTXD2
MTXD3
MTXD4
MTXD5
MTXD6
MTXD7
M4
K4
L3
UXDATA3/MTXD3
UXDATA4/MTXD4
L5
UXDATA5/MTXD5
M3
N5
UXDATA6/MTXD6
UXDATA7/MTXD7
H4
H5
J5
URSOC/MRXER/RMRXER
URENB/MRXDV
MRXER
MRXDV
MTXEN
MCRS
RMRXER
MRXER
MRXDV
MTXEN
MCRS
UXENB/MTXEN/RMTXEN
URCLAV/MCRS/RMCRSDV
UXSOC/MCOL
RMTXEN
J4
RMCRSDV
K3
MCOL
MCOL
K5
H1
N4
UXCLAV/GMTCLK
URCLK/MRCLK
GMTCLK
MRCLK
MTCLK
MRCLK
MTCLK
UXCLK/MTCLK/REFCLK
RMREFCLK
N3
M5
UXADDR3_GMDIO
MDIO
MDIO
MDIO
UXADDR4_GMDCLK
MDCLK
MDCLK
MDCLK
The on-chip PLL2 and PLL2 Controller generate all the clocks to the EMAC module. When enabled, the
input clock to the PLL2 Controller (CLKIN2) must have a 25 MHz frequency. For more information, see the
PLL2 and PLL2 Controller section of this document.
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6.18.2 EMAC Peripheral Register Description(s)
Table 6-46. Ethernet MAC (EMAC) Control Registers
HEX ADDRESS RANGE
02C8 0000
ACRONYM
TXIDVER
REGISTER NAME
Transmit Identification and Version Register
Transmit Control Register
02C8 0004
TXCONTROL
02C8 0008
TXTEARDOWN
-
Transmit Teardown Register
Reserved
02C8 000F
02C8 0010
RXIDVER
Receive Identification and Version Register
Receive Control Register
02C8 0014
RXCONTROL
02C8 0018
RXTEARDOWN
-
Receive Teardown Register
02C8 001C
Reserved
02C8 0020 - 02C8 007C
02C8 0180
-
Reserved
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
-
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
MAC Input Vector Register
02C8 0184
02C8 0188
02C8 018C
02C8 0190
02C8 0194 - 02C8 019C
02C8 01A0
Reserved
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
-
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
Reserved
01C8 01A4
01C8 01A8
01C8 01AC
01C8 01B0
01C8 01B4
01C8 01B8
01C8 01BC
02C8 00C0 - 02C8 00FC
02C8 0100
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
Receive Unicast Enable Set Register
02C8 0104
02C8 0108
Receive Unicast Clear Register
02C8 010C
Receive Maximum Length Register
02C8 0110
RXBUFFEROFFSET
RXFILTERLOWTHRESH
-
Receive Buffer Offset Register
02C8 0114
Receive Filter Low Priority Frame Threshold Register
Reserved
02C8 0118 - 02C8 011C
02C8 0120
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
Receive Channel 0 Flow Control Threshold Register
Receive Channel 1 Flow Control Threshold Register
Receive Channel 2 Flow Control Threshold Register
Receive Channel 3 Flow Control Threshold Register
Receive Channel 4 Flow Control Threshold Register
Receive Channel 5 Flow Control Threshold Register
Receive Channel 6 Flow Control Threshold Register
Receive Channel 7 Flow Control Threshold Register
Receive Channel 0 Free Buffer Count Register
Receive Channel 1 Free Buffer Count Register
Receive Channel 2 Free Buffer Count Register
Receive Channel 3 Free Buffer Count Register
02C8 0124
02C8 0128
02C8 012C
02C8 0130
02C8 0134
02C8 0138
02C8 013C
02C8 0140
02C8 0144
02C8 0148
02C8 014C
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Table 6-46. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
02C8 0150
ACRONYM
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFOCONTROL
MACCONFIG
SOFTRESET
-
REGISTER NAME
Receive Channel 4 Free Buffer Count Register
Receive Channel 5 Free Buffer Count Register
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
02C8 0154
02C8 0158
02C8 015C
02C8 0160
02C8 0164
MAC Status Register
02C8 0168
Emulation Control Register
02C8 016C
FIFO Control Register (Transmit and Receive)
MAC Configuration Register
02C8 0170
02C8 0174
Soft Reset Register
02C8 0178 - 02C8 01CC
02C8 01D0
Reserved
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MACHASH2
BOFFTEST
TPACETEST
RXPAUSE
TXPAUSE
-
MAC Source Address Low Bytes Register (Lower 32-bits)
MAC Source Address High Bytes Register (Upper 32-bits)
MAC Hash Address Register 1
02C8 01D4
02C8 01D8
02C8 01DC
MAC Hash Address Register 2
02C8 01E0
Back Off Test Register
02C8 01E4
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
02C8 01E8
02C8 01EC
Transmit Pause Timer Register
02C8 01F0 - 02C8 01FC
02C8 0200 - 02C8 02FC
02C8 0300 - 02C8 03FC
02C8 0400 - 02C8 04FC
02C8 0500
Reserved
(see Table 6-47)
-
EMAC Statistics Registers
Reserved
-
Reserved
MACADDRLO
MACADDRHI
MACINDEX
-
MAC Address Low Bytes Register
02C8 0504
MAC Address High Bytes Register
02C8 0508
MAC Index Register
02C8 050C - 02C8 05FC
02C8 0600
Reserved
TX0HDP
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive Channel 7 DMA Head Descriptor Pointer Register
02C8 0604
TX1HDP
02C8 0608
TX2HDP
02C8 060C
TX3HDP
02C8 0610
TX4HDP
02C8 0614
TX5HDP
02C8 0618
TX6HDP
02C8 061C
TX7HDP
02C8 0620
RX0HDP
02C8 0624
RX1HDP
02C8 0628
RX2HDP
02C8 062C
RX3HDP
02C8 0630
RX4HDP
02C8 0634
RX5HDP
02C8 0638
RX6HDP
02C8 063C
RX7HDP
Transmit Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
02C8 0640
02C8 0644
TX0CP
TX1CP
Transmit Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
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Table 6-46. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Transmit Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
02C8 0648
TX2CP
Transmit Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
02C8 064C
02C8 0650
02C8 0654
02C8 0658
02C8 065C
02C8 0660
02C8 0664
02C8 0668
02C8 066C
02C8 0670
02C8 0674
02C8 0678
TX3CP
TX4CP
TX5CP
TX6CP
TX7CP
RX0CP
RX1CP
RX2CP
RX3CP
RX4CP
RX5CP
RX6CP
Transmit Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
02C8 067C
RX7CP
-
02C8 0680 - 02C8 06FC
Reserved
Reserved
was State RAM Test Access Registers
Processor Read and Write Access to Head Descriptor Pointers and
Interrupt Acknowledge Registers
02C8 0700 - 02C8 077C
02C8 0780 - 02C8 0FFF
-
-
Reserved
Table 6-47. EMAC Statistics Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
02C8 0200
RXGOODFRAMES
Good Receive Frames Register
Broadcast Receive Frames Register
(Total number of good broadcast frames received)
02C8 0204
RXBCASTFRAMES
Multicast Receive Frames Register
(Total number of good multicast frames received)
02C8 0208
02C8 020C
02C8 0210
RXMCASTFRAMES
RXPAUSEFRAMES
RXCRCERRORS
Pause Receive Frames Register
Receive CRC Errors Register (Total number of frames received with
CRC errors)
Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors)
02C8 0214
02C8 0218
02C8 021C
RXALIGNCODEERRORS
RXOVERSIZED
Receive Oversized Frames Register
(Total number of oversized frames received)
Receive Jabber Frames Register
(Total number of jabber frames received)
RXJABBER
138
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Table 6-47. EMAC Statistics Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Receive Undersized Frames Register
(Total number of undersized frames received)
02C8 0220
RXUNDERSIZED
02C8 0224
02C8 0228
02C8 022C
RXFRAGMENTS
RXFILTERED
Receive Frame Fragments Register
Filtered Receive Frames Register
Received QOS Filtered Frames Register
RXQOSFILTERED
Receive Octet Frames Register
(Total number of received bytes in good frames)
02C8 0230
02C8 0234
RXOCTETS
Good Transmit Frames Register
(Total number of good frames transmitted)
TXGOODFRAMES
02C8 0238
02C8 023C
02C8 0240
02C8 0244
02C8 0248
02C8 024C
02C8 0250
02C8 0254
02C8 0258
02C8 025C
02C8 0260
02C8 0264
02C8 0268
02C8 026C
02C8 0270
02C8 0274
02C8 0278
02C8 027C
02C8 0280
02C8 0284
02C8 0288
TXBCASTFRAMES
TXMCASTFRAMES
TXPAUSEFRAMES
TXDEFERRED
Broadcast Transmit Frames Register
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
TXCOLLISION
Transmit Collision Frames Register
TXSINGLECOLL
TXMULTICOLL
TXEXCESSIVECOLL
TXLATECOLL
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
TXUNDERRUN
TXCARRIERSENSE
TXOCTETS
Transmit Underrun Error Register
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
FRAME64
Transmit and Receive 64 Octet Frames Register
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to 1518 Octet Frames Register
Network Octet Frames Register
FRAME65T127
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
RXSOFOVERRUNS
RXMOFOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame Overruns
Register
02C8 028C
RXDMAOVERRUNS
-
02C8 0290 - 02C8 02FC
Reserved
Table 6-48. EMAC Wrapper
HEX ADDRESS RANGE
02C8 1000 - 02C8 17FF
TBD - TBD
ACRONYM
REGISTER NAME
EMAC Control Module Descriptor Memory
Reserved
-
Table 6-49. EMAC CPPI RAM
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
02C8 2000 - 02C8 3FFF
-
EMAC CPPI RAM
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6.18.3 EMAC Electrical Data/Timing (MII, GMII, RMII, and RGMII)
6.18.3.1 EMAC MII and GMII Electrical Data/Timing
Table 6-50. Timing Requirements for MRCLK - MII and GMII Operation (see Figure 6-43)
-720
-850
-1000
NO.
UNIT
1000 Mbps
(GMII Only)
100 Mbps
10 Mbps
MIN
8
MAX
MIN
40
MAX
MIN
400
140
140
MAX
1
2
3
4
tc(MRCLK)
tw(MRCLKH)
tw(MRCLKL)
tt(MRCLK)
Cycle time, MRCLK
ns
ns
ns
ns
Pulse duration, MRCLK high
Pulse duration, MRCLK low
Transition time, MRCLK
2.8
2.8
14
14
1
3
3
4
1
4
2
3
MRCLK
Figure 6-43. MRCLK Timing (EMAC – Receive) [MII and GMII Operation]
Table 6-51. Timing Requirements for MTCLK - MII and GMII Operation (see Figure 6-44)
-720
-850
-1000
NO.
UNIT
100 Mbps
10 Mbps
MIN
MIN
40
MAX
MAX
1
2
3
4
tc(MTCLK)
tw(MTCLKH)
tw(MTCLKL)
tt(MTCLK)
Cycle time, MTCLK
400
ns
ns
ns
ns
Pulse duration, MTCLK high
Pulse duration, MTCLK low
Transition time, MTCLK
14
140
14
140
3
3
4
1
4
2
3
MTCLK
Figure 6-44. MTCLK Timing (EMAC – Transmit) [MII and GMII Operation]
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Table 6-52. Timing Requirements for GMTCLK - GMII Operation (see Figure 6-45)
-720
-850
-1000
NO.
UNIT
1000 Mbps
MIN
8
MAX
1
2
3
4
tc(GMTCLK)
tw(GMTCLKH)
tw(GMTCLKL)
tt(GMTCLK)
Cycle time, GMTCLK
ns
ns
ns
ns
Pulse duration, GMTCLK high
Pulse duration, GMTCLK low
Transition time, GMTCLK
2.8
2.8
1
4
1
4
2
3
GMTCLK
Figure 6-45. GMTCLK Timing (EMAC – Transmit) [GMII Operation]
Table 6-53. Timing Requirements for EMAC MII and GMII Receive 10/100/1000 Mbit/s(1) (see Figure 6-46)
-720
-850
-1000
NO.
UNIT
1000 Mbps
MIN
100/10 Mbps
MIN
MAX
MAX
Setup time, receive selected signals valid before
MRCLK high
1
2
tsu(MRXD-MRCLKH)
th(MRCLKH-MRXD)
2
0
8
8
ns
ns
Hold time, receive selected signals valid after
MRCLK high
(1) For MII, Receive selected signals include: MRXD[3:0], MRXDV, and MRXER. For GMII, Receive selected signals include: MRXD[7:0],
MRXDV, and MRXER.
1
2
MRCLK (Input)
MRXD7−MRXD4(GMII only),
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Figure 6-46. EMAC Receive Interface Timing [MII and GMII Operation]
Table 6-54. Switching Characteristics Over Recommended Operating Conditions for EMAC MII and GMII
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Table 6-54. Switching Characteristics Over Recommended Operating Conditions for EMAC MII and GMII
Transmit 10/100 Mbit/s (see Figure 6-47) (continued)
Transmit 10/100 Mbit/s(1) (see Figure 6-47)
-720
-850
-1000
NO.
PARAMETER
UNIT
100/10 Mbps
MIN
MAX
1
td(MTCLKH-MTXD)
Delay time, MTCLK high to transmit selected signals valid
5
25
ns
(1) For MII, Transmit selected signals include: MTXD[3:0] and MTXEN. For GMII, Transmit selected signals include: GMTXD[7:0] and
MTXEN.
1
MTCLK (Input)
MTXD7−MTXD4(GMII only),
MTXD3−MTXD0,
MTXEN (Outputs)
Figure 6-47. EMAC Transmit Interface Timing [MII and GMII Operation]
Table 6-55. Switching Characteristics Over Recommended Operating Conditions for EMAC GMII Transmit
1000 Mbit/s(1) (see Figure 6-48)
-720
-850
-1000
NO.
PARAMETER
UNIT
1000 Mbps
MIN
MAX
1
td(GMTCLKH-MTXD) Delay time, GMTCLK high to transmit selected signals valid
0.5
5
ns
(1) For GMII, Transmit selected signals include: GMTXD[7:0] and MTXEN.
1
GMTCLK (Input)
MTXD7−MTXD0,
MTXEN (Outputs)
Figure 6-48. EMAC Transmit Interface Timing [GMII Operation]
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6.18.3.2 EMAC RMII Electrical Data/Timing
An extra clock signal, RMREFCLK, running at 50 MHz is included as a convenience to the user. Note that
this reference clock is not a free-running clock. This should only be used by an external device if it does
not expect a valid clock during device reset.
Table 6-56. Switching Characteristics Over Recommended Operating Conditions for EMAC RMREFCLK -
RMII Operation (see Figure 6-49)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
20+TBD
TBD
1
2
3
4
tc(RFCLK)
tw(RFCLKH)
tw(RFCLKL)
tt(RFCLK)
Cycle time, RMREFCLK
20-TBD
TBD
ns
ns
ns
ns
Pulse duration, RMREFCLK high
Pulse duration, RMREFCLK low
Transition time, RMREFCLK
TBD
TBD
TBD
1
4
2
RMREFCLK
3
4
Figure 6-49. RMREFCLK Timing
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6.18.3.3 EMAC RGMII Electrical Data/Timing
An extra clock signal, RGREFCLK, running at 125 MHz is included as a convenience to the user. Note
that this reference clock is not a free-running clock. This should only be used by an external device if it
does not expect a valid clock during device reset.
Table 6-57. Switching Characteristics Over Recommended Operating Conditions for EMAC RGREFCLK -
RGMII Operation (see Figure 6-50)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
8+TBD
TBD
1
2
3
4
tc(RGFCLK)
tw(RGFCLKH)
tw(RGFCLKL)
tt(RGFCLK)
Cycle time, RGREFCLK
8-TBD
TBD
ns
ns
ns
ns
Pulse duration, RGREFCLK high
Pulse duration, RGREFCLK low
Transition time, RGREFCLK
TBD
TBD
TBD
1
4
2
RGREFCLK
3
4
Figure 6-50. RGREFCLK Timing
Table 6-58. Timing Requirements for RXC - RGMII Operation (see Figure 6-51)
-720
-850
-1000
NO.
UNIT
1000 Mbps
MIN MAX
100 Mbps
MIN MAX
10 Mbps
MIN
MAX
440
1
2
tc(RXC)
Cycle time, RXC
7.2
8.8
36
44
360
ns
ns
Pulse duration, RXC
high
tw(RXCH)
0.45*tc(RXC) 0.55*tc(RXC) 0.40*tc(RXC) 0.60*tc(RXC) 0.40*tc(RXC) 0.60*tc(RXC)
0.45*tc(RXC) 0.55*tc(RXC) 0.40*tc(RXC) 0.60*tc(RXC) 0.40*tc(RXC) 0.60*tc(RXC)
Pulse duration, RXC
low
3
4
tw(RXCL)
tt(RXC)
ns
ns
Transition time, RXC
0.75
0.75
0.75
Table 6-59. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps(1) (see Figure 6-51)
-720
-850
-1000
NO.
UNIT
MIN
MAX
5
6
tsu(RXD-RXCH)
th(RXCH-RXD)
Setup time, receive selected signals valid before RXC (at DSP) high/low
Hold time, receive selected signals valid after RXC (at DSP) high/low
1.0
1.0
ns
ns
(1) For RGMII, receive selected signals include: RXD[3:0] and RXCTL.
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1
4
2
4
3
RXC
(B)
(at DSP)
5
1st Half-byte
6
2nd Half-byte
(A)
(A)
RXD[3:0]
RXD[3:0]
RXDV
RXD[7:4]
RXERR
RXCTL
A. Data and control information is received using both edges of the clocks. RXD[3:0] carries data bits 3-0 on the rising
edge of RXC and data bits 7-4 on the falling edge of RXC. Similarly, RXCTL carries RXDV on rising edge of RXC and
RXERR on falling edge
B. RXC must be externally delayed relative to the data and control pins.
Figure 6-51. EMAC Receive Interface Timing [RGMII Operation](A)(B)
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Table 6-60. Timing Requirements for TXC - RGMII Operation for 10/100/1000 Mbit/s (see Figure 6-52)
-720
-850
-1000
NO.
UNIT
1000 Mbps
MIN MAX
100 Mbps
MIN MAX
10 Mbps
MIN
MAX
440
1
2
tc(TXC)
Cycle time, TXC
7.2
8.8
36
44
360
ns
ns
Pulse duration, TXC
high
tw(TXCH)
0.45*tc(TXC) 0.55*tc(TXC) 0.40*tc(TXC) 0.60*tc(TXC) 0.40*tc(TXC) 0.60*tc(TXC)
3
4
tw(TXCL)
tt(TXC)
Pulse duration, TXC low 0.45*tc(TXC) 0.55*tc(TXC) 0.40*tc(TXC) 0.60*tc(TXC) 0.40*tc(TXC) 0.60*tc(TXC)
Transition time, TXC 0.75 0.75 0.75
ns
ns
Table 6-61. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII
Transmit (1)(see Figure 6-52)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
5
6
tsu(TXD-TXCH)
th(TXCH-TXD)
Setup time, transmit selected signals valid before TXC (at DSP) high/low
Hold time, transmit selected signals valid after TXC (at DSP) high/low
1.2
1.2
ns
(1) For RGMII, transmit selected signals include: TXD[3:0] and TXCTL.
TXC at DSP pins
1
Internal TXC
4
4
2
3
(B)
TXC (at DSP)
1
5
(A)
1st Half-byte
2nd Half-byte
TXERR
TXD[3:0]
TXCTL
6
2
(A)
TXEN
A. Data and control information is transmitted using both edges of the clocks. TXD[3:0] carries data bits 3-0 on the rising
edge of TXC and data bits 7-4 on the falling edge of TXC. Similarly, TX_CTL carries TXEN on rising edge of TXC and
TXERR of falling edge.
B. TXC is delayed internally before being driven to the TXC pin.
Figure 6-52. EMAC Transmit Interface Timing [RGMII Operation](A)(B)
6.18.4 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus.
Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY
attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC
module for correct operation. The module is designed to allow almost transparent operation of the MDIO
interface, with very little maintenance from the core processor.
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The EMAC control module is the main interface between the device core processor, the MDIO module,
and the EMAC module. The relationship between these three components is shown in Figure 6-42.
The MDIO uses the same pins for the MII, GMII, and RMII modes. Standalone pins are included for the
RGMII mode due to specific voltage requirements. Only one mode can be used at a time. The mode used
is selected at device reset based on the MACSEL[1:0] configuration pins (for more detailed information,
see the Device Configurations section of this document). Table 6-45 above shows which multiplexed pin
are used in the MII, GMII, and RMII modes on the MDIO.
For more detailed information on the EMAC/MDIO, see the TBD User Guide (Literature Number
SPRUTBD).
6.18.4.1 MDIO Device-Specific Information
Clocking Information
The on-chip PLL2 and PLL2 Controller generate all the clocks to the MDIO module. When enabled, the
input clock to the PLL2 Controller (CLKIN2) must have a 25 MHz frequency. For more information, see the
PLL2 and PLL2 Controller section of this document.
6.18.4.2 MDIO Peripheral Register Description(s)
Table 6-66. MDIO Registers
HEX ADDRESS RANGE
02C8 1800
ACRONYM
VERSION
REGISTER NAME
MDIO Version Register
MDIO Control Register
02C8 1804
CONTROL
02C8 1808
ALIVE
MDIO PHY Alive Status Register
02C8 180C
LINK
MDIO PHY Link Status Register
02C8 1810
LINKINTRAW
LINKINTMASKED
-
MDIO Link Status Change Interrupt (Unmasked) Register
MDIO Link Status Change Interrupt (Masked) Register
Reserved
02C8 1814
02C8 1818 - 02C8 181C
02C8 1820
USERINTRAW
USERINTMASKED
USERINTMASKSET
USERINTMASKCLEAR
-
MDIO User Command Complete Interrupt (Unmasked) Register
MDIO User Command Complete Interrupt (Masked) Register
MDIO User Command Complete Interrupt Mask Set Register
MDIO User Command Complete Interrupt Mask Clear Register
Reserved
02C8 1824
02C8 1828
02C8 182C
02C8 1830 - 02C8 187C
02C8 1880
USERACCESS0
USERPHYSEL0
USERACCESS1
USERPHYSEL1
-
MDIO User Access Register 0
02C8 1884
MDIO User PHY Select Register 0
02C8 1888
MDIO User Access Register 1
02C8 188C
MDIO User PHY Select Register 1
02C8 1890 - 02C8 1FFF
Reserved
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6.18.4.3 MDIO Electrical Data/Timing
Table 6-67. Timing Requirements for MDIO Input (R)(G)MII (see Figure 6-55)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2a
2b
3
tc(MDCLK)
Cycle time, MDCLK
400
180
180
ns
ns
ns
ns
ns
ns
tw(MDCLK)
Pulse duration, MDCLK high
tw(MDCLK)
Pulse duration, MDCLK low
tt(MDCLK)
Transition time, MDCLK
5
4
tsu(MDIO-MDCLKH)
th(MDCLKH-MDIO)
Setup time, MDIO data input valid before MDCLK high
Hold time, MDIO data input valid after MDCLK high
10
10
5
1
MDCLK
3
4
MDIO
(input)
Figure 6-55. MDIO Input Timing
Table 6-68. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-56)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
7
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid
100
ns
1
MDCLK
7
MDIO
(output)
Figure 6-56. MDIO Output Timing
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6.19 Timers
The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send
synchronization events to the EDMA.
6.19.1 Timers Device-Specific Information
The C6455 device has two general-purpose timers, Timer0 and Timer1, each of which can be configured
as a general-purpose timer or a watchdog timer. When configured as a general-purpose timer, each timer
can be programmed as a 64-bit timer or as two separate 32-bit timers.
Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx
and TOUTLx are connected to the low counter. The high counter does not have any external device pins.
6.19.2 Timers Peripheral Register Description(s)
Table 6-69. Timer 0 Registers
HEX ADDRESS RANGE
0294 0000
ACRONYM
REGISTER NAME
COMMENTS
-
Reserved
0294 0004
EMUMGT_CLKSPD
Timer 0 emulation management/clock speed register
Reserved
0294 0008
-
-
0294 000C
Reserved
0294 0010
TIMLO
TIMHI
PRDLO
PRDHI
TCR
TGCR
WDTCR
-
Timer 0 lower counter register
Timer 0 higher counter register
Timer 0 lower period register
Timer 0 higher period register
Timer 0 control register
Timer 0 global control register
Timer 0 watchdog timer control register
Reserved
0294 0014
0294 0018
0294 001C
0294 0020
0294 0024
0294 0028
0294 002C
0294 0030
-
Reserved
0294 0034 - 0297 FFFF
-
Reserved
Table 6-70. Timer 1 Registers
HEX ADDRESS RANGE
0298 0000
ACRONYM
REGISTER NAME
Reserved
COMMENTS
-
0298 0004
EMUMGT_CLKSPD
Timer 1 emulation management/clock speed register
Reserved
0298 0008
-
0298 000C
0298 0010
-
Reserved
TIMLO
TIMHI
PRDLO
PRDHI
TCR
Timer 1 lower counter register
Timer 1 higher counter register
Timer 1 lower period register
Timer 1 higher period register
Timer 1 control register
0298 0014
0298 0018
0298 001C
0298 0020
0298 0024
TGCR
WDTCR
-
Timer 1 global control register
Timer 1 watchdog timer control register
Reserved
0298 0028
0298 002C
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Table 6-70. Timer 1 Registers (continued)
HEX ADDRESS RANGE
0298 0030
ACRONYM
REGISTER NAME
COMMENTS
-
Reserved
Reserved
0298 0034 - 0299 FFFF
-
6.19.3 Timers Electrical Data/Timing
Table 6-71. Timing Requirements for Timer Inputs(1) (see Figure 6-57)
-720
-850
-1000
NO.
UNIT
MIN
MAX
ns
1
2
tw(TINPH)
tw(TINPL)
Pulse duration, TINPLx high
Pulse duration, TINPLx low
12P
12P
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
Table 6-72. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs(1)
(see Figure 6-57)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
3
4
tw(TOUTH)
tw(TOUTL)
Pulse duration, TOUTLx high
Pulse duration, TOUTLx low
12P – 3
12P – 3
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
2
1
TINPLx
4
3
TOUTLx
Figure 6-57. Timer Timing
6.20 Enhanced Viterbi-Decoder Coprocessor (VCP2)
6.20.1 VCP2 Device-Specific Information
The C6455 device has a high-performance embedded coprocessor [Viterbi-Decoder Coprocessor (VCP2)
that significantly speeds up channel-decoding operations on-chip. The VCP2 operating at CPU clock
divided-by-4 can decode over 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels.
The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and
flexible polynomials, while generating hard decisions or soft decisions. Communications between the
VCP2 and the CPU are carried out through the EDMA controller.
The VCP2 supports:
•
•
•
Unlimited frame sizes
Code rates 3/4, 1/2, 1/3, 1/4, and 1/5
Constraint lengths 5, 6, 7, 8, and 9
150
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•
•
•
•
•
•
•
Programmable encoder polynomials
Programmable reliability and convergence lengths
Hard and soft decoded decisions
Tail and convergent modes
Yamamoto logic
Tail biting logic
Various input and output FIFO lengths
For more detailed information on the VCP2, see the TMS320C64x DSP Viterbi-Decoder Coprocessor 2
(VCP2) Reference Guide (literature number SPRUTBD). And TBD
6.20.2 VCP2 Peripheral Register Description(s)
Table 6-73. VCP2 Registers
EDMA BUS
HEX ADDRESS RANGE
CONFIGURATION BUS
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
VCP2 input configuration register 0
5800 0000
5800 0004
5800 0008
5800 000C
5800 0010
5800 0014
-
-
-
-
-
-
VCPIC0
VCPIC1
VCPIC2
VCPIC3
VCPIC4
VCPIC5
-
VCP2 input configuration register 1
VCP2 input configuration register 2
VCP2 input configuration register 3
VCP2 input configuration register 4
VCP2 input configuration register 5
Reserved
5800 0048
5800 004C
-
-
VCPOUT0
VCPOUT1
-
VCP2 output register 0
VCP2 output register 1
Reserved
5800 00A0
N/A
VCPWBM
-
VCP2 branch metrics write register
Reserved
5800 00C0
N/A
N/A
VCPRDECS VCP2 decisions read register
02B8 0000
02B8 0018
02B8 0020
02B8 0040
02B8 0044
02B8 0050
VCPPID
VCPEXE
VCPEND
VCP2 peripheral identification register [Value: 0xTBD]
N/A
VCP2 execution register
VCP2 endian register
N/A
N/A
VCPSTAT0 VCP2 status register 0
VCPSTAT1 VCP2 status register 1
N/A
N/A
VCPERR
VCP2 error register
Reserved
-
N/A
N/A
02B8 0060
VCPECTL
-
VCP2 emulation control register
Reserved
02B8 0064 - 02B9 FFFF
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6.21 Enhanced Turbo Decoder Coprocessor (TCP2)
6.21.1 TCP2 Device-Specific Information
The C6455 device has a high-performance embedded coprocessor [Turbo-Decoder Coprocessor (TCP2)
that significantly speeds up channel-decoding operations on-chip. The TCP2 operating at CPU clock
divided-by-2 can decode up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels (assuming 6
iterations). The TCP2 implements the max*log-map algorithm and is designed to support all polynomials
and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable
frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping
criteria are also programmable. Communications between the TCP2 and the CPU are carried out through
the EDMA controller.
The TCP2 supports:
•
•
•
•
•
•
•
•
•
•
•
Parallel concatenated convolutional turbo decoding using the MAP algorithm
All turbo code rates greater than or equal to 1/5
3GPP and CDMA2000 turbo encoder trellis
3GPP and CDMA2000 block sizes in standalone mode
Larger block sizes in shared processing mode
Both max log MAP and log MAP decoding
Sliding windows algorithm with variable reliability and prolog lengths
The prolog reduction algorithm
Execution of a minimum and maximum number of iterations
The SNR stopping criteria algorithm
The CRC stopping criteria algorithm
For more detailed information on the TCP2, see the TMS320C64x DSP Turbo-Decoder Coprocessor
(TCP) Reference Guide (literature number SPRU534). And TBD
6.21.2 TCP2 Peripheral Register Description(s)
Table 6-74. TCP2 Registers
EDMA BUS
HEX ADDRESS RANGE
CONFIGURATION BUS
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
TCP2 input configuration register 0
5000 0000
5000 0004
5000 0008
5000 000C
5000 0010
5000 0014
5000 0018
5000 001C
5000 0020
5000 0024
5000 0028
5000 002C
5000 0030
5000 0034
5000 0038
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TCPIC0
TCPIC1
TCPIC2
TCPIC3
TCPIC4
TCPIC5
TCPIC6
TCPIC7
TCPIC8
TCPIC9
TCPIC10
TCPIC11
TCPIC12
TCPIC13
TCPIC14
TCP2 input configuration register 1
TCP2 input configuration register 2
TCP2 input configuration register 3
TCP2 input configuration register 4
TCP2 input configuration register 5
TCP2 input configuration register 6
TCP2 input configuration register 7
TCP2 input configuration register 8
TCP2 input configuration register 9
TCP2 input configuration register 10
TCP2 input configuration register 11
TCP2 input configuration register 12
TCP2 input configuration register 13
TCP2 input configuration register 14
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Table 6-74. TCP2 Registers (continued)
EDMA BUS
HEX ADDRESS RANGE
CONFIGURATION BUS
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
5000 003C
-
TCPIC15
TCP2 input configuration register 15
5000 0040
-
TCPOUTP0 TCP2 output parameters register 0
TCPOUTP1 TCP2 output parameters register 1
TCPOUTP2 TCP2 output parameters register 2
5000 0044
-
5000 0048
-
N/A
5001 0000
TCPSP
TCPEXT0
TCPAP
TCP2 systematics and parities memory
TCP2 extrinsics memory 0
TCP2 apriori memory
5003 0000
N/A
5006 0000
N/A
5008 0000
N/A
TCPINTER TCP2 interleaver memory
500A 0000
N/A
TCPHD
TCPPID
TCPEXE
TCPEND
TCPERR
TCPSTAT
TCPECTL
-
TCP2 hard decisions memory
TCP2 peripheral identification register [Value: 0xTBD]
TCP2 execution register
TCP2 endian register
02BA 0000
02BA 004C
02BA 0050
02BA 0060
02BA 0068
02BA 0070
02BA 005C - 02BB FFFF
N/A
N/A
N/A
N/A
N/A
N/A
TCP2 error register
TCP2 status register
TCP2 emulation control register
Reserved
6.22 Peripheral Component Interconnect (PCI)
The PCI port for the TMS320C6000 supports connection of the DSP to PCI host via the integrated PCI
master/slave bus interface. For the C64x+ devices, like the C6455, the PCI port interfaces to the DSP via
the EDMA internal address generation hardware. This architecture allows for both PCI Master and Slave
transactions, while keeping the EDMA channel resources available for other applications.
For more detailed information on the PCI port peripheral module, see the TBD Reference Guide
(Literature Number SPRUTBD).
6.22.1 PCI Device-Specific Information
On the C6455 device, the PCI interface is multiplexed with the HPI, UTOPIA, or GPIO peripherals.
The PCI is controlled (enabled/disabled) by the PCI_EN pin (Y29) in conjunction with the MCSBP1_EN
(AEA5 pin [U28]). For more detailed information on the peripheral control, see the Device Configurations
section of this data sheet.
By default, the PCI Vendor ID/Device ID register is initialized to 0xB000 after reset.
6.22.2 PCI Peripheral Register Description(s)
Table 6-75. PCI Peripheral Registers
PCI HOST ACCESS
HEX ADDRESS OFFSET
DSP ACCESS
HEX ADDRESS RANGE
PCI HOST ACCESS
REGISTER NAME
DSP ACCESS
REGISTER NAME
ACRONYM
02C0 0000
02C0 0004
02C0 0008
02C0 000C
Reserved
Reserved
Reserved
Reserved
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Table 6-75. PCI Peripheral Registers (continued)
PCI HOST ACCESS
HEX ADDRESS OFFSET
DSP ACCESS
HEX ADDRESS RANGE
PCI HOST ACCESS
REGISTER NAME
DSP ACCESS
REGISTER NAME
ACRONYM
02C0 0010
02C0 0014
02C0 0018
02C0 001C
PCIIF Status Set
PCIIF Status Clear
Reserved
Reserved
PCIIF Host Interrupt Enable
Set
02C0 0020
02C0 0024
PCIIF Host Interrupt Enable
Clear
02C0 0028
02C0 002C
Reserved
Reserved
PCIIF Back End Application
Interrupt Enable Set
02C0 0030
02C0 0034
02C0 0038
PCIIF Back End Application
Interrupt Enable Clear
PCIIF Back End Application
Clock Management
02C0 003C - 02C0 007C
02C0 0080 - 02C0 00FC
Reserved
Reserved
PCIIF Vendor ID/Device ID
Mirror
0x00
0x04
0x08
02C0 0100
02C0 0104
02C0 0108
Vendor ID/Device ID
Command/Status
PCIIF Command/Status
Mirror
PCIIF Class Code/Revision
ID Mirror
Class Code/Revision ID
PCIIF BIST/Header
Type/Latency
Timer/Cacheline Size Mirror
BIST/Header Type/Latency
Timer/Cacheline Size
0x0C
02C0 010C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
02C0 0110
02C0 0114
02C0 0118
02C0 011C
02C0 0120
02C0 0124
02C0 0128
Base Address 0
Base Address 1
Base Address 2
Base Address 3
Base Address 4
Base Address 5
Reserved
PCIIF Base Address 0 Mask
PCIIF Base Address 1 Mask
PCIIF Base Address 2 Mask
PCIIF Base Address 3 Mask
PCIIF Base Address 4 Mask
PCIIF Base Address 5 Mask
Reserved
Subsystem ID/Subsystem
Vendor ID
PCIIF Subsystem Vendor
ID/Subsystem ID Mirror
0x2C
0x30
0x34
0x38
02C0 012C
02C0 0130
02C0 0134
02C0 0138
Reserved
Reserved
PCIIF Capabilities Pointer
Mirror
Capabilities Pointer
Reserved
Reserved
Max Latency/Min
Grant/Interrupt Pin/Interrupt
Line
PCIIF Max Latency/Min
Grant/Interrupt Pin/Interrupt
Line Mirror
0x3C
0x40
02C0 013C
02C0 0140
Power Management
Capabilities
Power Management
Capabilities Mirror
Power Management
Control/Status
Power Management
Control/Status Mirror
0x44
02C0 0144
02C0 0148 - 02C0 015C
02C0 0160
0x48 - 0xFF
Reserved
Reserved
PCIIF Power Management
D0 State Control
PCIIF Power Management
D1 State Control
02C0 0164
154
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Table 6-75. PCI Peripheral Registers (continued)
PCI HOST ACCESS
HEX ADDRESS OFFSET
DSP ACCESS
HEX ADDRESS RANGE
PCI HOST ACCESS
REGISTER NAME
DSP ACCESS
REGISTER NAME
ACRONYM
PCIIF Power Management
D2 State Control
02C0 0168
02C0 016C
PCIIF Power Management
D3 State Control
-
-
-
-
-
-
02C0 0170 - 02C0 017C
02C0 0180
-
-
-
-
-
-
Reserved
PCIIF Slave Control
Reserved
02C0 0184
02C0 0188 - 02C0 019C
02C0 01A0 - 02C0 01AC
02C0 01B0 - 02C0 01BC
Reserved
Reserved
Reserved
Slave Base Address
Translation Register 0
-
-
-
-
-
02C0 01C0
02C0 01C4
02C0 01C8
02C0 01CC
02C0 01D0
-
-
-
-
-
Slave Base Address
Translation Register 1
Slave Base Address
Translation Register 2
Slave Base Address
Translation Register 3
Slave Base Address
Translation Register 4
Slave Base Address
Translation Register 5
-
-
-
02C0 01D4
02C0 01D8 - 02C0 01DC
02C0 01E0
-
-
-
Reserved
PCIIF Base Address
Register 0 Mirror
PCIIF Base Address
Register 1 Mirror
-
-
-
-
02C0 01E4
02C0 01E8
02C0 01EC
02C0 01F0
-
-
-
-
PCIIF Base Address
Register 2 Mirror
PCIIF Base Address
Register 3 Mirror
PCIIF Base Address
Register 4 Mirror
PCIIF Base Address
Register 5 Mirror
-
-
-
02C0 01F4
02C0 01F8 - 02C0 02FC
02C0 0300
-
-
-
Reserved
Master Configuration/IO
Access Data
Master Configuration/IO
Access Address
-
02C0 0304
-
Master Configuration/IO
Access Command
-
-
-
02C0 0308
02C0 030C
02C0 0310
-
-
-
Reserved
Master Configuration
Register
-
-
-
-
-
-
-
02C0 0314
02C0 0318
02C0 031C
02C0 0320
02C0 0324
02C0 0328
02C0 032C
-
-
-
-
-
-
-
ADD_SUBS_0
ADD_SUBS_1
ADD_SUBS_2
ADD_SUBS_3
ADD_SUBS_4
ADD_SUBS_5
ADD_SUBS_6
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Table 6-75. PCI Peripheral Registers (continued)
PCI HOST ACCESS
HEX ADDRESS OFFSET
DSP ACCESS
HEX ADDRESS RANGE
PCI HOST ACCESS
REGISTER NAME
DSP ACCESS
REGISTER NAME
ACRONYM
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
02C0 0330
02C0 0334
02C0 0338
02C0 033C
02C0 0340
02C0 0344
02C0 0348
02C0 034C
02C0 0350
02C0 0354
02C0 0358
02C0 035C
02C0 0360
02C0 0364
02C0 0368
02C0 036C
02C0 0370
02C0 0374
02C0 0378
02C0 037C
02C0 0380
02C0 0384
02C0 0388
02C0 038C
02C0 0390
02C0 0394
02C0 0398
02C0 039C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADD_SUBS_7
ADD_SUBS_8
ADD_SUBS_9
ADD_SUBS_10
ADD_SUBS_11
ADD_SUBS_12
ADD_SUBS_13
ADD_SUBS_14
ADD_SUBS_15
ADD_SUBS_16
ADD_SUBS_17
ADD_SUBS_18
ADD_SUBS_19
ADD_SUBS_20
ADD_SUBS_21
ADD_SUBS_22
ADD_SUBS_23
ADD_SUBS_24
ADD_SUBS_25
ADD_SUBS_26
ADD_SUBS_27
ADD_SUBS_28
ADD_SUBS_29
ADD_SUBS_30
ADD_SUBS_31
vendor device id_prog
cmd_stat_prog
class_code_rev_id_prog
subsys_vendor_id_subsys_id
_prog
-
02C0 03A0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
02C0 03A4
02C0 03A8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max_lat_min_grant_prog
LRESET_REG
02C0 03AC
02C0 03B0
CONFIG_DONE_REG
base_addr_mask_reg0_prog
base_addr_mask_reg1_prog
base_addr_mask_reg2_prog
base_addr_mask_reg3_prog
base_addr_mask_reg4_prog
base_addr_mask_reg5_prog
base_address_reg0_prog
base_address_reg1_prog
base_address_reg2_prog
base_address_reg3_prog
base_address_reg4_prog
base_address_reg5_prog
Reserved
02C0 03B4
02C0 03B8
02C0 03BC
02C0 03C0
02C0 03C4
02C0 03C8
02C0 03CC
02C0 03D0
02C0 03D4
02C0 03D8
02C0 03DC
02C0 03E0 - 02C0 03FC
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6.22.3 PCI Electrical Data/Timing
6.22.3.1 Peripheral Component Interconnect (PCI) Timing
Table 6-76. Timing Requirements for PCLK(1) (see Figure 6-58)
-720
-850
-1000
NO.
UNIT
[33 MHz]
[66 MHz]
MIN
30
11
11
1
MAX
MIN
15
6
MAX
1
2
3
4
tc(PCLK)
Cycle time, PCLK
ns
ns
tw(PCLKH)
tw(PCLKL)
tsr(PCLK)
Pulse duration, PCLK high
Pulse duration, PCLK low
∆v/∆t slew rate, PCLK
6
ns
4
1.5
4
V/ns
(1) For 3.3-V operation, the reference points for the rise and fall transitions are measured at VILP MAXand VIHP MIN.
0.4 DV V MIN
DD
Peak to Peak for
3.3V signaling
1
4
2
PCLK
3
4
Figure 6-58. PCLK Timing
Table 6-77. Timing Requirements for PCI Reset (see Figure 6-59)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
tw(PRST)
Pulse duration, PRST
1
ms
tsu(PCLKA-PRSTH)
Setup time, PCLK active before PRST high
100
µs
PCLK
PRST
1
2
Figure 6-59. PCI Reset (PRST) Timing
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Table 6-78. Timing Requirements for PCI Inputs (see Figure 6-60)
-720
-850
-1000
NO.
UNIT
33 MHz
MIN
66 MHz
MIN
MAX
MAX
4
5
tsu(IV-PCLKH)
th(IV-PCLKH)
Setup time, input valid before PCLK high
Hold time, input valid after PCLK high
7
0
3
0
ns
ns
PCLK
4
5
PCI Input
Inputs Valid
Figure 6-60. PCI Input Timing (33-/66-MHz)
Table 6-79. Switching Characteristics Over Recommended Operating Conditions for PCI Outputs
(see Figure 6-61)
-720
-850
-1000
NO.
PARAMETER
UNIT
33 MHz
MIN
66 MHz
MIN
MAX
MAX
1a
1b
2
td(PCLKH-OV)
td(PCLKH-OIV)
td(PCLKH-OLZ)
td(PCLKH-OHZ)
Delay time, PCLK high to output valid
11
6
ns
ns
ns
ns
Delay time, PCLK high to output invalid
2
2
2
2
Delay time, PCLK high to output low impedance
Delay time, PCLK high to output high impedance
3
28
14
PCLK
1
1
PCI Output
2
3
Figure 6-61. PCI Output Timing (33-/66-MHz)
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6.23 UTOPIA
6.23.1 UTOPIA Device-Specific Information
The Universal Test and Operations PHY Interface for ATM (UTOPIA) peripheral is a 50 MHz, 8-Bit
Slave-only interface. The UTOPIA is more simplistic than the Ethernet MAC, in that the UTOPIA is
serviced directly by the EDMA. The UTOPIA peripheral contains two, two-cell FIFOs, one for transmit and
one for receive, with which to buffer up data sent/received across the pins. There is a transmit and a
receive event to the EDMA to enable servicing.
For more detailed information on the UTOPIA peripheral, see the TMS320C64x DSP Universal Test and
Operations PHY interface for ATM (UTOPIA) Reference Guide (literature number SPRU583).
6.23.2 UTOPIA Peripheral Register Description(s)
Table 6-80. UTOPIA Registers
HEX ADDRESS RANGE
02B4 0000
ACRONYM
REGISTER NAME
UCR
-
UTOPIA control register
Reserved
02B4 0004
02B4 0008
-
Reserved
02B4 000C
UIER
UIPR
CDR
EIER
EIPR
-
UTOPIA interrupt enable register
UTOPIA interrupt pending register
Clock detect register
02B4 0010
02B4 0014
02B4 0018
Error interrupt enable register
Error interrupt pending register
Reserved
02B4 001C
02B4 0020 - 02B4 01FF
02B4 0200 - 02B7 FFFF
-
Reserved
Table 6-81. UTOPIA Data Queues (Receive and Transmit) Registers
HEX ADDRESS RANGE
3C00 0000 - 3CFF FFFF
3D00 0000 - 3DFF FFFF
ACRONYM
URQ
REGISTER NAME
UTOPIA receive (Rx) data queue
UTOPIA transmit (Tx) data queue
UXQ
6.23.3 UTOPIA Electrical Data/Timing
Table 6-82. Timing Requirements for UXCLK(1) (see Figure 6-62)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
tc(UXCK)
Cycle time, UXCLK
20
ns
ns
tw(UXCKH)
Pulse duration, UXCLK high
0.4tc(UXCK)
0.6tc(UXCK)
(1) The reference points for the rise and fall transitions are measured at VIL MAXand VIH MIN.
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Table 6-82. Timing Requirements for UXCLK (see Figure 6-62) (continued)
-720
-850
-1000
NO.
UNIT
MIN
MAX
0.6tc(UXCK)
2
3
4
tw(UXCKL)
tt(UXCK)
Pulse duration, UXCLK low
Transition time, UXCLK
0.4tc(UXCK)
ns
ns
1
4
2
UXCLK
3
4
Figure 6-62. UXCLK Timing
Table 6-83. Timing Requirements for URCLK(1) (see Figure 6-63)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
3
4
tc(URCK)
tw(URCKH)
tw(URCKL)
tt(URCK)
Cycle time, URCLK
20
ns
ns
ns
ns
Pulse duration, URCLK high
Pulse duration, URCLK low
Transition time, URCLK
0.4tc(URCK)
0.6tc(URCK)
0.6tc(URCK)
2
0.4tc(URCK)
(1) The reference points for the rise and fall transitions are measured at VIL MAXand VIH MIN.
1
4
2
URCLK
3
4
Figure 6-63. URCLK Timing
Table 6-84. Timing Requirements for UTOPIA Slave Transmit (see Figure 6-65)
-720
-850
-1000
NO.
UNIT
MIN
MAX
2
3
8
9
tsu(UXAV-UXCH)
Setup time, UXADDR valid before UXCLK high
Hold time, UXADDR valid after UXCLK high
Setup time, UXENB low before UXCLK high
Hold time, UXENB low after UXCLK high
4
1
4
1
ns
ns
ns
ns
th(UXCH-UXAV)
tsu(UXENBL-UXCH)
th(UXCH-UXENBL)
160
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-85. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave
Transmit Cycles (see Figure 6-64)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
12
1
4
td(UXCH-UXDV)
Delay time, UXCLK high to UXDATA valid
3
3
3
9
3
3
ns
ns
ns
ns
ns
ns
td(UXCH-UXCLAV)
td(UXCH-UXCLAVL)
td(UXCH-UXCLAVHZ)
tw(UXCLAVL-UXCLAVHZ)
td(UXCH-UXSV)
Delay time, UXCLK high to UXCLAV driven active value
Delay time, UXCLK high to UXCLAV driven inactive low
Delay time, UXCLK high to UXCLAV going Hi-Z
Pulse duration (low), UXCLAV low to UXCLAV Hi-Z
Delay time, UXCLK high to UXSOC valid
12
5
12
6
18.5
7
10
12
UXCLK
1
3
P45
P46
N
P47
P48
H1
UXDATA[7:0]
UXADDR[4:0]
2
0 x1F
0x1F
N
N
0x1F
N + 1
7
0x1F
6
4
5
N
8
UXCLAV
UXENB
UXSOC
9
10
A. The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and UXSOC signals).
Figure 6-64. UTOPIA Slave Transmit Timing(A)
Table 6-86. Timing Requirements for UTOPIA Slave Receive (see Figure 6-64)
-720
-850
-1000
NO.
UNIT
MIN
4
MAX
1
2
tsu(URDV-URCH)
th(URCH-URDV)
tsu(URAV-URCH)
th(URCH-URAV)
tsu(URENBL-URCH)
th(URCH-URENBL)
tsu(URSH-URCH)
th(URCH-URSH)
Setup time, URDATA valid before URCLK high
Hold time, URADDR valid after URCLK high
Setup time, URADDR valid before URCLK high
Hold time, URADDR valid after URCLK high
Setup time, URENB low before URCLK high
Hold time, URENB low after URCLK high
Setup time, URSOC high before URCLK high
Hold time, URSOC high after URCLK high
ns
ns
ns
ns
ns
ns
ns
ns
1
3
4
4
1
9
4
10
11
12
1
4
1
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Table 6-87. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave
Receive Cycles (see Figure 6-65)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
12
5
6
7
8
td(URCH-URCLAV)
Delay time, URCLK high to URCLAV driven active value
Delay time, URCLK high to URCLAV driven inactive low
Delay time, URCLK high to URCLAV going Hi-Z
3
3
9
3
ns
ns
ns
ns
td(URCH-URCLAVL)
td(URCH-URCLAVHZ)
tw(URCLAVL-URCLAVHZ)
12
18.5
Pulse duration (low), URCLAV low to URCLAV Hi-Z
UXCLK
1
3
P45
P46
N
P47
P48
H1
UXDATA[7:0]
UXADDR[4:0]
2
0 x1F
0x1F
N
N
0x1F
N + 1
7
0x1F
6
4
5
N
8
UXCLAV
UXENB
UXSOC
9
10
A. The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and UXSOC signals).
Figure 6-65. UTOPIA Slave Receive Timing(A)
6.24 Serial Rapid I/O (RIO) Port
The SRIO Port on the C6455 device is a high-performance, low pin-count interconnect aimed for
embedded markets. The use of the Rapid I/O interconnect in a baseband board design can create a
homogeneous interconnect environment, providing even more connectivity and control among the
components. Rapid I/O is based on the memory and device addressing concepts of processor buses
where the transaction processing is managed completely by hardware. This enables the Rapid I/O
interconnect to lower the system cost by providing lower latency, reduced overhead of packet data
processing, and higher system bandwidth, all of which are key for wireless interfaces. The Rapid I/O
interconnect offers very low pin-count interfaces with scalable system bandwidth based on 10-Gigabit per
second (Gbps) bidirectional links.
The PHY part of the RIO consists of the physical layer and includes the input and output buffers (each
serial link consists of a differential pair), the 8-bit/10-bit encoder/decoder, the PLL clock recovery, and the
parallel-to-serial/serial-to-parallel converters.
The RapidIO interface should be designed to operate at a data rate of 3 125 Gbps per differential pair.
This equals 12.5 raw GBaud/s for the 4x RapidIO port, or approximately 9 Gbps data throughput rate.
162
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SPRS276A–MAY 2005–REVISED JULY 2005
6.24.1 Serial RIO Device-Specific Information
The approach to specifying interface timing for the SRIO Port is different than on other interfaces such as
EMIF, HPI, and McBSP. For these other interfaces the device timing was specified in terms of data
manual specifications and I/O buffer information specification (IBIS) models.
For the C6455 SRIO Port, Texas Instruments (TI) provides a printed circuit board (PCB) solution showing
two DSPs connected via a 4x SRIO link directly to the user. TI has performed the simulation and system
characterization to ensure all SRIO interface timings in this solution are met. The complete SRIO system
solution is documented in the Implementing Serial RapidIO (SRIO) PCB Layout on a TMS320C6455
Hardware Design Application Report (Literature Number SPRAAA8) [Document Release Pending].
The Serial RapidIO peripheral is a master peripheral in the C6455 DSP. It conforms to the RapidIO™
Interconnect Specification, Part VI: Physical Layer 1x/4x LP-Serial Specification, Revision 1.2.
TI only supports designs that follow the board design guidelines outlined in the SPRAAA8
application report.
6.24.2 Serial RIO Peripheral Register Description(s)
Table 6-88. RapidIO Control Registers
HEX ADDRESS RANGE
02D0 0000
02D0 0004
02D0 0008
02D0 000C
02D0 0010
02D0 0014
02D0 0018
02D0 001C
02D0 0020
02D0 0024
02D0 0028 - 02D0 002C
02D0 0030
02D0 0034
02D0 0038
02D0 003C
02D0 0040
02D0 0044
02D0 0048
02D0 004C
02D0 0050
02D0 0054
02D0 0058
02D0 005C
02D0 0060
02D0 0064
02D0 0068
02D0 006C
02D0 0070
ACRONYM
RIOPID
REGISTER NAME
RapidIO Peripheral Identification Register
RapidIO Peripheral Control Register
RapidIO DFT Control 1 Register
RapidIO DFT Control 2 Register
Reserved
RIO_PCR
RIO_DFT1
RIO_DFT2
-
-
Reserved
-
Reserved
-
Reserved
RIO_PER_SET_CNTL
RIO_PER_SET_CNTL2
-
RapidIO Peripheral Settings Control Register
RapidIO SerDes Enable PLL Control Register
Reserved
RIO_GBL_EN
RIO_GBL_EN_STAT
RIO_BLK0_EN
RIO_BLK0_EN_STAT
RIO_BLK1_EN
RIO_BLK1_EN_STAT
RIO_BLK2_EN
RIO_BLK2_EN_STAT
RIO_BLK3_EN
RIO_BLK3_EN_STAT
RIO_BLK4_EN
RIO_BLK4_EN_STAT
RIO_BLK5_EN
RIO_BLK5_EN_STAT
RIO_BLK6_EN
RIO_BLK6_EN_STAT
RIO_BLK7_EN
RapidIO Peripheral Global Enable Register
RapidIO Peripheral Global Enable Status Register
RapidIO Block0 Enable Register
RapidIO Block0 Enable Status Register
RapidIO Block1 Enable Register
RapidIO Block1 Enable Status Register
RapidIO Block2 Enable Register
RapidIO Block2 Enable Status Register
RapidIO Block3 Enable Register
RapidIO Block3 Enable Status Register
RapidIO Block4 Enable Register
RapidIO Block4 Enable Status Register
RapidIO Block5 Enable Register
RapidIO Block5 Enable Status Register
RapidIO Block6 Enable Register
RapidIO Block6 Enable Status Register
RapidIO Block7 Enable Register
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-88. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 0074
02D0 0078
02D0 007C
02D0 0080
02D0 0084
02D0 0088
02D0 008C
02D0 0090
02D0 0094
02D0 0098
02D0 009C
02D0 00A0
02D0 00A4
02D0 00A8
02D0 00AC
02D0 00B0
02D0 00B4
02D0 00B8
02D0 00BC
02D0 00C0
02D0 00C4
02D0 00C8
02D0 00CC
02D0 00D0
02D0 00D4
02D0 00D8
02D0 00DC
02D0 00E0
02D0 00E4
02D0 00E8
02D0 00EC
02D0 00F0
02D0 00F4
02D0 00F8 - 02D0 00FC
02D0 0100
02D0 0104
02D0 0108
02D0 010C
02D0 0110
02D0 0114
02D0 0118
02D0 011C
02D0 0120
02D0 0124
02D0 0128
02D0 012C
02D0 0130
ACRONYM
RIO_BLK7_EN_STAT
RIO_BLK8_EN
REGISTER NAME
RapidIO Block7 Enable Status Register
RapidIO Block8 Enable Register
RIO_BLK8_EN_STAT
RIO_GBL_PD_REQ
RIO_GBL_PD_ACK
RapidIO Block8 Enable Status Register
RapidIO Peripheral Global Powerdown Request Register
RapidIO Peripheral Global Powerdown Acknowledge Register
RapidIO Peripheral Global Powerdown Status Register
RapidIO BLK0 Powerdown Request Register
RapidIO BLK0 Powerdown Acknowledge Register
RapidIO BLK0 Power Down Status Register
RapidIO BLK1 Powerdown Acknowledge Register
RapidIO BLK1 Powerdown Status Register
RapidIO BLK1 Powerdown Status Register
RapidIO BLK2 Powerdown Request Register
RapidIO BLK2 Powerdown Acknowledge Register
RapidIO BLK2 Powerdown Status Register
RapidIO BLK3 Powerdown Request Register
RapidIO BLK3 Powerdown Acknowledge Register
RapidIO BLK3 Powerdown Status Register
RapidIO BLK4 Powerdown Request Register
RapidIO BLK4 Powerdown Acknowledge Register
RapidIO BLK4 Powerdown Status Register
RapidIO BLK5 Powerdown Request Register
RapidIO BLK5 Powerdown Acknowledge Register
RapidIO BLK5 Powerdown Status Register
RapidIO BLK6 Powerdown Request Register
RapidIO BLK6 Powerdown Acknowledge Register
RapidIO BLK6 Powerdown Status Register
RapidIO BLK7 Powerdown Request Register
RapidIO BLK7 Powerdown Acknowledge Register
RapidIO BLK7 Powerdown Status Register
RapidIO BLK8 Powerdown Request Register
RapidIO BLK8 Powerdown Acknowledge Register
RapidIO BLK8 Powerdown Status Register
Reserved
RIO_GBL_PD_STAT
RIO_BLK0_PD_REQ
RIO_BLK0_PD_ACK
RIO_BLK0_PD_STAT
RIO_BLK1_PD_REQ
RIO_BLK1_PD_ACK
RIO_BLK1_PD_STAT
RIO_BLK2_PD_REQ
RIO_BLK2_PD_ACK
RIO_BLK2_PD_STAT
RIO_BLK3_PD_REQ
RIO_BLK3_PD_ACK
RIO_BLK3_PD_STAT
RIO_BLK4_PD_REQ
RIO_BLK4_PD_ACK
RIO_BLK4_PD_STAT
RIO_BLK5_PD_REQ
RIO_BLK5_PD_ACK
RIO_BLK5_PD_STAT
RIO_BLK6_PD_REQ
RIO_BLK6_PD_ACK
RIO_BLK6_PD_STAT
RIO_BLK7_PD_REQ
RIO_BLK7_PD_ACK
RIO_BLK7_PD_STAT
RIO_BLK8_PD_REQ
RIO_BLK8_PD_ACK
RIO_BLK8_PD_STAT
-
RIO_SERDES_CFGRX0_CNTL
RIO_SERDES_CFGRX1_CNTL
RIO_SERDES_CFGRX2_CNTL
RIO_SERDES_CFGRX3_CNTL
RIO_SERDES_CFGTX0_CNTL
RIO_SERDES_CFGTX1_CNTL
RIO_SERDES_CFGTX2_CNTL
RIO_SERDES_CFGTX3_CNTL
RIO_SERDES_CFG1_CNTL
-
RapidIO SerDes RX Channel 0 CFG Register
RapidIO SerDes RX Channel 1 CFG Register
RapidIO SerDes RX Channel 2 CFG Register
RapidIO SerDes RX Channel 3 CFG Register
RapidIO SerDes TX Channel 0 CFG Register
RapidIO SerDes TX Channel 1 CFG Register
RapidIO SerDes TX Channel 2 CFG Register
RapidIO SerDes TX Channel 3 CFG Register
RapidIO SerDes Macro 1 CFG Control Register
Reserved
RIO_SERDES_CFG2_CNTL
-
RapidIO SerDes Macro 2 CFG Control Register
Reserved
RIO_SERDES_CFG3_CNTL
RapidIO SerDes Macro 3 CFG Control Register
164
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-88. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 0134
ACRONYM
REGISTER NAME
-
Reserved
02D0 0138
RIO_SERDES_CFG4_CNTL
RapidIO SerDes Macro 4 CFG Control Register
Reserved
02D0 013C
-
02D0 0140
RIO_SERDES_TESTCFG1_CNTL
RapidIO SerDes Macro 1 TESTCFG Control Register
RapidIO SerDes Macro 2 TESTCFG Control Register
RapidIO SerDes Macro 3 TESTCFG Control Register
RapidIO SerDes Macro 4 TESTCFG Control Register
Reserved
02D0 0144
RIO_SERDES_TESTCFG2_CNTL
02D0 0148
RIO_SERDES_TESTCFG3_CNTL
02D0 014C
RIO_SERDES_TESTCFG4_CNTL
02D0 0150 - 02D0 01FC
02D0 0200
-
RIO_CPU0_ICSR
RapidIO CPU0 Interrupt Status Register
Reserved
02D0 0204
-
02D0 0208
RIO_CPU0_ICCR
RapidIO CPU0 Interrupt Clear Register
Reserved
02D0 020C
-
02D0 0210
RIO_CPU1_ICSR
RapidIO CPU1 Interrupt Status Register
Reserved
02D0 0214
-
02D0 0218
RIO_CPU1_ICCR
RapidIO CPU1 Interrupt Clear Register
Reserved
02D0 021C
-
02D0 0220
RIO_CPU2_ICSR
RapidIO CPU2 Interrupt Status Register
Reserved
02D0 0224
-
02D0 0228
RIO_CPU2_ICCR
RapidIO CPU2 Interrupt Clear Register
Reserved
02D0 022C
-
02D0 0230
RIO_CPU3_ICSR
RapidIO CPU3 Interrupt Status Register
Reserved
02D0 0234
-
02D0 0238
RIO_CPU3_ICCR
RapidIO CPU3 Interrupt Clear Register
Reserved
02D0 023C
-
02D0 0240
RIO_RX_CPPI_ICSR
RapidIO RX CPPI Interrupt Status Register
Reserved
02D0 0244 - 02D0 024C
02D0 0250
-
RIO_TX_CPPI_ICSR
RapidIO TX CPPI Interrupt Status Register
Reserved
02D0 0254 - 02D0 025C
02D0 0260
-
RIO_LSU_ICSR
RapidIO LSU Status Interrupt Register
Reserved
02D0 0264
-
02D0 0268
RIO_LSU _ICCR
-
RapidIO LSU Clear Interrupt Register
Reserved
02D0 026C
RapidIO Error, Reset, and Special Event Status Interrupt Regis-
ter
02D0 0270
RIO_ERR_RST_EVNT_ICSR
02D0 0274
02D0 0278
-
Reserved
RIO_ERR_RST_EVNT_ICCR
RapidIO Error, Reset, and Special Event Clear Interrupt Register
Reserved
02D0 027C
-
02D0 0280
RIO_CPU0_ICRR
RIO_CPU0_ICRR2
-
RapidIO CPU0 Interrupt Condition Routing Register
RapidIO CPU0 Interrupt Condition Routing Register 2
Reserved
02D0 0284
02D0 0288 - 02D0 028C
02D0 0290
RIO_CPU1_ICRR
RIO_CPU1_ICRR2
-
RapidIO CPU1 Interrupt Condition Routing Register
RapidIO CPU1 Interrupt Condition Routing Register 2
Reserved
02D0 0294
02D0 0298 - 02D0 029C
02D0 02A0
RIO_CPU2_ICRR
RIO_CPU2_ICRR2
-
RapidIO CPU2 Interrupt Condition Routing Register
RapidIO CPU2 Interrupt Condition Routing Register 2
Reserved
02D0 02A4
02D0 02A8 - 02D0 02AC
02D0 02B0
RIO_CPU3_ICRR
RapidIO CPU3 Interrupt Condition Routing Register
C6455 Peripheral Information and Electrical Specifications
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-88. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 02B4
ACRONYM
RIO_CPU3_ICRR2
-
REGISTER NAME
RapidIO CPU3 Interrupt Condition Routing Register 2
Reserved
02D0 02B8 - 02D0 02BC
02D0 02C0
RIO_RX_CPPI _ICRR
RIO_RX_CPPI _ICRR2
RIO_RX_CPPI _ICRR3
-
RapidIO RX CPPI Interrupt Condition Routing Register
RapidIO RX CPPI Interrupt Condition Routing Register 2
RapidIO RX CPPI Interrupt Condition Routing Register 3
Reserved
02D0 02C4
02D0 02C8
02D0 02CC
02D0 02D0
RIO_TX_CPPI _ICRR
RIO_TX_CPPI _ICRR2
RIO_TX_CPPI _ICRR3
-
RapidIO TX CPPI Interrupt Condition Routing Register
RapidIO TX CPPI Interrupt Condition Routing Register 2
RapidIO TX CPPI Interrupt Condition Routing Register 3
Reserved
02D0 02D4
02D0 02D8
02D0 02DC
02D0 02E0
RIO_LSU_ICRR
RIO_LSU_ICRR2
RIO_LSU_ICRR3
RIO_LSU_ICRR4
RapidIO LSU Module Interrupt Condition Routing Register
RapidIO LSU Module Interrupt Condition Routing Register 2
RapidIO LSU Module Interrupt Condition Routing Register 3
RapidIO LSU Module Interrupt Condition Routing Register 4
02D0 02E4
02D0 02E8
02D0 02EC
RapidIO Error/Reset/special event Interrupt Condition
Routing Register
02D0 02F0
02D0 02F4
02D0 02F8
RIO_ERR_RST_EVNT_ICRR
RIO_ERR_RST_EVNT_ICRR2
RIO_ERR_RST_EVNT_ICRR3
RapidIO Error/Reset/special event Interrupt Condition
Routing Register 2
RapidIO Error/Reset/special event Interrupt Condition
Routing Register 3
02D0 02FC
02D0 0300
02D0 0304
02D0 0308
02D0 030C
02D0 0310
02D0 0314
02D0 0318
02D0 031C
02D0 0320
02D0 0324
02D0 0328
02D0 032C
02D0 0330
02D0 0334
02D0 0338
02D0 033C
02D0 0340 - 02D0 03FC
02D0 0400
02D0 0404
02D0 0408
02D0 040C
02D0 0410
02D0 0414
02D0 0418
02D0 041C
02D0 0420
02D0 0424
-
Reserved
RIO_INTDST0_Decode
RIO_INTDST1_Decode
RIO_INTDST2_Decode
RIO_INTDST3_Decode
RIO_INTDST4_Decode
RIO_INTDST5_Decode
RIO_INTDST6_Decode
RIO_INTDST7_Decode
RIO_INTDST0_Rate_CNTL
RIO_INTDST1_Rate_CNTL
RIO_INTDST2_Rate_CNTL
RIO_INTDST3_Rate_CNTL
RIO_INTDST4_Rate_CNTL
RIO_INTDST5_Rate_CNTL
RIO_INTDST6_Rate_CNTL
RIO_INTDST7_Rate_CNTL
-
RapidIO INTDST0 Interrupt Status Decode Register
RapidIO INTDST1 Interrupt Status Decode Register
RapidIO INTDST2 Interrupt Status Decode Register
RapidIO INTDST3 Interrupt Status Decode Register
RapidIO INTDST4 Interrupt Status Decode Register
RapidIO INTDST5 Interrupt Status Decode Register
RapidIO INTDST6 Interrupt Status Decode Register
RapidIO INTDST7 Interrupt Status Decode Register
RapidIO INTDST0 Interrupt Rate Control Register
RapidIO INTDST1 Interrupt Rate Control Register
RapidIO INTDST2 Interrupt Rate Control Register
RapidIO INTDST3 Interrupt Rate Control Register
RapidIO INTDST4 Interrupt Rate Control Register
RapidIO INTDST5 Interrupt Rate Control Register
RapidIO INTDST6 Interrupt Rate Control Register
RapidIO INTDST7 Interrupt Rate Control Register
Reserved
RIO_LSU1_Reg0
RapidIO LSU1 Control Reg0 Register
RIO_LSU1_Reg1
RapidIO LSU1 Control Reg1 Register
RIO_LSU1_Reg2
RapidIO LSU1 Control Reg2 Register
RIO_LSU1_Reg3
RapidIO LSU1 Control Reg3 Register
RIO_LSU1_Reg4
RapidIO LSU1 Control Reg4 Register
RIO_LSU1_Reg5
RapidIO LSU1 Command Reg5 Register
RapidIO LSU1 Status Reg6 Register
RIO_LSU1_Reg6
RIO_LSU1_FLOW_MASKS
RIO_LSU2_Reg0
RapidIO Core0 LSU Congestion Control Flow Mask Register
RapidIO LSU2 Control Reg0 Register
RIO_LSU2_Reg1
RapidIO LSU2 Control Reg1 Register
166
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SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-88. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 0428
02D0 042C
02D0 0430
02D0 0434
02D0 0438
02D0 043C
02D0 0440
02D0 0444
02D0 0448
02D0 044C
02D0 0450
02D0 0454
02D0 0458
02D0 045C
02D0 0460
02D0 0464
02D0 0468
02D0 046C
02D0 0470
02D0 0474
02D0 0478
02D0 047C
02D0 0480 - 02D0 04FC
02D0 0500
02D0 0504
02D0 0508
02D0 050C
02D0 0510
02D0 0514
02D0 0518
02D0 051C
02D0 0520
02D0 0524
02D0 0528
02D0 052C
02D0 0530
02D0 0534
02D0 0538
02D0 053C
02D0 0540
02D0 0544
02D0 0548
02D0 054C
02D0 0550 - 02D0 057C
02D0 0580
02D0 0584
02D0 0588
ACRONYM
REGISTER NAME
RIO_LSU2_Reg2
RapidIO LSU2 Control Reg2 Register
RIO_LSU2_Reg3
RapidIO LSU2 Control Reg3 Register
RIO_LSU2_Reg4
RapidIO LSU2 Control Reg4 Register
RIO_LSU2_Reg5
RapidIO LSU2 Command Reg5 Register
RIO_LSU2_Reg6
RapidIO LSU2 Status Reg6 Register
RIO_LSU2_FLOW_MASKS
RIO_LSU3_Reg0
RapidIO Core1 LSU Congestion Control Flow Mask Register
RapidIO LSU3 Control Reg0 Register
RIO_LSU3_Reg1
RapidIO LSU3 Control Reg1 Register
RIO_LSU3_Reg2
RapidIO LSU3 Control Reg2 Register
RIO_LSU3_Reg3
RapidIO LSU3 Control Reg3 Register
RIO_LSU3_Reg4
RapidIO LSU3 Control Reg4 Register
RIO_LSU3_Reg5
RapidIO LSU3 Command Reg5 Register
RIO_LSU3_Reg6
RapidIO LSU3 Status Reg6 Register
RIO_LSU3_FLOW_MASKS
RIO_LSU4_Reg0
RapidIO Core2 LSU Congestion Control Flow Mask Register
RapidIO LSU4 Control Reg0 Register
RIO_LSU4_Reg1
RapidIO LSU4 Control Reg1 Register
RIO_LSU4_Reg2
RapidIO LSU4 Control Reg2 Register
RIO_LSU4_Reg3
RapidIO LSU4 Control Reg3 Register
RIO_LSU4_Reg4
RapidIO LSU4 Control Reg4 Register
RIO_LSU4_Reg5
RapidIO LSU4 Command Reg5 Register
RIO_LSU4_Reg6
RapidIO LSU4 Status Reg6 Register
RIO_LSU4_FLOW_MASKS
-
RapidIO Core3 LSU Congestion Control Flow Mask Register
Reserved
RIO_Queue0_TxDMA_HDP
RIO_Queue1_TxDMA_HDP
RIO_Queue2_TxDMA_HDP
RIO_Queue3_TxDMA_HDP
RIO_Queue4_TxDMA_HDP
RIO_Queue5_TxDMA_HDP
RIO_Queue6_TxDMA_HDP
RIO_Queue7_TxDMA_HDP
RIO_Queue8_TxDMA_HDP
RIO_Queue9_TxDMA_HDP
RIO_Queue10_TxDMA_HDP
RIO_Queue11_TxDMA_HDP
RIO_Queue12_TxDMA_HDP
RIO_Queue13_TxDMA_HDP
RIO_Queue14_TxDMA_HDP
RIO_Queue15_TxDMA_HDP
RIO_Queue16_TxDMA_HDP
RIO_Queue17_TxDMA_HDP
RIO_Queue18_TxDMA_HDP
RIO_Queue19_TxDMA_HDP
-
RapidIO Queue0 TX DMA Head Descriptor Pointer Register
RapidIO Queue1 TX DMA Head Descriptor Pointer Register
RapidIO Queue2 TX DMA Head Descriptor Pointer Register
RapidIO Queue3 TX DMA Head Descriptor Pointer Register
RapidIO Queue4 TX DMA Head Descriptor Pointer Register
RapidIO Queue5 TX DMA Head Descriptor Pointer Register
RapidIO Queue6 TX DMA Head Descriptor Pointer Register
RapidIO Queue7 TX DMA Head Descriptor Pointer Register
RapidIO Queue8 TX DMA Head Descriptor Pointer Register
RapidIO Queue9 TX DMA Head Descriptor Pointer Register
RapidIO Queue10 TX DMA Head Descriptor Pointer Register
RapidIO Queue11 TX DMA Head Descriptor Pointer Register
RapidIO Queue12 TX DMA Head Descriptor Pointer Register
RapidIO Queue13 TX DMA Head Descriptor Pointer Register
RapidIO Queue14 TX DMA Head Descriptor Pointer Register
RapidIO Queue15 TX DMA Head Descriptor Pointer Register
RapidIO Queue16 TX DMA Head Descriptor Pointer Register
RapidIO Queue17 TX DMA Head Descriptor Pointer Register
RapidIO Queue18 TX DMA Head Descriptor Pointer Register
RapidIO Queue19 TX DMA Head Descriptor Pointer Register
Reserved
RIO_Queue0_TxDMA_CP
RIO_Queue1_TxDMA_CP
RIO_Queue2_TxDMA_CP
RapidIO Queue0 TX DMA Completion Pointer Register
RapidIO Queue1 TX DMA Completion Pointer Register
RapidIO Queue2 TX DMA Completion Pointer Register
C6455 Peripheral Information and Electrical Specifications
167
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-88. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 058C
02D0 0590
02D0 0594
02D0 0598
02D0 059C
02D0 05A0
02D0 05A4
02D0 05A8
02D0 05AC
02D0 05B0
02D0 05B4
02D0 05B8
02D0 05BC
02D0 05C0
02D0 05C4
02D0 05C8
02D0 05CC
02D0 05D0 - 02D0 05FC
02D0 0600
02D0 0604
02D0 0608
02D0 060C
02D0 0610
02D0 0614
02D0 0618
02D0 061C
02D0 0620
02D0 0624
02D0 0628
02D0 062C
02D0 0630
02D0 0634
02D0 0638
02D0 063C
02D0 0640
02D0 0644
02D0 0648
02D0 064C
02D0 0650 - 02D0 067C
02D0 0680
02D0 0684
02D0 0688
02D0 068C
02D0 0690
02D0 0694
02D0 0698
02D0 069C
ACRONYM
REGISTER NAME
RIO_Queue3_TxDMA_CP
RIO_Queue4_TxDMA_CP
RIO_Queue5_TxDMA_CP
RIO_Queue6_TxDMA_CP
RIO_Queue7_TxDMA_CP
RIO_Queue8_TxDMA_CP
RIO_Queue9_TxDMA_CP
RIO_Queue10_TxDMA_CP
RIO_Queue11_TxDMA_CP
RIO_Queue12_TxDMA_CP
RIO_Queue13_TxDMA_CP
RIO_Queue14_TxDMA_CP
RIO_Queue15_TxDMA_CP
RIO_Queue16_TxDMA_CP
RIO_Queue17_TxDMA_CP
RIO_Queue18_TxDMA_CP
RIO_Queue19_TxDMA_CP
-
RapidIO Queue3 TX DMA Completion Pointer Register
RapidIO Queue4 TX DMA Completion Pointer Register
RapidIO Queue5 TX DMA Completion Pointer Register
RapidIO Queue6 TX DMA Completion Pointer Register
RapidIO Queue7 TX DMA Completion Pointer Register
RapidIO Queue8 TX DMA Completion Pointer Register
RapidIO Queue9 TX DMA Completion Pointer Register
RapidIO Queue10 TX DMA Completion Pointer Register
RapidIO Queue11 TX DMA Completion Pointer Register
RapidIO Queue12 TX DMA Completion Pointer Register
RapidIO Queue13 TX DMA Completion Pointer Register
RapidIO Queue14 TX DMA Completion Pointer Register
RapidIO Queue15 TX DMA Completion Pointer Register
RapidIO Queue16 TX DMA Completion Pointer Register
RapidIO Queue17 TX DMA Completion Pointer Register
RapidIO Queue18 TX DMA Completion Pointer Register
RapidIO Queue19 TX DMA Completion Pointer Register
Reserved
RIO_Queue0_RxDMA_HDP
RIO_Queue1_RxDMA_HDP
RIO_Queue2_RxDMA_HDP
RIO_Queue3_RxDMA_HDP
RIO_Queue4_RxDMA_HDP
RIO_Queue5_RxDMA_HDP
RIO_Queue6_RxDMA_HDP
RIO_Queue7_RxDMA_HDP
RIO_Queue8_RxDMA_HDP
RIO_Queue9_RxDMA_HDP
RIO_Queue10_RxDMA_HDP
RIO_Queue11_RxDMA_HDP
RIO_Queue12_RxDMA_HDP
RIO_Queue13_RxDMA_HDP
RIO_Queue14_RxDMA_HDP
RIO_Queue15_RxDMA_HDP
RIO_Queue16_RxDMA_HDP
RIO_Queue17_RxDMA_HDP
RIO_Queue18_RxDMA_HDP
RIO_Queue19_RxDMA_HDP
-
RapidIO Queue0 RX DMA Head Descriptor Pointer Register
RapidIO Queue1 RX DMA Head Descriptor Pointer Register
RapidIO Queue2 RX DMA Head Descriptor Pointer Register
RapidIO Queue3 RX DMA Head Descriptor Pointer Register
RapidIO Queue4 RX DMA Head Descriptor Pointer Register
RapidIO Queue5 RX DMA Head Descriptor Pointer Register
RapidIO Queue6 RX DMA Head Descriptor Pointer Register
RapidIO Queue7 RX DMA Head Descriptor Pointer Register
RapidIO Queue8 RX DMA Head Descriptor Pointer Register
RapidIO Queue9 RX DMA Head Descriptor Pointer Register
RapidIO Queue10 RX DMA Head Descriptor Pointer Register
RapidIO Queue11 RX DMA Head Descriptor Pointer Register
RapidIO Queue12 RX DMA Head Descriptor Pointer Register
RapidIO Queue13 RX DMA Head Descriptor Pointer Register
RapidIO Queue14 RX DMA Head Descriptor Pointer Register
RapidIO Queue15 RX DMA Head Descriptor Pointer Register
RapidIO Queue16 RX DMA Head Descriptor Pointer Register
RapidIO Queue17 RX DMA Head Descriptor Pointer Register
RapidIO Queue18 RX DMA Head Descriptor Pointer Register
RapidIO Queue19 RX DMA Head Descriptor Pointer Register
Reserved
RIO_Queue0_RxDMA_CP
RIO_Queue1_RxDMA_CP
RIO_Queue2_RxDMA_CP
RIO_Queue3_RxDMA_CP
RIO_Queue4_RxDMA_CP
RIO_Queue5_RxDMA_CP
RIO_Queue6_RxDMA_CP
RIO_Queue7_RxDMA_CP
RapidIO Queue0 RX DMA Completion Pointer Register
RapidIO Queue1 RX DMA Completion Pointer Register
RapidIO Queue2 RX DMA Completion Pointer Register
RapidIO Queue3 RX DMA Completion Pointer Register
RapidIO Queue4 RX DMA Completion Pointer Register
RapidIO Queue5 RX DMA Completion Pointer Register
RapidIO Queue6 RX DMA Completion Pointer Register
RapidIO Queue7 RX DMA Completion Pointer Register
168
C6455 Peripheral Information and Electrical Specifications
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-88. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 06A0
ACRONYM
REGISTER NAME
RIO_Queue8_RxDMA_CP
RIO_Queue9_RxDMA_CP
RIO_Queue10_RxDMA_CP
RIO_Queue11_RxDMA_CP
RIO_Queue12_RxDMA_CP
RIO_Queue13_RxDMA_CP
RIO_Queue14_RxDMA_CP
RIO_Queue15_RxDMA_CP
RIO_Queue16_RxDMA_CP
RIO_Queue17_RxDMA_CP
RIO_Queue18_RxDMA_CP
RIO_Queue19_RxDMA_CP
-
RapidIO Queue8 RX DMA Completion Pointer Register
RapidIO Queue9 RX DMA Completion Pointer Register
RapidIO Queue10 RX DMA Completion Pointer Register
RapidIO Queue11 RX DMA Completion Pointer Register
RapidIO Queue12 RX DMA Completion Pointer Register
RapidIO Queue13 RX DMA Completion Pointer Register
RapidIO Queue14 RX DMA Completion Pointer Register
RapidIO Queue15 RX DMA Completion Pointer Register
RapidIO Queue16 RX DMA Completion Pointer Register
RapidIO Queue17 RX DMA Completion Pointer Register
RapidIO Queue18 RX DMA Completion Pointer Register
RapidIO Queue19 RX DMA Completion Pointer Register
Reserved
02D0 06A4
02D0 06A8
02D0 06AC
02D0 06B0
02D0 06B4
02D0 06B8
02D0 06BC
02D0 06C0
02D0 06C4
02D0 06C8
02D0 06CC
02D0 06D0 - 02D0 06FC
02D0 0700
RIO_TX_QUEUE_TEAR_DOWN
RIO_TX_CPPI_FLOW_MASKS0
RIO_TX_CPPI_FLOW_MASKS1
RIO_TX_CPPI_FLOW_MASKS2
RIO_TX_CPPI_FLOW_MASKS3
RIO_TX_CPPI_FLOW_MASKS4
-
RapidIO TX Queue Teardown Register
02D0 0704
RapidIO TX CPPI Supported Flow Masks 0 Register
RapidIO TX CPPI Supported Flow Masks 1 Register
RapidIO TX CPPI Supported Flow Masks 2 Register
RapidIO TX CPPI Supported Flow Masks 3 Register
RapidIO TX CPPI Supported Flow Masks 4 Register
Reserved
02D0 0708
02D0 070C
02D0 0710
02D0 0714
02D0 0718 - 02D0 073C
02D0 0740
RIO_RX_QUEUE_TEAR_DOWN
RIO_RX_CPPI_CNTL
RapidIO RX Queue Teardown Register
02D0 0744
RapidIO RX CPPI Control Register
02D0 0748 - 02D0 077C
02D0 0780
-
Reserved
RIO_RXU _MMBX0_MAP1
RIO_RXU _MMBX0_MAP2
RIO_RXU _MMBX0_MAP3
RIO_RXU _MMBX0_MAP4
RIO_RXU _MMBX1_MAP1
RIO_RXU _MMBX1_MAP2
RIO_RXU _MMBX1_MAP3
RIO_RXU _MMBX1_MAP4
RIO_RXU _MMBX2_MAP1
RIO_RXU _MMBX2_MAP2
RIO_RXU _MMBX2_MAP3
RIO_RXU _MMBX2_MAP4
RIO_RXU _MMBX3_MAP1
RIO_RXU _MMBX3_MAP2
RIO_RXU _MMBX3_MAP3
RIO_RXU _MMBX3_MAP4
-
RapidIO Multi-Segment 0 Message to Queue Map 1 Register
RapidIO Multi-Segment 0 Message to Queue Map 2 Register
RapidIO Multi-Segment 0 Message to Queue Map 3 Register
RapidIO Multi-Segment 0 Message to Queue Map 4 Register
RapidIO Multi-Segment 1 Message to Queue Map 1 Register
RapidIO Multi-Segment 1 Message to Queue Map 2 Register
RapidIO Multi-Segment 1 Message to Queue Map 3 Register
RapidIO Multi-Segment 1 Message to Queue Map 4 Register
RapidIO Multi-Segment 2 Message to Queue Map 1 Register
RapidIO Multi-Segment 2 Message to Queue Map 2 Register
RapidIO Multi-Segment 2 Message to Queue Map 3 Register
RapidIO Multi-Segment 2 Message to Queue Map 4 Register
RapidIO Multi-Segment 3 Message to Queue Map 1 Register
RapidIO Multi-Segment 3 Message to Queue Map 2 Register
RapidIO Multi-Segment 3 Message to Queue Map 3 Register
RapidIO Multi-Segment 3 Message to Queue Map 4 Register
Reserved
02D0 0784
02D0 0788
02D0 078C
02D0 0790
02D0 0794
02D0 0798
02D0 079C
02D0 07A0
02D0 07A4
02D0 07A8
02D0 07AC
02D0 07B0
02D0 07B4
02D0 07B8
02D0 07BC
02D0 07C0 - 02D0 07DC
02D0 07E0
RIO_TX_QUEUE_CNTL0
RIO_TX_QUEUE_CNTL1
RIO_TX_QUEUE_CNTL2
RIO_TX_QUEUE_CNTL3
-
RapidIO TX Queue Control 0 Register TBD
02D0 07E4
RapidIO TX Queue Control 1 Register
02D0 07E8
RapidIO TX Queue Control 2 Register
02D0 07EC
RapidIO TX Queue Control 3 Register
02D0 07F0 - 02D0 07FC
02D0 0800
Reserved
RIO_RXU_SMBX00_MAP
RIO_RXU_SMBX01_MAP
RapidIO Single-Segment 00 Message to Queue Map Register
RapidIO Single-Segment 01 Message to Queue Map Register
02D0 0804
C6455 Peripheral Information and Electrical Specifications
169
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-88. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 0808
02D0 080C
02D0 0810
02D0 0814
02D0 0818
02D0 081C
02D0 0820
02D0 0824
02D0 0828
02D0 082C
02D0 0830
02D0 0834
02D0 0838
02D0 083C
02D0 0840
02D0 0844
02D0 0848
02D0 084C
02D0 0850
02D0 0854
02D0 0858
02D0 085C
02D0 0860
02D0 0864
02D0 0868
02D0 086C
02D0 0870
02D0 0874
02D0 0878
02D0 087C
02D0 0880
02D0 0884
02D0 0888
02D0 088C
02D0 0890
02D0 0894
02D0 0898
02D0 089C
02D0 08A0
02D0 08A4
02D0 08A8
02D0 08AC
02D0 08B0
02D0 08B4
02D0 08B8
02D0 08BC
02D0 08C0
ACRONYM
REGISTER NAME
RIO_RXU_SMBX02_MAP
RIO_RXU_SMBX03_MAP
RIO_RXU_SMBX04_MAP
RIO_RXU_SMBX05_MAP
RIO_RXU_SMBX06_MAP
RIO_RXU_SMBX07_MAP
RIO_RXU_SMBX08_MAP
RIO_RXU_SMBX09_MAP
RIO_RXU_SMBX10_MAP
RIO_RXU_SMBX11_MAP
RIO_RXU_SMBX12_MAP
RIO_RXU_SMBX13_MAP
RIO_RXU_SMBX14_MAP
RIO_RXU_SMBX15_MAP
RIO_RXU_SMBX16_MAP
RIO_RXU_SMBX17_MAP
RIO_RXU_SMBX18_MAP
RIO_RXU_SMBX19_MAP
RIO_RXU_SMBX20_MAP
RIO_RXU_SMBX21_MAP
RIO_RXU_SMBX22_MAP
RIO_RXU_SMBX23_MAP
RIO_RXU_SMBX24_MAP
RIO_RXU_SMBX25_MAP
RIO_RXU_SMBX26_MAP
RIO_RXU_SMBX27_MAP
RIO_RXU_SMBX28_MAP
RIO_RXU_SMBX29_MAP
RIO_RXU_SMBX30_MAP
RIO_RXU_SMBX31_MAP
RIO_RXU_SMBX32_MAP
RIO_RXU_SMBX33_MAP
RIO_RXU_SMBX34_MAP
RIO_RXU_SMBX35_MAP
RIO_RXU_SMBX36_MAP
RIO_RXU_SMBX37_MAP
RIO_RXU_SMBX38_MAP
RIO_RXU_SMBX39_MAP
RIO_RXU_SMBX40_MAP
RIO_RXU_SMBX41_MAP
RIO_RXU_SMBX42_MAP
RIO_RXU_SMBX43_MAP
RIO_RXU_SMBX44_MAP
RIO_RXU_SMBX45_MAP
RIO_RXU_SMBX46_MAP
RIO_RXU_SMBX47_MAP
RIO_RXU_SMBX48_MAP
RapidIO Single-Segment 02 Message to Queue Map Register
RapidIO Single-Segment 03 Message to Queue Map Register
RapidIO Single-Segment 04 Message to Queue Map Register
RapidIO Single-Segment 05 Message to Queue Map Register
RapidIO Single-Segment 06 Message to Queue Map Register
RapidIO Single-Segment 07 Message to Queue Map Register
RapidIO Single-Segment 08 Message to Queue Map Register
RapidIO Single-Segment 09 Message to Queue Map Register
RapidIO Single-Segment 10 Message to Queue Map Register
RapidIO Single-Segment 11 Message to Queue Map Register
RapidIO Single-Segment 12 Message to Queue Map Register
RapidIO Single-Segment 13 Message to Queue Map Register
RapidIO Single-Segment 14 Message to Queue Map Register
RapidIO Single-Segment 15 Message to Queue Map Register
RapidIO Single-Segment 16 Message to Queue Map Register
RapidIO Single-Segment 17 Message to Queue Map Register
RapidIO Single-Segment 18 Message to Queue Map Register
RapidIO Single-Segment 19 Message to Queue Map Register
RapidIO Single-Segment 20 Message to Queue Map Register
RapidIO Single-Segment 21 Message to Queue Map Register
RapidIO Single-Segment 22 Message to Queue Map Register
RapidIO Single-Segment 23 Message to Queue Map Register
RapidIO Single-Segment 24 Message to Queue Map Register
RapidIO Single-Segment 25 Message to Queue Map Register
RapidIO Single-Segment 26 Message to Queue Map Register
RapidIO Single-Segment 27 Message to Queue Map Register
RapidIO Single-Segment 28 Message to Queue Map Register
RapidIO Single-Segment 29 Message to Queue Map Register
RapidIO Single-Segment 30 Message to Queue Map Register
RapidIO Single-Segment 31 Message to Queue Map Register
RapidIO Single-Segment 32 Message to Queue Map Register
RapidIO Single-Segment 33 Message to Queue Map Register
RapidIO Single-Segment 34 Message to Queue Map Register
RapidIO Single-Segment 35 Message to Queue Map Register
RapidIO Single-Segment 36 Message to Queue Map Register
RapidIO Single-Segment 37 Message to Queue Map Register
RapidIO Single-Segment 38 Message to Queue Map Register
RapidIO Single-Segment 39 Message to Queue Map Register
RapidIO Single-Segment 40 Message to Queue Map Register
RapidIO Single-Segment 41 Message to Queue Map Register
RapidIO Single-Segment 42 Message to Queue Map Register
RapidIO Single-Segment 43 Message to Queue Map Register
RapidIO Single-Segment 44 Message to Queue Map Register
RapidIO Single-Segment 45 Message to Queue Map Register
RapidIO Single-Segment 46 Message to Queue Map Register
RapidIO Single-Segment 47 Message to Queue Map Register
RapidIO Single-Segment 48 Message to Queue Map Register
170
C6455 Peripheral Information and Electrical Specifications
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-88. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 08C4
02D0 08C8
02D0 08CC
02D0 08D0
02D0 08D4
02D0 08D8
02D0 08DC
02D0 08E0
02D0 08E4
02D0 08E8
02D0 08EC
02D0 08F0
02D0 08F4
02D0 08F8
02D0 08FC
02D0 0900
02D0 0904
02D0 0908
02D0 090C
02D0 0910
02D0 0914
02D0 0918
02D0 091C
ACRONYM
REGISTER NAME
RIO_RXU_SMBX49_MAP
RIO_RXU_SMBX50_MAP
RIO_RXU_SMBX51_MAP
RIO_RXU_SMBX52_MAP
RIO_RXU_SMBX53_MAP
RIO_RXU_SMBX54_MAP
RIO_RXU_SMBX55_MAP
RIO_RXU_SMBX56_MAP
RIO_RXU_SMBX57_MAP
RIO_RXU_SMBX58_MAP
RIO_RXU_SMBX59_MAP
RIO_RXU_SMBX60_MAP
RIO_RXU_SMBX61_MAP
RIO_RXU_SMBX62_MAP
RIO_RXU_SMBX63_MAP
RIO_FLOW_CNTL0
RapidIO Single-Segment 49 Message to Queue Map Register
RapidIO Single-Segment 50 Message to Queue Map Register
RapidIO Single-Segment 51 Message to Queue Map Register
RapidIO Single-Segment 52 Message to Queue Map Register
RapidIO Single-Segment 53 Message to Queue Map Register
RapidIO Single-Segment 54 Message to Queue Map Register
RapidIO Single-Segment 55 Message to Queue Map Register
RapidIO Single-Segment 56 Message to Queue Map Register
RapidIO Single-Segment 57 Message to Queue Map Register
RapidIO Single-Segment 58 Message to Queue Map Register
RapidIO Single-Segment 59 Message to Queue Map Register
RapidIO Single-Segment 60 Message to Queue Map Register
RapidIO Single-Segment 61 Message to Queue Map Register
RapidIO Single-Segment 62 Message to Queue Map Register
RapidIO Single-Segment 63 Message to Queue Map Register
RapidIO Flow Control Table Entry Register0
RIO_FLOW_CNTL1
RapidIO Flow Control Table Entry Register1
RIO_FLOW_CNTL2
RapidIO Flow Control Table Entry Register2
RIO_FLOW_CNTL3
RapidIO Flow Control Table Entry Register3
RIO_FLOW_CNTL4
RapidIO Flow Control Table Entry Register4
RIO_FLOW_CNTL5
RapidIO Flow Control Table Entry Register5
RIO_FLOW_CNTL6
RapidIO Flow Control Table Entry Register6
RIO_FLOW_CNTL7
RapidIO Flow Control Table Entry Register7
RapidIO Peripheral-Specific Registers
02D0 0920 - 02D0 0FFC
02D0 1000
-
Reserved
RIO_DEV_ID
RIO_DEV_INFO
RIO_ASBLY_ID
RIO_ASBLY_INFO
RIO_PE_FEAT
RIO_SW_PORT
RIO_SRC_OP
RIO_DEST_OP
-
RapidIO Device Identity CAR Register
RapidIO Device Information CAR Register
RapidIO Assembly Identity CAR Register
RapidIO Assembly Information CAR Register
RapidIO Processing Element Features CAR Register
RapidIO Switch Port Information CAR Register
RapidIO Source Operations CAR Register
RapidIO Destination Operations CAR Register
Reserved
02D0 1004
02D0 1008
02D0 100C
02D0 1010
02D0 1014
02D0 1018
02D0 101C
02D0 1020 - 02D0 1038
02D0 1040
-
Reserved
02D0 1044 - 02D0 1048
-
Reserved
RapidIO Processing Element Logical Layer Control CSR
Register
02D0 104C
02D0 1050
02D0 1058
RIO_PE_LL_CTL
-
Reserved
RapidIO Local Configuration Space Base Address 0 CSR
Register
RIO_LCL_CFG_HBAR
RapidIO Local Configuration Space Base Address 1 CSR
Register
02D0 105C
RIO_LCL_CFG_BAR
02D0 1060
02D0 1064
RIO_BASE_ID
RapidIO Base Device ID CSR Register
Reserved
-
RIO_ HOST_BASE_ID_LOCK
RIO_ COMP_TAG
-
02D0 1068
RapidIO Host Base Device ID Lock CSR Register
RapidIO Component Tag CSR Register
Reserved
02D0 106C
02D0 1070 - 02D0 10F8
C6455 Peripheral Information and Electrical Specifications
171
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-88. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
02D0 10FC
-
Reserved
RapidIO Extended Features - LP Serial Registers
RapidIO 1x/4x LP-Serial Port Maintenance Block Header
Register
02D0 1100
RIO_ SP_MB_HEAD
02D0 1104 - 02D0 1118
02D0 111C
-
Reserved
-
Reserved
02D0 1120
RIO_SP_LT_CTL
RapidIO Port Link Time-Out Control CSR Register
RapidIO Port Response Time-Out Control CSR Register
Reserved
02D0 1124
RIO_SP_RT_CTL
02D0 1128
-
02D0 112C
-
Reserved
02D0 1130 -02D0 1138
02D0 113C
-
Reserved
RIO_SP_GEN_CTL
RIO_SP0_LM_REQ
RIO_SP0_LM_RESP
RIO_SP0_ACKID_STAT
-
RapidIO Port General Control CSR Register
RapidIO Port 0 Link Maintenance Request CSR Register
RapidIO Port 0 Link Maintenance Response CSR Register
RapidIO Port 0 Local AckID Status CSR Register
Reserved
02D0 1140
02D0 1144
02D0 1148
02D0 114C - 02D0 1150
02D0 1154
-
Reserved
02D0 1158
RIO_SP0_ERR_STAT
RIO_SP0_CTL
RIO_SP1_LM_REQ
RIO_SP1_LM_RESP
RIO_SP1_ACKID_STAT
-
RapidIO Port 0 Error and Status CSR Register
RapidIO Port 0 Control CSR Register
RapidIO Port 1 Link Maintenance Request CSR Register
RapidIO Port 1 Link Maintenance Response CSR Register
RapidIO Port 1 Local AckID Status CSR Register
Reserved
02D0 115C
02D0 1160
02D0 1164
02D0 1168
02D0 116C- 02D0 1170
02D0 1174
-
Reserved
02D0 1178
RIO_SP1_ERR_STAT
RIO_SP1_CTL
RIO_SP2_LM_REQ
RIO_SP2_LM_RESP
RIO_SP2_ACKID_STAT
-
RapidIO Port 1 Error and Status CSR Register
RapidIO Port 1 Control CSR Register
RapidIO Port 2 Link Maintenance Request CSR Register
RapidIO Port 2 Link Maintenance Response CSR Register
RapidIO Port 2 Local AckID Status CSR Register
Reserved
02D0 117C
02D0 1180
02D0 1184
02D0 1188
02D0 118C - 02D0 1190
02D0 1194
-
Reserved
02D0 1198
RIO_SP2_ERR_STAT
RIO_SP2_CTL
RIO_SP3_LM_REQ
RIO_SP3_LM_RESP
RIO_SP3_ACKID_STAT
-
RapidIO Port 2 Error and Status CSR Register
RapidIO Port 2 Control CSR Register
RapidIO Port 3 Link Maintenance Request CSR Register
RapidIO Port 3 Link Maintenance Response CSR Register
RapidIO Port 3 Local AckID Status CSR Register
Reserved
02D0 119C
02D0 11A0
02D0 11A4
02D0 11A8
02D0 11AC - 02D0 11B0
02D0 11B4
-
Reserved
02D0 11B8
RIO_SP3_ERR_STAT
RIO_SP3_CTL
-
RapidIO Port 3 Error and Status CSR Register
RapidIO Port 3 Control CSR Register
Reserved
02D0 11BC
02D0 11C0 - 02D0 1FFC
RapidIO Extended Feature - Error Management Registers
02D0 2000
02D0 2004
02D0 2008
02D0 200C
RIO_ERR_RPT_BH
-
RapidIO Error Reporting Block Header Register
Reserved
RIO_ERR_DET
RIO_ERR_EN
RapidIO Logical/Transport Layer Error Detect CSR Register
RapidIO Logical/Transport Layer Error Enable CSR Register
RapidIO Logical/Transport Layer High Address Capture CSR
Register
02D0 2010
RIO_H_ADDR_CAPT
172
C6455 Peripheral Information and Electrical Specifications
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-88. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
02D0 2014
RIO_ADDR_CAPT
RapidIO Logical/Transport Layer Address Capture CSR Register
RapidIO Logical/Transport Layer Device ID Capture CSR
Register
02D0 2018
RIO_ID_CAPT
02D0 201C
02D0 2020 - 02D0 2024
02D0 2028
RIO_CTRL_CAPT
-
RapidIO Logical/Transport Layer Control Capture CSR Register
Reserved
RIO_PW_TGT_ID
RIO_PKT_TIME_LIVE
-
RapidIO Port-Write Target Device ID CSR Register
RapidIO Packet Time-to-Live CSR Register
Reserved
02D0 202C
02D0 2030 - 02D0 203C
02D0 2040
RIO_SP0_ERR_DET
RIO_SP0_RATE_EN
RapidIO Port 0 Error Detect CSR Register
RapidIO Port 0 Error Enable CSR Register
02D0 2044
02D0 2048
RIO_SP0_ERR_ATTR_CAPT_DBG0 RapidIO Port 0 Attributes Error Capture CSR Register
RapidIO Port 0 Packet/Control Symbol Error Capture CSR0
02D0 204C
02D0 2050
02D0 2054
02D0 2058
RIO_SP0_ERR_CAPT_0_DBG1
Register
RapidIO Port 0 Packet/Control Symbol Error Capture CSR1
RIO_SP0_ERR_CAPT_1_DBG2
Register
RapidIO Port 0 Packet/Control Symbol Error Capture CSR2
RIO_SP0_ERR_CAPT_2_DBG3
Register
RapidIO Port 0 Packet/Control Symbol Error Capture CSR3
RIO_SP0_ERR_CAPT_3_DBG4
Register
02D0 205C - 02D0 2064
02D0 2068
-
Reserved
RIO_SP0_ERR_RATE
RIO_SP0_ERR_THRESH
-
RapidIO Port 0 Error Rate CSR Register
RapidIO Port 0 Error Rate Threshold CSR Register
Reserved
02D0 206C
02D0 2070 - 02D0 207C
02D0 2080
RIO_SP1_ERR_DET
RIO_SP1_RATE_EN
RIO_SP1_ERR_ATTR_CAPT
RapidIO Port 1 Error Detect CSR Register
RapidIO Port 1 Error Enable CSR Register
RapidIO Port 1 Attributes Error Capture CSR Register
02D0 2084
02D0 2088
RapidIO Port 1 Packet/Control Symbol Error Capture CSR0
Register
02D0 208C
02D0 2090
02D0 2094
02D0 2098
RIO_SP1_ERR_CAPT_0
RIO_SP1_ERR_CAPT_1
RIO_SP1_ERR_CAPT_2
RIO_SP1_ERR_CAPT_3
RapidIO Port 1 Packet/Control Symbol Error Capture CSR1
Register
RapidIO Port 1 Packet/Control Symbol Error Capture CSR2
Register
RapidIO Port 1 Packet/Control Symbol Error Capture CSR3
Register
02D0 209C - 02D0 20A4
02D0 20A8
-
Reserved
RIO_SP1_ERR_RATE
RIO_SP1_ERR_THRESH
-
RapidIO Port 1 Error Rate CSR Register
RapidIO Port 1 Error Rate Threshold CSR Register
Reserved
02D0 20AC
02D0 20B0 - 02D0 20BC
02D0 20C0
RIO_SP2_ERR_DET
RIO_SP2_RATE_EN
RIO_SP2_ERR_ATTR_CAPT
RapidIO Port 2 Error Detect CSR Register
RapidIO Port 2 Error Enable CSR Register
RapidIO Port 2 Attributes Error Capture CSR Register
02D0 20C4
02D0 20C8
RapidIO Port 2 Packet/Control Symbol Error Capture CSR0
Register
02D0 20CC
02D0 20D0
02D0 20D4
02D0 20D8
RIO_SP2_ERR_CAPT_0
RIO_SP2_ERR_CAPT_1
RIO_SP2_ERR_CAPT_2
RIO_SP2_ERR_CAPT_3
RapidIO Port 2 Packet/Control Symbol Error Capture CSR1
Register
RapidIO Port 2 Packet/Control Symbol Error Capture CSR2
Register
RapidIO Port 2 Packet/Control Symbol Error Capture CSR3
Register
02D0 20DC - 02D0 20E4
02D0 20E8
-
Reserved
RIO_SP2_ERR_RATE
RapidIO Port 2 Error Rate CSR Register
C6455 Peripheral Information and Electrical Specifications
173
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-88. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 20EC
ACRONYM
RIO_SP3_RATE_EN
-
REGISTER NAME
RapidIO Port 3 Error Enable CSR Register
Reserved
02D0 20F0 - 02D0 20FC
02D0 2100
RIO_SP3_ERR_DET
RIO_SP3_RATE_EN
RIO_SP3_ERR_ATTR_CAPT
RapidIO Port 3 Error Detect CSR Register
RapidIO Port 3 Error Enable CSR Register
02D0 2104
02D0 2108
RapidIO Port 3 Attributes Error Capture CSR Register
RapidIO Port 3 Packet/Control Symbol Error Capture CSR0
Register
02D0 210C
02D0 2110
02D0 2114
02D0 2118
RIO_SP3_ERR_CAPT_0
RIO_SP3_ERR_CAPT_1
RIO_SP3_ERR_CAPT_2
RIO_SP3_ERR_CAPT_3
RapidIO Port 3 Packet/Control Symbol Error Capture CSR1
Register
RapidIO Port 3 Packet/Control Symbol Error Capture CSR2
Register
RapidIO Port 3 Packet/Control Symbol Error Capture CSR3
Register
02D0 211C - 02D0 2124
02D0 2128
-
Reserved
RIO_SP3_ERR_RATE
RIO_SP3_ERR_THRESH
-
RapidIO Port 3 Error Rate CSR Register
RapidIO Port 3 Error Rate Threshold CSR Register
Reserved
02D0 212C
02D0 2130 - 02D1 0FFC
Implementation Registers
02D1 1000 - 02D1 1FFC
02D1 2000
-
Reserved
RIO_SP_IP_DISCOVERY_TIMER
RIO_SP_IP_MODE
RapidIO Port IP Discovery Timer in 4x Mode Register
RapidIO Port IP Mode CSR Register
Reserved
02D0 2004
02D1 2008 - 02D1 200C
02D1 2010
-
RIO_SP_IP_PW_IN_CAPT0
RIO_SP_IP_PW_IN_CAPT1
RIO_SP_IP_PW_IN_CAPT2
RIO_SP_IP_PW_IN_CAPT3
-
RapidIO Port-Write-In Capture 0 CSR Register
RapidIO Port-Write-In Capture 1 CSR Register
RapidIO Port-Write-In Capture 2 CSR Register
RapidIO Port-Write-In Capture 3 CSR Register
Reserved
02D1 2014
02D1 2018
02D1 201C
02D1 2020 - 02D1 3FFC
02D1 4000
RIO_SP0_RST_OPT
RIO_SP0_CTL_INDEP
RIO_SP0_SILENCE_TIMER
RapidIO Port 0 Reset Option CSR Register
RapidIO Port 0 Control Independent Register
RapidIO Port 0 Silence Timer Register
02D1 4004
02D1 4008
RapidIO Port 0 Multicast-Event Control Symbol Request
Register
02D1 400C
RIO_SP0_MULT_EVNT_CS
02D1 4010
02D1 4014
-
Reserved
RIO_SP0_CS_TX
-
RapidIO Port 0 Control Symbol Transmit Register
Reserved
02D1 4018 - 02D1 40FC
02D1 4100
RIO_SP1_RST_OPT
RIO_SP1_CTL_INDEP
RIO_SP1_SILENCE_TIMER
RapidIO Port 1 Reset Option CSR Register
RapidIO Port 1 Control Independent Register
RapidIO Port 1 Silence Timer Register
02D1 4104
02D1 4108
RapidIO Port 1 Multicast-Event Control Symbol Request
Register
02D1 410C
RIO_SP1_MULT_EVNT_CS
02D1 4110
02D1 4114
-
Reserved
RIO_SP1_CS_TX
-
RapidIO Port 1 Control Symbol Transmit Register
Reserved
02D1 4118 - 02D1 41FC
02D1 4200
RIO_SP2_RST_OPT
RIO_SP2_CTL_INDEP
RIO_SP2_SILENCE_TIMER
RapidIO Port 2 Reset Option CSR Register
RapidIO Port 2 Control Independent Register
RapidIO Port 2 Silence Timer Register
02D1 4204
02D1 4208
RapidIO Port 2 Multicast-Event Control Symbol Request
Register
02D1 420C
02D1 4210
RIO_SP2_MULT_EVNT_CS
-
Reserved
174
C6455 Peripheral Information and Electrical Specifications
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-88. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D1 4214
ACRONYM
RIO_SP2_CS_TX
-
REGISTER NAME
RapidIO Port 2 Control Symbol Transmit Register
Reserved
02D1 4218 - 02D1 42FC
02D1 4300
RIO_SP3_RST_OPT
RIO_SP3_CTL_INDEP
RIO_SP3_SILENCE_TIMER
RapidIO Port 3 Reset Option CSR Register
RapidIO Port 3 Control Independent Register
RapidIO Port 3 Silence Timer Register
02D1 4304
02D1 4308
RapidIO Port 3 Multicast-Event Control Symbol Request
Register
02D1 430C
RIO_SP3_MULT_EVNT_CS
02D1 4310
02D1 4314
-
Reserved
RIO_SP3_CS_TX
RapidIO Port 3 Control Symbol Transmit Register
02D1 4318 - 02D2 0FFF
02D2 1000 - 02DF FFFF
-
-
Reserved
Reserved
6.24.3 Serial RIO Electrical Data/Timing
The TMS320C6455 Serial Rapid IO (SRIO) Hardware Designer's Resource Guide Application Report
(Literature Number SPRAAA8) specifies a complete printed circuit board (PCB) solution for the C6455 as
well as a list of compatible SRIO devices showing two DSPs connected via a 4x SRIO link. TI has
performed the simulation and system characterization to ensure all SRIO interface timings in this solution
are met; therefore, no electrical data/timing information is supplied here for this interface.
TI only supports designs that follow the board design guidelines outlined in the Implementing
Serial RapidIO (SRIO) PCB Layout on a TMS320C6455 Hardware Design Application Report
(Literature number SPRAAA8) [Document Release Pending].
6.25 General-Purpose Input/Output (GPIO)
6.25.1 GPIO Device-Specific Information
On the C6455 the GPIO peripheral pins GP[TBD:TBD] are muxed with the UTOPIA, PCI, and McBSP1
peripheral pins and the SYSCLK3 signal. For more detailed information on device/peripheral configuration
and the C6455 device pin muxing, see the Device Configurations section of this data sheet.
6.25.2 GPIO Peripheral Register Descrption(s)
Table 6-89. GPIO Registers
HEX ADDRESS RANGE
02B0 0000
ACRONYM
PID
REGISTER NAME
GPIO peripheral identification register [value: 0xTBD]
GPIO peripheral control register
GPIO interrupt per bank enable register
Reserved
02B0 0004
PCR
02B0 0008
GPIO_BINTEN
-
02B0 000C
02B0 0010
GPIO_DIR
GPIO direction register
02B0 0014
GPIO_OUT_DATA
GPIO_SET_DATA
GPIO_CLR_DATA
GPIO_IN_DATA
GPIO_RIS_TRIG
GPIO_FAL_TRIG
GPIO output data register
02B0 0018
GPIO set data register
02B0 001C
02B0 0020
GPIO clear data register
GPIO input data register
02B0 0024
GPIO rising edge interrupt register
GPIO falling edge interrupt register
02B0 0028
C6455 Peripheral Information and Electrical Specifications
175
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Table 6-89. GPIO Registers (continued)
HEX ADDRESS RANGE
02B0 002C
ACRONYM
REGISTER NAME
GPIO interrupt status register
GPIO_INSTAT
02B0 0030 - 02B0 008C
02B0 0090 - 02B0 00FF
02B0 0100 - 02B0 3FFF
-
-
-
Reserved
Reserved
Reserved
176
C6455 Peripheral Information and Electrical Specifications
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
6.25.3 GPIO Electrical Data/Timing
Table 6-90. Timing Requirements for GPIO Inputs(1)(2) (see Figure 6-66)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
tw(GPIH)
tw(GPIL)
Pulse duration, GPIx high
Pulse duration, GPIx low
12P
12P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize
the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP
enough time to access the GPIO register through the CFGBUS.
Table 6-91. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs(1)
(see Figure 6-66)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
3
4
tw(GPOH)
tw(GPOL)
Pulse duration, GPOx high
Pulse duration, GPOx low
36P – 8(2)
36P – 8(2)
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
2
1
GPIx
4
3
GPOx
Figure 6-66. GPIO Port Timing
C6455 Peripheral Information and Electrical Specifications
177
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
6.26 IEEE 1149.1 JTAG
The JTAG interface is used for BSDL testing and emulation of the DSP device.
6.26.1 JTAG Device-Specific Information
6.26.1.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6455 DSP includes an internal pulldown (IPD) on the TRST pin to ensure
that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be
properly initialized.
6.26.2 JTAG Peripheral Register Description(s)
6.26.3 JTAG Electrical Data/Timing
Table 6-92. Timing Requirements for JTAG Test Port (see Figure 6-67)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
3
4
tc(TCK)
Cycle time, TCK
35
10
9
ns
ns
ns
tsu(TDIV-TCKH)
th(TCKH-TDIV)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
Table 6-93. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 6-67)
-720
-850
-1000
MIN
-3
NO.
PARAMETER
UNIT
MAX
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
18
ns
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 6-67. JTAG Test-Port Timing
178
C6455 Peripheral Information and Electrical Specifications
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
Revision History
This data sheet revision history highlights the technical changes made to the SPRS276 device-specific
data sheet to make it an SPRS276A revision.
Scope: Applicable updates to the C64x device family, specifically relating to the TMS320C6455 device,
have been incorporated. The TMS320C6455 device is at the product preview (PP) stage of development
(see ADDS/CHANGES/DELETES).
Continued incorporation of new format/outline structure. Updated/corrected device-specific information for
clarity.
SEE
ADDS/CHANGES/DELETES
Global Change
Updated document outline structure
Moved all Peripheral Register Descriptions to C64x+ Peripheral Information and Electrical Specifications
section
Features:
Updated Features List
Description:
Updated section
Device Overview, CPU (DSP Core) Description:
Updated section
Bootmode:
Updated/Moved the section
Deleted Bootmode Types not supported
Device Configuration:
Updated section
Added PRI_ALLOC register section
Terminal Functions table:
Updated/Changed the specified default functions
Added pin numbers
C64x+ Peripheral Information and Electrical Specifications Section:
Updated/Changed the section to include electrical data/timing
Revision History
179
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276A–MAY 2005–REVISED JULY 2005
7 Mechanical Data
7.1 Thermal Data
The following table(s) show the thermal resistance characteristics for the PBGA - ZTZ mechanical
package.
Table 7-1. Thermal Resistance Characteristics (S-PBGA Package) [ZTZ]
NO
1
°C/W
1.45
8.34
16.1
13.0
11.9
10.7
0.37
0.89
1.01
1.17
7.6
Air Flow (m/s(1)
)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
N/A
N/A
0.00
1.0
2
3
4
RΘJA
PsiJT
PsiJB
Junction-to-free air
Junction-to-package top
Junction-to-board
5
2.0
6
3.0
0.00
1.0
7
8
1.5
3.00
0.00
1.0
6.7
6.4
1.5
5.8
3.00
(1) m/s = meters per second
7.2 Packaging Information
The following packaging information and addendum reflect the most current released data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
180
Mechanical Data
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TMX320C6455ZTZ
TMX320C6455ZTZ7
TMX320C6455ZTZ8
ACTIVE
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
ZTZ
697
697
697
1
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
ZTZ
ZTZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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相关型号：
TMX320C6455ZTZ720
IC 64-BIT, 66.67 MHz, OTHER DSP, PBGA697, 24 X 24 MM, 0.80 MM PITCH, PLASTIC, BGA-697, Digital Signal Processor
TI
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