TNETE100APGE [TI]
PCI ETHERNETE CONTROLLER SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN;
| 型号： | TNETE100APGE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PCI ETHERNETE CONTROLLER SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN 局域网 局域网（LAN）标准 以太网：16GBASE-T PC |
| 文件： | 总26页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
Single-Chip Ethernet Controller for the
Integrated 10 Base-T, and 10 Base-5
Arithmetic Unit Interface (AUI)
Physical-Layer Interface
– Single-Chip IEEE 802.3 and Blue Book
Ethernet-Compliant Solution
– DSP-Based Digital Phase-Locked Loop
– Smart Squelch Allows for Transparent
Link Testing
Peripheral Component Interconnect (PCI)
Local Bus
†
– 32-Bit PCI Glueless Host Interface
– Compliant With PCI Local-Bus
Specification (Revision 2.0)
– 0-MHz to 33-MHz Operation
– 3-V or 5-V I/O Operation
– Adaptive Performance Optimization
(APO) by Texas Instruments (TI ) for
Highest Available PCI Bandwidth
– High-Performance Bus Master
Architecture With Byte-Aligning Direct
Memory Access (DMA) Controller for
Low Host CPU and Bus Utilization
– Plug-and-Play Compatible
– Transmission Waveshaping
– Autopolarity (Reverse Polarity
Correction)
– External/Internal Loopback Including
Twisted Pair and AUI
– 10 Base-2 Supported Through AUI
Interface
Media-Independent Interface (MII) for
Connecting 100-Mbps External
Transceivers
– Compliant MII for IEEE 802.3u
Transceivers
Supports 32-Bit Data Streaming on PCI Bus
– Time-Division Multiplexed Static
Random-Access Memory (SRAM)
– 2-Gbps Internal Bandwidth
– Supports 100 Base-TX, 100 Base-T4, and
100 Base-FX
– Super Set Supports IEEE 802.12
Transceivers
– Supports Ethernet and Token-Ring
Framing Formats for 100VG-AnyLAN
– Link-Pulse Detection for Determining
Wire Rate
Driver Compatible With All Previous
ThunderLAN Components
Switched Ethernet Compatible
Full-Duplex Compatible
– Independent Transmit and Receive
Channels
– Two Transmit Channels for Demand
Priority
Low-Power CMOS Technology
– Green PC Compatible
– Microsoft Advanced Power
Management
Supports Multiple Protocols With a Single
Driver Suite–Optimized Shared Interrupts
No On-Board Memory Required
Auto-Negotiation (N-Way) Compatible
Multimedia-Ready Architecture
EEPROM Interface Supports Jumperless
Design and Autoconfiguration
Hardware Statistics Registers for
Management-Information Base (MIB)
Supports the Card-Bus Card Information
Structure (CIS) Pointer Register
DMTF (Desktop Management Task Force)
Compatible
‡
IEEE Standard 1149.1 Test-Access Port
(JTAG)
144-Pin Quad Flat Packages (PCM Suffix)
and Thin Quad Flat Packages (PGE Suffix)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
‡
The PCI Local-Bus Specification, Revision 2.0 should be used as a reference with this document.
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
ThunderLAN, Adaptive Performance Optimization, and TI are trademarks of Texas Instruments Incorporated.
Ethernet is a registered trademark of Xerox Corporation.
Microsoft is a registered trademark of Microsoft Corp.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
10 Base-T
Physical
Layer
10 Base-T
Ethernet
FIFO
Registers
Ethernet
LAN
Controller
10/100 Mbps
10 Base-5
(AUI)
PCI
Bus Master
Control
Interface
PCI
Bus
Multiplexed
SRAM
Media-
Independent
Interface
FIFO
Figure 1. ThunderLAN Architecture
description
ThunderLAN is a high-speed networking architecture that provides a complete PCI-to-10 Base-T/AUI Ethernet
solution with the flexibility to handle 100-Mbps Ethernet protocols as networking demands grow.
The TNETE100A, an implementation of the ThunderLAN architecture, is an intelligent protocol network
interface. The ThunderLAN SRAM FIFO-based architecture eliminates the need for external memory and offers
a single-chip glueless PCI-to-10 Base-T/AUI (IEEE 802.3) solution with an on-board physical layer interface.
Modular support for 100 Base-T (IEEE 802.3u), and 100VG-AnyLAN (IEEE 802.12) is provided by a superset
of the industry-standard media independent interface (MII). ThunderLAN uses a single driver suite to support
multiple networking protocols.
The glueless PCI interface supports 32-bit streaming, operates at speeds up to 33 MHz and is capable of
internal data-transfer rates up to 2 Gbps, taking full advantage of all available PCI bandwidth. The TNETE100A
offers jumperless autoconfiguration using PCI configuration read/write cycles. Customizable configuration
registers, which can be autoloaded from an external serial EEPROM, allow designers of TNETE100A-based
systems to give their systems a unique identification code. The TNETE100A PCI interface, developed in
conjunction with other leaders in the semiconductor and computer industries, has been tested vigorously on
multiple platforms to ensure compatibility across a wide array of available PCI products. In addition, the
ThunderLAN drivers and ThunderLAN architecture use TI’s patented adaptive performance optimization (APO)
technology to adjust dynamically critical parameters for minimum latency, minimum host CPU utilization, and
maximum system performance. This technology ensures that the maximum capabilities of the PCI interface are
used by automatically tuning the controller to the specific system in which it is operating.
The MII, an industry-standard interface for connecting a variety of external IEEE 802.3u physical layer
interfaces, is supported fully by the TNETE100A. In addition, the TNETE100A features an IEEE
802.12-compliant superset of the MII to allow for support of 100VG-AnyLAN physical layer interfaces. This
allows TNETE100A-based systems to support 100 Base-TX, 100 Base-FX, 100 Base-T4, and 100VG-AnyLAN
cabling schemes for maximum flexibility as each new physical-layer interface becomes available in the
marketplace.
An intelligent protocol handler (PH) implements the serial protocols of the network. The PH is designed for
minimum overhead related to multiple protocols, using common state machines to implement 95 percent of the
total PH. On transmit, the PH serializes data, adds framing and cyclic redundancy check (CRC) fields, and
interfaces to the network physical layer (PHY) chip. On receive, it provides address recognition, CRC and error
checking, frame disassembly, and deserialization. Data for multiple channels is passed to and from the PH by
way of circular-buffer FIFOs in the FIFO SRAM.
ThunderLAN is the first multimedia-ready architecture and is capable of prioritized data regardless of the
selected protocol. The demand-priority protocol supports two priorities of frames: normal and priority. The two
transmit channels provide independent host channels for these two frame types. Carrier-sense multiple access
with collision detection (CSMA/CD) protocols only support a single priority of frame, but the two channels can
be used to prioritize network access. All received frames pass through the single receive-channel.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
description (continued)
Compliant with IEEE Standard 1149.1 (JTAG), the TNETE100A provides a five-pin test-access port that is used
for boundary-scan testing.
The TNETE100A is available in a 144-pin thin quad flat package and quad flat package.
differences between TNETE100 and TNETE100A:
The TNETE100A implements the CIS pointer register as defined in the PC card standard. This register can be
found in the PCI configuration registers at offset 28h. For other differences between the TNETE100 and
TNETE100A, consult the ThunderLAN Programmer’s Guide (literature number SPWU013).
pin assignments
PCM AND PGE PACKAGES
(TOP VIEW)
PAD24
PC/BE3
ARCVN
1
108
107
106
105
104
103
102
101
100
99
2
V
DDR
V
ARCVP
FRCVN
3
SSI
PIDSEL
PAD23
4
V
5
DDR
V
FRCVP
6
DDI
PAD22
PAD21
PAD20
V
7
SSR
V
8
SST
AXMTN
AXMTP
FXMTN
FXMTP
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SSI
98
PAD19
PAD18
PAD17
97
96
V
DDT
95
V
MRST
DDI
94
PAD16
PC/BE2
V
MDIO
DDL
93
92
PFRAME
V
SSL
91
V
MDCLK
MRXER
MRXDV
SSL
90
PIRDY
PTRDY
89
88
PDEVSEL
V
SSI
87
V
MRXD3
MRXD2
MRXD1
DDL
86
PSTOP
PPERR
PSERR
85
84
V
DDL
83
V
MRXD0
MRCLK
MCRS
MCOL
SSI
82
PPAR
PC/BE1
PAD15
PAD14
81
80
79
V
DDL
78
V
MTXER
MTXEN
MTXD3
SSI
77
PAD13
PAD12
76
75
V
V
DDI
SSL
74
PAD11
PAD10
MTXD2
MTXD1
73
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
functional block diagram
TNETE100A
(ThunderLAN)
TRST
AXMTP
AXMTN
ARCVP
ARCVN
ACOLP
ACOLN
FXMTP
FXMTN
FRCVP
FRCVN
FXTL1
TMS
TCLK
TDO
TDI
IEEE
1149.1
Test-
Access
Port
Test-Access
Port
AUI
Interface
(TAP)
10-Mbps
Ethernet
Physical
Layer
(PHY)
Interface
PCI
Interface
PCIIF
Config
& I/O
Memory
Registers
10 Base-T
Interface
FXTL2
Configuration
EEPROM
EDCLK
EDIO
S
l
FIREF
Config
EEPROM
Interface
a
Interface
v
FATEST
e
EAD[7:0]
FPREGs
(FIFO
Pointer
BIOS ROM
and
MTCLK
MTXEN
MTXER
MCOL
BIOS
ROM/LED
Driver
EXLE
EALE
EOE
LED I/F
Registers)
Interface
PAD[31:0]
MTXD[3:0]
MRXD[3:0]
Protocol
Handler
(PH)
Address
and Data
FSRAM
(FIFO SRAM)
PC/BE[3:0]
PPAR
MII
MCRS
MRCLK
MRXDV
MRXER
MDCLK
MDIO
3
128
Byte List
MII
PFRAME
PTRDY
PIRDY
64
64
1.5K-Byte
Rx Buffer
Interface
Control
M
a
s
t
e
r
0.75K-Byte
Tx Buffer
PSTOP
DMA
Controller
PDEVSEL
PIDSEL
MRST
0.75K-Byte
Tx Buffer
PPERR
PSERR
Error
Reporting
PREQ
PGNT
Bus
Arbitration
PCLK
PCLKRUN
PRST
System
Control
PINTA
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
Pin Functions
DESCRIPTION
TEST PORT
PIN
NAME
†
TYPE
NO.
Test clock. TCLK is used to clock state information and test data into and out of the device during
operation of the test port.
TCLK
124
126
125
I
I
Test data input. TDI is used to shift test data and test instructions serially into the device during
operation of the test port.
TDI
Test data output. TDO is used to shift test data and test instructions serially out of the device during
operation of the test port.
TDO
O
TMS
123
121
I
I
Test mode select. TMS is used to control the state of the test port controller within TNETE100A.
Test reset. TRST is used for asynchronous reset of the test port controller.
TRST
PCI INTERFACE
PAD31
PAD30
PAD29
PAD28
PAD27
PAD26
PAD25
PAD24
PAD23
PAD22
PAD21
PAD20
PAD19
PAD18
PAD17
PAD16
PAD15
PAD14
PAD13
PAD12
PAD11
PAD10
PAD9
135
137
138
140
141
143
144
1
I/O
I/O
I/O
PCI address/data bus. Byte 3 (most significant) of the PCI address/data bus.
5
7
8
9
PCI address/data bus. Byte 2 of the PCI address/data bus.
11
12
13
15
29
30
32
33
35
36
38
39
PCI address/data bus. Byte 1 of the PCI address/data bus.
PAD8
†
I = input, O = output, I/O = 3-state input/output
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
Pin Functions (Continued)
PIN
NAME
†
DESCRIPTION
PCI INTERFACE (CONTINUED)
TYPE
NO.
PAD7
42
43
45
46
47
49
50
51
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
PAD0
I/O
PCI address/data bus. Byte 0 (least significant) of the PCI address/data bus.
PCI clock. PCLK is the clock reference for all PCI bus operations. All other PCI pins except PRST and
PINTA are sampled on the rising edge of PCLK. All PCI bus timing parameters are defined with respect
to this edge.
PCLK
131
53
I
Clock run control. PCLKRUN is the active-low PCI clock request/grant signal that allows the
TNETE100A to indicate when an active PCI clock is required. (This is an open drain.)
‡
I/O
PCLKRUN
PC/BE3
PC/BE2
PC/BE1
PC/BE0
2
PCI bus command and byte enables:PC/BE3 enables byte 3 (MSbyte) of the PCI address/data bus.
PC/BE2 enables byte 2 of PCI address/data bus.
16
28
41
I/O
PC/BE1 enables byte 1 of PCI address/data bus.
PC/BE0 enables byte 0 (LSbyte) of PCI address/data bus.
PCI device select. PDEVSEL indicates that the driving device has decoded one of its addresses as
the target of the current access. The TNETE100A drives PDEVSEL when it decodes an access to one
of its registers. As a bus master, the TNETE100A monitors PDEVSEL to detect accesses to illegal
memory addresses.
PDEVSEL
PFRAME
21
17
I/O
I/O
PCI cycle frame. PFRAME is driven by the active bus master to indicate the beginning and duration
of an access. PFRAME is asserted to indicate the start of a bus transaction and remains asserted
during the transaction, only being deasserted in the final data phase.
PCI bus grant. PGNT is asserted by the system arbiter to indicate that the TNETE100A has been
granted control of the PCI bus.
PGNT
132
4
I
I
PIDSEL
PINTA
PCI initialization device select. PIDSEL is the chip select for access to PCI configuration registers.
PCI interrupt. PINTA is the interrupt request from the TNETE100A. PCI interrupts are shared, so this
is an open-drain (wired-OR) output.
128
O/D
PCI initiator ready. PIRDY is driven by the active bus master to indicate that it is ready to complete the
current data phase of a transaction. A data phase is not completed until both PIRDY and PTRDY are
sampled asserted. When the TNETE100A is a bus master, it uses PIRDY to align incoming data on
reads or outgoing data on writes with its internal RAM-access synchronization (maximum one cycle
at the beginning of burst). When the TNETE100A is a bus slave, it extends the access appropriately
until both PIRDY and PTRDY are asserted.
PIRDY
19
20
I/O
I/O
PCI target ready. PTRDY is driven by the selected device (bus slave or target) to indicate that it is ready
to complete the current data phase of a transaction. A data phase is not completed until both PIRDY
and PTRDY are sampled asserted.
PTRDY
ThunderLAN uses PTRDY to ensure every direct I/O (DIO) operation is correctly interlocked.
PCI parity. PPAR carries even parity across PAD[31:0] and PC/BE[3:0]. It is driven by the TNETE100A
during all address and write cycles as a bus master and during all read cycles as a bus slave.
PPAR
27
24
I/O
I/O
PPERR
PCI parity error. PPERR indicates a data parity error on all PCI transactions except special cycles.
†
‡
I = input, I/O = 3-state input/output, O/D = open-drain output
Open drain
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
Pin Functions (Continued)
PIN
NAME
†
DESCRIPTION
PCI INTERFACE (CONTINUED)
TYPE
NO.
PCI bus request. PREQ is asserted by the TNETE100A to request control of the PCI bus. This is not
a shared signal.
PREQ
134
I/O
PRST
129
25
I
PCI reset signal
PSERR
PSTOP
O/D
I/O
PCI system error. PSERR indicates parity errors or special cycle data parity errors.
PCI stop. PSTOP indicates the current target is requesting the master to stop the current transaction.
23
BIOS ROM/LED DRIVER INTERFACE
EPROM address/data. EAD[7:0] is a multiplexed byte-bus that is used to address and read data from
an external BIOS ROM.
EAD7
EAD6
EAD5
EAD4
EAD3
EAD2
EAD1
EAD0
54
55
56
57
59
60
61
62
•
•
•
On the cycle when EXLE is asserted low, EAD[7:0] is driven with the high byte of the
address.
On the cycle when EALE is asserted low, EAD[7:0] is driven with the low byte of the
address.
When EOE is asserted, BIOS ROM data should be placed on the bus.
I/O
These pins also can be used to drive external-status LEDs. Low-current (2–5 mA) LEDs can be
connected directly (through appropriate resistors). High-current LEDs can be driven through buffers
or from the BIOS ROM address latches.
EPROM address latch enable. EALE is driven low to latch the low (least significant) byte of the BIOS
ROM address from EAD[0:7].
EALE
EOE
65
64
66
O
O
O
EPROM output enable. When EOE is active (low), EAD[0:7] is in the high-impedance mode and the
output of the BIOS ROM should be placed on EAD[0:7].
EPROM extended address latch enable. EXLE is driven low to latch the high (most significant) byte
of the BIOS ROM address from EAD[0:7].
EXLE
CONFIGURATION EEPROM INTERFACE
EEPROM data clock. EDCLK transfers serial clocked data to the 2K-bit serial EEPROMs (24C02) (see
Note 1). EDCLK requires an external pullup for EEPROM operation.
EDCLK
EDIO
68
69
O
EEPROM data I/O. EDIO is the bidirectional serial data/address line to the 2K-bit serial EEPROM
(24C02). EDIO requires an external pullup for EEPROM operation. Tying EDIO to ground disables the
EEPROM interface and prevents autoconfiguration of the PCI configuration register.
I/O
MEDIA-INDEPENDENT INTERFACE (100-Mbps CSMA/CD AND DEMAND PRIORITY)
Collision sense
•
•
In CSMA/CD mode, assertion of MCOL indicates a network collision.
In demand-priority mode, MCOL (active low) is used to acknowledge a transmission request.
The TNETE100A begins frame transmission 50 MTCLK cycles after the assertion (low) of
MCOL.
MCOL
80
I
MCRS
81
91
I
Carrier sense. MCRS indicates a frame-carrier signal is being received.
Management data clock. MDCLK is part of the serial management interface to physical-media
independent (PMI)/PHY chip.
MDCLK
O
MDIO
93
82
95
I/O
I
Management data I/O. MDIO is part of the serial management interface to PMI/PHY chip.
Receive clock. MRCLK is the receive clock source from the attached PHY and PMI device.
MII reset. MRST is the reset signal to the PMI/PHY front-end (active low).
MRCLK
MRST
O
†
I = input, O = output, I/O = 3-state input/output, O/D = open-drain output
NOTE 1: This pin should be tied to V
DD
with a 4.7-k – 10-k pullup resistor.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
Pin Functions (Continued)
PIN
NAME
†
DESCRIPTION
TYPE
NO.
MEDIA-INDEPENDENT INTERFACE (100-Mbps CSMA/CD AND DEMAND PRIORITY) (CONTINUED)
Receive data. MRXD[3:0] is the nibble-receive data from the physical-media dependent (PMD)
MRXD0
83
85
86
87
front end. In demand-priority mode, ThunderLAN reads the frame priority of incoming frames on these
pins on the cycle before assertion of MRXDV (the cycle before frame reception begins).
MRXD1
MRXD2
MRXD3
I
•
MRXD1 indicates the transmission priority of the received frame. A value of zero indicates
normal transmission, and a value of one indicates priority transmission.
Data on these pins is always synchronous to MRCLK.
MRXDV
MRXER
MTCLK
89
90
71
I
I
I
Receive data valid. MRXDV indicates data on MRXD[3:0] is valid.
Receive error. MRXER indicates reception of a coding error on received data.
Transmit clock. MTCLK is the transmit clock source from the attached PHY and PMI device.
Transmit data. MTXD[3:0] is the nibble-transmit data from TNETE100A. When MTXEN is asserted,
these pins carry transmit data. In demand-priority mode, the TNETE100A drives the request state of
the controller on these pins when MTXEN is not asserted (frame transmission not in progress).
MTXD0
MTXD1
MTXD2
MTXD3
72
73
74
76
•
•
MTXD0 asserted indicates the TNETE100A is requesting frame transmission.
MTXD1 indicates the transmission priority required. A value of zero indicates normal
transmission, and a value of one indicates high-priority transmission.
O
Data on these pins is always synchronous to MTCLK.
MTXER
MTXEN
78
77
O
O
Transmit error. MTXER allows coding errors to be propagated across the MII.
Transmit enable. MTXEN indicates valid transmit data on MTXD[3:0].
NETWORK INTERFACE (10 Base-T AND AUI)
ACOLN
ACOLP
111
109
AUI receive pair. ACOLN and ACOLP are differential line receiver inputs and connect to receive pair
through transformer isolation, etc.
A
A
A
ARCVN
ARCVP
108
106
AUI receive pair. ARCVN and ARCVP are differential line receiver inputs and connect to receive pair
through transformer isolation, etc.
AXMTP
AXMTN
99
100
AUI transmit pair. AXMTP and AXMTN are differential line-transmitter outputs.
Analog test pin. FATEST provides access to the filter of the reference PLL. This pin must be left as a
“no connect”.
FATEST
FIREF
118
116
120
A
A
A
Current reference. FIREF is used to set a current reference for the analog circuitry.
Front-end only pin. When FONLY is tied high, all TNETE100A functions other than the on-chip front
end are disabled. The MII pins allow the PHY to be used as a standalone 10 Base-T front end.
FONLY
FRCVN
FRCVP
105
103
10 Base-T receive pair. FRCVN and FRCVP are differential line-receiver inputs and connect to receive
pair through transformer isolation, etc.
A
A
A
FXTL1
FXTL2
113
114
Crystal oscillator pins. FXTL1 is driven from a 20-MHz crystal oscillator module.
10 Base-T transmit pair. FXMTP and FXMTN are differential line-transmitter outputs.
FXMTP
FXMTN
97
98
†
I = input, O = output, A = Analog
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
Pin Functions (Continued)
PIN
†
DESCRIPTION
TYPE
NAME
NO.
POWER
6, 14,
34, 48,
122, 136,
142
PCI V
DD
pins. V
DDI
pins provide power for the PCI I/O pin drivers. Connect V
supply when using 5-V signals on the PCI bus. Connect V
3-V signals on the PCI bus
pins to a 5-V power
DDI
pins to a 3-V power supply when using
DDI
V
V
PWR
PWR
DDI
22, 37,
58, 70,
79, 84,
94, 130
Logic V
DD DDL
be connected to a 5-V power supply.
pins (5 V). V
pins provide power for internal TNETE100A logic, and they should always
DDL
V
V
115
PWR
PWR
Analog power pin. V
Analog power pin. V
Analog power pin. V
is the 5-V power for the crystal oscillator circuit.
DDOSC
DDOSC
104
107
is the 5-V power for the receiver circuitry.
DDR
DDR
V
V
96
PWR
PWR
is the 5-V power for the transmitter circuitry.
DDT
DDT
117
Analog power pin. V
is the 5-V power for the voltage controller oscillator (VCO) and filter input.
DDVCO
DDVCO
3, 10, 26,
31, 40,
52, 67,
88, 127,
139
V
SSI
PWR
PCI I/O ground pins
18, 44,
63, 75,
92, 133
V
SSL
PWR
Logic ground pins
V
V
112
PWR
PWR
Analog power pin. Ground for crystal oscillator circuit
Analog power pin. Ground for receiver circuitry
SSOSC
102
110
SSR
V
V
101
119
PWR
PWR
Analog power pin. Ground for transmitter circuitry
Analog power pin. Ground for VCO and filter input
SST
SSVCO
†
PWR = power
architecture
The major blocks of the TNETE100A include the PCI interface (PCIIF), protocol handler (PH), media
independent interface (MII), physical layer (PHY), FIFO pointer registers (FPREGS), FIFO SRAM (FSRAM),
and a test-access port (TAP). The functionality of these blocks is described in the following sections.
PCI interface (PCIIF)
The TNETE100A PCIIF contains a byte-aligning DMA controller that allows frames to be fragmented into any
byte length and transferred to any byte address while supporting 32-bit data streaming. For multipriority
networks, it can provide multiple data channels, each with separate lists, commands, and status. Data for the
channels is passed to and from the PH by way of circular buffer FIFOs in the SRAM, controlled through FIFO
registers. The configuration EEPROM interface (CEI), BIOS ROM/LEDdriver interface (BRI), configuration and
I/O memory registers (CIOREGS), and DMA controller are subblocks of the PCIIF. The features of these
subblocks are described in the following subsections.
configuration EEPROM interface (CEI)
The CEI provides a means for autoconfiguration of the PCI configuration registers. Certain registers in the PCI
configuration space can be loaded using the CEI. Autoconfiguration allows builders of TNETE100A-based
systems to customize the contents of these registers to identify their own system, rather than to use the TI
defaults. The EEPROM is read at power up and can then be read from, and written to, under program control.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
BIOS ROM/LED driver interface (BRI)
The BRI addresses and reads data from an external BIOS ROM through a multiplexed byte-wide bus. The ROM
address/data pins also can be multiplexed to drive external status LEDs.
configuration and I/O memory registers (CIOREGS)
The CIOREGS reside in the configuration space, which is 256 bytes in length. The first 64 bytes of the
configuration space comprise the header region, which is defined explicitly by the PCI standard.
DMA controller (DMAC)
The DMAC is responsible for coordinating TNETE100A requests for mastership of the PCI bus. The DMAC
provides byte-aligning DMA control, allowing byte-size fragmented frames to be transferred to any byte address
while supporting 32-bit data streaming.
protocol handler (PH)
The PH implements the serial protocols of the network. On transmit, it serializes data, adds framing and CRC
fields, and interfaces to the network PHY. On receive, it provides address recognition, CRC and error checking,
frame disassembly, and deserialization. Data for multiple channels is passed to and from the PH by way of
circular buffer FIFOs in the FSRAM controlled through FPREGS. The PH supports an MII that is compatible with
the IEEE 802.12 and IEEE 802.3u logic.
media-independent interface (MII)
The MII provides both MAC-level 100 Base-T (IEEE 802.3u) and 100VG-AnyLAN (IEEE 802.12) controller
functions to external PHY chips that handle the PHY functions for 100-Mbps CSMA/CD and demand priority.
The MII also is used to communicate with the on-chip 10 Base-T PHY which is located at address 0x1F.
10 Base-T physical layer (PHY)
The PHY acts as an on-chip front-end providing physical layer functions for 10 Base-5 (AUI), 10 Base-2 and
10 Base-T (twisted pair). The PHY provides Manchester encoding/decoding from MII nibble-format data, smart
squelch, jabber detection, link pulse detection, autopolarity control, 10 Base-T transmission waveshaping, and
antialiasing filtering. Connection to the AUI drop cable for the 10 Base-T twisted pair is made through simple
isolation transformers (see Figure 2) and no external filter networks are required. Suitable external termination
components allow the use of either shielded or unshielded twisted-pair cable (150 or 100 ). Some of the
key features of the on-chip PHY are listed as follow:
Integrated filters
Integrated MII, including encoder/decoder
10 Base-T transceiver
AUI transceiver
10 Base-2 transceiver
Autopolarity (reverse polarity correction)
Loopback for twisted pair and AUI
Full-duplex mode for simultaneous 10 Base-T transmission and reception
Low power
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
10 Base-T physical layer (PHY) (continued)
FXMTP
FXMTN
FRCVP
RJ-45
PCI
TNETE100A
FRCVN
Figure 2. Schematic for 10 Base-T Network Interface Using TNETE100A
FIFO pointer registers (FPREGS)
The FPREGS are used to implement circular buffer FIFOs in the SRAM. They are a collection of pointer and
counter registers used to maintain the FIFO operation. Both the PCIIF and PH use FPREGS to determine where
to read or write data in the SRAM and to determine how much data the FIFO contains. Unique receive and
transmit FIFO registers are needed for each data channel supported.
FIFO SRAM (FSRAM)
The FSRAM is a conventional SRAM array accessed synchronously to the PCI bus clock. Access to the RAM
is allocated on a time-division multiplexed (TDM) basis, rather than through a conventional shared bus. This
removes the need for bus arbitration and provides ensured bandwidth. Half of the RAM accesses (every other
cycle) are allocated to the PCI controller. It has a 64-bit access port to the RAM, giving it 1 Gbps of bandwidth,
sufficient to support 32-bit data streaming on the PCI bus. The PH has one-quarter of the RAM accesses, and
its port may be up to 64 bits wide. A 64-bit port for the PH provides 512 Mbps of bandwidth, more than sufficient
for a full-duplex 100-Mbps network. The remaining RAM accesses can be allocated toward providing even more
PH bandwidth. The RAM is accessible also (for diagnostic purposes) from the TNETE100A internal data bus.
Host DIO (mapped I/O) accesses are used by the host to access internal TNETE100A registers and for
controller test.
Features of the FIFO SRAM include:
3.375K bytes of FSRAM
–
–
–
1.5K-byte FIFO for receive
Two 0.75K-byte FIFOs for the two transmit channels
Three 128-byte lists
In one-channel mode, the two transmit channels are combined, providing a single 1.5K-byte FIFO for a
single transmit channel.
Supporting 1.5K bytes of FIFO per channel allows full-frame buffering of Ethernet frames. PCI latency is such
that a minimum of 500 bytes of storage is required to support 100-Mbps LANs.
test-access port (TAP)
Compliant with IEEE Standard 1149.1, the TAP is composed of five pins that are used to interface serially with
the device and the board on which it is installed for boundary-scan testing.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
†
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
DD
Input voltage range (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.15 W
Operating case temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 95°C
Junction-to-ambient package thermal impedance,
airflow = 100 LFPM, T PGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.4°C/W
C
JA(100)
Junction-to-ambient package thermal impedance,
airflow = 0 LFPM, T PGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51°C/W
JA(0)
Junction-to-ambient package thermal impedance,
airflow = 0 LFPM, T PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4°C/W
JA(0)
airflow = 100 LFPM, T
PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38.0°C/W
JA(100)
Junction-to-case package thermal impedance, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.22°C/W
JC
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 2: Voltage values are with respect to V , and all V
SS SS
pins should be routed so as to minimize inductance to system ground.
The recommended operating conditions and the electrical characteristics tables are divided into groups,
depending on pin function:
PCI interface pins
Logic pins
Physical layer pins
The PCI signal pins are operated in one of two modes shown in the PCI tables.
5-V signal mode
3-V signal mode
recommended operating conditions (PCI interface pins only) (see Note 3)
3-V SIGNALING
OPERATION
5-V SIGNALING
OPERATION
UNIT
MIN
NOM
MAX
3.6
MIN NOM
MAX
5.25
+0.5
V
V
V
Supply voltage (PCI)
3
3.3
4.75
2.0
5
V
V
DD
‡
‡
High-level input voltage
0.5
V
DD
V
+0.5
V
DD
IH
DD
0.5
‡
–0.5
‡
‡
Low-level input voltage, TTL-level signal (see Note 4)
–0.5
0.8
–2
V
IL
I
High-level output current
TTL outputs
–0.5
1.5
mA
OH
Low-level output current (see
Note 5)
‡
I
TTL outputs
6
mA
OL
‡
Specified by design SPICE IV Curve (please refer to PCI specification revision 2.1, section 4.2, paragraph 2 for explanation)
NOTES: 3. PCI interface pins include PCLKRUN, PFRAME, PTRDY, PIRDY, PSTOP, PDEVSEL, PIDSEL, PPERR, PSERR, PREQ, PGNT,
PCLK, PPAR, PRST, PINTA, PAD[31:0], and PC/BE[3:0].
4. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels
only.
5. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst
case).
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(PCI interface pins)
3-V SIGNALING
OPERATION
5-V SIGNALING
OPERATION
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
High-level output voltage, TTL-level
signal (see Note 6)
‡
V
V
V
V
= MIN,
I
I
= MAX
0.9
V
DD
2.4
V
V
OH
DD
OH
Low-level output voltage, TTL-level
signal
‡
= MAX,
= MAX
= 0 V
0.1
V
0.5
OL
DD
OL
DD
V
V
= MAX,
= MAX,
V
V
10
10
DD
O
I
High-impedance output current
µA
µA
OZ
= V
–10
– 10
DD
O
DD
Input current, any input or input/out-
put
I
I
V = V
I
to V
10
10
I
SS
DD
Supply current I/O
V
DD
= MAX
50
10
60
10
mA
pF
DD
§
C
Input capacitance, any input
f = 1 MHz,
Others at 0 V
Others at 0 V
i
Output capacitance, any output or
C
f = 1 MHz,
10
10
pF
o
§
input/output
†
‡
§
For conditions shown as MIN/MAX, use the appropriate value specified under the recommended operating conditions.
Assured by SPICE IV Curve (please refer to PCI specification revision 2.1, section 4.2, paragraph 2 for explanation)
Specified by design
NOTE 6: The following signals require an external pullup resistor: PSERR, PINTA.
recommended operating conditions (logic pins) (see Note 7)
MIN NOM
MAX
5.25
+0.3
UNIT
V
V
V
V
Supply voltage (5 V only)
4.75
2
5
DD
High-level input voltage
V
V
IH
DD
Low-level input voltage, TTL-level signal (see Note 4)
High-level output current
–0.3
0.8
–4
4
V
IL
I
TTL outputs
TTL outputs
mA
mA
OH
OL
I
Low-level output current (see Note 5)
NOTES: 4. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels
only.
5. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst
case).
7. Logic pins include V
, EAD[7:0], EXLE, EALE, EOE, EDCLK, EDIO, FONLY, MTCLK, MTXEN, MTXER, MCOL, MTXD[3:0],
DDL
MRXD[3:0], MCRS, MRCLK, MRXDV, MRXER, MDCLK, MDIO, MRST.
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(logic pins)
†
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
V
V
V
High-level output voltage, TTL-level signal
Low-level output voltage, TTL-level signal
V
V
V
V
= MIN,
= MAX,
= MIN,
= MIN,
I
I
= MAX
= MAX
2.4
OH
DD
DD
DD
DD
OH
0.5
10
V
OL
OL
V
V
= V
DD
= 0 V
O
I
O
High-impedance output current
Input current
µA
µA
–10
10
O
I
I
V = V
I
to V
DD
SS
‡
‡
‡
‡
§
100 Mbps
10 Mbps
100 Mbps
10 Mbps
150
190
183
228
210
Supply current @ 25 MHz (PCLK) (See Note 8)
I
V
DD
= NOM/MAX
mA
DD
§
285
Supply current @ 33 MHz (PCLK) (See Note 8)
¶
C
C
Input capacitance, any input
f = 1 MHz,
f = 1 MHz,
Others at 0 V
Others at 0 V
10
10
pF
pF
i
¶
Output capacitance, any output or input/output
o
†
‡
§
¶
For conditions shown as MIN/MAX, use the appropriate value specified under the recommended operating conditions.
Characterized in system test not tested
Characterized but not tested
Specified by design/process
NOTE 8: Actual operating current is less than these maximum values. These maximum values were obtained under specially produced
worst-case test conditions, which are not sustained during normal device operation.
recommended operating conditions (physical layer pins) (see Note 9)
JEDEC
SYMBOL
MIN NOM
4.75
MAX
UNIT
V
DD
Supply voltage
5
5.25
V
NOTE 9: Physical layer pins include V
, V , ACOLN, ACOLP, ARCVN, ARCVP, AXMTP, AXMTN, FATEST, FIREF,
, V
, V
DDOSC DDR DDT DDVCO
FRCVN, FRCVP, FXTL1, FXTL2, FXMTP, and FXMTN.
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(physical interface pins)
10 Base-T receiver input (FRCVP, FRCVN)
JEDEC
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
#
V
Differential input voltage
V
0.6
2.8
4
V
I(DIFF)
ID
#
I
Common-mode current
I
IC
mA
mV
mV
(CM)
V
V
Rising input pair squelch threshold (see Note 10)
Falling input pair squelch threshold
V
V
= V
= V
,
,
See Note 11
See Note 11
360
SQ+
CM
SB
–360
SQ–
CM
SB
#
Refer to recommended operating conditions
NOTES: 10. V
is the voltage level at which input is assured to be seen as data.
is the self-bias voltage of the input pair FRCVP and FRCVN.
SQ
11.
V
SB
10 Base-T transmitter drive characteristics (FXMTP, FXMTN)
JEDEC
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
V
Differential voltage at specified slew rate
Common-mode output voltage
Differential voltage output
V
2.2
0
2.8
4
V
V
SLW
O(CM)
O(DIFF)
O(I)
OD(SLEW)
V
See Figure 3d
OC
OD
V
Into open circuit
5.25
50
V
Output idle differential voltage
V
mV
mA
OD(IDLE)
¶
I
Output current, fault condition
I
300
O(FC)
O(FC)
¶
Specified by design/process
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
AUI receiver input (ARCVP, ARCVN, ACOLP, ACOLN)
JEDEC
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
†
†
V
V
V
Differential input voltage 1
V
V
See Note 12
See Note 13
0
0
3
V
I(DIFF)1
I(DIFF)2
(SQ–)
ID(1)
Differential input voltage 2
100
mV
mV
ID(2)
Falling input pair squelch threshold
–325
†
Refer to recommended operating conditions
NOTES: 12. Common-mode frequency range : 0 Hz to 40 kHz
13. Common-mode frequency range : 40 kHz to 10 MHz
AUI transmitter drive characteristics (AXMTP, AXMTN)
JEDEC
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
‡
V
V
V
Differential output voltage
V
See Note 14
240
1300
50
mV
mV
mV
mA
O(DIFF)1
OI(DIFF)
OI(DIFF)U
O(FC)
OD(1)
†
Output idle differential voltage
Output differential undershoot
V
OD(IDLE)
†§
V
100
150
OD(IDLE)U
‡
I
Output current, fault condition
I
O(FC)
†
‡
§
Refer to recommended operating conditions
Specified by design
Characterized but not tested
NOTE 14: The differential voltage is measured as per Figure 3b.
crystal oscillator characteristics
JEDEC
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
1.7
MAX
2.8
UNIT
V
V
Input self-bias voltage
V
IB
SB(FXTL1)
V
V
= V
= V
(FXTL2)
(FXTL1)
SB(FXTL1)
SB(FXTL1)
I
I
High-level output current (see Note 4)
I
– 1.3
– 5.0
mA
OH(FXTL2)
OH
+ 0.5 V
– 0.5 V
V
V
= V
= V
(FXTL2)
(FXTL1)
SB(FXTL1)
SB(FXTL1)
Low-level output current
I
0.4
1.5
mA
OL(FXTL2)
OL
NOTE 4: Thealgebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels only.
PARAMETER MEASUREMENT INFORMATION
Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels
are compatible with TTL devices.
Output transition times are specified as follows: For a high-to-low transition on either an input or output signal,
the level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low
is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level
at which the signal is said to be high is 2 V, as shown below.
TheriseandfalltimesarenotspecifiedbutareassumedtobethoseofstandardTTLdevices, whicharetypically
1.5 ns.
2 V (high)
0.8 V (low)
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
test measurement
The test-load circuit shown in Figure 3 represents the programmable load of the tester pin electronics that are
used to verify timing parameters of the TNETE100A output signals.
I
OL
50 Ω
Test
Point
AXMTP
AXMTN
Test
Point
TTL
50 Ω
Output
Under
Test
78 Ω
V
LOAD
C
L
X1
I
OH
(b) AXMTP AND AXMTN TEST LOAD (AC TESTING)
X1 – Fil – Mag 23Z90 (1:1)
(a) TTL OUTPUT TEST LOAD
50 Ω
25 Ω
25 Ω
Test
Point
FXMTP
FXMTN
50 Ω
FIREF
180 Ω
X2
(d) FXMTP AND FXMTN TEST LOAD (AC TESTING)
X2 – Fil – Mag 23Z128 (1: √2)
(c) FIREF TEST CIRCUIT
50 Ω
Test
FXMTP
FXMTN
Point
50 Ω
50 Ω
Test
Point
50 Ω
(e) FXMTP AND FXMTN TEST LOAD (DC TESTING)
in recommended operating conditions
Where: I
I
=
=
=
Refer to I
Refer to I
OL
OH
LOAD
OL
OH
in recommended operating conditions
V
1.5 V, typical dc-level verification or
0.7 V, typical timing verification
C
=
18 pF, typical load-circuit capacitance
L
Figure 3. Test and Load Circuit
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
switching characteristics for PCI 5-V and 3.3-V (see Note 15, Figure 3 and Figure 4)
PARAMETER
MIN
2
MAX
11
UNIT
ns
†
t
t
t
t
Delay time, PCLK to bused signals valid (see Notes 16 and 17)
VAL
Delay time, PCLK to bused signals valid point-to-point (see Notes 16 and 17)
2
12
ns
VAL(PTP)
on
Float-to-active delay
Active-to-float delay
2
ns
28
ns
off
†
Characterized by design
NOTES: 15. Some of the timing symbols in this table are not currently listed with EIA or JEDEC standards for semiconductor symbology but are
consistent with the PCI Local-Bus Specification, Revision 2.0.
16. Minimum times are measured with a 0-pF equivalent load; maximum times are measured with a 50-pF equivalent load. Actual test
capacitance may vary, but results should be correlated to these specifications.
17. PREQ and PGNT are point-to-point signals and have differentoutput valid delay and input setup times than do bused signals. PGNT
has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused.
timing requirements for PCI 5-V and 3.3-V (see Note 15 and Figure 4)
MIN
7
MAX
UNIT
ns
t
t
t
Setup time, bused signals valid to PCLK (see Note 17)
Setup time to PCLK—point-to-point (see Note 17)
Input hold time from PCLK
su
10, 12
0
ns
su(PTP)
h
ns
‡
‡
100 Mbps
10 Mbps
30
50
ns
t
c
Cycle time, PCLK (see Note 18)
30
500
ns
t
t
t
Pulse duration, PCLK high
Pulse duration, PCLK low
12
ns
w(H)
w(L)
slew
12
ns
‡
Slew rate, PCLK (see Note 19)
1
4
V/ns
‡
Specified by design and system specifications.
NOTES: 15. Some of the timing symbols in this table are not currently listed with EIA or JEDEC standards for semiconductor symbology but are
consistent with the PCI Local-Bus Specification, Revision 2.0.
17. PREQ and PGNT are point-to-point signals and have differentoutput valid delay and input setup times than do bused signals. PGNT
has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused.
18. As a requirement for frame transmission/reception, the minimum PCLK frequency varies with network speed. The clock may only
be stopped in a low state.
19. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform.
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
2 V
5-V Clock
1.5 V
0.8 V
t
c
t
w(H)
t
w(L)
0.475
0.4
V
DD
DD
3.3-V Clock
V
0.325
V
DD
t
VAL
Output
Delay
3-State
Output
t
on
t
off
t
h
t
su
Inputs
Valid
V
max
Input
Figure 4. PCI 5-V and 3.3-V Timing
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
†
timing requirements for MII receive (see Figure 5)
MIN
10
MAX
UNIT
ns
t
t
Setup time, MRXD[3:0], MRXDV, MRXER (see Note 20)
Hold time, MRXD[3:0], MRXDV, MRXER (see Note 20)
su(MRX pins)
10
ns
h(MRX pins)
†
switching characteristics for MII transmit (see Figure 3 and Figure 5)
PARAMETER
MIN
MAX
UNIT
t
Delay time, MTCLK to MTXD[3:0], MTXEN, and MTXER outputs (see Note 21)
0
25
ns
d(MTX pins)
†
Both MCRS and MCOL are driven asynchronously by the PHY.
NOTES: 20. MRXD[3:0] is driven by the PHY on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the edge
of MRCLK. MRXD[3:0] timing must be met during clock periods where MRXDV is asserted. MRXDV is asserted and deasserted
by the PHY on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the rising edge of MRCLK.
MRXER is driven by the PHY on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the rising
edge of MRCLK. MRXER timing must be met during clock periods when MRXDV is asserted.
21. MTXD[3:0] is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted and deasserted by the
reconciliation sublayer synchronous to the MTCLK rising edge. MTXER is driven synchronous to the rising edge of MTCLK.
MTCLK
MTXD[3:0],
MTXEN,
MTXER
t
d(MTX pins)
MRCLK
MRXD[3:0],
MRXDV,
MRXER
t
su(MRX pins)
t
h(MRX pins)
Figure 5. MII Transmit and Receive Timing
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
timing requirements for management data I/O (MDIO) (see Figure 6)
MIN
MAX
UNIT
t
Access time, MDIO valid from MDCLK high (see Note 22)
0
300
ns
a(MDCLKH-MDIOV)
switching characteristics for management data I/O (MDIO) (see Figure 3 and Figure 7)
PARAMETER
MIN
10
MAX
UNIT
ns
t
t
Delay time, MDIO valid to MDCLK high (see Note 23)
Delay time, MDCLK high to MDIO changing (see Note 23)
d(MDIOV-MDCLKH)
10
ns
d(MDCLKH-MDIOX)
NOTES: 22. When the MDIO signal is sourced by the PMI/PHY, it is sampled by TNETE100A synchronous to the rising edge of MDCLK.
23. MDIO is a bidirectional signal that can be sourced by TNETE100A or the PMI/PHY. When TNETE100A sources the MDIO signal,
TNETE100A asserts MDIO synchronous to the rising edge of MDCLK.
MDCLK
MDIO
t
a(MDCLKH-MDIOV)
Figure 6. Management Data I/O Timing (Sourced by PHY)
MDCLK
MDIO
t
d(MDIOV-MDCLKH)
t
d(MDCLKH-MDIOX)
Figure 7. Management Data I/O Timing (Sourced by TNETE100A)
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
†
timing requirements for BIOS ROM and LED interface (see Figure 8)
MIN
MAX
UNIT
ns
t
t
Setup time, data
Hold time, data
250
su
0
ns
h
†
switching characteristics for BIOS ROM and LED interface (see Figure 3 and Figure 8)
PARAMETER
MIN
MAX
UNIT
Delay time, address high byte valid to EXLE low (address high byte setup time for external
latch)
t
t
0
ns
d(EADV-EXLEL)
Delay time, EXLE low to address high byte invalid (address high byte hold time for external
latch)
10
ns
d(EXLEL-EADZ)
t
t
t
Delay time, address low byte valid to EALE low (address low byte setup time for external latch)
Delay time, EALE low to address low byte invalid (address low byte hold time for external latch)
Access time, address
0
10
ns
ns
ns
d(EADV-EALEL)
d(EALEL-EADZ)
a
288
†
The EPROM interface, consisting of 11 pins, requires only two TTL ’373 latches to latch the high and low addresses.
High
Address
Low
Address
Data
EAD[7:0]
t
d(EADV-EXLEL)
t
d(EADV-EALEL)
t
d(EXLEL-EADZ)
t
d(EALEL-EADZ)
EXLE
EALE
EOE
t
a
t
su
t
h
Figure 8. BIOS ROM and LED Interface Timing
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
switching characteristics for configuration EEPROM interface (see Figure 3 and Figure 9)
PARAMETER
MIN
0
MAX
100
3.5
UNIT
kHz
µs
f
t
t
t
t
t
t
t
t
t
t
t
t
Clock frequency, EDCLK
CLK(EDCLK)
d(EDCLKL-EDIOV)
d(EDIO free)
d(EDIOV-EDCLKL)
w(L)
EDCLK low to EDIO data in valid
0.3
4.7
4
Time the bus must be free before a new transmission can start
Delay time, EDIO valid after EDCLK low (start condition hold time for EEPROM)
Low period, clock
µs
µs
4.7
4
µs
High period, clock
µs
w(H)
Delay time, EDCLK high to EDIO valid (start condition setup time)
Delay time, EDCLK low to EDIO changing (data out hold time)
Delay time, EDIO valid to EDCLK high (data out setup time)
Rise time, EDIO and EDCLK
4.7
0
µs
d(EDCLKH-EDIOV)
d(EDCLKL-EDIOX)
d(EDIOV-EDCLKH)
r
µs
250
ns
1
µs
Fall time, EDIO and EDCLK
300
ns
f
Delay time, EDCLK high to EDIO high (stop condition setup time)
Delay time, EDCLK low to EDIO changing (data in hold time)
4.7
µs
d(EDCLKH-EDIOH)
d(EDCLKL-EDIOX)
300
ns
t
r
t
w(H)
t
t
w(L)
f
EDCLK
t
d(EDCLKL-EDIOX)
d(EDCLKH-EDIOV)
t
d(EDCLKH-EDIOH)
t
t
d(EDIOV-EDCLKL)
t
d(EDIOV-EDCLKH)
EDIO (OUT)
t
d(EDIO free)
t
d(EDCLKL-EDIOX)
t
d(EDCLKL-EDIOV)
EDIO (IN)
Figure 9. Configuration EEPROM Interface Timing
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
†
timing requirements for crystal oscillator (see Figure 10)
MIN
TYP
MAX
UNIT
ms
ns
‡
100
t
t
t
t
t
Delay time from minimum V
DD
high level to first valid FXTL1 full swing period
d(VDDH–FXTL1V)
‡
‡
Pulse duration at FXTL1 high
Pulse duration at FXTL1 low
Transition time of FXTL1
Cycle time, FXTL1
13
w(H)
13
ns
w(L)
7
50
ns
t
ns
c
Tolerance of FXTL1 input frequency
0.01
%
†
The FXTL signal can be driven by either a 20-MHz crystal using the FXTL1 and FXTL2 pins or by a 20-MHz crystal oscillator driving the FXTL1
pin.
‡
This specification is provided as an aid to board design. This specification is not tested during manufacturing testing.
Minimum V
High Level
DD
V
DD
t
c
t
w(H)
t
d(VDDH–FXTL1V)
t
t
FXTL1
t
t
t
w(L)
Figure 10. Crystal Oscillator Timing
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
MECHANICAL DATA
PCM (S-PQFP-G***)
PLASTIC QUAD FLATPACK
144 PIN SHOWN
NO. OF
A
108
73
PINS***
22,75 TYP
25,35 TYP
144
160
109
72
0,38
0,22
M
0,13
0,65
144
37
0,16 NOM
1
36
A
28,20
Gage Plane
SQ
SQ
27,80
31,45
30,95
0,25
0,25 MIN
3,60
3,20
1,03
0,73
Seating Plane
0,10
4,10 MAX
4040024/B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-022
D. The 144 PCM is identical to the 160 PCM except that four leads per corner are removed.
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ThunderLAN TNETE100A
PCI ETHERNET CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
M
0,08
0,17
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°–7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
TNETE100PM
PCI ETHERNETE CONTROLLER WITH POWER MANAGEMENT SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
TI
©2020 ICPDF网 联系我们和版权申明