TPA2010D1YZF [TI]
2.5-W MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER; 2.5W单声道无滤波器D类音频功率放大器
| 型号： | TPA2010D1YZF |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5-W MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER |
| 文件： | 总23页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003
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FEATURES
APPLICATIONS
D
Maximum Battery Life and Minimum Heat
− Efficiency With an 8-Ω Speaker:
− 88% at 400 mW
D
Ideal for Wireless or Cellular Handsets and
PDAs
− 80% at 100 mW
− 2.8-mA Quiescent Current
− 0.5-µA Shutdown Current
Only Three External Components
DESCRIPTION
D
− Optimized PWM Output Stage Eliminates
LC Output Filter
− Internally Generated 250-kHz Switching
Frequency Eliminates Capacitor and
Resistor
The TPA2010D1 is a 2.5-W high efficiency filter-free
class-D audio power amplifier in a 1.45 mm × 1.45 mm
wafer chip scale package (WCSP) that requires only three
external components.
− Improved PSRR (−75 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) Eliminates Need
for a Voltage Regulator
− Fully Differential Design Reduces RF
Rectification and Eliminates Bypass
Capacitor
Features like 88% efficiency, −75-dB PSRR, improved
RF-rectification immunity, and 8 mm total PCB area make
the TPA2010D1 ideal for cellular handsets. A fast start-up
time of 1 ms with minimal pop makes the TP2010D1 ideal
for PDA applications.
2
− Improved CMRR Eliminates Two Input
Coupling Capacitors
In cellular handsets, the earpiece, speaker phone, and
melody ringer can each be driven by the TPA2010D1. The
TPA2010D1 allows independent gain while summing
signals from seperate sources, and has a low 36 µV noise
floor, A-weighted.
D
Wafer Chip Scale Packaging (WCSP)
− NanoFreeE Lead-Free (YZF)
− NanoStarE SnPb (YEF)
APPLICATION CIRCUIT
9-BALL
WAFER CHIP SCALE
YZF, YEF PACKAGES
TPA2010D1 DIMENSIONS
(TOP VIEW OF PCB)
To Battery
Internal
Oscillator
V
DD
C
S
R
R
I
+
−
IN−
IN+
IN+
A1
GND
A2
V
O−
V
O+
PWM
H−
Bridge
_
+
A3
Differential
Input
V
O−
V
PV
DD
GND
B3
DD
I
1,55 mm
1,40 mm
B1
B2
GND
Bias
Circuitry
IN− SHUTDOWN
V
O+
SHUTDOWN
C1
C2
C3
TPA2010D1
1,55 mm
1,40 mm
Note: Pin A1 is marked with a “0” for
Pb−free (YZF) and a “1” for SnPb (YEF).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree and NanoStar are trademarks of Texas Instruments.
ꢁꢒ ꢌ ꢆꢕ ꢓ ꢀꢏ ꢌꢍ ꢆ ꢂꢀꢂ ꢖꢗ ꢘꢙ ꢚ ꢛꢜ ꢝꢖꢙꢗ ꢖꢞ ꢟꢠ ꢚ ꢚ ꢡꢗꢝ ꢜꢞ ꢙꢘ ꢢꢠꢣ ꢤꢖꢟ ꢜꢝꢖ ꢙꢗ ꢥꢜ ꢝꢡꢇ ꢁꢚ ꢙꢥꢠ ꢟꢝꢞ
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ꢁꢚ ꢙ ꢥꢠꢟ ꢝ ꢖꢙ ꢗ ꢢꢚ ꢙ ꢟ ꢡ ꢞ ꢞ ꢖꢗ ꢪ ꢥꢙ ꢡ ꢞ ꢗꢙꢝ ꢗꢡ ꢟꢡ ꢞꢞ ꢜꢚ ꢖꢤ ꢩ ꢖꢗꢟ ꢤꢠꢥ ꢡ ꢝꢡ ꢞꢝꢖ ꢗꢪ ꢙꢘ ꢜꢤ ꢤ ꢢꢜ ꢚ ꢜꢛ ꢡꢝꢡ ꢚ ꢞꢇ
Copyright 2003, Texas Instruments Incorporated
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SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ORDERING INFORMATION
T
PACKAGE
PART NUMBER
SYMBOL
AJZ
A
(1)
Wafer chip scale package (YEF)
TPA2010D1YEF
TPA2010D1YZF
−40°C to 85°C
(1)
Wafer chip scale packaging − Lead free (YZF)
AKO
(1)
The YEF and YZF packages are only available taped and reeled. To order add the suffix “R” to the end of the part number for a reel of 3000, or
add the suffix “T” to the end of the part number for a reel of 250 (e.g. TPA2010D1YEFR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TPA2010D1
−0.3 V to 6 V
−0.3 V to 7 V
In active mode
Supply voltage, V
DD
In SHUTDOWN mode
Input voltage, V
−0.3 V to V
+ 0.3 V
I
DD
Continuous total power dissipation
Operating free-air temperature, T
See Dissipation Rating Table
−40°C to 85°C
−40°C to 125°C
−65°C to 150°C
260°C
A
Operating junction temperature, T
J
Storage temperature, T
stg
YZF
YEF
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
235°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
2.5
NOM
MAX
UNIT
V
Supply voltage, V
DD
5.5
High-level input voltage, V
IH
SHUTDOWN
1.3
0
V
V
DD
Low-level input voltage, V
IL
SHUTDOWN
0.35
V
Input resistor, R
Gain ≤ 20 V/V (26 dB)
15
kΩ
V
I
Common mode input voltage range, V
IC
V
DD
= 2.5 V, 5.5 V, CMRR ≤ −49 dB
0.5
−40
V −0.8
DD
85
Operating free-air temperature, T
°C
A
PACKAGE DISSIPATION RATINGS
DERATING
FACTOR
T
≤ 25°C
T
= 70°C
T = 85°C
A
POWER RATING
A
A
PACKAGE
(1)
POWER RATING
POWER RATING
YEF
YZF
7.8 mW/°C
7.8 mW/°C
780 mW
429 mW
312 mW
780 mW
429 mW
312 mW
(1)
Derating factor measure with High K board.
2
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SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003
ELECTRICAL CHARACTERISTICS
T
A
= 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
= 2.5 V to 5.5 V
MIN
TYP
MAX
25
UNIT
mV
dB
Output offset voltage (measured
differentially)
|V
|
V = 0 V, A = 2 V/V, V
1
OS
I
V
DD
PSRR
CMRR
Power supply rejection ratio
V
DD
= 2.5 V to 5.5 V
−75
−68
−55
−49
V
V
= 2.5 V to 5.5 V, V = V /2 to 0.5 V
DD
IC
IC
− 0.8 V
DD
Common mode rejection ratio
dB
= V /2 to V
DD DD
I
I
High-level input current
Low-level input current
V
V
V
V
V
V
V
V
V
V
V
= 5.5 V, V = 5.8 V
100
5
µA
µA
IH
DD
I
= 5.5 V, V = −0.3 V
I
IL
DD
= 5.5 V, no load
= 3.6 V, no load
= 2.5 V, no load
3.4
2.8
2.2
0.5
700
500
400
>1
4.9
DD
I
Quiescent current
Shutdown current
mA
DD
(Q)
3.2
2
DD
I
= 0.35 V, V
(SHUTDOWN)
= 2.5 V to 5.5 V
DD
µA
(SD)
= 2.5 V
= 3.6 V
= 5.5 V
DD
DD
DD
r
Static drain-source on-state resistance
mΩ
DS(on)
Output impedance in SHUTDOWN
Switching frequency
= 0.4 V
kΩ
(SHUTDOWN)
f
= 2.5 V to 5.5 V
200
250
300
kHz
(sw)
DD
DD
315 kW
RI
285 kW 300 kW
V
V
Gain
V
= 2.5 V to 5.5 V
RI
RI
Resistance from shutdown to GND
300
kΩ
OPERATING CHARACTERISTICS
T
A
= 25°C, Gain = 2 V/V, R = 8 Ω (unless otherwise noted)
L
PARAMETER
TEST CONDITIONS
MIN
TYP
2.5
1.3
MAX
UNIT
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 5 V
THD + N= 10%, f = 1 kHz,
= 3.6 V
= 2.5 V
= 5 V
W
R = 4 Ω
L
0.52
2.08
THD + N= 1%, f = 1 kHz,
= 3.6 V
= 2.5 V
= 5 V
1.06
W
W
W
R = 4 Ω
L
0.42
P
O
Output power
1.45
THD + N= 10%, f = 1 kHz,
= 3.6 V
= 2.5 V
= 5 V
0.73
R = 8 Ω
L
0.33
1.19
THD + N= 1%, f = 1 kHz,
= 3.6 V
= 2.5 V
0.59
R = 8 Ω
L
0.26
V
V
V
V
= 5 V, P = 1 W, R = 8 Ω, f = 1 kHz
0.18%
0.19%
0.20%
DD
DD
DD
DD
O
L
= 3.6 V, P = 0.5 W, R = 8 Ω, f = 1 kHz
THD+N Total harmonic distortion plus noise
O
L
= 2.5 V, P = 200 mW, R = 8 Ω, f = 1 kHz
O
L
= 3.6 V, Inputs ac-
f = 217 Hz,
k
Supply ripple rejection ratio
Signal-to-noiseratio
−67
97
dB
dB
SVR
grounded with C = 2 µF
V
= 200 mV
pp
i
(RIPPLE)
R = 8 Ω
SNR
V
DD
= 5 V,
P
= 1 W,
O
L
V
= 3.6 V,
DD
No weighting
48
f = 20 Hz to 20 kHz,
Inputs ac-grounded with
C = 2 µF
V
n
Output voltage noise
µV
RMS
A weighting
f = 217 Hz
36
i
CMRR
Common mode rejection ratio
Input impedance
V
DD
= 3.6 V, V = 1 V
IC
−63
150
1
dB
kΩ
ms
pp
Z
I
142
158
Start-up time from shutdown
V
DD
= 3.6 V
3
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SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
YEF, YZF
C1
IN−
IN+
I
I
Negative differential input
Positive differential input
Power supply
A1
V
V
B1
I
DD
C3
O
I
Positive BTL output
O+
GND
A2, B3
A3
High-current ground
Negative BTL output
Shutdown terminal (active low logic)
Power supply
V
O−
O
I
SHUTDOWN
PVDD
C2
B2
I
FUNCTIONAL BLOCK DIAGRAM
150 kΩ
*Gain =
*Gain = 2 V/V
V
DD
R
I
B1, B2
V
DD
+
_
Gate
Drive
Deglitch
Logic
150 kΩ
A3
V
C1
A1
C2
IN−
IN+
O−
_
_
+
_
+
_
+
+
C3
V
150 kΩ
+
_
O+
Gate
Drive
Deglitch
Logic
TTL
SD Input
Startup
Protection
Logic
OC
Detect
SHUTDOWN
Buffer
A2, B3
GND
Biases
and
References
Ramp
300 kΩ
Generator
Notes:
150 kΩ
2 x
* Total gain =
R
I
4
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SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Efficiency
vs Output power
1, 2
P
D
Power dissipation
Supply current
vs Output power
3, 4
vs Output power
5, 6
I
I
Quiescent current
Shutdown current
vs Supply voltage
vs Shutdown voltage
vs Supply voltage
vs Load resistance
vs Output power
7
(Q)
8
(SD)
9
P
Output power
O
10, 11
12, 13
vs Frequency
14, 15, 16, 17
THD+N Total harmonic distortion plus noise
vs Common-mode input voltage
vs Frequency
18
K
SVR
Supply voltage rejection ratio
19, 20, 21
vs Time
22
23
24
25
26
GSM power supply rejection
Supply voltage rejection ratio
vs Frequency
K
SVR
vs Common-mode input voltage
vs Frequency
CMRR Common-mode rejection ratio
vs Common-mode input voltage
TEST SET-UP FOR GRAPHS
C
C
TPA2010D1
I
R
R
I
+
IN+
OUT+
+
30 kHz
Low Pass
Filter
Measurement
Measurement
Input
−
Load
I
Output
−
I
IN−
OUT−
GND
V
DD
1 µF
+
−
V
DD
Notes:
(1) C was Shorted for any Common-Mode input voltage measurement
I
(2) A 33-µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
(3) The 30-kHz low-pass filter is required even if the analyzer has an internal low-pass filter. An RC low pass filter (100 Ω, 47 nF) is
used on each output for the data sheet graphs.
5
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SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003
EFFICIENCY
vs
EFFICIENCY
vs
POWER DISSIPATION
vs
OUTPUT POWER
OUTPUT POWER
OUTPUT POWER
1.4
1.2
100
90
80
70
60
50
40
30
20
10
90
80
70
60
50
Class-AB 5 V, 4 Ω
V
= 5 V,
DD
= 4 Ω,
V
= 5 V,
DD
R
L
V
R
= 3.6 V,
33 µH
R
L
= 8 Ω, 33 µH
DD
V
R
= 2.5 V,
= 4 Ω, 33 µH
1
0.8
0.6
0.4
0.2
0
DD
L
= 8 Ω, 33 µH
L
V
R
= 2.5 V,
DD
= 4 Ω, 33 µH
Class-AB 5 V, 8 Ω
L
40
30
20
10
Class AB.
= 5 V,
Class AB.
= 5 V,
V
R
DD
= 4 Ω
V
= 5 V, R = 4 Ω,
L
DD
V
R
L
DD
= 8 Ω
L
V
= 5 V, R = 8 Ω
L
DD
1.5
− Output Power − W
0
0
0.2 0.4 0.6 0.8
1.2 1.4 1.6 1.8
0
1
2
1
0
0.4
0.6
0.8
1.2
0.2
0
0.5
1
2
2.5
P
− Output Power − W
P
− Output Power − W
O
P
O
O
Figure 1
Figure 2
Figure 3
SUPPLY CURRENT
vs
OUTPUT POWER
SUPPLY CURRENT
vs
OUTPUT POWER
POWER DISSIPATION
vs
OUTPUT POWER
600
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
300
250
200
150
100
50
R
= 4 Ω, 33 µH
L
R
V
= 8 Ω, 33 µH
L
V
= 3.6 V
500
400
DD
Class-AB 3.6 V, 4 Ω
=
3.6 V
DD
V
= 2.5 V
DD
Class-AB 3.6 V, 8 Ω
300
200
V
=
3.6 V, R = 4 Ω
DD
L
V
= 2.5 V
0.8
DD
100
0
V
= 5 V,
DD
V
= 3.6 V,
V
=
5 V
DD
DD
R
L
= 8 Ω, 33 µH
0
0
0.5
1
1.5
2
2.5
0.2 0.4
0.6
1.2
1.4
0
1
0
0.2
0.4
0.6
0.8
1
1.2
P
− Output Power − W
P
− Output Power − W
O
O
P
− Output Power − W
O
Figure 4
Figure 5
Figure 6
SUPPLY CURRENT
vs
SHUTDOWN CURRENT
vs
OUTPUT POWER
vs
SUPPLY VOLTAGE
SHUTDOWN VOLTAGE
LOAD RESISTANCE
5
4.5
4
3
2
P
at 10% THD
O
Gain = 2 V/V
f = 1 kHz
2.5
1.5
1
V
DD= 5V
R
L
= 8 Ω, (resistive)
2
R
L
= 8 Ω,
V
= 5 V
DD
33 µH
V
DD = 3.6V
3.5
3
1.5
V
= 3.6 V
DD
V
1
DD = 2.5 V
V
= 2.5 V
DD
0.5
0
2.5
2
0.5
0
No Load
2.5
3
3.5
4
4.5
5
5.5
4
8
12
16
20
24
28
32
0
0.1
0.2
0.3
0.4
0.5
Shutdown Voltage − V
V
− Supply Voltage − V
R
L
− Load Resistance − Ω
DD
Figure 7
Figure 8
Figure 9
6
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SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
LOAD RESISTANCE
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
3
2.5
2
2.5
2
20
Gain = 2 V/V
f = 1 kHz
P
at 1% THD
O
R
L
= 4 Ω,
Gain = 2 V/V
f = 1 kHz,
Gain = 2 V/V
10
5
f = 1 kHz
R
L
= 4 Ω, 10% THD
V
DD=5V
2.5 V
R
L
= 4 Ω, 1% THD
1.5
1
3 V
2
1
V
DD = 3.6 V
1.5
1
3.6 V
5 V
V
DD = 2.5V
0.5
0.5
0
0.5
0
R
= 8 Ω,10% THD
L
0.2
0.1
R
L
= 8 Ω,1% THD
2.5
3
3.5
4
4.5
5
4
8
12
16
20
24
28
32
20m 50m 100m 200m 500m
− Output Power − W
1
2
3
V
− Supply Voltage − V
CC
R
L
− Load Resistance − Ω
P
O
Figure 12
Figure 10
Figure 11
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
vs
OUTPUT POWER
20
FREQUENCY
FREQUENCY
10
5
10
5
V
= 5 V
V
= 3.6 V
DD
DD
R
= 8 Ω,
L
P
= 25 mW
C
R
= 2 µF
C
R
= 2 µF
O
I
P
= 50 mW
I
2.5 V
O
f = 1 kHz,
10
5
= 8 Ω
= 8 Ω
L
L
Gain = 2 V/V
2
1
Gain = 2 V/V
Gain = 2 V/V
2
1
P
= 125 mW
O
3 V
P
= 250 mW
O
0.5
3.6 V
5 V
P
= 500 mW
O
0.5
2
1
P
= 1W
O
0.2
0.1
0.2
0.1
0.05
0.5
0.05
0.02
0.01
0.2
0.1
0.02
0.01
0.005
20
50 100 200 500 1k 2k
5k 10k 20k
5m 10m 20m 50m 100m 200m 500m 1
− Output Power − W
2
20
50 100 200 500 1k 2k
5k 10k 20k
f − Frequency − Hz
f − Frequency − Hz
P
O
Figure 13
Figure 14
Figure 15
TOTAL HARMONIC DISTORTION + NOISE
vs
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs
vs
COMMON MODE INPUT VOLTAGE
FREQUENCY
FREQUENCY
10
5
10
10
5
PO = 250 mW
= 2 µF
V
C
R
= 2.5 V
= 2 µF
f = 1 kHz
DD
P
= 15 mW
C
I
R
L
O
I
P
= 200 mW
O
= 4 Ω
= 8 Ω
L
Gain = 2 V/V
Gain = 2 V/V
2
1
V
= 3.6 V
2
DD
P
= 75 mW
O
1
V
= 3 V
DD
V
= 2.5 V
DD
0.5
0.5
P
= 200 mW
O
1
0.2
0.2
0.1
V
= 2.5 V
DD
V
= 5 V
DD
0.1
0.05
0.05
0.02
0.01
V
= 5 V
0.02
0.01
DD
V
= 3.6 V
V
= 4 V
DD
DD
0.1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
20
50 100 200 500 1k 2k
5k 10k 20k
20
50 100 200 500
10k 20k
1k 2k
5k
V
− Common Mode Input Voltage − V
f − Frequency − Hz
f − Frequency − Hz
IC
Figure 18
Figure 16
Figure 17
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SUPPLY RIPPLE REJECTION RATIO
SUPPLY RIPPLE REJECTION RATIO
SUPPLY RIPPLE REJECTION RATIO
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
−30
−40
−50
−60
−70
−80
−90
−30
−30
Inputs ac-grounded
Inputs ac-grounded
Inputs floating
= 8 Ω
C
R
= 2 µF
C
R
= 2 µF
I
I
R
= 4 Ω
L
= 8 Ω
L
L
−40
−40
−50
−60
−70
−80
−90
Gain = 2 V/V
Gain = 2 V/V
V
= 2.5 V
V
= 2. 5 V
−50
−60
−70
DD
DD
V
= 3.6 V
DD
V
= 5 V
DD
V
= 3.6 V
DD
V
= 3.6 V
1 k
DD
−80
−90
V
= 5 V
V
= 5 V
DD
DD
V
= 2.5 V
DD
20
100
1 k
10 k20 k
20
100
1 k
10 k 20 k
20
100
10 k20 k
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 19
Figure 20
Figure 21
GSM POWER SUPPLY REJECTION
GSM POWER SUPPLY REJECTION
vs
vs
TIME
FREQUENCY
0
−50
C1 − High
3.6 V
V
DD
200 mV/div
−100
−150
C1 − Amp
512 mV
0
V
C
Shown in Figure 22
DD
= 2 µF,
I
C1 − Duty
12%
Inputs ac-grounded
Gain = 2V/V
−50
V
OUT
20 mV/div
−100
−150
0
400
800
1200
1600
2000
f − Frequency − Hz
t − Time − 2 ms/div
Figure 22
Figure 23
COMMON-MODE REJECTION RATIO
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE REJECTION RATIO
SUPPLY RIPPLE REJECTION RATIO
vs
vs
FREQUENCY
DC COMMON MODE VOLTAGE
0
0
−50
V
= 200 mV
−10
IC
PP
−10
R
= 8 Ω
L
Gain = 2 V/V
−20
−30
−40
−55
−60
−65
−70
−75
−20
−30
−40
−50
−60
V
= 3.6 V
DD
V
= 2.5 V
DD
−50
−60
V
= 3.6 V
DD
V
= 3.6 V
DD
V
= 2. 5 V
DD
V
= 5 V
DD
−70
−80
V
= 5 V,
DD
Gain = 2
−70
−80
−90
−100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
1
2
3
4
5
20
100
1 k
10 k 20 k
V
− Common Mode Input Voltage − V
DC Common Mode Voltage − V
f − Frequency − Hz
IC
Figure 24
Figure 25
Figure 26
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APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIER
The TPA2010D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier
consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The
common-mode feedback ensures that the common-mode voltage at the output is biased around V /2
DD
regardless of the common-mode voltage at the input. The fully differential TPA2010D1 can still be used with
a single-ended input; however, the TPA2010D1 should be used with differential inputs when in a noisy
environment, like a wireless handset, to ensure maximum noise rejection.
Advantages of Fully DIfferential Amplifiers
D
Input-coupling capacitors not required:
−
The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. For
example, if a codec has a midsupply lower than the midsupply of the TPA2010D1, the common-mode
feedback circuit will adjust, and the TPA2010D1 outputs will still be biased at midsupply of the
TPA2010D1. The inputs of the TPA2010D1 can be biased from 0.5V to V
biased outside of that range, input-coupling capacitors are required.
– 0.8 V. If the inputs are
DD
D
D
Midsupply bypass capacitor, C
, not required:
(BYPASS)
−
−
The fully differential amplifier does not require a bypass capacitor. This is because any shift in the
midsupply affects both positive and negative channels equally and cancels at the differential output.
Better RF−immunity:
GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The
transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the
signal much better than the typical audio amplifier.
COMPONENT SELECTION
Figure 27 shows the TPA2010D1 typical schematic with differential inputs and Figure 28 shows the
TPA2010D1 with differential inputs and input capacitors, and Figure 29 shows the TPA2010D1 with
single-ended inputs. Differential inputs should be used whenever possible because the single-ended inputs are
much more susceptible to noise.
Table 1. Typical Component Values
REF DES
VALUE
EIA SIZE
0402
MANUFACTURER
Panasonic
PART NUMBER
ERJ2RHD154V
R
I
150 kΩ ( 0.5%)
1 µF (+22%, −80%)
3.3 nF ( 10%)
C
S
0402
Murata
GRP155F50J105Z
GRP033B10J332K
C (1)
I
0201
Murata
(1)
C is only needed for single-ended input or if V
is not between 0.5 V and V
– 0.8 V. C = 3.3 nF
DD I
I
ICM
(with R = 150 kΩ) gives a high-pass corner frequency of 321 Hz.
I
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Input Resistors (R )
I
The input resistors (R ) set the gain of the amplifier according to equation (1).
I
(1)
2 x 150 kW
V
V
ǒ Ǔ
Gain +
R
I
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic
distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or
better to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays
with 1% matching can be used with a tolerance greater than 1%.
Place the input resistors very close to the TPA2010D1 to limit noise injection on the high-impedance nodes.
For optimal performance the gain should be set to 2 V/V or lower. Lower gain allows the TPA2010D1 to operate
at its best, and keeps a high voltage at the input making the inputs less susceptible to noise.
Decoupling Capacitor (C )
S
The TPA2010D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically
1 µF, placed as close as possible to the device V
lead works best. Placing this decoupling capacitor close
DD
to the TPA2010D1 is very important for the efficiency of the class-D amplifier, because any resistance or
inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering
lower-frequency noise signals, a 10 µF or greater capacitor placed near the audio power amplifier would also
help, but it is not required in most applications because of the high PSRR of this device.
Input Capacitors (C )
I
The TPA2010D1 does not require input coupling capacitors if the design uses a differential source that is biased
from 0.5 V to V
– 0.8 V (shown in Figure 27). If the input signal is not biased within the recommended
DD
common−mode input range, if needing to use the input as a high pass filter (shown in Figure 28), or if using
a single-ended source (shown in Figure 29), input coupling capacitors are required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, f , determined in
c
equation (2).
1
f +
c
ǒ
Ǔ
2p R C
I I
(2)
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application.
Equation (3) is reconfigured to solve for the input coupling capacitance.
1
C +
I
ǒ
cǓ
2p R f
I
(3)
If the corner frequency is within the audio band, the capacitors should have a tolerance of 10% or better,
because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
For a flat low-frequency response, use large input coupling capacitors (1 µF). However, in a GSM phone the
ground signal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation.
The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum.
10
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To Battery
Internal
Oscillator
V
DD
C
S
R
R
I
+
−
IN−
IN+
V
O+
PWM
H−
Bridge
_
+
Differential
Input
V
O−
I
GND
Bias
Circuitry
SHUTDOWN
TPA2010D1
Filter-Free Class D
Figure 27. Typical TPA2010D1 Application Schematic With Differential Input for a Wireless Phone
To Battery
Internal
Oscillator
V
DD
C
S
C
C
I
R
R
I
IN−
IN+
V
O+
PWM
H−
Bridge
_
+
Differential
Input
V
O−
I
I
GND
Bias
Circuitry
SHUTDOWN
TPA2010D1
Filter-Free Class D
Figure 28. TPA2010D1 Application Schematic With Differential Input and Input Capacitors
To Battery
Internal
Oscillator
V
DD
C
S
C
I
R
R
I
IN−
IN+
Single-ended
Input
V
O+
PWM
H−
Bridge
_
+
V
O−
I
C
I
GND
Bias
Circuitry
SHUTDOWN
TPA2010D1
Filter-Free Class D
Figure 29. TPA2010D1 Application Schematic With Single-Ended Input
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SUMMING INPUT SIGNALS WITH THE TPA2010D1
Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources
that need separate gain. The TPA2010D1 makes it easy to sum signals or use separate signal sources with
different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone
would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo
headphones require summing of the right and left channels to output the stereo signal to the mono speaker.
Summing Two Differential Input Signals
Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each
input source can be set independently (see equations (4) and (5), and Figure 30).
V
O
I1
2 x 150 kW
V
V
ǒ Ǔ
Gain 1 +
Gain 2 +
+
+
V
R
I1
(4)
(5)
V
V
O
I2
2 x 150 kW
V
ǒ Ǔ
R
V
I2
If summing left and right inputs with a gain of 1 V/V, use R = R = 300 kΩ.
I1
I2
If summing a ring tone and a phone signal, set the ring-tone gain to Gain 2 = 2 V/V, and the phone gain to
gain 1 = 0.1 V/V. The resistor values would be. . .
R
= 3 MΩ, and = R = 150 kΩ.
I2
I1
R
I1
I1
+
−
Differential
Input 1
R
To Battery
Internal
Oscillator
V
DD
C
S
R
I2
+
IN−
IN+
V
O+
PWM
H−
Bridge
_
+
Differential
Input 2
V
O−
R
I2
−
GND
Bias
Circuitry
SHUTDOWN
Filter-Free Class D
Figure 30. Application Schematic With TPA2010D1 Summing Two Differential Inputs
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Summing a Differential Input Signal and a Single-Ended Input Signal
Figure 31 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple
in through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-ended
input is set by C , shown in equation (8). To assure that each input is balanced, the single-ended input must
I2
be driven by a low-impedance source even if the input is not in use
V
O
I1
2 x 150 kW
V
V
ǒ Ǔ
Gain 1 +
+
V
R
I1
(6)
(7)
(8)
V
V
O
I2
2 x 150 kW
V
ǒ Ǔ
Gain 2 +
+
R
V
I2
1
+ ǒ2p R c2Ǔ
C
I2
f
I2
If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ring
tone might be limited to a single-ended signal. Phone gain is set at gain 1 = 0.1 V/V, and the ring-tone gain is
set to gain 2 = 2 V/V, the resistor values would be…
R
= 3 MΩ, and = R = 150 kΩ.
I2
I1
The high pass corner frequency of the single-ended input is set by C . If the desired corner frequency is less
I2
than 20 Hz...
1
C
C
u
I2
I2
ǒ
Ǔ
2p 150kW 20Hz
u 53 pF
R
R
I1
Differential
To Battery
I1
Input 1
Internal
Oscillator
V
DD
C
S
C
I2
R
I2
Single-Ended
Input 2
IN−
IN+
V
O+
PWM
H−
Bridge
_
+
V
O−
R
I2
C
I2
GND
Bias
SHUTDOWN
Circuitry
Filter-Free Class D
Figure 31. Application Schematic With TPA2010D1 Summing Differential Input and
Single-Ended Input Signals
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Summing Two Single-Ended Input Signals
Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner
frequencies (f and f ) for each input source can be set independently (see equations (9) through (12), and
c1
c2
Figure 32). Resistor, R , and capacitor, C , are needed on the IN+ terminal to match the impedance on the IN−
P
P
terminal. The single-ended inputs must be driven by low impedance sources even if one of the inputs is not
outputting an ac signal.
V
O
I1
2 x 150 kW
V
V
ǒ Ǔ
Gain 1 +
+
V
R
I1
(9)
V
O
2 x 150 kW
V
V
ǒ Ǔ
Gain 2 +
+
V
R
(10)
(11)
I2
I2
1
C
+ ǒ2p R c1Ǔ
I1
f
I1
1
+ ǒ2p R c2Ǔ
C
I2
f
I2
(12)
(13)
C
+ C ) C
P
I1
I2
R
+ ǒR
R
I1
I1
I2
I2
R
P
Ǔ
) R
(14)
C
C
I1
R
R
I1
Single-Ended
Input 1
To Battery
Internal
Oscillator
V
DD
C
S
I2
I2
Single-Ended
Input 2
IN−
V
O+
PWM
H−
Bridge
_
+
V
O−
R
P
IN+
C
P
GND
Bias
Circuitry
SHUTDOWN
Filter-Free Class D
Figure 32. Application Schematic With TPA2010D1 Summing Two Single-Ended Inputs
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SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003
BOARD LAYOUT
In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined
(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the
opening size is defined by the copper pad width. Figure 33 and Table 2 show the appropriate diameters for a
WCSP layout. The TPA2010D1 evaluation module (EVM) layout is shown in the next section as a layout
example.
Copper
Trace Width
Solder
Pad Width
Solder Mask
Opening
Copper Trace
Thickness
Solder Mask
Thickness
Figure 33. Land Pattern Dimensions
Table 2. Land Pattern Dimensions
SOLDER PAD
DEFINITIONS
SOLDER MASK
OPENING
COPPER
THICKNESS
STENCIL
THICKNESS
COPPER PAD
STENCIL OPENING
Nonsolder mask
defined (NSMD)
275 µm
(+0.0, −25 µm)
375 µm
(+0.0, −25 µm)
1 oz max (32 µm)
275 µm x 275 µm Sq.
(rounded corners)
125 µm thick
NOTES:A. Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside the solder mask opening. Wider
trace widths reduce device stand off and impact reliability.
NOTES:B. Recommend solder paste is Type 3 or Type 4.
NOTES:C. Best reilability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended
application.
NOTES:D. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 µm to avoid a reduction in thermal fatigue performance.
NOTES:E. Solder mask thickness should be less than 20 µm on top of the copper circuit pattern.
NOTES:F. Best solder stencil preformance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in
inferior solder paste volume control.
NOTES:G. Trace routing away from WCSP device should be balanced in X & Y directions to avoid unintentional component movement due to solder
wetting forces.
15
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Component Location
Place all the external components very close to the TPA2010D1. The input resistors need to be very close to
the TPA2010D1 input pins so noise does not couple on the high impedance nodes between the input resistors
and the input amplifier of the TPA2010D1. Placing the decoupling capacitor, CS, close to the TPA2010D1 is
important for the efficiency of the class-D amplifier. Any resistance or inductance in the trace between the device
and the capacitor can cause a loss in efficiency.
Trace Width
Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCB
traces. Figure 34 shows the layout of the TPA2010D1 evaluation module (EVM).
For high current pins (V , GND V , and V ) of the TPA2010D1, use 100-µm trace widths at the solder balls
DD
O+
O−
and at least 500-µm PCB traces to ensure proper performance and output power for the device.
For input pins (IN−, IN+, and SHUTDOWN) of the TPA2010D1, use 75-µm to 100-µm trace widths at the solder
balls. IN− and IN+ pins need to run side-by-side to maximize common-mode noise cancellation. Placing input
resistors, R , as close to the TPA2010D1 as possible is recommended.
IN
75 mm
100 mm
100 mm
100 mm
375 mm
275 mm
(+0, −25 mm)
(+0, −25 mm)
100 mm
Circular Solder Mask Opening
Paste Mask (Stencil)
= Copper Pad Size
75 mm
100 mm
75 mm
Figure 34. Close Up of TPA2010D1 Land Pattern From TPA2010D1 EVM
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EFFICIENCY AND THERMAL INFORMATION
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the YEF and YEZ packages are shown in the dissipation rating table. Converting this to θ
:
JA
1
1
q
+
+
+ 128.2°CńW
JA
0.0078
Derating Factor
(15)
Given θ of 128.2°C/W, the maximum allowable junction temperature of 125°C, and the maximum internal
JA
dissipation of 0.4 W (2.25 W, 4-Ω load, 5-V supply, from Figure 3), the maximum ambient temperature can be
calculated with the following equation.
T Max + T Max * q
P
+ 125 * 128.2 (0.4) + 73.7°C
A
J
JA Dmax
(16)
Equation (16) shows that the calculated maximum ambient temperature is 73.7°C at maximum power
dissipation with a 5-V supply and 4-Ω a load, see Figure 3. The TPA2010D1 is designed with thermal protection
that turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Also,
using speakers more resistive than 4-Ω dramatically increases the thermal performance by reducing the output
current and increasing the efficiency of the amplifier.
ELIMINATING THE OUTPUT FILTER WITH THE TPA2010D1
This section focuses on why the user can eliminate the output filter with the TPA2010D1.
Effect on Audio
The class-D amplifier outputs a pulse-width modulated (PWM) square wave, which is the sum of the switching
waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the
frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are
much greater than 20 kHz, so the only signal heard is the amplified input audio signal.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA005Dxx family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, V . Therefore,
DD
the differential pre-filtered output varies between positive and negative V , where filtered 50% duty cycle
DD
yields 0 volts across the load. The traditional class-D modulation scheme with voltage and current waveforms
is shown in Figure 35. Note that even at an average of 0 volts across the load (50% duty cycle), the current
to the load is high causing a high loss and thus causing a high supply current.
OUT+
OUT−
+5 V
Differential Voltage
0 V
Across Load
−5 V
Current
Figure 35. Traditional Class-D Modulation Scheme’s Output Voltage and
Current Waveforms Into an Inductive Load With no Input
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TPA2010D1 Modulation Scheme
The TPA2010D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUT+ and OUT− are now in phase with each other with no input. The duty cycle of OUT+ is greater
than 50% and OUT− is less than 50% for positive voltages. The duty cycle of OUT+ is less than 50% and OUT−
is greater than 50% for negative voltages. The voltage across the load sits at 0 volts throughout most of the
2
switching period greatly reducing the switching current, which reduces any I R losses in the load.
OUT+
OUT−
Output = 0 V
Differential
+5 V
Voltage
0 V
Across
−5 V
Load
Current
OUT+
OUT−
Output > 0 V
Differential
Voltage
Across
Load
+5 V
0 V
−5 V
Current
Figure 36. The TPA2010D1 Output Voltage and Current Waveforms Into an Inductive Load
Efficiency: Why You Must Use a Filter With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 × V
and the time at each voltage
DD
is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current
from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA2010D1 modulation scheme has very little loss in the load without a filter because the pulses are very
short and the change in voltage is V
making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but
for most applications the filter is not needed.
instead of 2 × V . As the output power increases, the pulses widen
DD
DD
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to
flow through the filter instead of the load. The filter has less resistance than the speaker that results in less power
dissipated, which increases efficiency.
18
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SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003
Effects of Applying a Square Wave Into a Speaker
If the amplitude of a square wave is high enough and the frequency of the square wave is within the bandwidth
of the speaker, a square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil.
A 250-kHz switching frequency, however, is not significant because the speaker cone movement is proportional
2
to 1/f for frequencies beyond the audio band. Therefore, the amount of cone movement at the switching
frequency is very small. However, damage could occur to the speaker if the voice coil is not designed to handle
the additional power. To size the speaker for added power, the ripple current dissipated in the load needs to
be calculated by subtracting the theoretical supplied power, P
, from the actual supply power,
SUPTHEORETICAL
P
, at maximum output power, P
. The switching power dissipated in the speaker is the inverse of the
SUP
OUT
measured efficiency, η
, minus the theoretical efficiency, η
.
MEASURED
THEORETICAL
P
P
+ P
–P
(at max output power)
(at max output power)
1
SPKR
SUP SUP THEORETICAL
(17)
P
P
SUP
OUT
SUP THEORETICAL
+
–
SPKR
P
P
OUT
(18)
(19)
1
ǒ
Ǔ(at max output power)
P
+ P
*
h
h
SPKR
OUT
MEASURED
THEORETICAL
R
L
hTHEORETICAL +
(at max output power)
R
) 2r
L
DS(on)
(20)
The maximum efficiency of the TPA2010D1 with a 3.6 V supply and an 8-Ω load is 86% from equation (20).
Using equation (19) with the efficiency at maximum power (84%), we see that there is an additional 17 mW
dissipated in the speaker. The added power dissipated in the speaker is not an issue as long as it is taken into
account when choosing the speaker.
19
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ꢁꢂ
ꢃ
ꢄꢅ
ꢄ
ꢆꢅ
www.ti.com
SLOS417A − OCTOBER 2003 − REVISED DECEMBER 2003
When to Use an Output Filter
Design the TPA2010D1 without an output filter if the traces from amplifier to speaker are short. The TPA2010D1
passed FCC and CE radiated emissions with no shielding with speaker trace wires 100 mm long or less.
Wireless handsets and PDAs are great applications for class-D without a filter.
A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter, and the
frequency sensitive circuit is greater than 1 MHz. This is good for circuits that just have to pass FCC and CE
because FCC and CE only test radiated emissions greater than 30 MHz. If choosing a ferrite bead, choose one
with high impedance at high frequencies, but very low impedance at low frequencies.
Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads
from amplifier to speaker.
Figure 37 and Figure 38 show typical ferrite bead and LC output filters.
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 37. Typical Ferrite Chip Bead Filter (Chip bead example: NEC/Tokin: N2012ZPS121)
33 µH
OUTP
1 µF
33 µH
OUTN
1 µF
Figure 38. Typical LC Output Filter, Cutoff Frequency of 27 kHz
20
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