TPA3002D2PHPR_技术文档

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

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FEATURES

DESCRIPTION

D

9-W/Ch Into an 8-Ω Load From 12-V Supply

The TPA3002D2 is a 9-W (per channel) efficient, Class-D

audio amplifier for driving bridged-tied stereo speakers.

The TPA3002D2 can drive stereo speakers as low as 8 Ω.

The high efficiency of the TPA3002D2 eliminates the need

for external heatsinks when playing music.

D

Efficient, Class-D Operation Eliminates

Heatsinks and Reduces Power Supply

Requirements

32-Step DC Volume Control From −40 dB to

36 dB

Line Outputs For External Headphone

Amplifier With Volume Control

Regulated 5-V Supply Output for Powering

TPA6110A2

Space-Saving, Thermally-Enhanced

PowerPAD Packaging

D

Stereo speaker volume is controlled with a dc voltage

applied to the volume control terminal offering a range of

gain from –40 dB to 36 dB. Line outputs, for driving external

headphone amplifier inputs, are also dc voltage controlled

with a range of gain from –56 dB to 20 dB.

An integrated 5-V regulated supply is provided for

powering an external headphone amplifier.

Thermal and Short-Circuit Protection

APPLICATIONS

D

LCD Monitors and TVs

Powered Speakers

D

PVCC

10 nF

PVCC

10 nF

10 µF

Cs

0.1 µF

Cbs

Cs

Ccpr

SDZ

SD

VCLAMPR

Crinn

1 µF

MODE_OUT

RINN

MODE_OUT

Crinp

1 µF

C2p5

MODE

AVCC

MODE

RINP

AVCC

1 µF

Clinp

V2P5

Cvcc

10 µF

Cs

0.1 µF

1 µF

Clinn

LINP

VAROUTR

VAROUTL

AGND

RLINE_OUT

LLINE_OUT

1 µF

LINN

TPA3002D2

1 µF

AVDDREF

VREF

AVDD

Cosc

Cvdd

VREF

AVDD

100 nF

Rosc

VARDIFF

VARMAX

VOLUME

REFGND

COSC

VARDIFF

220 pF

ROSC

VARMAX

120 kΩ

VOL

AGND

Ccpl

VCLAMPL

REFGND

1 µF

10

kΩ

10

kΩ

Cs

Cbs

0.1 µF

Cs

10 nF

10 µF

PVCC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

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Copyright  2002−2004, Texas Instruments Incorporated

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

PACKAGED DEVICE

T

A

(1)

48-PIN HTQFP (PHP)

−40°C to 85°C

TPA3002D2PHP

(1)

The PHP package is available taped and reeled. To order a taped and

reeled part, add the suffix R to the part number (e.g., TPA3002D2PHPR).

PIN ASSIGNMENTS

PHP PACKAGE

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37

SD

RINN

RINP

V2P5

LINP

LINN

1

2

3

4

5

6

7

8

9

10

36 VCLAMPR

35 MODE_OUT

34 MODE

33

32 VAROUTR

VAROUTL

30 AGND

AV

CC

31

TPA3002D2

AV REF

DD

VREF

VARDIFF

VARMAX

29

DD

28 COSC

27 ROSC

26 AGND

VOLUME 11

12

REFGND

VCLAMPL

25

13 14 15 16 17 18 19 20 21 22 23 24

2

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

FUNCTIONAL BLOCK DIAGRAM

V2P5

PVCC

V2P5

VClamp

Gen

VAROUTR

V2P5

VCLAMPR

BSRN

Gain

Adj.

PVCCR(2)

Gate

Drive

Cint2

ROUTN(2)

RINN

PGNDR

Deglitch &

Modulation

Logic

Gain

Adj.

Rfdbk2

BSRP

PVCCR(2)

RINP

V2P5

Gate

Drive

ROUTP(2)

PGNDR

Cint2

VREF

VOLUME

VARDIFF

VARMAX

To Gain Adj.

Blocks

Gain

Control

REFGND

ROSC

OC

V2P5

Detect

Ramp

Thermal

VDDok

VCCok

Biases

Startup

Generator

VDD

&

Protection

Logic

COSC

References

AVCC

AVDDREF

AVDD

AVCC

5V LDO

PVCC

AGND

TTL Input

Buffer

SD

VClamp

Gen

VCLAMPL

MODE

MODE_OUT

BSLN

Mode

Control

PVCCL(2)

Gate

Cint2

LOUTN(2)

Drive

V2P5

LINN

LINP

PGNDL

BSLP

Deglitch &

Modulation

Logic

Gain

Adj.

Rfdbk2

PVCCL(2)

Rfdbk2

Gate

Drive

LOUTP(2)

PGNDL

V2P5

Cint2

Gain

Adj.

VAROUTL

3

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NO.

AGND

NAME

26, 30

33

−

Analog ground for digital/analog cells in core

AV

High-voltage analog power supply (8.5 V to 14 V)

5-V Regulated output capable of 100-mA output

CC

DD

29

O

AV REF

DD

7

5-V Reference output—provided for connection to adjacent VREF terminal.

BSLN

BSLP

BSRN

BSRP

COSC

LINN

13

I/O Bootstrap I/O for left channel, negative high-side FET

I/O Bootstrap I/O for left channel, positive high-side FET

I/O Bootstrap I/O for right channel, negative high-side FET

I/O Bootstrap I/O for right channel, positive high-side FET

24

48

37

28

I/O I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5

6

I

Negative differential audio input for left channel

Positive differential audio input for left channel

Class-D 1/2-H-bridge negative output for left channel

Class-D 1/2-H-bridge positive output for left channel

LINP

5

LOUTN

LOUTP

MODE

16, 17

20, 21

34

O

I

Input for MODE control. A logic high on this pin places the amplifier in the variable output mode and the Class-D

outputs are disabled. A logic low on this pin places the amplifier in the Class-D mode and Class-D stereo outputs

are enabled. Variable outputs (VAROUTL and VAROUTR) are still enabled in Class-D mode to be used as

line-level outputs for external amplifiers.

MODE_OUT

35

O

Output for control of the variable output amplifiers. When the MODE pin (34) is a logic high, the MODE_OUT

pin is driven low. When the MODE pin (34) is a logic low, the MODE_OUT pin is driven high. This pin is intended

for MUTE control of an external headphone amplifier. Leave unconnected when not used for headphone

amplifiercontrol.

PGNDL

PGNDR

PVCCL

PVCCR

REFGND

18, 19

42, 43

14, 15

22, 23

38,39

46, 47

12

−

Power ground for left channel H-bridge

Power ground for right channel H-bridge

Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or AV

Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or AV

Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or AV

Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or AV

.

CC

Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC

ground to this terminal.

RINP

3

2

I

Positive differential audio input for right channel

Negative differential audio input for right channel

RINN

ROSC

ROUTN

ROUTP

SD

27

I/O Current setting resistor for ramp generator. Nominally equal to 1/8*V

CC

44, 45

40, 41

1

O

I

Class-D 1/2-H-bridge negative output for right channel

Class-D 1/2-H-bridge positive output for right channel

Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to V

.

CC

VARDIFF

9

I

DC voltage to set the difference in gain between the Class-D and VAROUT outputs. Connect to GND or

AV REF if VAROUT outputs are unconnected.

DD

VARMAX

10

I

DC voltage that sets the maximum gain for the VAROUT outputs. Connect to GND or AV REF if VAROUT

DD

outputs are unconnected.

VAROUTL

VAROUTR

VCLAMPL

VCLAMPR

VOLUME

VREF

31

32

25

36

11

8

O

−

I

Variable output for left channel audio. Line level output for driving external HP amplifier.

Variable output for right channel audio. Line level output for driving external HP amplifier.

Internally generated voltage supply for left channel bootstrap capacitors.

Internally generated voltage supply for right channel bootstrap capacitors.

DC voltage that sets the gain of the Class-D and VAROUT outputs.

Analog reference for gain control section.

I

V2P5

4

O

−

2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended inputs.

Connect to AGND and PGND—should be center point for both grounds.

—

Thermal

Pad

4

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

UNIT

Supply voltage range:

Input voltage range, V

AV

CC,

PV

CC

−0.3 V to 15 V

0 V to 5.5 V

MODE, VREF, VARDIFF, VARMAX, VOLUME

SD

−0.3 V to V + 0.3 V

CC

I

RINN, RINP, LINN, LINP

−0.3 V to 7 V

120 mA

AV

DD

Supply current

Output current,

AVDDREF

10 mA

VAROUTL, VAROUTR

20 mA

Continuous total power dissipation

Operating free-air temperature range, T

See Dissipation Rating Table

−40°C to 85°C

−40°C to 150°C

−65°C to 150°C

260°C

A

Operating junction temperature range, T

Storage temperature range, T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

PACKAGE DISSIPATION RATINGS

PACKAGE

T

A

≤ 25°C

DERATING FACTOR

T

A

= 70°C

T = 85°C

A

(1)

PHP

4.3 W

34.7 mW/°C

2.7 W

2.2 W

(1)

The PowerPAD must be soldered to a thermal land on the printed circuit board. Please refer to the PowerPAD

Thermally Enhanced Package application note (SLMA002).

RECOMMENDED OPERATING CONDITIONS

MIN

8.5

MAX

14

UNIT

Supply voltage, V

CC

PV , AV

CC

V

CC

Volume reference voltage

VREF

3.0

5.5

Volume control pins, input voltage

VARDIFF, VARMAX, VOLUME

SD

2

High-level input voltage, V

IH

V

MODE

SD

3.5

0.8

2

Low-level input voltage, V

IL

MODE

High-level output voltage, V

MODE_OUT, I

= 1 mA

AV −100mV

DD

V

OH

Low-level output voltage, V

= −1 mA

AGND+100mV

OL

MODE, V = 5 V, V

= 14 V

1

30

1

uA

kHz

°C

I

CC

High-level input current, I

IH

SD, V = 14 V, V

CC

I

MODE, V = 0 V, V

= 14 V

I

CC

Low-level input current, I

IL

SD, V = 0 V, V

CC

1

I

Oscillator frequency, f

OSC

225

−40

275

85

Operating free-air temperature, T

A

5

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

DC ELECTRICAL CHARACTERISTICS

T

A

= 25°C, V

= 12 V, R = 8 Ω (unless otherwise noted)

CC

L

PARAMETER

TEST CONDITIONS

MIN

TYP

10

0.5x 0.55x

MAX

UNIT

mV

Class-D Output offset voltage

(measured differentially)

INN and INP connected together,

Gain = 36 dB

| V

OS

|

65

0.45x

V2P5 (terminal 4)

2.5-V Bias voltage

No load

V

AV

DD

I

V

= 0 to 100 mA, SD = 2 V,

= 8 V to 14 V

O

CC

AV

DD

5-V Regulated output

4.5

5.0

5.5

PSRR

Class-D power supply rejection ratio

Class-D mode quiescent current

V

= 11.5 V to 12.5 V

−80

16

7

dB

mA

CC

I

MODE = 2 V, SD = 2 V

28.5

9

CC(class-D)

Variable output mode quiescent current MODE = 3.5 V, SD = 2 V

Class-D mode RMS current at max

CC(varout)

I

R

= 8 Ω, P = 9 W

2

A

CC(class-D – max power)

CC(SD)

L

O

power

I

Supply current in shutdown mode

SD = 0.8 V

1

300

250

550

10

uA

High side

Low side

Total

V

I

= 12 V,

CC

= 1 A,

r

Drain-source on-state resistance

mΩ

O

ds(on)

T = 25°C

J

590

AC ELECTRICAL CHARACTERISTICS FOR CLASS-D OUTPUTS

T

A

= 25°C, V

= 12 V, R = 8 Ω (unless otherwise noted)

CC

L

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

V

= 11.5 V to 12.5 V from 10 Hz to 1 kHz,

CC

k

Supply ripple rejection ratio

Continuous output power

−67

dB

SVR

Gain = 36 dB

THD+N = 1%, f = 1 kHz, R = 8 Ω

7.5

9

W

L

P

O

n

THD+N = 10%, f = 1 kHz, R = 8 Ω

L

79

µV

20 Hz to 22 kHz, No filter, Gain = 0.5 dB

−82

100

−80

−77

−63

dBV

µV

V

Output integrated noise floor

20 Hz to 22 kHz, A-weighted filter,

Gain = 13.2 dB

dBV

dB

Crosstalk, Class-D−Left → Class-D−Right

Crosstalk, Class-D → VAROUT

Gain = 13.2 dB, P = 1 W, R = 8 Ω

O L

Maximum output at THD < 0.5%, Gain = 36 dB

dB

Maximum output at THD+N < 0.5%,

f= 1 kHz, Gain = 36 dB

SNR

Signal-to-noise ratio

96

dB

Thermal trip point

Thermal hystersis

150

20

°C

CHARACTERISTICS FOR VAROUT OUTPUTS

PARAMETER

TEST CONDITIONS

Measured between V2P5 and VAROUT,

Gain = 20 dB, R = 10 kΩ

MIN

TYP

MAX UNITS

|V

|

Output offset voltage

10

mV

OS

L

A

= 7.3 dB, f = 1 kHz, P = 6 mW, R = 32 Ω

0.025%

0.002%

−74

V

O

L

THD+N Total harmonic distortion + noise

A

V

= 7.3 dB, f = 1 kHz, R = 2 kΩ, V = 1 V

rms

L

O

PSRR

DC power supply rejection ratio

Supply ripple rejection ratio

Gain = 20 dB

dB

k

Gain = 20 dB, f = 1 kHz

−95

SVR

Crosstalk, VAROUTL → VAROUTR

Crosstalk, VAROUT → Class-D

Maximum output at THD < 0.5%, Gain = 20 dB

20 Hz to 22 kHz, Gain = 20 dB

−60

−74

75

V

n

Output integrated noise floor

µV

20 Hz to 22 kHz, Gain = −0.3 dB

15

6

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

Table 1. DC Volume Control for Class-D Outputs

VOLTAGE ON THE

VOLUME PIN AS A

PERCENTAGE OF VREF

(INCREASING VOLUME

OR FIXED GAIN)

VOLTAGE ON THE

VOLUME PIN AS A

PERCENTAGE OF

VREF (DECREASING

VOLUME)

GAIN OF CLASS-D

AMPLIFIER

dB

%

(1)

−75

0 − 4.5

0 − 2.9

4.5 − 6.7

2.9 − 5.1

−40.0

−37.5

−35.0

−32.4

−29.9

−27.4

−24.8

−22.3

−19.8

−17.2

−14.7

−12.2

−9.6

6.7 − 8.91

8.9 − 11.1

11.1 − 13.3

13.3 − 15.5

15.5 − 17.7

17.7 − 19.9

19.9 − 22.1

22.1 − 24.3

24.3 − 26.5

26.5 − 28.7

28.7 − 30.9

30.9 − 33.1

33.1 − 35.3

35.3 − 37.5

37.5 − 39.7

39.7 − 41.9

41.9 − 44.1

44.1 − 46.4

46.4 − 48.6

48.6 − 50.8

50.8 − 53.0

53.0 − 55.2

55.2 − 57.4

57.4 − 59.6

59.6 − 61.8

61.8 − 64.0

64.0 − 66.2

66.2 − 68.4

68.4 − 70.6

> 70.6

5.1 − 7.2

7.2 − 9.4

9.4 − 11.6

11.6 − 13.8

13.8 − 16.0

16.0 − 18.2

18.2 − 20.4

20.4 − 22.6

22.6 − 24.8

24.8 − 27.0

27.0 − 29.1

29.1 − 31.3

31.3 − 33.5

33.5 − 35.7

35.7 − 37.9

37.9 − 40.1

40.1 − 42.3

42.3 − 44.5

44.5 − 46.7

46.7 − 48.9

48.9 − 51.0

51.0 − 53.2

53.2 − 55.4

55.4 − 57.6

57.6 − 59.8

59.8 − 62.0

62.0 − 64.2

64.2 − 66.4

66.4 − 68.6

>68.6

−7.1

−4.6

−2.0

†

0.5

3.1

5.6

8.1

10.7

13.2

15.7

18.3

20.8

23.3

25.9

28.4

30.9

33.5

(1)

36.0

(1)

Tested in production. Remaining steps are specified by design.

7

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Table 2. DC Volume Control for VAROUT Outputs

VAROUT_VOLUME (V) − VAROUT_VOLUME (V)

GAIN OF VAROUT

AMPLIFIER

FROM FIGURE 35 − AS

A PERCENTAGE OF

VREF (INCREASING

VOLUME OR FIXED

GAIN)

− FROM FIGURE 35 −

AS A PERCENTAGE OF

VREF (DECREASING

VOLUME)

dB

%

(1)

−66

0 − 4.5

0 − 2.9

4.5 − 6.7

2.9 − 5.1

−56.0

−53.5

−50.9

−48.4

−45.9

−43.3

−40.8

−38.3

−35.7

−33.2

−30.7

−28.1

−25.6

−23.1

−20.5

−18.0

−15.5

6.7 − 8.91

8.9 − 11.1

11.1 − 13.3

13.3 − 15.5

15.5 − 17.7

17.7 − 19.9

19.9 − 22.1

22.1 − 24.3

24.3 − 26.5

26.5 − 28.7

28.7 − 30.9

30.9 − 33.1

33.1 − 35.3

35.3 − 37.5

37.5 − 39.7

39.7 − 41.9

41.9 − 44.1

44.1 − 46.4

46.4 − 48.6

48.6 − 50.8

50.8 − 53.0

53.0 − 55.2

55.2 − 57.4

57.4 − 59.6

59.6 − 61.8

61.8 − 64.0

64.0 − 66.2

66.2 − 68.4

68.4 − 70.6

> 70.6

5.1 − 7.2

7.2 − 9.4

9.4 − 11.6

11.6 − 13.8

13.8 − 16.0

16.0 − 18.2

18.2 − 20.4

20.4 − 22.6

22.6 − 24.8

24.8 − 27.0

27.0 − 29.1

29.1 − 31.3

31.3 − 33.5

33.5 − 35.7

35.7 − 37.9

37.9 − 40.1

40.1 − 42.3

42.3 − 44.5

44.5 − 46.7

46.7 − 48.9

48.9 − 51.0

51.0 − 53.2

53.2 − 55.4

55.4 − 57.6

57.6 − 59.8

59.8 − 62.0

62.0 − 64.2

64.2 − 66.4

66.4 − 68.6

>68.6

(1)

−13.0

−10.4

−7.9

−5.3

−2.8

−0.3

2.3

4.8

7.3

9.9

12.4

14.9

17.5

(1)

20.0

(1)

Tested in production. Remaining steps are specified by design.

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURE

1

Class-D Efficiency

vs Output power

vs Load resistance

vs Supply voltage

vs Output Power

vs Supply voltage

vs Gain

P

O

Class-D Output power

2

3

I

Class-D Supply current

4

CC

5

I

Shutdown supply current

Class-D Input resistance

6

O(sd)

7

vs Frequency

8, 9

10, 11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

THD+N

Class-D Total harmonic distortion + noise

vs Output power

vs Frequency

k

Class-D Supply ripple rejection ratio

Class-D Closed loop response

Class-D Intermodulation performance

Class-D Input offset voltage

Class-D Crosstalk

SVR

vs Common-mode input voltage

vs Frequency

Class-D Mute attenuation

vs Frequency

Class-D Shutdown attenuation

Class-D Common-mode rejection ratio

VAROUT Input resistance

vs Frequency

vs Gain

VAROUT Noise

vs Frequency

VAROUT Closed Loop Response

VAROUT Common-mode rejection ratio

VAROUT Crosstalk

vs Frequency

vs Output power

vs Output voltage

vs Frequency

THD+N

VAROUT Total harmonic distortion + noise

VAROUT Supply ripple rejection ratio

k

SVR

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EFFICIENCY

vs

OUTPUT POWER

vs

LOAD RESISTANCE

100

16

14

f = 1 kHz,

LC Filter,

Class-D,

Resistive Load,

R

L

= 8 Ω

90

80

70

60

50

40

30

20

T

A

= 25°C

12

10

8

V

= 12 V,

CC

THD = 10%

V

= 12 V,

CC

THD = 1%

6

4

V

= 12 V,

CC

Class-D,

LC Filter,

Resistive Load

2

0

V

= 8.5 V,

10

0

CC

V

= 8.5 V,

CC

THD = 10%

THD = 1%

0

2

4

6

8

10

8

10

12

14

16

P

O

− Output Power − W

R

L

− Load Resistance − Ω

Figure 1

Figure 2

OUTPUT POWER

vs

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

17

14

SD = 2 V,

MODE = 2 V,

Class-D,

No Load

16

12

10

15

14

8 Ω Speaker

10% THD+N

8

13

12

6

4

2

8 Ω Speaker

1% THD+N

11

10

T

= 25°C

A

8.5

9

10

11

12

13

14

8.5

9

10

11

12

13

14

V

CC

− Supply Voltage − V

V

CC

− Supply Voltage − V

Figure 3

Figure 4

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SUPPLY CURRENT

vs

SHUTDOWN SUPPLY CURRENT

vs

OUTPUT POWER

SUPPLY VOLTAGE

2.5

2.2

2

V

= 12 V,

SD = 0 V

No Load

CC

MODE = 2 V,

Class-D,

Stereo,

2.0

1.5

1.8

1.6

1.4

1.2

T

A

= 25°C

8 Ω

1.0

0.5

0

1

16 Ω

0.8

0.6

0.4

0

5

10

15

20

8.5

9

10

V

11

12

13

14

− Supply Voltage − V

P

O

− Output Power − W

CC

Figure 6

Figure 5

TOTAL HARMONIC DISTORTION + NOISE

INPUT RESISTANCE

vs

FREQUENCY

GAIN

1

120

100

80

V

R

= 8 V

CC

= 8 Ω

Class-D

L

Gain = +36 dB

Class-D

P

O

= 3 W

0.1

60

40

P

O

= 0.25 W

P

O

= 1.5 W

20

0

0.01

20

100

1k

10k

−50

−30

−10

10

30

50

f − Frequency − Hz

Gain − dB

Figure 7

Figure 8

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

FREQUENCY

10

1

V

R

= 12 V

CC

= 8 Ω

V

R

= 8 V

CC

= 8 Ω

L

Gain = +36 dB

Class-D

Gain = +13.2 dB

Class-D

1

P

O

= 0.5 W

P

O

= 5 W

f = 1 kHz

0.1

f = 20 Hz

0.1

P

O

= 2.5 W

0.01

10 m

100 m

1

10

100

1k

10k

P

O

− Output Power − W

f − Frequency − Hz

Figure 9

Figure 10

TOTAL HARMONIC DISTORTION + NOISE

SUPPLY RIPPLE REJECTION RATIO

vs

OUTPUT POWER

FREQUENCY

10

−40

R

= 8 Ω,

L

V

R

= 12 V

CC

= 8 Ω

C2P5 = 1 µF,

Class-D

L

−45

−50

−55

−60

−65

−70

Gain = +13.2 dB

Class-D

1

f = 20 Hz

V

CC

= 8 V

f = 1 kHz

0.1

V

CC

= 12 V

−75

−80

0.01

10 m

100 m

1

10

20

100

1 k

10 k 20 k

P

O

− Output Power − W

f − Frequency − Hz

Figure 11

Figure 12

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INTERMODULATION PERFORMANCE

CLOSED LOOP RESPONSE

Gain

0

100

50

V

= 12 V, 19 kHz, 20 kHz,

CC

1:1, P = 1 W, R = 8 Ω

−20

O

L

50

0

Gain = +13.2 dB,

BW =20 Hz to 22 kHz,

Class-D

−40

−60

0

No Filter

Phase

−50

−100

−150

−200

−250

−80

−100

−150

−200

−250

−100

−120

−140

V

= 12 V,

CC

Gain = +36 dB,

= 8 Ω

R

L

Class-D

50 100

1 k

10 k

10

100

1 k

10 k

100 k

1 M

f − Frequency − Hz

Figure 13

Figure 14

INPUT OFFSET VOLTAGE

vs

CROSSTALK

vs

COMMON-MODE INPUT VOLTAGE

FREQUENCY

6

5

4

3

0

−10

−20

−30

−40

V

= 12 V,

V

= 12 V

CC

C2P5 = 1 µF,

= 1 W,

CC

Class-D

P

O

Gain = +13.2 dB,

Class-D,

R

= 8 Ω

L

−50

−60

2

1

−70

0

−80

−90

−1

0

1

2

3

4

5

20 k

10 k

20

100

1 k

V

ICM

− Common-Mode Input Voltage − V

f − Frequency − Hz

Figure 15

Figure 16

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MUTE ATTENUATION

vs

SHUTDOWN ATTENUATION

vs

FREQUENCY

−30

−80

−85

V

R

= 12 V,

V

= 12 V,

CC

= 8 Ω,

CC

R = 8 Ω,

L

−40

L

V = 1 V

I

V = 1 V

I

rms

−50 Class-D,

−90 Gain = +13.2 dB,

VOLUME = 0 V

Class-D

−95

−60

−70

−80

−100

−105

−110

−115

−120

−90

−100

−110

−120

−130

−125

−130

10

100

1 k

10 k

10

100

1 k

10 k

f − Frequency − Hz

Figure 17

Figure 18

INPUT RESISTANCE

COMMON-MODE REJECTION RATIO

vs

GAIN

vs

FREQUENCY

160

−40

−50

−60

VAROUT

V

R

= 12 V,

CC

= 8 Ω,

140

120

100

L

C2P5 = 1 µF,

Class-D

80

60

−70

−80

40

−90

20

0

−100

−50

−30

−10

10

30

10

100

1 k

10 k

100 k

Gain − dB

f − Frequency − Hz

Figure 19

Figure 20

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NOISE

vs

FREQUENCY

CLOSED LOOP RESPONSE

175

0

12.9

9.3

Gain

150

V

= 12 V,

−20

−40

CC

Gain = +20 dB,

= 8 Ω

125

100

75

R

L

5.8

2.2

Inputs AC Coupled to GND,

VAROUT,

−60

No Filter

50

−80

−1.3

−4.8

25

Phase

−100

−120

−140

−160

−180

−200

0

−25

−50

−8.4

−11.9

−15.4

−19.0

−22.5

−75

V

= 12 V,

CC

−100

−125

−150

−175

Gain = +7.9

dB,

R

= 8 Ω

L

VAROUT

10

100

1 k

10 k

20

100

1 k

10 k

f − Frequency − Hz

Figure 21

Figure 22

COMMON-MODE REJECTION RATIO

CROSSTALK (VAROUTL-TO-VAROUTR)

vs

FREQUENCY

−40

0

V

R

= 12 V,

V

= 1 V

CC

= 8 Ω ,

O rms,

−42

−44

−46

−48

−50

−52

−54

−56

−10

R = 10 kΩ,

L

VAROUT

L

C2P5 = 1 µF,

VAROUT

−20

−30

−40

−50

G = 20 dB

G = 10 dB

G = 0 dB

G = −10 dB

−60

−70

−80

−58

−60

−90

−100

20

100

1 k

10 k

20

100

1 k

10 k

f− Frequency − Hz

f − Frequency − Hz

Figure 23

Figure 24

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

OUTPUT VOLTAGE

20

10

V

R

= 12 V

= 32 Ω,

CC

L

10

V

R

= 12 V

CC

= 10 kΩ,

Gain = +6 dB,

VAROUT

L

Gain = +6 dB

VAROUT

2

1

2

1

0.2

0.1

0.2

0.1

f = 1 kHz

f = 20 kHz

f = 1 kHz

0.02

0.01

0.02

0.01

f = 20 Hz

0.001

20 m

100 m

1

2

20 µ

100 µ 200 µ

1 m 2 m

10 m 20 m

V

O

− Output Voltage − V

RMS

P

O

− Output Power − W

Figure 25

Figure 26

TOTAL HARMONIC DISTORTION + NOISE

SUPPLY RIPPLE REJECTION RATIO

vs

FREQUENCY

10

−40

−50

−60

−70

−80

−90

V

= 12 V

= 32 Ω,

= 5 mW,

CC

L

R

P

V

= 12 V

CC

VAROUT

O

2

1

Gain = +7.9 dB,

VAROUT

0.2

0.1

0.02

−100

−110

0.01

0.005

20

100

1 k

10 k

20

100

1 k

10 k

f − Frequency − Hz

f − frequency − Hz

Figure 27

Figure 28

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

APPLICATION INFORMATION

C22

1 nF

C23

1 nF

L1

L2

(Bead)

10 µF

PGND

0.1uF

C10

10 nF

C19

10 nF

C18

C15

0.1uF

C9

C7

SD

VCLAMPR

MODE_OUT

GND

SHUTDOWN

C1

PGND

1 µF

RINN

MODEB

RIN−

C2

1 µF

MODE

RINP

C5

1 µF

C13

0.1 µF

C16

10 µF

AVCC

AGND

VCC

V2P5

C3

1 µF

LINP

VAROUTR

VAROUTL

AVDD

C4

1 µF

LINN

LIN−

VAROUTL

AGND

TPA3002D2

1 µF

AVDDREF

VREF

C14

AVDD

COSC

C6

T7

100 nF

R1

P3

50k

VARDIFF

VARMAX

VOLUME

REFGND

10 µF

T6

220pF

P2

50 kΩ

ROSC

AGND

T5

120 kΩ

P1

50 kΩ

AGND

GND

C8

GND

VCLAMPL

1 µF

PGND

AGND

C11

C12

C20

C21

0.1 µF

C17

10 nF

10 µF

PGND

L3

L4

(Bead)

C24

1nF

C25

1nF

Figure 29. Stereo Class-D With Single-Ended Inputs

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

10 µF

BSRP

BSLP

PVCCR

PVCCL

VCC

PVCCR

ROUTP

PGNDR

VCC

LOUTP

ROUT+

LOUT+

PGNDL

LOUTN

GND

PGNDR

ROUTN

PVCCR

BSRN

ROUT−

VCC

LOUTN

LOUT−

VCC

PVCCL

BSLN

Figure 30. Stereo Class-D With Single-Ended Inputs and Stereo Headphone Amplifier Interface

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CLASS-D OPERATION

This section focuses on the class-D operation of the TPA3002D2.

Traditional Class-D Modulation Scheme

The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output

where each output is 180 degrees out of phase and changes from ground to the supply voltage, V . Therefore,

CC

the differential prefiltered output varies between positive and negative V , where filtered 50% duty cycle yields

CC

0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown

in Figure 31. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is

high, causing high loss, thus causing a high supply current.

OUTP

OUTN

+12 V

Differential Voltage

0 V

Across Load

−12 V

Current

Figure 31. Traditional Class-D Modulation Scheme’s Output Voltage and

Current Waveforms Into an Inductive Load With No Input

TPA3002D2 Modulation Scheme

The TPA3002D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage.

However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater

than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50%

and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout

2

most of the switching period, greatly reducing the switching current, which reduces any I R losses in the load.

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OUTP

OUTN

Output = 0 V

Differential

+12 V

Voltage

0 V

Across

−12 V

Load

Current

OUTP

OUTN

Output > 0 V

Differential

Voltage

Across

Load

+12 V

0 V

−12 V

Current

Figure 32. The TPA3002D2 Output Voltage and Current Waveforms Into an Inductive Load

Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme

The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform

results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple

current is large for the traditional modulation scheme, because the ripple current is proportional to voltage

multiplied by the time at that voltage. The differential voltage swing is 2 × V , and the time at each voltage

CC

is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current

from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both

resistive and reactive, whereas an LC filter is almost purely reactive.

The TPA3002D2 modulation scheme has very little loss in the load without a filter because the pulses are very

short and the change in voltage is V

instead of 2 × V . As the output power increases, the pulses widen,

CC

making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but

for most applications the filter is not needed.

An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to

flow through the filter instead of the load. The filter has less resistance than the speaker, which results in less

power dissipation, therefore increasing efficiency.

Effects of Applying a Square Wave Into a Speaker

Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the

waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the

square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching

2

frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f

for frequencies beyond the audio band.

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Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency

switching current. The amount of power dissipated in the speaker may be estimated by first considering the

overall efficiency of the system. If the on-resistance (r

) of the output transistors is considered to cause the

ds(on)

dominant loss in the system, then the maximum theoretical efficiency for the TPA3002D2 with an 8-Ω load is

as follows:

_{Efficiency (theoretical, %) + R ń}ǒ_RL_) r

Ǔ

100% + 8ń(8 ) 0.58) 100% + 93.24%

L

ds(on)

(1)

The maximum measured output power is approximately 7.5 W with an 12-V power supply. The total theoretical

power supplied (P ) for this worst-case condition would therefore be as follows:

(total)

P

+ P ńEfficiency + 7.5 W ń 0.9324 + 8.04 W

(total)

O

(2)

The efficiency measured in the lab using an 8-Ω speaker was 89%. The power not accounted for as dissipated

across the r may be calculated by simply subtracting the theoretical power from the measured power:

ds(on)

Other losses + P

(measured) * P

(theoretical) + 8.43 * 8.04 + 0.387 W

(total)

(3)

The quiescent supply current at 14 V is measured to be 14.3 mA. It can be assumed that the quiescent current

encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any

remaining power is dissipated in the speaker and is calculated as follows:

P

+ 0.387 W * (14 V 14.3 mA) + 0.19 W

(dis)

(4)

Note that these calculations are for the worst-case condition of 7.5 W delivered to the speaker. Since the 0.19 W

is only 2.5% of the power delivered to the speaker, it may be concluded that the amount of power actually

dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the

specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the

power generated from a clipping waveform.

When to Use an Output Filter

Design the TPA3002D2 without the filter if the traces from amplifier to speaker are short (< 1 inch). Powered

speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without

a filter.

Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and

CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high

impedance at high frequencies, but very low impedance at low frequencies.

Use a LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long wires from

the amplifier to the speaker.

33 µH

OUTP

C

2

L

1

C

1

0.1 µF

0.47 µF

33 µH

OUTN

C

3

L

2

0.1 µF

Figure 33. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

Ferrite

Chip Bead

OUTP

1 nF

Ferrite

Chip Bead

OUTN

Figure 34. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)

VOLUME CONTROL OPERATION

Three pins labeled VOLUME, VARDIFF, and VARMAX control the class-D volume when driving speakers and

the VAROUT volume. All of these pins are controlled with a dc voltage, which should not exceed VREF.

When driving speakers in class-D mode, the VOLUME pin is the only pin that controls the gain. Table 1 lists

the gain in class-D mode as determined by the voltage on the VOLUME pin in reference to the voltage on VREF.

If using a resistor divider to fix the gain of the amplifier, the VREF terminal can be directly connected to

AVDDREF and a resistor divider can be connected across VREF and REFGND. (See Figure 29 in the

Applications Section). For fixed gain, calculate the resistor divider values necessary to center the voltage

between the two percentage points given in the first column of Table 1. For example, if a gain of 10.7 dB is

desired, the resistors in the divider network can both be 10 kΩ. With these resistor values, a voltage of 50%

× VREF will be present at the VOLUME pin and result in a class-D gain of 10.7 dB.

If using a DAC to control the class-D gain, VREF and REFGND should be connected to the reference voltage

for the DAC and the GND terminal of the DAC, respectively. For the DAC application, AVDDREF would be left

unconnected. The reference voltage of the DAC provides the reference to the internal gain circuitry through the

VREF input and any fluctuations in the DAC output voltage will not affect the TPA3002D2 gain. The percentages

in the first column of Table 1 should be used for setting the voltages of the DAC when the voltage on the

VOLUME terminal is increased. The percentages in the second column should be used for the DAC voltages

when decreasing the voltage on the VOLUME terminal. Two lookup tables should be used in software to control

the gain based on an increase or decrease in the desired system volume. This is explained further in a section

below.

If using an analog potentiometer to control the gain, it should be connected between VREF and REFGND.

VREF can be connected to AVDDREF or an external voltage source, if desired. The first and second column

in Table 1 should be used to determine the point at which the gain changes depending on the direction that the

potentiometer is turned. If the voltage on the center tap of the potentiometer is increasing, the first column in

Table 1 should be referenced to determine the trip points. If the voltage is decreasing, the trip points in the

second column should be referenced.

The trip point, where the gain actually changes, is different depending on whether the voltage on the VOLUME

terminal is increasing or decreasing as a result of hysteresis about each trip point. The hysteresis ensures that

the gain control is monotonic and does not oscillate from one gain step to another. A pictorial representation

of the volume control can be found in Figure 36. The graph focuses on three gain steps with the trip points

defined in the first and second columns of Table 1 for class-D gain. The dotted lines represent the hysteresis

about each gain step.

VARDIFF AND VARMAX OPERATION

The TPA3002D2 allows the user to specify a difference between the class-D gain and VAROUT gain. This is

desirable to avoid any listening discomfort when plugging in headphones. When interfacing with the variable

outputs, the VARDIFF and VARMAX pins control the VAROUT channel gain proportional to the gain set by the

voltage on the VOLUME pin. When VARDIFF = 0 V, the difference between the class-D gain and the VAROUT

gain is 16 dB. As the voltage on the VARDIFF terminal is increased, the VAROUT channel gain decreases.

Internal to the TPA3002D2 device, the voltage on the VARDIFF terminal is subtracted from the voltage on the

VOLUME terminal and this value is used to determine the VAROUT gain.

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Some audio systems require that the gain be limited in the VAROUT mode to a level that is comfortable for

headphone listening. The VARMAX terminal controls the maximum gain for the VAROUT channels.

The functionality of the VARDIFF and VARMAX pin are combined to fix the VAROUT channel gain. A block

diagram of the combined functionality is shown in Figure 35. The value obtained from the block diagram for

VAROUT_VOLUME is a DC voltage that can be used in conjunction with Table 2 to determine the VAROUT

channel gain. Table 2 lists the gain in VAROUT mode as determined by the VAROUT_VOLUME voltage in

reference to the voltage on VREF.

The timing of the volume control circuitry is controlled by an internal 30 Hz clock. This clock determines the rate

at which the gain changes when adjusting the voltage on the external volume control pins. The gain updates

every 4 clock cycles (nominally 133 ms based on a 30Hz clock) to the next step until the final desired gain is

reached. For example, if the TPA3002D2 is currently in the +0.53 db class-D gain step and the VOLUME pin

is adjusted for maximum gain at +36 dB, the time required for the gain to reach 36dB is 14 steps x 133 ms/step

= 1.862 seconds. Referencing Table 1, there are 14 steps between the +0.53 dB gain step and the maximum

gain step of +36 dB.

VARDIFF (V)

VARMAX (V)

−

Is VARMAX>

(VOLUME−VARDIFF)

?

YES

+

VOLUME−VARDIFF

VOLUME (V)

VAROUT_VOLUME (V) = VOLUME (V) − VARDIFF (V)

NO

VAROUT_VOLUME (V) = VARMAX (V)

Figure 35. Block Diagram of VAROUT Volume Control

Decreasing Voltage on VOLUME Terminal

5.6

3.1

0.5

Increasing Voltage on VOLUME Terminal

2.00

(40.1%*VREF)

2.21

(44.1%*VREF)

(42.3%*VREF)

2.10 2.11

(41.9%*VREF)

Voltage on VOLUME Pin − V

Figure 36. DC Volume Control Operation, VREF = 5 V

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MODE OPERATION

The MODE pin is an input for controlling the output mode of the TPA3002D2. A logic HIGH on this pin disables

the Class-D outputs. A logic LOW on this pin enables the class-D outputs. The VAROUT outputs are active in

both modes and can be used as line level inputs to an external powered subwoofer while driving internal stereo

speakers with the class-D outputs. The trip levels are defined in the specifications table.

For interfacing with an external headphone amplifier like the TPA6110A2, the MODE pin can be connected to

the switch on a headphone jack. When configured like Figure 30, the class-D outputs will be disabled when a

headphone plug is inserted into the headphone jack.

MODE_OUT OPERATION

for controlling the SHUTDOWN pin on an external headphone amplifier like the TPA6110A2 or for interfacing

with other logic. The output voltages for a given load condition are given in the specifications table.

This output is controlled by the MODE pin logic. When the MODE input is driven to a logic low, the MODE_OUT

output drives to a logic high. Conversely, when the MODE pin is driven to a logic high, the MODE_OUT output

drives LOW. The MODE_OUT output is simply the inverted state of the MODE input.

It is designed in this manner because the TPA6110A2 SHUTDOWN input is active high. This allows the

TPA3002D2 to place the TPA6110A2 into the shutdown state when driving internal speakers in the Class-D

mode. Conversely, the MODE_OUT pin drives low to enable the TPA6110A2 headphone amplifier when

headphones are plugged into the headphone jack and the MODE input is driven high.

SELECTION OF COSC AND ROSC

The switching frequency is determined using the values of the components connected to ROSC (pin 27) and

COSC (pin 28) and may be calculated with the following equation:

f

= 6.6 / (R

* C

)

OSC

INTERNAL 2.5-V BIAS GENERATOR CAPACITOR SELECTION

The internal 2.5-V bias generator (V2P5) provides the internal bias for the preamplifier stages on both the

class-D amplifiers and the variable amplifiers. The external input capacitors and this internal reference allow

the inputs to be biased within the optimal common-mode range of the input preamplifiers.

The selection of the capacitor value on the V2P5 terminal is critical for achieving the best device performance.

During startup or recovery from the shutdown state, the V2P5 capacitor determines the rate at which the

amplifier starts up. When the voltage on the V2P5 capacitor equals 0.75xV2P5, or 75% of its final value, the

device turns on and the class-D outputs start switching. The startup time is not critical for the best depop

performance since any pop sound that is heard is the result of the class-D outputs switching on and not the

startup time. However, at least a 0.47-µF capacitor is recommended for the V2P5 capacitor.

A secondary function of the V2P5 capacitor is to filter high frequency noise on the internal 2.5-V bias generator.

INPUT RESISTANCE

Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest

value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the −3 dB

or cutoff frequency also changes by over six times.

Z

f

C

i

Z

i

IN

Input

Signal

The −3-dB frequency can be calculated using equation 5. Input impedance (Z ) vs Gain can be found in

i

Figure 7.

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1

f

+

*3dB

2p Z C

(5)

i i

INPUT CAPACITOR, C

I

In the typical application an input capacitor (C ) is required to allow the amplifier to bias the input signal to the

i

proper dc level (V2P5)for optimum operation. In this case, C and the input impedance of the amplifier (Z ) form

i

a high-pass filter with the corner frequency determined in equation 6.

−3 dB

(6)

1

f

+

c

2pZ C

i

f

c

The value of C is important, as it directly affects the bass (low frequency) performance of the circuit. Consider

i

the example where Z is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 6

i

is reconfigured as equation 7.

1

C +

i

2pZ f

c

(7)

i

In this example, C is 0.4 µF, so one would likely choose a value in the range of 0.47 µF to 1 µF. If the gain is

i

known and will be constant, use Z from Figure 7 (Input Impedance vs Gain) to calculate C . Calculations for

i

C should be based off the impedance at the lowest gain step intended for use in the system. A further

i

consideration for this capacitor is the leakage path from the input source through the input network (C ) and the

i

feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that

reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or

ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor

should face the amplifier input in most applications as the dc level there is held at 2.5 V, which is likely higher

than the source dc level. Note that it is important to confirm the capacitor polarity in the application.

Power Supply Decoupling, C

S

The TPA3002D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling

to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also

prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is

achieved by using two capacitors of different types that target different types of noise on the power supply leads.

For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance

(ESR) ceramic capacitor, typically 0.1 µF placed as close as possible to the device V

lead works best. For

CC

filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near

the audio power amplifier is recommended. The 10-µF capacitor also serves as local storage capacitor for

supplying current during large signal transients on the amplifier outputs.

BSN and BSP Capacitors

The full H-bridge output stages use only NMOS transistors. They therefore require bootstrap capacitors for the

high side of each output to turn on correctly. A 10-nF ceramic capacitor, rated for at least 25 V, must be

connected from each output to its corresponding bootstrap input. Specifically, one 10-nF capacitor must be

connected from xOUTP to xBSP, and one 10-nF capacitor must be connected from xOUTN to xBSN. (See the

application circuit diagram in Figure 29.)

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The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating

power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching

cycle, the bootstrap capacitors attempt to hold the gate-to-source voltage high enough to keep the high-side

MOSFETs turned on. However, there is a leakage path and the voltage on the bootstrap capacitors slowly

decrease while the high-side is conducting.

By driving the outputs into heavy clipping with a sine wave of less than 50 Hz, the bootstrap voltage can

decrease below the minimum V required to keep the high-side output MOSFET turned on. When this occurs,

gs

the output transistor becomes a source-follower and the output drops from V

on pins 25 and 36).

to approximately V

(voltage

CC

clamp

For the majority of applications, driving a square wave at low frequencies is not a design consideration and the

recommended bootstrap capacitor value of 10 nF is acceptable. However, if this is a concern, increasing the

bootstrap capacitors holds the gate voltage for a longer period of time and the drop in the output voltage does

not occur. A value of 220 nF is recommended with a 51 Ω resistor placed in series between the outputs and

bootstrap pins. The 51 Ω series resistor is necessary to limit the current charging and discharging the bootstrap

capacitors.

VCLAMP Capacitors

To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two

internal regulators clamp the gate voltage. Two 1-µF capacitors must be connected from VCLAMPL (pin 25)

and VCLAMPR (pin 36) to ground and must be rated for at least 25 V. The voltages at the VCLAMP terminals

vary with V

and may not be used for powering any other circuitry.

CC

Internal Regulated 5-V Supply (AV

)

DD

The AV

terminal (pin 29) is the output of an internally-generated 5-V supply, used for the oscillator,

DD

preamplifier, and volume control circuitry. It requires a 0.1-µF to 1-µF capacitor, placed very close to the pin,

to ground to keep the regulator stable. The regulator may be used to power an external headphone amplifier

or other circuitry, up to a current limit specified in the specification table. When powering external circuitry, like

the TPA6110A2 headphone amplifier, an additional 10 µF or larger capacitor should be added to the AV

terminal.

DD

AV

− POWER-UP RESPONSE

DD

Power−Up

Ch1

(AV

)

DD

AV

DD

(pin 29)

Ch2

(AV

AV

(pin 33)

CC

)

CC

Ch1 2 V/div

Ch2 5 V/div

M 10.0 µs

Figure 37. Power-Up Response

Differential Input

The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel.

To use the TPA3002D2 EVM with a differential source, connect the positive lead of the audio source to the INP

input and the negative lead from the audio source to the INN input. To use the TPA3002D2 with a single-ended

source, ac ground the INP input through a capacitor equal in value to the input capacitor on INN and apply the

audio source to the INN input. In a single-ended input application, the INP input should be ac-grounded at the

audio source instead of at the device input for best noise performance.

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SD OPERATION

The TPA3002D2 employs a shutdown mode of operation designed to reduce supply current (I ) to the

CC

absolute minimum level during periods of nonuse for power conservation. The SD input terminal should be held

high (see specification table for trip point)during normal operation when the amplifier is in use. Pulling SD low

causes the outputs to mute and the amplifier to enter a low-current state, I

left unconnected, because amplifier operation would be unpredictable.

= 10 µA. SD should never be

CC(SD)

POWER-OFF POP REDUCTION

For the best power-off pop performance, the amplifier should be placed in the shutdown mode prior to removing

the power supply voltage.

Another method to reduce power-off pop can be implemented in the hardware. A 100-µF − 150-µF capacitor

can be added to the AV

terminal in parallel with the 100-nF capacitor shown in Figure 29. The additional

DD

capacitance holds up the regulator voltage for a longer period of time and results in smaller power-off pop.

USING LOW-ESR CAPACITORS

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal)

capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this

resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this

resistance the more the real capacitor behaves like an ideal capacitor.

SHORT-CIRCUIT PROTECTION

The TPA3002D2 has short circuit protection circuitry on the outputs that prevents damage to the device during

output-to-output shorts, output-to-GND shorts, and output-to-V

shorts. When a short-circuit is detected on

CC

the outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling

the voltage on the SD pin to a logic low and back to the logic high state for normal operation. This will clear the

short-circuit flag and allow for normal operation if the short was removed. If the short was not removed, the

protection circuitry will again activate.

The trip-point for the short-circuit protection is nominally set at 8 A. However, this trip point can vary with PCB

layout and the separation of AV

and PV . It is important to connect the AV

pin as close as possible to

CC

all of the PV

pins with a wide (>20 mils) trace. This minimizes the inductance between the two pins and allows

CC

the short-circuit protection to trip at the nominal current. If the inductance between these two pins is large, the

short-circuit protection may inadvertently trip when drive low impedance loads into heavy clipping.

THERMAL PROTECTION

Thermal protection on the TPA3002D2 prevents damage to the device when the internal die temperature

exceeds 150°C. There is a 15 degree tolerance on this trip point from device to device. Once the die

temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are

disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by

20°C. The device begins normal operation at this point with no external system interaction.

THERMAL CONSIDERATIONS: OUTPUT POWER AND MAXIMUM AMBIENT TEMPERATURE

To calculate the maximum ambient temperature, the following equation may be used:

T

= T

– Θ P

JA Dissipated

Amax

Jmax

where: T

= 150°C

Jmax

Θ

= 19°C/W

(2-Layer PCB, 5 sq. in. copper, see Figure 38)

To estimate the power dissipation, the following equation may be used:

= P x ((1 / Efficiency) – 1)

JA

(8)

P

Dissipated

O(average)

Efficiency = ~85% for an 8-Ω load

= ~75% for a 4-Ω load

(9)

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

Example. What is the maximum ambient temperature for an application that requires the TPA3002D2 to drive

7.5 W into stereo 8-Ω speakers?

P

= 15 W × ((1 / 0.85) – 1) = 2.65 W

(P = 7.5 W × 2)

O

Dissipated

T

= 150°C – (19°C/W × 2.65 W) =

Amax

99.65°C

This calculation shows that the TPA3002D2 can drive 7.5 W into an 8-Ω speaker up to the absolute maximum

ambient temperature rating of 85°C, which must never be exceeded.

Figure 38 and Figure 39 show the results of several thermal experiments conducted with the TPA3002D2. Both

figures show that the best thermal performance can be achieved with more copper area for heat dissipation

and an adequate number of thermal vias.

Figure 38 shows two curves for a 2-layer and 4-layer PCB. The 2-layer PCB layout was tightly controlled with

a fixed amount of 2 oz. copper on the bottom layer of the PCB. The amount of copper is shown on the x-axis.

Nine thermal vias of 13 mil (0,33 mm) diameter were drilled under the PowerPad and connected to the bottom

layer. The top layer only consisted of traces for signal routing.

The 4-layer PCB layout was also tightly controlled with a fixed amount of 2 oz. copper in middle GND layer. The

top layer only consisted of traces for signal routing. The bottom and other middle layer were left blank. Nine

thermal vias of 0,33 mm diameter were drilled under the PowerPAD and connected to the middle layer.

Figure 39 shows the effect of the number of thermal vias drilled under the PowerPAD on the thermal

performance of the PCB. The experiment was conducted with a 2-layer PCB and 3 square inches of copper

on the bottom layer. For the best thermal performance, at least 16 vias in a 4x4 pattern should be used under

the PowerPAD. Refer to the TPA3002D2 EVM User’s Manual (SLOU151), for an example layout with a 4x4

via pattern. PCB gerber files are available at request.

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PRINTED CIRCUIT BOARD (PCB) LAYOUT

Because the TPA3002D2 is a class-D amplifier that switches at a high frequency, the layout of the printed circuit

board (PCB) should be optimized according to the following guidelines for the best possible performance.

D

Decoupling capacitors — As described on page 28, the high-frequency 0.1-µF decoupling capacitors

should be placed as close to the PVCC (pin 14, 15, 22, 23, 38, 39, 46, 47) and AV (pin 33) terminals

CC

as possible. The V2P5 (pin 4) capacitor, AV

(pin 29) capacitor, and VCLAMP (pins 25, 36) capacitor

DD

should also be placed as close to the device as possible. Large (10 µF or greater) bulk power supply

decoupling capacitors should be placed near the TPA3002D2 on the PVCCL, PVCCR, and AV

terminals.

CC

D

Grounding — The AV

(pin 33) decoupling capacitor, AV

(pin 29) capacitor, V2P5 (pin 4) capacitor,

DD

CC

COSC (pin 28) capacitor, and ROSC (pin 27) resistor should each be grounded to analog ground (AGND,

pin 26 and pin 30). The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power

ground (PGND, pins 18, 19, 42, 43). Analog ground and power ground may be connected at the

PowerPAD, which should be used as a central ground connection or star ground for the TPA3002D2.

Basically, an island should be created with a single connection to PGND at the PowerPAD.

D

Output filter — The ferrite EMI filter (Figure 34) should be placed as close to the output terminals as

possible for the best EMI performance. The LC filter (Figure 33 should be placed close to the outputs. The

capacitors used in both the ferrite and LC filters should be grounded to power ground.

PowerPAD — The PowerPAD must be soldered to the PCB for proper thermal performance and optimal

reliability. The dimensions of the PowerPAD thermal land should be 5 mm by 5 mm (197 mils by 197 mils).

The PowerPAD size measures 4,55 x 4,55 mm. Four rows of solid vias (four vias per row, 0,3302 mm or

13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a

solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid

vias, not thermal relief or webbed vias. For additional information, please refer to the PowerPAD Thermally

Enhanced Package application note (SLMA002).

For an example layout, refer to the TPA3002D2 Evaluation Module (TPA3002D2EVM) User Manual

(SLOU151). Both the EVM user manual and the PowerPAD application note are available on the TI web site

at http://www.ti.com.

THERMAL RESISTANCE

vs

THERMAL RESISTANCE

vs

COPPER AREA 2-LAYER PCB

COPPER AREA 4-LAYER PCB

35

30

35

30

25

20

15

20

15

1

1.5

2

2.5

3

3.5

4

4.5

5

1

2

3

4

5

Copper Area − sq. Inches

Figure 38. Thermal Resistance

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SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

THERMAL RESISTANCE

vs

THERMAL VIA QUANTITY 2-LAYER PCB

25

24

23

22

21

20

4

6

8

10

12

14

16

Thermal Via Quantity (13 Mil Diameter)

Figure 39. Thermal Resistance

BASIC MEASUREMENT SYSTEM

This application note focuses on methods that use the basic equipment listed below:

D

Audio analyzer or spectrum analyzer

Digital multimeter (DMM)

Oscilloscope

Twisted pair wires

Signal generator

Power resistor(s)

Linear regulated power supply

Filter components

EVM or other complete audio circuit

Figure 40 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine

wave is normally used as the input signal since it consists of the fundamental frequency only (no other

harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The

analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to

reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement

system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package.

The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling

capacitors, (C ), so no additional coupling is required. The generator output impedance should be low to avoid

IN

attenuating the test signal, and is important since the input resistance of APAs is not very high (about 10 kΩ).

Conversely the analyzer-input impedance should be high. The output impedance, R

, of the APA is normally

OUT

in the hundreds of milliohms and can be ignored for all but the power-related calculations.

Figure 40(a) shows a class-AB amplifier system. They take an analog signal input and produce an analog signal

output. These amplifier circuits can be directly connected to the AP-II or other analyzer input.

This is not true of the class-D amplifier system shown in Figure 40(b), which requires low pass filters in most

cases in order to measure the audio output waveforms. This is because it takes an analog input signal and

converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some

analyzers.

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Power Supply

Analyzer

R_L

Signal

Generator

APA

20 Hz − 20 kHz

(a) Basic Class-AB

Power Supply

Class-D APA

Low-Pass RC

Filter

Analyzer

20 Hz − 20 kHz

Signal

Generator

†

R_L

Low-Pass RC

Filter

†

For efficiency measurements with filter-free class-D amplifiers, R should be an inductive load like a

L

speaker.

(b) Filter-Free and Traditional Class-D

Figure 40. Audio Measurement Systems

The TPA3002D2 uses a modulation scheme that does not require an output filter for operation, but they do

sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs

cannot accurately process the rapidly changing square-wave output and therefore record an extremely high

level of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the

analyzer can measure the output sine wave.

DIFFERENTIAL INPUT AND BTL OUTPUT

All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs.

Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.

Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly

used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180

degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling

the output power to the load and eliminating a dc blocking capacitor.

A block diagram of the measurement circuit is shown in Figure 41. The differential input is a balanced input,

meaning the positive (+) and negative (−) pins will have the same impedance to ground. Similarly, the BTL output

equates to a balanced output.

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Evaluation Module

Audio Power

Amplifier

Generator

Analyzer

Low-Pass

RC Filter

C_IN

R_GEN

R_IN

R_OUT

R_ANA

C_ANA

R_L

V_GEN

Low-Pass

RC Filter

R_GEN

R_ANA

C_ANA

Twisted-Pair Wire

Figure 41. Differential Input—BTL output Measurement Circuit

The generator should have balanced outputs and the signal should be balanced for best results. An unbalanced

output can be used, but it may create a ground loop that will affect the measurement accuracy. The analyzer

must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common mode

noise in the circuit and providing the most accurate measurement.

The following general rules should be followed when connecting to APAs with differential inputs and BTL

outputs:

D

Use a balanced source to supply the input signal.

Use an analyzer with balanced inputs.

Use twisted-pair wire for all connections.

Use shielding when the system environment is noisy.

Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large

currents (see Table 3).

Table 3 shows the recommended wire size for the power supply and load cables of the APA system. The real

concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations

are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C.

Table 3. Recommended Minimum Wire Size for Power Cables

P

(W)

R

(Ω)

AWG SIZE

DC POWER LOSS

(MW)

AC POWER LOSS

(MW)

OUT

L

10

4

18

22

28

16

3.2

2.0

1.5

40

8.0

6.1

18

42

8.5

8.1

6.2

2

4

18 22

3.7

2.1

1.6

1

8

22

< 0.75

8

22 28

CLASS-D RC LOW-PASS FILTER

An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width

modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff

frequency is set above the audio band. The high frequency of the square wave has negligible impact on

measurement accuracy because it is well above the audible frequency range and the speaker cone cannot

respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the

class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx).

The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 42.

R is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should

L

be available and substituted for R

and C

. The filter components, R

and C

, can then be derived

ANA

FILT

for the system. The filter should be grounded to the APA near the output ground pins or at the power supply

ground pin to minimize ground loops.

32

www.ti.com

ꢀ ꢁꢂ ꢃꢄꢄ ꢅꢆ ꢅ

SLOS402C − DECEMBER 2002 − REVISED JANUARY 2004

Load

RC Low-Pass Filters

R_FILT

AP Analyzer Input

C_ANA

R_ANA

C_FILT

V_L= V

IN

R_L

V_OUT

R_FILT

C_ANA

R_ANA

C_FILT

To APA

GND

Figure 42. Measurement Low-Pass Filter Derivation Circuit—Class-D APAs

The transfer function for this circuit is shown in equation (10) where ω = R , R = R

C

R

and

O

EQ EQ EQ

FILT

ANA

C

= (C

+ C

). The filter frequency should be set above f

, the highest frequency of the measurement

EQ

FILT

ANA

MAX

bandwidth, to avoid attenuating the audio signal. Equation (11) provides this cutoff frequency, f . The value of

C

R

must be chosen large enough to minimize current that is shunted from the load, yet small enough to

FILT

minimize the attenuation of the analyzer-input voltage through the voltage divider formed by R

and R

.

FILT

ANA

A rule of thumb is that R

error to less than 1% for R

should be small (~100 Ω) for most measurements. This reduces the measurement

ANA

FILT

≥ 10 kΩ.

R

ANA

ǒ Ǔ

R

)R

V

ANA

FILT

OUT

+

ǒ Ǔ

V

w

IN

_{1 ) j}ǒ Ǔ

w

O

(10)

Ǹ

f

+ 2 f

C

MAX

(11)

An exception occurs with the efficiency measurements, where R

must be increased by a factor of ten to

FILT

reduce the current shunted through the filter. C

cutoff frequency. See Table 4 for the recommended filter component values.

must be decreased by a factor of ten to maintain the same

FILT

Once f is determined and R is selected, the filter capacitance is calculated using equation (12). When the

C

FILT

calculated value is not available, it is better to choose a smaller capacitance value to keep f above the minimum

C

desired value calculated in equation (11).

1

C

+

FILT

2p f R

C

FILT

(12)

based on common component values. The value of f

C

Table 4 shows recommended values of R

and C

FILT

was originally calculated to be 28 kHz for an f

of 20 kHz. C

, however, was calculated to be 57000 pF,

MAX

FILT

but the nearest values of 56000 pF and 51000 pF were not available. A 47000 pF capacitor was used instead,

and f is 34 kHz, which is above the desired value of 28 kHz.

C

Table 4. Typical RC Measurement Filter Values

MEASUREMENT

Efficiency

All other measurements

R

C

FILT

1 000 Ω

100 Ω

5 600 pF

56 000 pF

33

PACKAGE OPTION ADDENDUM

www.ti.com

18-Apr-2006

PACKAGING INFORMATION

Orderable Device

TPA3002D2PHP

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTQFP

PHP

48

250 Green (RoHS & CU NIPDAU Level-4-260C-72 HR

no Sb/Br)

TPA3002D2PHPG4

TPA3002D2PHPR

TPA3002D2PHPRG4

HTQFP

PHP

250 Green (RoHS & CU NIPDAU Level-4-260C-72 HR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-4-260C-72 HR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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型号：	TPA3002D2PHPR
厂家：	TEXAS INSTRUMENTS
描述：	9-W STEREO CLASS-D AUDIO POWER AMPLFIER WITH DC VOLUME CONTROL 9 -W立体声D类音频功率放大器采用直流音量控制AMPLFIER 音频控制集成电路消费电路商用集成电路放大器功率放大器 PC
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