TPA3106D1VFPG4 [TI]
40-W MONO CLASS-D AUDIO POWER AMPLIFIER; 40 -W单声道D类音频功率放大器器
| 型号： | TPA3106D1VFPG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 40-W MONO CLASS-D AUDIO POWER AMPLIFIER |
| 文件： | 总36页 (文件大小：1475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA3106D1
HLQFP
www.ti.com
SLOS516C –OCTOBER 2007–REVISED AUGUST 2010
40-W MONO CLASS-D AUDIO POWER AMPLIFIER
Check for Samples: TPA3106D1
1
FEATURES
APPLICATIONS
•
•
Televisions
Powered Speakers
•
•
•
40-W Into an 8-Ω Load From a 25-V Supply
Operates From 10 V to 26 V
Efficient Class-D Operation Eliminates the
Need for Heat Sinks
DESCRIPTION
The TPA3106D1 is a 40-W efficient, Class-D audio
power amplifier for driving bridged-tied stereo
speakers. The TPA3106D1 can drive stereo speakers
as low as 4Ω. The high efficiency, ~92%, of the
TPA3106D1 eliminates the need for an external heat
sink when playing music.
•
•
•
Four Selectable, Fixed Gain Settings
Differential Inputs
Thermal and Short-Circuit Protection With
Auto Recovery Feature
•
•
Clock Output for Synchronization With
Multiple Class-D Devices
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 20, 26, 32, 36 dB.
Surface Mount 7×7, 32-pin HLQFP Package
The outputs are fully protected against shorts to
GND, VCC, and output-to-output shorts with an auto
recovery feature and monitor output.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2010, Texas Instruments Incorporated
TPA3106D1
SLOS516C –OCTOBER 2007–REVISED AUGUST 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
VCC
VI
Supply voltage
AVCC, PVCC
–0.3 V to 30 V
–0.3 V to VCC + 0.3 V
–0.3 V to VREG + 0.5 V
See Thermal Information Table
–40°C to 85°C
SHUTDOWN, MUTE
Input voltage
GAIN0, GAIN1, INN, INP, MSTR/SLV, SYNC
Continuous total power dissipation
TA
Operating free-air temperature range
Operating junction temperature range(2)
Storage temperature range
TJ
–40°C to 150°C
Tstg
RLoad
–65°C to 150°C
Load resistance
3.2 Ω Minimum
Human body model (3) (all pins)
Charged-device model (4) (all pins)
±2 kV
Electrostatic discharge
±500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The TPA3106D1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical
Briefs SLMA002 for more information about using the HTQFP thermal pad.
(3) In accordance with JEDEC Standard 22, Test Method A114-B.
(4) In accordance with JEDEC Standard 22, Test Method C101-A
THERMAL INFORMATION
TPA3106D1
THERMAL METRIC(1) (2)
UNITS
VFP (32 PINS)
qJA
Junction-to-ambient thermal resistance
28.23
32.4
16.6
1
qJCtop
qJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
yJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
yJB
6.7
qJCbot
1.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
10
2
MAX
UNIT
VCC
VIH
VIL
Supply voltage
PVCC, AVCC
26
V
V
V
High-level input voltage
Low-level input voltage
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, SYNC
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, SYNC
SHUTDOWN, VI = VCC, VCC = 24 V
0.8
125
75
2
IIH
High-level input current
MUTE, VI = VCC, VCC = 24 V
µA
GAIN0, GAIN1, MSTR/SLV, SYNC, VI = VREG, VCC = 24 V
SHUTDOWN, VI = 0, VCC = 24 V
2
IIL
Low-level input current
µA
SYNC, MUTE, GAIN0, GAIN1, MSTR/SLV, VI = 0 V, VCC = 24 V
FAULT, IOH = 1 mA
1
VOH
VOL
fOSC
High-level output voltage
Low-level output voltage
Oscillator frequency
VREG – 0.6
200
V
V
FAULT, IOL = -1 mA
AGND + 0.4
300
ROSC resistor = 100 kΩ
kHz
2
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RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
TA
Operating free-air temperature
–40
85
°C
DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = 0 V, Gain = 36 dB
MIN
TYP MAX UNIT
Class-D output offset voltage (measured
| VOS
|
5
50
mV
differentially)
Bypass reference for input amplifier
4-V internal supply voltage
VBYP, no load
1.2
3.8
1.35 1.55
V
V
VREG, no load, VCC = 10 V to 26 V
4.1
–70
14
4.4
17
VCC = 12 V to 24 V, inputs ac coupled to
AGND, Gain = 36 dB
PSRR
DC Power supply rejection ratio
dB
ICC
Quiescent supply current
SHUTDOWN = 2 V, MUTE = 0 V, no load
SHUTDOWN = 0.8 V, no load
MUTE = 2 V, no load
mA
µA
ICC(SD)
Quiescent supply current in shutdown mode
215 250
ICC(MUTE) Quiescent supply current in mute mode
6
200
200
9
mA
High Side
VCC = 12 V, IO = 500 mA,
TJ = 25°C
rDS(on)
Drain-source on-state resistance
Low side
mΩ
Total
400 500
GAIN0 = 0.8 V
GAIN1 = 0.8 V
19
25
31
35
20
26
32
36
25
0.1
21
27
33
37
dB
dB
GAIN0 = 2 V
G
Gain
GAIN0 = 0.8 V
GAIN1 = 2 V
GAIN0 = 2 V
tON
Turn-on time
Turn-off time
C(VBYP) = 1 µF, SHUTDOWN = 2 V
C(VBYP) = 1 µF, SHUTDOWN = 0.8 V
ms
ms
tOFF
DC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Class-D output offset voltage (measured
differentially)
| VOS
|
VI = 0 V, Gain = 36 dB
5
50
mV
Bypass reference for input amplifier
4-V internal supply voltage
VBYP, no load
VREG, no load
1.2
3.8
1.35 1.55
V
V
4.1
–70
10
4.4
14
VCC = 12 V to 24 V, Inputs ac coupled to
AGND, Gain = 36 dB
PSRR
DC Power supply rejection ratio
dB
ICC
Quiescent supply current
SHUTDOWN = 2 V, MUTE = 0 V, no load
SHUTDOWN = 0.8 V, no load
MUTE = 2 V, no load
mA
µA
ICC(SD)
Quiescent supply current in shutdown mode
130 180
ICC(MITE) Quiescent supply current in mute mode
5
200
200
7
mA
High Side
VCC = 12 V, IO = 500 mA,
TJ = 25°C
rDS(on)
Drain-source on-state resistance
Low side
mΩ
Total
400 500
GAIN0 = 0.8 V
GAIN1 = 0.8 V
19
25
31
35
20
26
32
36
25
0.1
21
27
33
37
dB
dB
GAIN0 = 2 V
G
Gain
GAIN0 = 0.8 V
GAIN1 = 2 V
GAIN0 = 2 V
tON
Turn-on time
Turn-off time
C(VBYP) = 1 µF, SHUTDOWN = 2 V
C(VBYP) = 1 µF, SHUTDOWN = 0.8 V
ms
ms
tOFF
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AC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MI
N
TYP MAX UNIT
200 mVPP ripple from 20 Hz–1 kHz,
KSVR
Supply ripple rejection
–88
dB
Gain = 20 dB, Inputs ac-coupled to AGND
THD+N = 7%, f = 1 kHz, VCC = 24 V
THD+N = 10%, f = 1 kHz, VCC = 24 V
32
40
25
PO
Continuous output power
THD+N < 7%, f = 1 kHz, VCC = 24 V, RL = 4 Ω, Thermally limited
by package
W
Total harmonic distortion +
noise
0.2%
THD+N
Vn
f = 1 kHz, PO = 20 W (half-power)
125
–80
µV
Output integrated noise
Signal-to-noise ratio
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
dBV
Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB,
A-weighted
SNR
102
dB
Thermal trip point
Thermal hysteresis
150
30
°C
°C
AC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
KSVR
Supply ripple rejection
–88
dB
THD+N = 7%, f = 1 kHz
8.7
9.2
THD+N = 10%, f = 1 kHz
PO
Continuous output power
W
THD+N = 7%, f = 1 kHz, RL = 4 Ω
THD+N = 10%, f = 1 kHz, RL = 4 Ω
RL = 8 Ω, f = 1 kHz, PO = 5 W
RL = 4 Ω, f = 1 kHz, PO = 8 W
15.6
16.4
0.11%
0.15%
100
THD+N Total harmonic distortion + noise
µV
Vn
Output integrated noise
Signal-to-noise ratio
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80
dBV
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SNR
98
dB
Thermal trip point
Thermal hysteresis
150
30
°C
°C
4
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SLOS516C –OCTOBER 2007–REVISED AUGUST 2010
32-PIN HTQFP (VFP)
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Active low. Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic levels with
compliance to AVCC.
SHUTDOWN
29
I
INP
1
2
5
6
I
I
I
I
Positive audio input
INN
Negative audio input
GAIN0
GAIN1
Gain select least significant bit. TTL logic levels with compliance to VREG.
Gain select most significant bit. TTL logic levels with compliance to VREG.
Active high. Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z, LOW = outputs
enabled). TTL logic levels with compliance to AVCC.
MUTE
30
I
TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only reports short-circuit faults.
Thermal faults are not reported on this terminal.
FAULT
BSP
31
23
O
I/O Bootstrap I/O for left channel, positive high-side FET.
14, 15,
26–28
PVCC
OUTP
PGND
Power supply for left channel H-bridge, not internally connected to AVCC.
21, 22
O
O
Class-D 1/2-H-bridge positive output
Power ground for H-bridge.
16, 17,
24, 25
OUTN
BSN
19, 20
18
Class-D 1/2-H-bridge negative output
I/O Bootstrap I/O for left channel, negative high-side FET.
Internally generated voltage supply forbootstrap capacitor.
Analog ground for digital/analog cells in core.
VCLAMP
AGND
ROSC
13
3, 4, 12
9
I/O I/O for current setting resistor of ramp generator.
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Master/Slave select for determining direction of SYNC terminal. HIGH=Master mode, SYNC terminal is
an output; LOW = slave mode, SYNC terminal accepts a clock input. TTL logic levels with compliance to
VREG.
MSTR/SLV
7
I
Clock input/output for synchronizing multiple class-D devices. Direction determined by MSTR/SLV
terminal. Input signal not to exceed VREG.
SYNC
VBYP
8
I/O
O
Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up time via external capacitor
sizing.
11
4-V regulated output for use by internal cells, GAINx, MUTE, and MSTR/SLV pins only. Not specified for
driving other external circuitry.
VREG
AVCC
10
32
O
High-voltage analog power supply. Not internally connected to PVCCL.
Connect to AGND and PGND – should be star point for both grounds. Internal resistive connection to
AGND and PGND. Thermal vias on the PCB should connect this pad to a large copper area on an
internal or bottom layer for the best thermal performance. The Thermal Pad must be soldered to the
PCB for mechanical reliability.
Thermal Pad
—
—
FUNCTIONAL BLOCK DIAGRAM
PVCC
PVCC
VCLAMP
PVCC
VBYP
AVCC
BSN
VBYP
AVCC
Gain Control
Gate
Drive
OUTN
VClamp
Gen
INN
INP
Gain
Control
PWM
Logic
PVCC
VBYP
BSP
Gate
Drive
To Gain Adj.
Blocks &
Startup Logic
GAIN0
GAIN1
Gain
Control
OUTP
PGND
4
Gain Control
FAULT
SC
Detect
AVCC
VBYP
Thermal
VREGok
VCCok
ROSC
SYNC
VREG
AVCC
Ramp
Generator
Biases
&
References
Startup
Protection
Logic
MSTR/SLV
VREG
4V Reg
VREG
TTL Input Buffer
(VCC Compliant)
SHUTDOWN
TTL Input Buffer
(VREG
Compliant)
MUTE
AGND
6
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TYPICAL CHARACTERISTICS
Table 1. TABLE OF GRAPHS
Y-AXIS
X-AXIS
FIGURE
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 16
Figure 18
Figure 19
Total Harmonic Distortion + N (%)
Total Harmonic Distortion + N (%)
Total Harmonic Distortion + N (%)
Total Harmonic Distortion + N (%)
Total Harmonic Distortion + N (%)
Total Harmonic Distortion + N (%)
Total Harmonic Distortion + N (%)
Total Harmonic Distortion + N (%)
Total Harmonic Distortion + N (%)
Total Harmonic Distortion + N (%)
Total Harmonic Distortion + N (%)
Total Harmonic Distortion + N (%)
Closed Loop Response
Frequency (Hz) (BTL)
Frequency (Hz) (BTL)
Frequency (Hz) (BTL)
Frequency (Hz) (BTL)
Frequency (Hz) (BTL)
Frequency (Hz) (BTL)
Output Power (W) (BTL)
Output Power (W) (BTL)
Output Power (W) (BTL)
Output Power (W) (BTL)
Output Power (W) (BTL)
Output Power (W) (BTL)
Frequency (Hz) (BTL)
Frequency (Hz) (BTL)
Supply Voltage (V) (BTL)
Supply Voltage (V) (BTL)
Output Power (W) (BTL)
Output Power (W) (BTL)
Output Power (W) (BTL)
Closed Loop Response
PO – Output Power (W)
PO – Output Power (W)
Efficiency (%)
Efficiency (%)
Efficiency (%)
ICC – Supply Current (A)
PO – Total Output Power (W) (BTL)
PO – Total Output Power (W) (BTL)
Frequency (Hz) (BTL)
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
ICC – Supply Current (A)
kSVR – Supply Rejection Ratio (dB)
kSVR – Supply Rejection Ratio (dB)
kSVR – Supply Rejection Ratio (dB)
Frequency (Hz) (BTL)
Frequency (Hz) (BTL)
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY
FREQUENCY
10
10
V
= 18 V,
V
= 12 V,
CC
= 8W,
CC
= 8W,
R
R
L
Gain = 20 dB
L
Gain = 20 dB
P
= 5 W
P
= 2.5 W
O
O
1
1
0.1
0.1
P
= 10 W
O
P
= 5 W
O
P
= 1 W
P
= 0.5 W
O
O
0.01
0.01
0.003
0.003
20
100
1k
f - Frequency - Hz
10k 20k
10k 20k
20
100
1k
f - Frequency - Hz
Figure 1.
Figure 2.
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TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY
FREQUENCY
10
5
10
V
= 12 V,
CC
V
= 24 V,
CC
R
= 6 W,
L
R
= 8 W,
L
Gain = 20 dB
L = 15 mH,
C = 2 mF,
Gain = 20 dB
2
1
P
= 5 W
P
= 5 W
O
O
1
0.5
0.2
0.1
P
= 10 W
O
0.1
0.05
P = 1 W
O
0.02
0.01
P
= 1 W
O
0.005
0.01
0.002
0.001
0.003
20
100 200
1k 2k
10k 20k
10k 20k
20
100
1k
f - Frequency - Hz
f - Frequency - Hz
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY
FREQUENCY
10
5
10
5
V
= 18 V,
V
= 12 V,
CC
= 6 W,
CC
= 4 W,
R
R
L
L
2
1
2
1
L = 22 mH,
C = 1 mF,
Gain = 20 dB
L = 15 mH,
C = 2 mF,
Gain = 20 dB
P
= 5 W
P
= 5 W
O
O
0.5
0.5
0.2
0.1
0.2
0.1
P
= 10 W
O
P
= 1 W
0.05
0.05
O
P
= 1 W
O
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20
100 200 1k 2k
f - Frequency - Hz
10k 20k
20
100 200
1k 2k
10k 20k
f - Frequency - Hz
Figure 5.
Figure 6.
8
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TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
20
10
20
V
= 12 V,
V
= 18 V,
CC
= 8 W,
CC
= 8 W,
R
R
L
L
Gain = 20 dB
Gain = 20 dB
1
1
10 kHz
1 kHz
10 kHz
20 Hz
0.1
0.1
20 Hz
1 kHz
1
0.01
0.01
10m
100m
1
10 20 40
10m
100m
10 20 40
P
- Output Power - W
P
- Output Power - W
O
O
Figure 7.
Figure 8.
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
20
10
10
V
= 12 V,
V
= 24 V,
CC
CC
= 8 W,
R
= 6 W,
R
L
L
L = 22 mH,
C = 1 mF,
Gain = 20 dB
Gain = 20 dB
1
1
10 kHz
1 kHz
20 Hz
10 kHz
0.1
0.1
20 Hz
1 kHz
0.01
0.01
100m
P
1
10
50
10m
100m
1
10 20 40
10m
- Output Power - W
O
P
- Output Power - W
O
Figure 9.
Figure 10.
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TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
10
10
V
= 18 V,
CC
V
= 12 V,
CC
R
= 6 W,
L
R
= 4 W,
L
L = 22 mH,
C = 1 mF,
Gain = 20 dB
L = 15 mH,
C = 2 mF,
Gain = 20 dB
1
1
1 kHz
1 kHz
10 kHz
10 kHz
0.1
0.1
20 Hz
20 Hz
0.01
0.01
10m
1
10
50
10m
100m
P
1
10
50
100m
P
- Output Power - W
- Output Power - W
O
O
Figure 11.
Figure 12.
CLOSED LOOP RESPONSE
CLOSED LOOP RESPONSE
vs
vs
FREQUENCY
FREQUENCY
+200
+200
20
20
V
= 24 V, V = 100 mVrms
I
CC
V
= 12 V, V = 100 mVrms
I
CC
+100
+0
+100
+0
1
1
Measurement Low-Pass Filter:
R = 100 W, C = 10 nF
Measurement Low-Pass Filter:
R = 100 W, C = 10 nF
100m
10m
1m
100m
-100
-200
-100
-200
10m
1m
10k
100k
20
100
1k
10k
100k
20
100
1k
f - Frequency - Hz
f - Frequency - Hz
Figure 13.
Figure 14.
10
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OUTPUT POWER
vs
OUTPUT POWER
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
45
40
35
30
25
20
15
10
5
25
20
15
10
5
RL = 8 W
Gain = 20 dB
THD+N=10%
THD+N = 10%
THD+N = 1%
THD+N=1%
RL = 4 W
Gain = 20 dB
0
10
11
12
13
14
10
12
14
16
18
20
22
24
26
Supply Voltage – V
VCC - Supply Voltage - V
Figure 15.
Figure 16.
EFFICIENCY
vs
EFFICIENCY
vs
OUTPUT POWER (BTL)
OUTPUT POWER (BTL)
90
80
100
90
80
70
60
50
40
30
20
10
0
VCC = 12 V
VCC = 18 V
70
60
50
40
30
20
RL = 4 W
VCC = 12 V
RL = 6 W
10
0
0.1
3
7
11 15 19 23 27 31 35 39
0.1
3
7
11
15
19
23
Power Out – W
Power Out – W
Figure 17.
Figure 18.
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EFFICIENCY
vs
SUPPLY CURRENT
vs
OUTPUT POWER (BTL)
TOTAL OUTPUT POWER
100
2.5
2
VCC = 18 V
VCC = 12 V
R
L
= 8 Ω
90
80
70
60
50
40
30
20
10
0
Gain = 32 dB
VCC = 24 V
V
CC
= 18 V
V
CC
= 12 V
1.5
V
CC
= 24 V
1
0.5
0
RL = 8 W
0.1
3
7
11 15 19 23 27 31 35 39
0
10
20
30
40
Power Out – W
PLACE HOLDER
P
O
− Total Output Power − W
Figure 19.
Figure 20.
SUPPLY CURRENT
vs
SUPPLY RIPPLE REJECTION RATIO
vs
TOTAL OUTPUT POWER
FREQUENCY
2.5
+0
V
V
= 12 V,
CC
= 200 mVp-p
ripple
RL = 8 W
-20
2
1.5
-40
-60
VIN = 12 V
1
RL = 4 W
Gain = 20 dB
0.5
-80
0
0.1
-100
1
3
5
7
9
11 13 15 17 19
10k 20k
20
100
1k
Power Out – W
f - Frequency - Hz
Figure 21.
Figure 22.
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SUPPLY RIPPLE REJECTION RATIO
SUPPLY RIPPLE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
+0
-20
-40
-60
+0
V
V
= 18 V,
V
V
= 24 V,
CC
CC
= 200 mVp-p
= 200 mVp-p
ripple
ripple
RL = 8 W
RL = 8 W
-20
-40
-60
-80
-80
-100
-100
20
100
1k
10k 20k
10k 20k
20
100
1k
f - Frequency - Hz
f - Frequency - Hz
Figure 23.
Figure 24.
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APPLICATION INFORMATION
SDZ
MUTE
FAULT
VCC
VCC
Analog
Audio In
INP
PGND
BSP
1.0 mF
20 Ω
INN
33 mH
0.22μF
OUTP
1.0 mF
AGND
C17
1nF
1μF
AGND
OUTP
TPA3106D1
GAIN0
GAIN0
GAIN1
OUTN
OUTN
1nF
1μF
33 mH
GAIN1
MSTR/SLV
SYNC
BSN
MSTR/SLV
20 Ω
SYNC
PGND
Connected at PowerPad
with single point
connection
AGND
PGND
Figure 25. TPA3106D1 Application Circuit With Single-Ended Inputs
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CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3106D1.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out-of-phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0
V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 26. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss and thus causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
0 V
Across Load
-12 V
Current
Figure 26. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an
Inductive Load With No Input
TPA3106D1 Modulation Scheme
The TPA3106D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and
OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most
of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
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OUTP
OUTN
Output = 0 V
Differential
+12 V
Voltage
0 V
Across
-12 V
Load
Current
OUTP
OUTN
Output > 0 V
Differential
Voltage
Across
Load
+12 V
0 V
-12 V
Current
Figure 27. The TPA3100D2 Output Voltage and Current Waveforms Into an Inductive Load
Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3106D1 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
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When to Use an Output Filter for EMI Suppression
Design the TPA3106D1 without the filter if the traces from amplifier to speaker are short (< 10 cm). Powered
speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without
a filter.
Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and
CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high
impedance at high frequencies, but low impedance at low frequencies.
Use an LC output filter if there are low frequency (<1 MHz) EMI-sensitive circuits and/or there are long wires
from the amplifier to the speaker.
When both an LC filter and a ferrite bead filter are used, the LC filter should be placed as close as possible to
the IC followed by the ferrite bead filter.
33 mH
OUTP
L1
C2
1 mF
33 mH
OUTN
L2
C3
1 mF
Figure 28. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
C2
2.2 mF
L1
15 mH
OUTN
C3
L2
2.2 mF
Figure 29. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 30. Typical Ferrite Chip Bead Filter (Chip Bead Example: Fair-Rite 2512067007Y3)
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Adaptive Dynamic Range Control
TPA3106D1
TPA3106D1
Nearest Competitor
Nearest Competitor
t - Time = 100 ms/div
t - Time = 20 ms/div
Figure 31. 1-kHz Sine Output at 10% THD+N
Figure 32. 8-kHz Sine Output at 10% THD+N
The Texas Instruments patent-pending adaptive dynamic range control (ADRC) technology removes the notch
inherent in class-D audio power amplifiers when they come out of clipping. This effect is more severe at higher
frequencies as shown in Figure 32.
Gain Setting via GAIN0 and GAIN1 Inputs
The gain of the TPA3106D1 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 2 are realized by changing the taps on the input resistors and feedback resistors inside
the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings
are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance
from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 12.8 kΩ, which is the absolute minimum input impedance of the TPA3106D1. At the lower gain
settings, the input impedance could increase as high as 38.4 kΩ
Table 2. Gain Setting
INPUT IMPEDANCE
AMPLIFIER GAIN (dB)
(kΩ)
TYP
32
GAIN1
GAIN0
TYP
20
0
0
1
1
0
1
0
1
26
16
32
16
36
16
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INPUT RESISTANCE
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 16 kΩ ±20%, to
the largest value, 32 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the –3 dB or
cutoff frequency may change when changing gain steps.
Z
f
C
i
Z
i
IN
Input
Signal
The –3-dB frequency can be calculated using Equation 1. Use the ZI values given in Table 2.
1
f =
2p Zi Ci
(1)
INPUT CAPACITOR, CI
In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a
high-pass filter with the corner frequency determined in Equation 2.
-3 dB
1
2p Zi Ci
fc
=
f
c
(2)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is
reconfigured as Equation 3.
1
Ci =
2p Zi fc
(3)
In this example, CI is 0.4 µF; so, one would likely choose a value of 0.47 mF as this value is commonly used. If
the gain is known and is constant, use ZI from Table 2 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network (CI) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at 2 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.
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Power Supply Decoupling, CS
The TPA3106D1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 mF to 1 µF placed as close as possible to the device VCC lead works best. For
filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 100 mF per input lines (Pins 14,
15 and pins 26, 27, 28) or greater placed near the audio power amplifier is recommended. The 100 mF capacitor
also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs.
The PVCC terminals provide the power to the output transistors, so a 100 µF or larger capacitor should be
placed on each PVCC terminal. A 10 µF capacitor on the AVCC terminal is adequate.
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be
connected from xOUTP to BSxx, and one 220-nF capacitor must be connected from xOUTN to BSxx. (See the
application circuit diagram in Figure 25.)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
VCLAMP Capacitors
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two
internal regulators clamp the gate voltage. Two 1-mF capacitors must be connected from VCLAMPL and
VCLAMPR to ground and must be rated for at least 16 V. The voltages at the VCLAMPx terminals may vary with
VCC and may not be used for powering any other circuitry.
Internal Regulated 4-V Supply (VREG)
The VREG terminal (pin 10) is the output of an internally generated 4-V supply, used for the oscillator,
preamplifier, and gain control circuitry. It requires a 10-nF capacitor, placed close to the pin, to keep the regulator
stable.
This regulated voltage can be used to control GAIN0, GAIN1, MSTR/SLV, and MUTE terminals, but should not
be used to drive external circuitry.
VBYP Capacitor Selection
The internal bias generator (VBYP) nominally provides a 1.25-V internal bias for the preamplifier stages. The
external input capacitors and this internal reference allow the inputs to be biased within the optimal
common-mode range of the input preamplifiers.
The selection of the capacitor value on the VBYP terminal is critical for achieving the best device performance.
During power up or recovery from the shutdown state, the VBYP capacitor determines the rate at which the
amplifier starts up. When the voltage on the VBYP capacitor equals VBYP, the device starts a 16.4-ms timer.
When this timer completes, the outputs start switching. The charge rate of the capacitor is calculated using the
standard charging formula for a capacitor, I = C x dV/dT. The charge current is nominally equal to 250µA and dV
is equal to VBYP. For example, a 1-µF capacitor on VBYP would take 5 ms to reach the value of VBYP and
begin a 16.4-ms count before the outputs turn on. This equates to a turn-on time of <30 ms for a 1-µF capacitor
on the VBYP terminal.
A secondary function of the VBYP capacitor is to filter high-frequency noise on the internal 1.25-V bias generator.
A value of at least 0.47µF is recommended for the VBYP capacitor. For the best power-up and shutdown pop
performance, the VBYP capacitor should be greater than or equal to the input capacitors.
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ROSC Resistor Selection
The resistor connected to the ROSC terminal controls the class-D output switching frequency using Equation 4:
1
FOSC
=
2 x ROSC x COSC
(4)
COSC is an internal capacitor that is nominally equal to 20 pF. Variation over process and temperature can
result in a ±15% change in this capacitor value.
For example, if ROSC is fixed at 100 kΩ, the frequency from device to device with this fixed resistance could
vary from 217 kHz to 294 kHz with a 15% variation in the internal COSC capacitor. The tolerance of the ROSC
resistor should also be considered to determine the range of expected switching frequencies from device to
device. It is recommended that 1% tolerance resistors be used.
Differential Input
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3106D1 with a differential source, connect the positive lead of the audio source to the INP input and
the negative lead from the audio source to the INN input. To use the TPA3106D1 with a single-ended source, ac
ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply
the audio source to either input. In a single-ended input application, the unused input should be ac grounded at
the audio source instead of at the device input for best noise performance.
SHUTDOWN OPERATION
The TPA3106D1 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held
high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling
SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave
SHUTDOWN unconnected, because amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown or mute mode prior to removing the
power supply voltage.
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MUTE OPERATION
The MUTE pin is an input for controlling the output state of the TPA3106D1. A logic high on this terminal
disables the outputs. A logic low on this pin enables the outputs. This terminal may be used as a quick
disable/enable of outputs when changing channels on a television or transitioning between different audio
sources.
The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be
used to reduce the quiescent current to the absolute minimum level.
The MUTE terminal can also be used with the FAULT output to automatically recover from a short-circuit event.
When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been
detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault
flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is
removed from the output. If a short remains at the output, the cycle continues until the short is removed.
If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate
can be used to combine the functionality of the FAULT output and external MUTE control, see Figure 33.
TPA3106D1
External GPIO
Control
MUTE
FAULT
Figure 33. External MUTE Control
MSTR/SLV and SYNC operation
The MSTR/SLV and SYNC terminals can be used to synchronize the frequency of the class-D output switching
when using multiple amplifiers in a single application. When the MSTR/SLV terminal is high, the output switching
frequency is determined by the selection of the resistor connected to the ROSC terminal (see ROSC Resistor
Selection). The SYNC terminal becomes an output in this mode, and the frequency of this output is also
determined by the selection of the ROSC resistor. This TTL compatible, push-pull output can be connected to
other TPA310X devices such as TPA3100D2, configured in slave mode. The output switching is synchronized to
avoid beat frequencies that could occur in the audio band when two class-D amplifiers in the same system are
switching at slightly different frequencies.
When the MSTR/SLV terminal is low, the output switching frequency is determined by the incoming square wave
on the SYNC input. The SYNC terminal becomes an input in this mode and accepts a TTL compantible square
wave from another TPA310X audio amplifier configured in teh master mode or from an external GPIO. If
connecting to an external GPIO, recommended frequencies are 200 kHz to 300 kHz for proper device operation,
and the maximum amplitude is 4 V.
The sync drive on the TPA3106D1 has been improved relative to other TPA310X devices, so please use the
TPA3106D1 as the MASTER when connected in synchronous operation with other device of the TPA310X
family.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
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SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE
The TPA3106D1 has short-circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short circuit is detected on the
outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the
voltage on the SHUTDOWN pin or MUTE pin. This clears the short-circuit flag and allows for normal operation if
the short was removed. If the short was not removed, the protection circuitry again activates.
The FAULT terminal can be used for automatic recovery from a short-circuit event, or used to monitor the status
with an external GPIO. For automatic recovery from a short-circuit event, connect the FAULT terminal directly to
the MUTE terminal. When a short-circuit event occurs, the FAULT terminal transitions high indicating a
short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and
clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes
if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short
is removed. If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired,
an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see
Figure 33.
THERMAL PROTECTION
Thermal protection on the TPA3106D1 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30°C. The device
begins normal operation at this point with no external system interaction.
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PRINTED-CIRCUIT BOARD (PCB) LAYOUT GENERAL GUIDELINES
Because the TPA3106D1 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
•
•
•
Decoupling capacitors—The high-frequency 1-mF decoupling capacitors should be placed as close to the
PVCC and AVCC terminals as possible. The VBYP capacitor, VREG capacitor, and VCLAMP capacitor
should be placed near the TPA3106D1 on the PVCCL, PVCCR, and AVCC.
Grounding—The AVCC decoupling capacitor, VREG capacitor, VBYP capacitor, and ROSC resistor should
each be grounded to analog ground. Analog ground and power ground should be connected at the thermal
pad, which should be used as a central ground connection or star ground for the TPA3106D1.
Output filter—The ferrite EMI filter (if used) should be placed as close to the output terminals as possible for
the best EMI performance. The LC filter should be placed close to the outputs.
For an example layout, see the TPA3106D1 Evaluation Module User Manual, (SLOU191). Both the EVM user
manual and the thermal pad application note are available on the TI Web site at http://www.ti.com.
BASIC MEASUREMENT SYSTEM
This application note focuses on methods that use the basic equipment listed below:
•
•
•
•
•
•
•
•
•
Audio analyzer or spectrum analyzer
Digital multimeter (DMM)
Oscilloscope
Twisted-pair wires
Signal generator
Power resistor(s)
Linear regulated power supply
Filter components
EVM or other complete audio circuit
Figure 34 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine
wave is normally used as the input signal because it consists of the fundamental frequency only (no other
harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The
analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to
reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement
system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package.
The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling
capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid
attenuating the test signal, and is important because the input resistance of PAs is not high. Conversely, the
analyzer-input impedance should be high. The output resistance, ROUT, of the PA is normally in the hundreds of
milliohms and can be ignored for all but the power-related calculations.
Figure 34(a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal
output. This amplifier circuit can be directly connected to the AP-II or other analyzer input.
This is not true of the class-D amplifier system shown in Figure 34(b), which requires low-pass filters in most
cases in order to measure the audio output waveforms. This is because it takes an analog input signal and
converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some
analyzers.
24
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SLOS516C –OCTOBER 2007–REVISED AUGUST 2010
Power Supply
Analyzer
RL
20 Hz - 20 kHz
Signal
Generator
APA
(a) Basic Class-AB
Power Supply
Low-Pass RC
Filter
Analyzer
Signal
Generator
RL
(See note A)
Class-D APA
20 Hz - 20 kHz
Low-Pass RC
Filter
(b) Filter-Free and Traditional Class-D
A. For efficiency measurements with filter-free Class-D, RL should be an inductive load like a speaker.
Figure 34. Audio Measurement Systems
The device uses a modulation scheme that does not require an output filter for operation, but they do sometimes
require an RC low-pass filter when making measurements. This is because some analyzer inputs cannot
accurately process the rapidly changing square-wave output and therefore record an extremely high level of
distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer can
measure the output sine wave.
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DIFFERENTIAL INPUT AND BTL OUTPUT
All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs.
Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.
Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly
used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180
degrees out of phase. The load is connected between these pins. BTL configuration has the added benefits of
quadrupling the output power to the load and eliminating a dc blocking capacitor.
A block diagram of the measurement circuit is shown in Figure 35. The differential input is a balanced input,
meaning the positive (+) and negative (–) pins have the same impedance to ground. Similarly, the BTL output
equates to a balanced output.
Evaluation Module
Audio Power
Generator
Analyzer
Amplifier
Low-Pass
RC Filter
CIN
RGEN
RIN
RIN
ROUT
RANA
CANA
RL
VGEN
CIN
Low-Pass
RC Filter
ROUT
RGEN
RANA
CANA
Twisted-Pair Wire
Twisted-Pair Wire
Figure 35. Differential Input, BTL Output Measurement Circuit
The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced
output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must
also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in
the circuit and providing the most accurate measurement.
The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:
•
•
•
•
•
Use a balanced source to supply the input signal.
Use an analyzer with balanced inputs.
Use twisted-pair wire for all connections.
Use shielding when the system environment is noisy.
Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 3).
Table 3 shows the recommended wire size for the power supply and load cables of the APA system. The real
concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations
are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C.
Table 3. Recommended Minimum Wire Size for Power Cables
DC POWER LOSS
(MW)
AC POWER LOSS
(MW)
POUT (W)
RL(Ω)
AWG Size
10
4
4
8
8
18
18
22
22
22
22
28
28
16
3.2
2
40
8
18
3.7
2.1
1.6
42
8.5
8.1
6.2
2
1
8
< 0.75
1.5
6.1
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CLASS-D RC LOW-PASS FILTER
An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width
modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff
frequency is set above the audio band. The high frequency of the square wave has negligible impact on
measurement accuracy because it is well above the audible frequency range, and the speaker cone cannot
respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the
class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx).
The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 36. RL
is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be
available and substituted for RANA and CANA. The filter components, RFILT and CFILT, can then be derived for the
system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin
to minimize ground loops.
Load
RC Low-Pass Filters
RFILT
AP Analyzer Input
RANA
CANA
CFILT
VL= V
IN
RL
VOUT
RFILT
RANA
CANA
CFILT
To APA
GND
Figure 36. Measurement Low-Pass Filter Derivation Circuit-Class-D APAs
The transfer function for this circuit is shown in Equation 5 where wO = REQCEQ, REQ = RFILT || RANA and
CEQ = (CFILT + CANA). The filter frequency should be set above fMAX, the highest frequency of the measurement
bandwidth, to avoid attenuating the audio signal. Equation 6 provides this cutoff frequency, fC. The value of RFILT
must be chosen large enough to minimize current that is shunted from the load, yet small enough to minimize the
attenuation of the analyzer-input voltage through the voltage divider formed by RFILT and RANA. A general rule is
that RFILT should be small (~100 Ω) for most measurements. This reduces the measurement error to less than
1% for RANA ≥ 10 kΩ.
RANA
(
)
RANA + RFILT
VOUT
VIN
=
w
1 + j
wO
(5)
(6)
f =
Ö2 x fmax
c
An exception occurs with the efficiency measurements, where RFILT must be increased by a factor of ten to
reduce the current shunted through the filter. CFILT must be decreased by a factor of ten to maintain the same
cutoff frequency. See Table 4 for the recommended filter component values.
Once fC is determined and RFILT is selected, the filter capacitance is calculated. When the calculated value is not
available, it is better to choose a smaller capacitance value to keep fC above the minimum desired value
calculated in Equation 7.
1
CFILT
=
2p x fc x RFILT
(7)
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Table 4 shows recommended values of RFILT and CFILT based on common component values. The value of fC
was originally calculated to be 28 kHz for an fMAX of 20 kHz. CFILT, however, was calculated to be 57,000 pF, but
the nearest values of 56,000 pF and 51,000 pF were not available. A 47,000-pF capacitor was used instead, and
fC is 34 kHz, which is above the desired value of 28 kHz.
Table 4. Typical RC Measurement Filter Values
MEASUREMENT
Efficiency
RFILT
1000 Ω
100 Ω
CFILT
5,600 pF
56,000 pF
All other measurements
spacer
REVISION HISTORY
Changes from Revision B (March 2007) to Revision C
Page
•
Replaced the Dissipations Ratings Table with the Thermal Information Table .................................................................... 2
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TPA3106D1VFP
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
HLQFP
HLQFP
HLQFP
HLQFP
VFP
32
32
32
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
TPA3106D1
TPA3106D1VFPG4
TPA3106D1VFPR
TPA3106D1VFPRG4
ACTIVE
ACTIVE
ACTIVE
VFP
VFP
VFP
250
1000
1000
Green (RoHS
& no Sb/Br)
-40 to 85
TPA3106D1
TPA3106D1
TPA3106D1
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3106D1VFPR
HLQFP
VFP
32
1000
330.0
16.4
9.6
9.6
1.9
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HLQFP VFP 32
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
TPA3106D1VFPR
1000
Pack Materials-Page 2
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