TPA3110D2-Q1 [TI]
具有 SpeakerGuard™ 的汽车类 15W、2 通道、8V 至 26V 电源模拟输入 D 类音频放大器;
| 型号： | TPA3110D2-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 SpeakerGuard™ 的汽车类 15W、2 通道、8V 至 26V 电源模拟输入 D 类音频放大器 放大器 音频放大器 |
| 文件： | 总36页 (文件大小：2566K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPA3110D2-Q1
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
具有 SpeakerGuard™ 的 TPA3110D2-Q1 15W 无滤波器
立体声 D 类音频功率放大器
1 特性
3 说明
1
•
符合汽车应用 标准
具有符合 AEC-Q100 标准的下列特性：
TPA3110D2-Q1 是一款用于驱动桥接式立体声扬声器
的 15W（每通道）高效、D 类音频功率放大器。高级
电磁干扰 (EMI) 抑制技术能够在满足电磁兼容 (EMC)
要求的同时使用户能够在输出端上使用价格低廉的磁珠
滤波器。SpeakerGuard 保护电路系统包含一个可调节
功率限制器和一个 DC 检测电路。可调节功率限制器
允许用户设置一个低于芯片电源电压的虚拟电压轨，以
便限制通过扬声器的电量。DC 检测电路可以测量脉宽
调制 (PWM) 信号的频率和振幅，如果输入电容器受损
或者输入端存在短路，它就会关闭输出级。
•
–
–
–
器件温度 1 级：–40°C 至 125°C 的环境工作温
度范围
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H2
器件组件充电模式 (CDM) ESD 分类等级 C2
•
•
•
由 16V 电源供电时，每通道 15W 进入 8Ω 负载
（在 10% 总谐波失真 (THD)+N 时）
由 13V 电源供电时，每通道 10W 进入 8Ω 负载
（在 10% THD+N 时）
TPA3110D2-Q1 可以驱动低至 4Ω 的立体声扬声器。
该器件具有 90% 的高效率，播放音乐时无需外部散热
器。
由 16V 电源供电时，30W 进入 4Ω 单声道负载
（在 10% THD+N 时）
•
•
•
•
效率高达 90% 的 D 类操作免除了对散热片的需要
宽电源电压范围可实现在 8V 至 26V 的范围内运行
无滤波器运行
输出受到完全的保护以防止到 GND，VCC 和输出到输
出的短接。短路保护和热保护均含有自动恢复功能。
SpeakerGuard™保护电路包括可调节功率限制器
和直流保护
器件信息(1)
•
•
直通式外引脚简化了电路板布局
器件型号
封装
封装尺寸（标称值）
TPA3110D2-Q1
HTSSOP (28)
9.70mm × 4.40mm
具有自动恢复选项的稳健耐用的引脚至引脚短路保
护和热保护
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
•
•
•
出色的 THD+N 和无爆音性能
4 个可选固定增益设置
差分输入
图 1. TPA3110D2-Q1 简化应用原理图
1mF
OUTL+
OUTL-
LINP
LINN
TPA3110D2-Q1
Audio
Source
2 应用
FERRITE
BEAD
OUTPL
OUTR+
OUTR-
RINP
RINN
15W
8W
FILTER
OUTNL
•
针对混合动力汽车/电动汽车 (HEV/EV) 的汽车噪音
生成
GAIN0
GAIN1
FERRITE
BEAD
OUTPR
OUTNR
•
•
汽车用紧急呼叫系统 (eCall)
15W
8W
FILTER
PLIMIT
PBTL
汽车信息娱乐系统（即音响主机、连接网关、组合
仪表、远程信息处理和导航）
Fault
SD
•
适用于盲点检测、安全和警报系统的 ADAS 噪音生
成
8 to 26V
PVCC
•
•
专业音频设备（高性能放大器、高级麦克风）
航空与航天音频系统
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS794
TPA3110D2-Q1
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com.cn
目录
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 18
Power Supply Recommendations...................... 25
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions...................... 4
6.4 Thermal Information.................................................. 5
6.5 DC Characteristics .................................................... 5
6.6 DC Characteristics .................................................... 5
6.7 AC Characteristics .................................................... 6
6.8 AC Characteristics .................................................... 6
6.9 Typical Characteristics ............................................. 7
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 14
8
9
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 27
11 器件和文档支持 ..................................................... 28
11.1 器件支持 ............................................................... 28
11.2 文档支持 ............................................................... 28
11.3 社区资源................................................................ 28
11.4 商标....................................................................... 28
11.5 静电放电警告......................................................... 28
11.6 Glossary................................................................ 28
12 机械、封装和可订购信息....................................... 28
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (December 2012) to Revision B
Page
•
已添加 引脚配置和功能 部分、ESD 额定值 表、特性 说明部分，器件功能模式，应用和实施部分，电源相关建议部
分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分 ................................................................................ 1
Changes from Original (September, 2012) to Revision A
Page
•
Changed TA from 25°C to –40°C to 125°C in DC and AC Characteristics tables.................................................................. 5
2
Copyright © 2012–2015, Texas Instruments Incorporated
TPA3110D2-Q1
www.ti.com.cn
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP With PowerPAD™ IC Package
Top View
1
2
28
27
SD
PVCCL
PVCCL
BSPL
FAULT
3
4
5
6
26
25
24
23
LINP
LINN
OUTPL
PGND
OUTNL
GAIN0
GAIN1
7
22
21
20
19
18
17
16
15
AVCC
AGND
GVDD
PLIMIT
BSNL
8
BSNR
9
OUTNR
PGND
OUTPR
BSPR
10
11
12
13
14
RINN
RINP
NC
PVCCR
PVCCR
PBTL
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled), TTL
logic levels with compliance to AVCC.
1
SD
I
Open drain output used to display short circuit or DC detect fault status. Voltage compliant to
AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin.
Otherwise, both short circuit faults and DC detect faults must be reset by cycling PVCC.
2
FAULT
O
3
4
5
6
7
8
LINP
LINN
I
I
Positive audio input for left channel, biased at 3 V.
Negative audio input for left channel, biased at 3 V.
Gain select least significant bit, TTL logic levels with compliance to AVCC.
Gain select most significant bit, TTL logic levels with compliance to AVCC.
Analog supply
GAIN0
GAIN1
AVCC
AGND
I
I
P
—
Analog signal ground, connect to the thermal pad.
High-side FET gate drive supply. The nominal voltage is 7 V. GVDD should also be used as
a supply for the PLIMIT function.
9
GVDD
O
I
Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit.
Connect directly to GVDD for no power limit.
10
PLIMIT
11
12
13
14
RINN
RINP
NC
I
I
Negative audio input for right channel, biased at 3 V.
Positive audio input for right channel, biased at 3 V.
Not connected
—
I
PBTL
Parallel BTL mode switch
Power supply for right channel H-bridge. Right channel and left channel power supply inputs
are connect internally.
15
16
PVCCR
PVCCR
P
P
Power supply for right channel H-bridge. Right channel and left channel power supply inputs
are connect internally.
17
18
19
20
21
22
23
24
25
26
BSPR
OUTPR
PGND
OUTNR
BSNR
I
O
—
O
I
Bootstrap I/O for right channel, positive high-side FET
Class-D H-bridge positive output for right channel
Power ground for the H-bridges
Class-D H-bridge negative output for right channel
Bootstrap I/O for right channel, negative high-side FET
Bootstrap I/O for left channel, negative high-side FET
Class-D H-bridge negative output for left channel
Power ground for the H-bridges
BSNL
I
OUTNL
PGND
OUTPL
BSPL
O
—
O
I
Class-D H-bridge positive output for left channel
Bootstrap I/O for left channel, positive high-side FET
Copyright © 2012–2015, Texas Instruments Incorporated
3
TPA3110D2-Q1
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
Power supply for left channel H-bridge. Right channel and left channel power supply inputs
are connect internally.
27
PVCCL
P
P
Power supply for left channel H-bridge. Right channel and left channel power supply inputs
are connect internally.
28
PVCCL
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
30
UNIT
V
VCC Supply voltage
AVCC, PVCC
VCC + 0.3
< 10
V
SD, GAIN0, GAIN1, PBTL, FAULT(2)
V/ms
V
Interface pin
voltage
VI
PLIMIT
–0.3
–0.3
GVDD + 0.3
6.3
RINN, RINP, LINN, LINP
BTL: PVCC > 15 V
BTL: PVCC ≤ 15 V
PBTL
V
4.8
Minimum load
resistance
RL
3.2
3.2
Continuous total power dissipation
Operating free-air temperature
Operating junction temperature(3)
See the Thermal Information Table
TA
–40
–40
–65
125
150
150
°C
°C
°C
TJ
Tstg
Storage temperature
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-kΩ resistor in series
with the pins, per application note SLUA626.
(3) The TPA3110D2-Q1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal
protection shutdown. See TI Technical Brief SLMA002 for more information about using the TSSOP thermal pad.
6.2 ESD Ratings
VALUE
±4000
±250
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Machine Model (MM) per JESD22-A115
V(ESD)
Electrostatic discharge
V
±200
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
VIH
VIL
VOL
IIH
Supply voltage
PVCC, AVCC
8
2
26
V
V
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level input current
Low-level input current
Operating free-air temperature
SD, GAIN0, GAIN1, PBTL
SD, GAIN0, GAIN1, PBTL
0.8
0.8
50
V
FAULT, RPULL-UP = 100k, VCC = 26 V
SD, GAIN0, GAIN1, PBTL, VI = 2 V, VCC = 18 V
SD, GAIN0, GAIN1, PBTL, VI = 0.8 V, VCC = 18 V
V
µA
µA
°C
IIL
5
TA
–40
125
4
Copyright © 2012–2015, Texas Instruments Incorporated
TPA3110D2-Q1
www.ti.com.cn
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
6.4 Thermal Information
TPA3110D2-Q1
THERMAL METRIC(1)(2)
PWP (HTSSOP)
UNIT
28 Pins
30.3
33.5
17.5
0.9
θJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
7.2
θJCbot
0.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
6.5 DC Characteristics
TA = –40°C to 125°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = 0 V, Gain = 36 dB
SD = 2 V, no load, PVCC = 24 V
MIN
TYP MAX UNIT
Class-D output offset voltage (measured
differentially)
| VOS
|
1.5
15
mV
ICC
ICC(SD)
Quiescent supply current
32
50
mA
µA
Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 24 V
250 400
240
High side
VCC = 12 V, IO = 500 mA,
rDS(on)
Drain-source on-state resistance
TJ = 25°C
mΩ
dB
Low side
240
GAIN0 = 0.8 V
GAIN0 = 2 V
GAIN0 = 0.8 V
GAIN0 = 2 V
19
25
31
35
20
26
32
36
14
2
21
27
33
37
GAIN1 = 0.8 V
G
Gain
GAIN1 = 2 V
dB
ton
Turn-on time
SD = 2 V
ms
μs
V
tOFF
Turn-off time
SD = 0.8 V
GVDD
tDCDET
Gate drive supply
DC detect time
IGVDD = 100 μA
V(RINN) = 6 V, VRINP = 0 V
6.4
6.9
420
7.4
ms
6.6 DC Characteristics
TA = –40°C to 125°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Class-D output offset voltage (measured
differentially)
| VOS
|
VI = 0 V, Gain = 36 dB
1.5
15
35
mV
ICC
ICC(SD)
Quiescent supply current
SD = 2 V, no load, PVCC = 12 V
20
200
240
240
20
mA
µA
Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 12 V
High side
VCC = 12 V, IO = 500 mA,
rDS(on)
Drain-source on-state resistance
TJ = 25°C
mΩ
dB
Low side
GAIN0 = 0.8 V
GAIN0 = 2 V
GAIN0 = 0.8 V
GAIN0 = 2 V
19
25
31
35
21
27
33
37
GAIN1 = 0.8 V
26
G
Gain
32
GAIN1 = 2 V
dB
36
tON
Turn-on time
SD = 2 V
14
ms
μs
V
tOFF
Turn-off time
SD = 0.8 V
IGVDD = 2 mA
2
GVDD
Gate drive supply
6.4
6.9
7.4
Output voltage maximum under PLIMIT
control
VO
V(PLIMIT) = 2 V; VI = 1 VRMS
6.75
7.90 8.75
V
Copyright © 2012–2015, Texas Instruments Incorporated
5
TPA3110D2-Q1
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com.cn
6.7 AC Characteristics
TA = –40°C to 125°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
200 mVPP ripple at 1 kHz,
Gain = 20 dB, inputs AC-coupled to AGND
KSVR
PO
Power supply ripple rejection
Continuous output power
–70
dB
W
THD+N = 10%, f = 1 kHz, VCC = 16 V
15
0.1%
65
THD+N Total harmonic distortion + noise
VCC = 16 V, f = 1 kHz, PO = 7.5 W (half-power)
µV
dBV
dB
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
VO = 1 VRMS, Gain = 20 dB, f = 1 kHz
–80
Crosstalk
–100
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SNR
fOSC
Signal-to-noise ratio
102
dB
Oscillator frequency
Thermal trip point
Thermal hysteresis
250
310
150
15
350
kHz
°C
°C
6.8 AC Characteristics
TA = –40°C to 125°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
Supply ripple rejection
Continuous output power
TEST CONDITIONS
MIN
TYP
MAX UNIT
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, inputs AC-coupled to AGND
KSVR
PO
–70
dB
W
THD+N = 10%, f = 1 kHz; VCC = 13 V
10
0.06%
65
THD+N Total harmonic distortion + noise
RL = 8 Ω, f = 1 kHz, PO = 5 W (half-power)
µV
dBV
dB
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
Po = 1 W, Gain = 20 dB, f = 1 kHz
–80
Crosstalk
–100
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SNR
fOSC
Signal-to-noise ratio
102
dB
Oscillator frequency
Thermal trip point
Thermal hysteresis
250
310
150
15
350
kHz
°C
°C
6
Copyright © 2012–2015, Texas Instruments Incorporated
TPA3110D2-Q1
www.ti.com.cn
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
6.9 Typical Characteristics
All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the
measurements.
10
1
10
Gain = 20 dB
= 12 V
Gain = 20 dB
V = 18 V
CC
V
CC
Z
L
= 8 Ω + 66 µH
Z = 8Ω+ 66 µH
L
1
0.1
0.1
P
O
= 5 W
P
O
= 10 W
P
O
= 1 W
P
= 0.5 W
0.01
0.001
O
0.01
0.001
P
O
= 5 W
P
O
= 2.5 W
20
100
1k
f − Frequency − Hz
10k 20k
20
100
1k
f − Frequency − Hz
10k 20k
G001
G002
Figure 2. Total Harmonic Distortion vs Frequency (BTL)
Figure 3. Total Harmonic Distortion vs Frequency (BTL)
10
10
Gain = 20 dB
Gain = 20 dB
V
Z
= 12 V
= 6 Ω + 47 µH
V
Z
= 24 V
= 8 Ω + 66 µH
CC
CC
L
L
1
1
0.1
0.1
P = 10 W
O
P
O
= 5 W
P
O
= 1 W
P
O
= 0.5 W
0.01
0.001
0.01
0.001
P
O
= 2.5 W
P
O
= 5 W
20
100
1k
f − Frequency − Hz
10k 20k
20
100
1k
f − Frequency − Hz
10k 20k
G003
G004
Figure 4. Total Harmonic Distortion vs Frequency (BTL)
Figure 5. Total Harmonic Distortion vs Frequency (BTL)
10
10
Gain = 20 dB
Gain = 20 dB
V
= 18 V
= 6 Ω + 47 µH
V
= 12 V
CC
CC
Z = 4 Ω + 33 µH
L
Z
L
1
1
P
O
= 10 W
0.1
0.1
P
O
= 10 W
P
O
= 1 W
0.01
0.001
0.01
0.001
P
O
= 1 W
P
O
= 5 W
P
O
= 5 W
20
100
1k
f − Frequency − Hz
10k 20k
20
100
1k
f − Frequency − Hz
10k 20k
G005
G006
Figure 6. Total Harmonic Distortion vs Frequency (BTL)
Figure 7. Total Harmonic Distortion vs Frequency (BTL)
Copyright © 2012–2015, Texas Instruments Incorporated
7
TPA3110D2-Q1
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com.cn
Typical Characteristics (continued)
All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the
measurements.
10
10
Gain = 20 dB
= 12 V
Gain = 20 dB
V = 18 V
CC
V
CC
Z
L
= 8 Ω + 66 µH
Z
L
= 8 Ω + 66 µH
1
1
f = 20 Hz
f = 1 kHz
f = 20 Hz
0.1
f = 1 kHz
0.1
0.01
0.001
0.01
0.001
f = 10 kHz
10
f = 10 kHz
0.1
0.01
0.1
1
− Output Power − W
50
0.01
1
− Output Power − W
10
50
P
O
G007
P
O
G008
Lighter color represents thermally limited region.
Figure 8. Total Harmonic Distortion + Noise vs Output
Power (BTL)
Figure 9. Total Harmonic Distortion + Noise vs Output
Power (BTL)
10
10
Gain = 20 dB
Gain = 20 dB
V
CC
= 24 V
V
CC
= 12 V
Z
L
= 8 Ω + 66 µH
Z
L
= 6 Ω + 47 µH
1
1
f = 1 kHz
f = 1 kHz
f = 20 Hz
0.1
0.1
0.01
0.001
0.01
0.001
f = 20 Hz
0.1
f = 10 kHz
0.1
f = 10 kHz
10
0.01
1
50
0.01
1
P − Output Power − W
O
10
50
P
O
− Output Power − W
G009
G010
Figure 10. Total Harmonic Distortion + Noise vs Output
Power (BTL)
Figure 11. Total Harmonic Distortion + Noise vs Output
Power (BTL)
10
10
Gain = 20 dB
Gain = 20 dB
V
CC
= 18 V
V
CC
= 12 V
Z
L
= 6 Ω + 47 µH
Z
L
= 4 Ω + 33 µH
1
1
f = 1 kHz
f = 1 kHz
f = 20 Hz
0.1
0.1
0.01
0.001
0.01
0.001
f = 20 Hz
0.1
f = 10 kHz
0.1
f = 10 kHz
0.01
1
10
50
0.01
1
10
50
P
O
− Output Power − W
P − Output Power − W
O
G011
G012
Figure 12. Total Harmonic Distortion + Noise vs Output
Power (BTL)
Figure 13. Total Harmonic Distortion + Noise vs Output
Power (BTL)
8
Copyright © 2012–2015, Texas Instruments Incorporated
TPA3110D2-Q1
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ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Typical Characteristics (continued)
All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the
measurements.
16
14
12
10
8
35
30
25
20
15
10
5
Gain = 20 dB
Gain = 20 dB
= 24 V
V
Z
= 12 V
V
CC
CC
= 4 Ω + 33 µH
L
Z
L
= 8 Ω + 66 µH
6
4
2
0
0
1
2
3
4
5
6
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
PLIMIT
− PLIMIT Voltage − V
G014
V
PLIMIT
− PLIMIT Voltage − V
G013
Note: Dashed lines represent thermally limited regions.
Figure 14. Maximum Output Power vs PLIMIT Voltage (BTL)
Figure 15. Output Power vs PLIMIT Voltage (BTL)
30
100
40
35
30
25
20
15
10
5
Gain = 20 dB
Z
L
= 8 Ω + 66 µH
50
25
20
15
10
5
Phase
Gain
0
−50
−100
−150
−200
−250
−300
THD = 10%
THD = 1%
C = 1 µF
I
Gain = 20 dB
Filter = Audio Precision AUX-0025
= 12 V
V = 0.1 Vrms
V
CC
I
Z
L
= 8 Ω + 66 µH
0
6
8
10 12 14 16 18 20 22 24 26
− Supply Voltage − V
0
20
100
1k
f − Frequency − Hz
10k
100k
V
CC
G016
G015
Note: Dashed lines represent thermally limited regions.
Figure 17. Output Power vs Supply Voltage (BTL)
Figure 16. Gain/Phase vs Frequency (BTL)
25
100
Gain = 20 dB
V
CC
= 12 V
90
80
70
60
50
40
30
20
10
0
V
CC
= 18 V
Z
L
= 4 Ω + 33 µH
V
CC
= 24 V
20
15
10
5
THD = 10%
THD = 1%
Gain = 20 dB
= 8 Ω + 66 µH
Z
L
0
6
8
10
12
14
16
18
0
5
10
15
P − Output Power − W
O
20
25
30
35
40
V
− Supply Voltage − V
CC
G017
G018
Note: Dashed lines represent thermally limited regions.
Note: Dashed lines represent thermally limited regions.
Figure 18. Output Power vs Supply Voltage (BTL)
Figure 19. Efficiency vs Output Power (BTL)
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ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com.cn
Typical Characteristics (continued)
All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the
measurements.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
CC
= 12 V
V
= 18 V
CC
V
CC
= 12 V
V
= 18 V
CC
V
CC
= 24 V
Gain = 20 dB
Gain = 20 dB
LC Filter = 22 µH + 0.68 µF
= 8 Ω
Z
= 6 Ω + 47 µH
L
R
L
0
5
10
15
20
25
0
5
10
15
20
25
P
O
− Output Power − W
G019
P
O
− Output Power − W
G032
Note: Dashed lines represent thermally limited regions.
Figure 20. Efficiency vs Output Power (BTL With LC Filter)
Figure 21. Efficiency vs Output Power (BTL)
100
100
90
90
V
CC
= 12 V
V
CC
= 12 V
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
= 18 V
CC
Gain = 20 dB
H + 0.68
20
Gain = 20 dB
Z = 4 Ω + 33 µH
L
LC Filter = 22 µ
µF
R
= 6 Ω
L
0
5
10
15
25
0
3
6
9
12
P − Output Power − W
O
15
18
P
O
− Output Power − W
G033
G020
Figure 22. Efficiency vs Output Power (BTL With LC Filter)
Figure 23. Efficiency vs Output Power (BTL)
2.6
100
2.4
90
V
CC
= 18 V
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
CC
= 12 V
80
70
60
50
40
30
20
10
0
V
CC
= 12 V
V
CC
= 24 V
Gain = 20 dB
LC Filter = 22 µH + 0.68 µF
= 4 Ω
Gain = 20 dB
= 8 Ω + 66 µH
Z
L
R
L
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
P
O(Tot)
− Total Output Power − W
G021
P
O
− Output Power − W
G034
Note: Dashed lines represent thermally limited regions.
Figure 24. Efficiency vs Output Power (BTL With LC Filter)
Figure 25. Supply Current vs Total Output Power (BTL)
10
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TPA3110D2-Q1
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ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Typical Characteristics (continued)
All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the
measurements.
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
−20
Gain = 20 dB
= 4 Ω + 33 µH
Gain = 20 dB
−30
Z
L
V = 12 V
CC
V
= 1 Vrms
O
L
−40
Z
= 8 Ω + 66 µH
−50
−60
V
CC
= 12 V
−70
−80
Right to Left
−90
−100
−110
−120
−130
Left to Right
0
5
10
15
20
25
30
20
100
1k
f − Frequency − Hz
10k 20k
P
− Total Output Power − W
O(Tot)
G022
G023
Note: Dashed lines represent thermally limited regions.
Figure 27. Crosstalk vs Frequency (BTL)
Figure 26. Supply Current vs Total Output Power (BTL)
0
10
Gain = 20 dB
Gain = 20 dB
V
= 200 mV
pp
= 8 Ω + 66 µH
V
Z
= 24 V
= 4 Ω + 33 µH
ripple
CC
Z
L
−20
−40
L
1
P
O
= 5 W
−60
0.1
V
CC
= 12 V
P
O
= 0.5 W
−80
0.01
0.001
−100
P
O
= 2.5 W
−120
20
100
1k
f − Frequency − Hz
10k 20k
20
100
1k
f − Frequency − Hz
10k 20k
G024
G025
Figure 28. Supply Ripple Rejection Ratio vs Frequency
(BTL)
Figure 29. Total Harmonic Distortion vs Frequency (PBTL)
10
100
40
35
30
25
20
15
10
5
Gain = 20 dB
V
CC
= 24 V
50
Z
L
= 4 Ω + 33 µH
Phase
Gain
1
0
f = 1 kHz
−50
−100
−150
−200
−250
−300
0.1
C = 1 µF
I
Gain = 20 dB
0.01
0.001
Filter = Audio Precision AUX-0025
= 24 V
V = 0.1 Vrms
V
CC
f = 20 Hz
I
Z
L
= 8 Ω + 66 µH
f = 10 kHz
10
0
20
0.01
0.1
1
50
100
1k
f − Frequency − Hz
10k
100k
P
− Output Power − W
O
G026
G027
Figure 30. Total Harmonic Distortion + Noise vs Output
Power (PBTL)
Figure 31. Gain/Phase vs Frequency (PBTL)
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www.ti.com.cn
Typical Characteristics (continued)
All measurements taken at 1 kHz, unless otherwise noted. The TPA3110D2-Q1 EVM (which is available at ti.com) made the
measurements.
40
35
30
25
20
15
10
5
100
90
80
70
60
50
40
30
20
10
0
Gain = 20 dB
= 4 Ω + 33 µH
Z
L
V
= 18 V
CC
V
CC
= 12 V
THD = 10%
THD = 1%
Gain = 20 dB
= 4 Ω + 33 µH
Z
L
0
6
8
10
12
14
16
18
20
0
5
10
15 20
25 30
35 40 45
V
CC
− Supply Voltage − V
G028
P
O
− Output Power − W
G029
Note: Dashed lines represent thermally limited regions.
Figure 33. Efficiency vs Output Power (PBTL)
Figure 32. Output Power vs Supply Voltage (PBTL)
0
2.8
Gain = 20 dB
2.6
Gain = 20 dB
Z
= 4 Ω + 33 µH
V
= 200 mV
ripple pp
= 8 Ω + 66 µH
L
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Z
L
−20
−40
V
= 12 V
CC
−60
V
= 12 V
CC
V
CC
= 18 V
−80
−100
−120
0
5
10
15 20
25
30
35 40 45
20
100
1k
f − Frequency − Hz
10k 20k
P
O
− Output Power − W
G030
G031
Figure 34. Supply Current vs Output Power (PBTL)
Figure 35. Supply Ripple Rejection Ratio vs Frequency
(PBTL)
12
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TPA3110D2-Q1
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ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
7 Detailed Description
7.1 Overview
The TPA3110D2-Q1 is AEC-Q100 qualified with a temperature grade 1 (-40°C to 125°C), HBM ESD
classification level H2, and CDM ESD classification level C2. This automotive audio amplifier also features
several protection mechanisms as follows:
•
•
•
DC Current Detection
–
The TPA3110D2-Q1 protects speakers from DC current by reporting a fault on the FAULT pin and turning
the amplifier outputs to a Hi-Z state when a DC current is detected. The PVCC supply must be cycled to
clear this fault.
Short-Circuit Protection and Automatic Recovery
–
The TPA3110D2-Q1 has short circuit protection from the output pins to VCC, GND, or to each other. If a
short circuit is detected, it will be reported on the FAULT pin and the amplifier outputs will be switched to a
Hi-Z state. The fault can be cleared by cycling the SD pin.
Thermal Protection
–
When the die temperature exceeds 150°C (±15°C) the device enters the shutdown state and the amplifier
outputs are disabled. The TPA3110D2-Q1 recovers automatically when the temperature decreases by
15°C
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7.2 Functional Block Diagram
GVDD
PVCCL
BSPL
PVCCL
PBTL Select
OUTPL FB
Gate
Drive
OUTPL
OUTPL FB
PGND
BSNL
LINP
PWM
Logic
Gain
Control
PLIMIT
GVDD
PVCCL
LINN
PVCCL
OUTNL FB
OUTNL FB
FAULT
SD
Gate
Drive
OUTNL
TTL
Buffer
SC Detect
DC Detect
GAIN0
GAIN1
PGND
Gain
Control
Biases and
References
Ramp
Generator
Startup Protection
Logic
Thermal
Detect
PLIMIT
Reference
PLIMIT
UVLO/OVLO
GVDD
PVCCL
BSNR
AVDD
GVDD
PVCCL
LDO
Regulator
AVCC
GVDD
Gate
Drive
OUTNR
OUTNN FB
OUTNR FB
RINN
RINP
PGND
BSPR
PWM
Logic
Gain
Control
PLIMIT
GVDD
PVCCL
PVCCL
OUTNP FB
Gate
Drive
OUTPR
TTL
Buffer
PBTL Select
PBTL
Select
PBTL
OUTPR FB
AGND
PGND
7.3 Feature Description
7.3.1 DC Detect
TPA3110D2-Q1 has circuitry which protects the speakers from DC current which might occur due to defective
capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault is reported on the
FAULT pin as a low state. The DC detect fault also causes the amplifier to shut down by changing the state of
the outputs to Hi-Z. To clear the DC detect it is necessary to cycle the PVCC supply. Cycling SD does NOT clear
a DC detect fault.
A DC detect fault is issued when the output differential duty-cycle of either channel exceeds 14% (for example,
57%, –43%) for more than 420 msec at the same polarity. This feature protects the speaker from large DC
currents or AC currents less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low
at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive
and negative inputs to avoid nuisance DC detect faults.
The minimum differential input voltages required to trigger the DC detect are shown in Table 1. The inputs must
remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect.
14
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TPA3110D2-Q1
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ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Table 1. DC Detect Threshold
AV (dB)
20
VIN (mV, Differential)
112
56
26
32
36
28
17
7.3.2 Short-Circuit Protection and Automatic Recovery Feature
TPA3110D2-Q1 has protection from overcurrent conditions caused by a short circuit on the output stage. The
short-circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a
Hi-Z state when the short-circuit protection latch is engaged. The latch can be cleared by cycling the SD pin
through the low state.
If automatic recovery from the short-circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This allows the FAULT pin function to automatically drive the SD pin low, which clears the short-circuit
protection latch.
7.3.3 Thermal Protection
Thermal protection on the TPA3110D2-Q1 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device
begins normal operation at this point with no external system interaction.
Thermal protection faults are NOT reported on the FAULT terminal.
7.3.4 GVDD Supply
The GVDD supply is used to power the gates of the output full bridge transistors. It can also be used to supply
the PLIMIT voltage divider circuit. Add a 1-μF capacitor to ground at this pin.
7.4 Device Functional Modes
7.4.1 PBTL Select
Use the PBTL pin to select between PBTL mode when held high or BTL mode when held low. Connect the
speaker between the right and left outputs, with the positive and negative output from each channel tied together.
7.4.2 Gain Setting Through GAIN0 and GAIN1 Inputs
The gain of the TPA3110D2-Q1 is set to one of four options by the state of the GAIN0 and GAIN1 pins.
Changing the gain setting also changes the input impedance of the TPA3110D2-Q1.
Refer to Table 2 for a list of the gain settings.
Table 2. Gain Setting
AMPLIFIER GAIN (dB)
INPUT IMPEDANCE (kΩ)
GAIN1
GAIN0
TYP
20
TYP
60
30
15
9
0
0
1
1
0
1
0
1
26
32
36
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7.4.3 SD Operation
The SD pin can be used to enter the shutdown mode which mutes the amplifier and causes the TPA3110D2-Q1
to enter a low-current state. This mode can also be triggered to improve power-off pop performance.
7.4.4 PLIMIT
The PLIMIT pin limits the output peak-to-peak voltage based on the voltage supplied to the PLIMIT pin. The peak
output voltage is limited to four times the voltage at the PLIMIT pin.
Vinput
PLIMIT = 6.96V Pout = 11.8W
PLIMIT = 3V Pout = 10W
PLIMIT = 1.8V Pout = 5W
TPA3110D2-Q1
Power Limit Function
Vin=1.13V
Freq=1kHz RLoad=8W
PP
Figure 36. PLIMIT Circuit Operation
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply
connected to PVCC. This virtual rail is four times the voltage at the PLIMIT pin. This output voltage can be used
to calculate the maximum output power for a given maximum input voltage and speaker impedance.
2
æ
ö
æ
ç
è
ö
÷
ø
RL
x VP
ç
÷
ç
÷
RL + 2 x RS
è
ø
POUT
Where:
=
for unclipped power
2 x RL
(1)
RS is the total series resistance including RDS(on), and any resistance in the output filter.
RL is the load resistance.
VP is the peak amplitude of the output possible within the supply rail.
VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP
POUT (10%THD) = 1.25 × POUT (unclipped)
16
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TPA3110D2-Q1
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ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Table 3. PLIMIT Typical Operation
OUTPUT POWER
(W)
Output Voltage
TEST CONDITIONS
PLIMIT VOLTAGE
Amplitude (VP-P
)
PVCC = 24 V, VIN = 1 VRMS
,
,
,
,
,
,
,
,
,
36.1 (thermally
limited)
6.97
2.94
2.34
1.62
6.97
3
43
RL = 8 Ω, Gain = 26 dB
PVCC = 24 V, VIN = 1 VRMS
RL = 8 Ω, Gain = 26 dB
15
10
25.2
20
PVCC = 24 V, VIN = 1 VRMS
RL = 8 Ω, Gain = 26 dB
PVCC = 24 V, VIN = 1 VRMS
RL = 8 Ω, Gain = 26 dB
5
14
PVCC = 24 V, VIN = 1 VRMS
RL = 8 Ω, Gain = 20 dB
12.1
27.7
23
PVCC = 24 V, VIN = 1 VRMS
RL = 8 Ω, Gain = 20 dB
PVCC = 24 V, VIN = 1 VRMS
RL = 8 Ω, Gain = 20 dB
1.86
6.97
1.76
5
10.55
5
14.8
23.5
15
PVCC = 12 V, VIN = 1 VRMS
RL = 8 Ω, Gain = 20 dB
PVCC = 12 V, VIN = 1 VRMS
RL = 8 Ω, Gain = 20 dB
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ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPA3110D1-Q1 device is an automotive class-D audio amplifier. It accepts either a stereo single ended or
differential analog input, amplifies the signal, and drives up to 15W across two bridge tied loads, usually stereo
speakers. Because an analog input is needed, this device is often paired with a codec or audio DAC if the audio
source is digital.
The four digital input/output pins, GAIN0, GAIN1, SD, and FAULT, can be pulled up to PVCC. When connecting
these terminals to PVCC, a 100 kΩ-resistor must be put in series to limit the slew rate. One of four gain settings
is used depending on the configuration of GAIN0 and GAIN1. The SD pin is used to put the device in shutdown
or normal mode. The FAULT pin is used to indicate if a DC detect or short circuit fault was detected. The next
few sections explains design considerations and how to choose the external components.
8.2 Typical Application
PVCC
100 μF
0.1 μF
1000 pF
100 kΩ
Control
System
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
SD
PVCCL
PVCCL
BSPL
1 kΩ
FAULT
LINP
0.22 μF
1 mF
FB
1 mF
LINN
GAIN0
GAIN1
AVCC
OUTPL
PGND
OUTNL
BSNL
1000 pF
1000 pF
PVCC
10 Ω
FB
1 mF
0.22 μF
0.22 μF
TPA3110D2-Q1
FB
AGND
GVDD
PLIMIT
RINN
RINP
NC
BSNR
1 mF
9
20
19
18
1000 pF
OUTNR
PGND
OUTPR
BSPR
1 mF
1 mF
10 kΩ
10
11
10 kΩ
1000 pF
Audio
Source
12
13
14
17
16
15
FB
0.22 μF
1 mF
PVCCR
0.1 μF
100 μF
1000 pF
PBTL
PVCCR
GND
29
PowerPAD
PVCC
Figure 37. Stereo Class-D Amplifier With BTL Output and Single-Ended Inputs With Power Limiting
18
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TPA3110D2-Q1
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ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Typical Application (continued)
PVCC
100 μF
0.1 μF
1000 pF
100 kΩ
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Control
SD
PVCCL
PVCCL
BSPL
System
1 kΩ
FAULT
LINP
3
0.47 μF
4
LINN
GAIN0
GAIN1
AVCC
OUTPL
PGND
OUTNL
BSNL
5
FB
6
AVCC
1000 pF
7
PVCC
10 Ω
TPA3110D2-Q1
1 mF
8
BSNR
OUTNR
PGND
AGND
GVDD
PLIMIT
1000 pF
9
1 mF
FB
10
11
12
13
14
0.47 μF
1 mF
OUTPR
BSPR
RINN
RINP
NC
Audio
Source
1 mF
PVCCR
PVCCR
0.1 μF
(1)
100 μF
1000 pF
100 kW
PBTL
AVCC
GND
29
PowerPAD
PVCC
(1) A 100-kΩ resistor is needed if the PVCC slew rate is more than 10 V/ms.
Figure 38. Stereo Class-D Amplifier With PBTL Output and Single-Ended Input
8.2.1 Design Requirements
The typical requirements for designing the external components around the TPA3110D1-Q1 include efficiency
and EMI/EMC performance. For most applications, only a ferrite bead is needed to filter unwanted emissions.
The ripple current is low enough that an LC filter is typically not needed. As the output power increases, causing
the ripple current to increase, an LC filter can be added to improve efficiency. An LC filter can also be added in
cases where additional EMI suppression is needed.
In addition to discussing how to choose a ferrite bead and when to use an LC filter, the following sections also
discuss the input filter and power supply decoupling. The input filter must be chosen with the input impedance of
the amplifier in mind. The cut-off frequency should be chosen so that bass performance is not impacted. Power
supply decoupling is important to ensure that noise from the power line does not impact the audio quality of the
amplifier output.
Copyright © 2012–2015, Texas Instruments Incorporated
19
TPA3110D2-Q1
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com.cn
Typical Application (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 TPA3110D2-Q1 Modulation Scheme
The TPA3110D2-Q1 uses a modulation scheme that allows operation without the classic LC reconstruction filter
when the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The OUTP
and OUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty
cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of
OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load
sits at 0 V throughout most of the switching period, reducing the switching current, which reduces any I2R losses
in the load.
See Figure 43 for a plot of the output waveforms.
8.2.2.2 Ferrite Bead Filter Considerations
Using the advanced emissions suppression technology in the TPA3110D2-Q1 amplifier, it is possible to design a
high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to
accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite
bead used in the filter.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, so it is important to select a material that is effective in the 10- to 100-MHz range which is key to
the operation of the Class-D amplifier. Many of the specifications regulating consumer electronics have
emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30-MHz
and above range from appearing on the speaker wires and the power supply lines which are good antennas for
these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the
range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance,
the resonant frequency of the ferrite bead and capacitor filter should be less than 10 MHz.
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In
this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak
current the amplifier sees. If these specifications are not available, it is also possible to estimate the bead current
handling capability by measuring the resonant frequency of the filter output at low power and at maximum power.
A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of tested
ferrite beads that work well with the TPA3110D2-Q1 include 28L0138-80R-10 and HI1812V101R-10 from
Steward and the 742792510 from Wurth Electronics.
A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics works best.
Additional EMC improvements may be obtained by adding snubber networks from each of the Class-D outputs to
ground. Suggested values for a simple RC series snubber network would be 10 Ω in series with a 330-pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the PGND or the PowerPAD™ integrated
circuit package beneath the chip.
20
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TPA3110D2-Q1
www.ti.com.cn
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Typical Application (continued)
70
60
50
FCC Class B
40
30
20
10
0
30M
230M
430M
630M
830M
f - Frequency - Hz
Figure 39. TPA3110D2-Q1 EMC Spectrum With FCC Class-B Limits
8.2.2.3 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional Class-D amplifier needs an output filter is because the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is
half the period for the traditional modulation scheme. An ideal LC Filter is needed to store the ripple current from
each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC Filter is almost purely reactive.
The TPA3110D2-Q1 modulation scheme has little loss in the load without a filter because the pulses are short
and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making
the ripple current larger. Ripple current could be filtered with an LC Filter for increased efficiency, but for most
applications the filter is not needed.
An LC Filter with a cutoff frequency less than the Class-D switching frequency allows the switching current to
flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
8.2.2.4 When to Use an Output Filter for EMI Suppression
The TPA3110D2-Q1 has been tested with a simple ferrite bead filter for a variety of applications including long
speaker wires up to 125 cm and high power. The TPA3110D2-Q1 EVM passes FCC Class-B specifications
under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic
second order Butterworth filter similar to those shown in the figures below can be used.
Some systems have little power supply decoupling from the AC line but are also subject to line conducted
interference (LCI) regulations. These include systems powered by wall warts and power bricks. In these cases,
the LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using low
frequency ferrite material can also be effective at preventing line conducted interference.
Copyright © 2012–2015, Texas Instruments Incorporated
21
TPA3110D2-Q1
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com.cn
Typical Application (continued)
33 mH
OUTP
C2
L1
1 mF
33 mH
OUTN
C3
L2
1 mF
Figure 40. Typical LC Output Filter, Cutoff Frequency Of 27 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
C2
L1
2.2 mF
15 mH
OUTN
C3
2.2 mF
L2
Figure 41. Typical LC Output Filter, Cutoff Frequency Of 27 kHz, Speaker Impedance = 4 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 42. Typical Ferrite Chip Bead Filter (Chip Bead Example)
22
Copyright © 2012–2015, Texas Instruments Incorporated
TPA3110D2-Q1
www.ti.com.cn
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
Typical Application (continued)
8.2.2.5 Input Resistance
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the
largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the –3 dB or
cutoff frequency may change when changing gain steps.
Z
f
C
i
Z
i
IN
Input
Signal
The –3-dB frequency can be calculated using Equation 2. Use the ZI values given in Table 2.
1
f =
2p Zi Ci
(2)
8.2.2.6 Input Capacitor, CI
In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper DC level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a high-
pass filter with the corner frequency determined in Equation 3.
-3 dB
1
2p Zi Ci
fc
=
f
c
(3)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 3 is
reconfigured as Equation 4.
1
Ci =
2p Zi fc
(4)
In this example, CI is 0.13 µF; so, one would likely choose a value of 0.15 μF as this value is commonly used. If
the gain is known and is constant, use ZI from Table 2 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network (CI) and the feedback network to the load. This
leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the DC level there is held at 3 V, which is likely higher than the source DC level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create DC offset
voltages and it is important to ensure that boards are cleaned properly.
8.2.2.7 BSN and BSP Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 0.22-μF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 0.22-μF capacitor must be
connected from OUTPx to BSPx, and one 0.22-μF capacitor must be connected from OUTNx to BSNx. (See the
application circuit diagram in 图 1.)
Copyright © 2012–2015, Texas Instruments Incorporated
23
TPA3110D2-Q1
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com.cn
Typical Application (continued)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
8.2.2.8 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3110D2-Q1 with a differential source, connect the positive lead of the audio source to the INP input
and the negative lead from the audio source to the INN input. To use the TPA3110D2-Q1 with a single-ended
source, AC-ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP
and apply the audio source to either input. In a single-ended input application, the unused input should be AC-
grounded at the audio source instead of at the device input for best noise performance. For good transient
performance, the impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input DC blocking capacitors to become completely charged during the 14 ms power-up time. If the
input capacitors are not allowed to completely charge, there will be some additional sensitivity to component
matching which can result in pop if the input components are not well matched.
8.2.2.9 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
8.2.3 Application Curve
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
OUTN
Negative Output
0V
OUTP-OUTN
-PVCC
0A
Speaker
Current
Figure 43. The TPA3110D2-Q1 Output Voltage and Current Waveforms into an Inductive Load
24
Copyright © 2012–2015, Texas Instruments Incorporated
TPA3110D2-Q1
www.ti.com.cn
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
9 Power Supply Recommendations
The TPA3110D2-Q1 is a high-performance CMOS audio amplifier that requires adequate power supply
decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply
decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker.
Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of
noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond
wire and copper trace inductances as well as lead frame capacitance, a good quality low equivalent-series-
resistance (ESR) ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be
placed as close to the device PVCC pins and system ground (either PGND pins or PowerPAD™ integrated
circuit package) as possible. For mid-frequency noise due to filter resonances or PWM switching transients as
well as digital hash on the line, another good quality capacitor typically 0.1 μF to 1 µF placed as close as
possible to the device PVCC leads works best.
For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 μF or greater placed
near the audio power amplifier is recommended. The 220-μF capacitor also serves as a local storage capacitor
for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the
power to the output transistors, so a 220-µF or larger capacitor should be placed on each PVCC terminal. A 10-
µF capacitor on the AVCC terminal is adequate. Also, a small decoupling resistor between AVCC and PVCC can
be used to keep high frequency Class-D noise from entering the linear input amplifiers.
Copyright © 2012–2015, Texas Instruments Incorporated
25
TPA3110D2-Q1
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
The TPA3110D2-Q1 can be used with a small, inexpensive ferrite bead output filter for most applications.
However, since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the
printed circuit board. The following suggestions help to meet EMC requirements.
•
Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC terminals as possible. Large (220-µF or greater) bulk power supply decoupling capacitors should
be placed near the TPA3110D2-Q1 on the PVCCL and PVCCR supplies. Local, high-frequency bypass
capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the
thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR
ceramic capacitor between 220 pF and 1000 pF and a larger good quality mid-frequency cap of value
between 0.1 μF and 1 μF to the PVCC connections at each end of the chip.
•
•
Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
PGND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
Grounding—The AVCC (pin 7) decoupling capacitor should be grounded to analog ground (AGND). The
PVCC decoupling capacitors should connect to PGND. Analog ground and power ground should be
connected at the thermal pad, which should be used as a central ground connection or star ground for the
TPA3110D2-Q1.
•
•
Output filter—The ferrite EMI filter (Figure 42) should be placed as close to the output terminals as possible
for the best EMI performance. The LC Filter (Figure 40 and Figure 41) should be placed close to the outputs.
The capacitors used in both the ferrite and LC Filters should be grounded to power ground.
Thermal pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35 mm. Seven rows
of solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application
Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB
footprints, see the figures at the end of this data sheet.
For an example layout, see the TPA3110D2-Q1 Evaluation Module User's Guide, SLOU263. Both the EVM
user's guide and the thermal pad application report are available on the TI website at http://www.ti.com.
26
Copyright © 2012–2015, Texas Instruments Incorporated
TPA3110D2-Q1
www.ti.com.cn
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
10.2 Layout Example
Large bulk
decoupling
capacitor
Smaller high
frequency
decoupling
capacitors
To PVCC
supply
SD
PVCCL
PVCCL
BSPL
FAULT
LINP
LINN
Thermal Pad
OUTPL
PGND
OUTNL
BSNL
Speaker
GAIN0
GAIN1
AVCC
AGND
GVDD
PLIMIT
RINN
RINP
NC
Ferrite Bead
Connect to PVCC supply
Vias to ground
plane
BSNR
OUTNR
PGND
OUTPR
BSPR
Ferrite Bead
Audio input
PVCCR
PVCCR
PBTL
Connect to ground
plane layer
To PVCC
supply
Smaller high
frequency
Via
decoupling
capacitors
Copper trace/pour
Thermal pad
Large bulk
decoupling
capacitor
Figure 44. TPA3110D2-Q1 Layout Example for PBTL Output
版权 © 2012–2015, Texas Instruments Incorporated
27
TPA3110D2-Q1
ZHCSAA4B –SEPTEMBER 2012–REVISED SEPTEMBER 2015
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
TI PCB 热量计算器
11.2 文档支持
11.2.1 相关文档
如需相关文档，请参阅：
《TPA3111D1 的高电压引脚上的最大压摆率》，SLUA626
《PowerPAD™ 热增强型封装》，SLMA002
《TPA3110D2-Q1 评估模块用户指南》，SLOU263
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
SpeakerGuard, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
28
版权 © 2012–2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPA3110D2QPWPRQ1
ACTIVE
HTSSOP
PWP
28
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPA3110Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3110D2QPWPRQ1 HTSSOP PWP
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 28
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TPA3110D2QPWPRQ1
2000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 28
4.4 x 9.7, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/B
www.ti.com
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TPA3111D1PWP
10-W mono, 8- to 26-V supply, analog input Class-D audio amplifier w/ filter free & SpeakerGu 28-HTSSOP -40 to 85
TI
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