TPA3111D1-Q1 [TI]
具有 SpeakerGuard™ 的汽车类 10W、单通道、8V 至 26V 电源模拟输入 D 类音频放大器;
| 型号： | TPA3111D1-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 SpeakerGuard™ 的汽车类 10W、单通道、8V 至 26V 电源模拟输入 D 类音频放大器 放大器 音频放大器 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPA3111D1-Q1
ZHCS790E –MARCH 2012–REVISED DECEMBER 2015
具有 Speakerguard™ 的 TPA3111D1-Q1 10W 无滤波器单声道 D 类音频
功率放大器
1 特性
3 说明
1
•
•
汽车电子 应用认证
具有符合 AEC-Q100 的下列结果：
TPA3111D1-Q1 器件是一款用于驱动桥接式扬声器的
10W 高效 D 类音频功率放大器。高级 EMI 抑制技术
能够在满足 EMC 要求的同时使用户能够在输出端上使
用价格低廉的磁珠滤波器。SpeakerGuard™ 保护电路
系统包含一个可调节功率限制器和一个直流检测电路。
可调节功率限制器允许用户设置低于芯片电源电压的虚
拟电压轨，以便限制通过扬声器的电量。直流检测电路
可以测量 PWM 信号的频率和振幅，如果输入电容器
受损或者输入端存在短路，它就会关断输出级。
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
器件人体放电模型 (HBM) 静电放电 (ESD) 分类
等级 H2
器件 CDM ESD 分类等级 C2
•
•
•
•
由 12V 电源供电时，10W 功率进入 8Ω 负载（在
10% 总谐波失真 (THD)+N 时）
由 8V 电源供电时，7W 功率进入 4Ω 负载（在
10% THD+N 时）
TPA3111D1-Q1 可驱动一个低至 4Ω 的单声道扬声
器。播放音乐时，TPA3111D1-Q1 器件大于 90% 的
高效率免除了对于外部散热片的需要。
进入 8Ω 负载的 94% 高效 D 类运行免除了对散热
片的需要
宽电源电压范围允许在 8 至 26 V 的电压范围内工
作
输出受到完全的保护以防止到 GND，VCC，和输出到
输出的短接。短路保护和热保护均含有自动恢复功能。
•
•
无滤波器运行
器件信息(1)
SpeakerGuard™扬声器保护包括可调节功率限制
器和 DC 保护
器件型号
封装
封装尺寸（标称值）
•
•
直通式外引脚简化了电路板布局设计
TPA3111D1-Q1
HTSSOP (28)
9.70mm × 4.40mm
具有自动恢复选项的稳健耐用引脚至引脚短路保护
和热保护
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
简化应用示意图
•
•
•
出色的 THD+N 和无爆音性能
4 个可选固定增益设置
差分输入
1 µF
OUT+
OUT–
INP
INN
TPA3111D1-Q1
Audio
Source
2 应用
Ferrite
Bead
Filter
OUTP
OUTN
10 W
8 Ω
•
针对混合动力汽车/电动汽车 (HEV/EV) 的汽车噪音
生成
GAIN0
GAIN1
PLIMIT
•
•
汽车紧急呼叫 (eCall) 系统
汽车信息娱乐系统（音响主机、仪表盘、远程信息
处理、导航）
Fault
SD
PVCC
8 to 26 V
•
•
汽车连接网关
专业音频设备(PA 扬声器、工作室耳机、高性能放
大器、高级麦克风）
•
航空与航天音频系统
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS759
TPA3111D1-Q1
ZHCS790E –MARCH 2012–REVISED DECEMBER 2015
www.ti.com.cn
目录
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
Power Supply Recommendations...................... 21
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 DC Characteristics: VCC = 24 V ................................ 5
6.6 DC Characteristics: VCC = 12 V ............................... 5
6.7 AC Characteristics: VCC = 24 V ................................ 6
6.8 AC Characteristics: VCC = 12 V ................................ 6
6.9 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 22
11 器件和文档支持 ..................................................... 23
11.1 文档支持................................................................ 23
11.2 社区资源................................................................ 23
11.3 商标....................................................................... 23
11.4 静电放电警告......................................................... 23
11.5 Glossary................................................................ 23
12 机械、封装和可订购信息....................................... 23
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision D (August 2015) to Revision E
Page
•
Updated active-low pin names to include the overbar throughout the document ............................................................... 10
Changes from Revision C (December 2012) to Revision D
Page
•
已添加 ESD 额定值表，特性 说明 部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文
档支持部分以及机械、封装和可订购信息部分........................................................................................................................ 1
Changes from Revision B (September 2012) to Revision C
Page
•
•
•
•
•
Changed AEC-Q100-003 to per JESD22-A115 in Abs Max table. ........................................................................................ 4
Changed TA from 25°C to –40°C to 125°C............................................................................................................................. 5
Changed TA from 25°C to –40°C to 125°C............................................................................................................................. 5
Changed TA from 25°C to –40°C to 125°C............................................................................................................................. 6
Changed TA from 25°C to –40°C to 125°C............................................................................................................................. 6
2
Copyright © 2012–2015, Texas Instruments Incorporated
TPA3111D1-Q1
www.ti.com.cn
ZHCS790E –MARCH 2012–REVISED DECEMBER 2015
5 Pin Configuration and Functions
PWP Package
28-Pin HSSOP With PowerPAD™
Top View
SD
FAULT
GND
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PVCC
PVCC
BSN
2
3
GND
4
OUTN
PGND
OUTN
BSN
GAIN0
GAIN1
AVCC
AGND
GVDD
PLIMIT
INN
5
6
7
Thermal
Pad
8
BSP
9
OUTP
PGND
OUTP
BSP
10
11
12
13
14
INP
NC
PVCC
PVCC
AVCC
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
AGND
AVCC
AVCC
BSN
NO.
8
—
P
P
I
Analog supply ground, connect to the thermal pad.
Analog supply
7
14
Connect AVCC supply to this pin
Bootstrap I/O for negative high-side FET
Bootstrap I/O for positive high-side FET
22, 26
17, 21
BSP
I
Open drain output used to display short circuit or DC-detect fault status. Voltage compliant to AVCC. Short
circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise both short circuit
faults and DC-detect faults must be reset by cycling PVCC.
FAULT
2
O
GAIN0
GAIN1
GND
5
6
I
I
Gain select least significant bit. TTL logic levels with compliance to AVCC.
Gain select most significant bit. TTL logic levels with compliance to AVCC.
Connect to local ground
3, 4
—
High-side FET gate drive supply, nominal voltage is 7 V. This pin can also be used as supply for PLIMIT
divider. Add a 1-μF capacitor to ground at this pin.
GVDD
9
O
INN
11
12
I
Negative audio input, biased at 3 V.
Positive audio input, biased at 3 V.
Not connected
INP
I
NC
13
—
O
O
—
OUTN
OUTP
PGND
23, 25
18, 20
19, 24
Class-D H-bridge negative output
Class-D H-bridge positive output
Power ground for the H-bridges
Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a 1-μF capacitor to ground
at this pin.
PLIMIT
PVCC
SD
10
I
P
I
15, 16,
27, 28
Power supply for H-bridge. PVCC pins are also connected internally.
Shutdown logic input for audio amplifier (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels
with compliance to AVCC.
1
Copyright © 2012–2015, Texas Instruments Incorporated
3
TPA3111D1-Q1
ZHCS790E –MARCH 2012–REVISED DECEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
30
UNIT
V
VCC
Supply voltage
AVCC, PVCC
VCC + 0.3 V
< 10
V
(2)
SD, FAULT,GAIN0, GAIN1, AVCC
V/ms
V
VI
Interface pin voltage
PLIMIT
–0.3
–0.3
GVDD + 0.3
6.3
INN, INP
V
Continuous total power dissipation
See Thermal Information
Minimum load
BTL
RL
3.2
resistance
TA
Operating free-air temperature range
Operating junction temperature range(3)
Storage temperature range
–40
–40
–65
125
150
150
°C
°C
°C
TJ
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-kΩ resistor in series
with the pins, per application note SLUA626.
(3) The TPA3111D1-Q1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal
protection shutdown. See TI Technical Brief SLMA002 for more information about using the PowerPAD.
6.2 ESD Ratings
VALUE
±4000
±250
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Machine model
V(ESD)
Electrostatic discharge
V
±200
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
VIH
VIL
VOL
IIH
Supply voltage
PVCC, AVCC
8
2
26
V
V
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level input current
Low-level input current
Operating free-air temperature
SD, GAIN0, GAIN1
SD, GAIN0, GAIN1
0.8
0.8
50
V
FAULT, RPULLUP = 100 kΩ, VCC = 26 V
SD, GAIN0, GAIN1, VI = 2, VCC = 18 V
SD, GAIN0, GAIN1, VI = 0.8 V, VCC = 18 V
V
µA
µA
°C
IIL
5
TA
–40
125
4
Copyright © 2012–2015, Texas Instruments Incorporated
TPA3111D1-Q1
www.ti.com.cn
ZHCS790E –MARCH 2012–REVISED DECEMBER 2015
6.4 Thermal Information
TPA3111D1-Q1
(1)
THERMAL METRIC
PWP (HTSSOP)
UNIT
28 PINS
30.3
33.5
17.5
0.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
ψJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.2
RθJC(bot)
0.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 DC Characteristics: VCC = 24 V
TA = –40°C to 125°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = 0 V, Gain = 36 dB
SD = 2 V, no load, PVCC = 21 V
MIN
TYP MAX UNIT
Class-D output offset voltage (measured
differentially)
| VOS
|
1.5
15
mV
ICC
ICC(SD)
Quiescent supply current
40
400
240
240
20
mA
µA
Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 21 V
High side
rDS(on)
Drain-source on-state resistance
Gain
IO = 500 mA, TJ = 25°C
GAIN1 = 0.8 V
mΩ
Low side
GAIN0 = 0.8 V
GAIN0 = 2 V
GAIN0 = 0.8 V
GAIN0 = 2 V
19
25
31
35
21
27
33
37
26
G
dB
32
GAIN1 = 2 V
36
tON
Turnon time
SD = 2 V
10
ms
μs
V
tOFF
Turnoff time
SD = 0.8 V
IGVDD = 2 mA
2
GVDD
Gate drive supply
6.5
6.9
7.3
6.6 DC Characteristics: VCC = 12 V
TA = –40°C to 125°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = 0 V, Gain = 36 dB
SD = 2 V, no load, PVCC = 12 V
MIN
TYP MAX UNIT
Class-D output offset voltage (measured
differentially)
| VOS
|
1.5
15
mV
ICC
ICC(SD)
Quiescent supply current
20
200
240
240
20
mA
µA
Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 12 V
High side
rDS(on)
Drain-source on-state resistance
Gain
IO = 500 mA, TJ = 25°C
GAIN1 = 0.8 V
mΩ
Low side
GAIN0 = 0.8 V
GAIN0 = 2 V
GAIN0 = 0.8 V
GAIN0 = 2 V
19
25
31
35
21
27
33
37
26
G
dB
32
GAIN1 = 2 V
36
tON
Turnon time
SD = 2 V
10
ms
μs
V
tOFF
Turnoff time
SD = 0.8 V
IGVDD = 2 mA
2
GVDD
Gate drive supply
6.5
6.9
7.3
Output voltage maximum under PLIMIT
control
PLIMIT
VPLIMIT = 2 V; VI = 6-V differential
6.75
7.90 8.75
V
Copyright © 2012–2015, Texas Instruments Incorporated
5
TPA3111D1-Q1
ZHCS790E –MARCH 2012–REVISED DECEMBER 2015
www.ti.com.cn
6.7 AC Characteristics: VCC = 24 V
TA = –40°C to 125°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, inputs AC-coupled to AGND
KSVR
PO
Power supply ripple rejection
Continuous output power
–70
dB
W
THD+N ≤ 0.1%, f = 1 kHz, VCC = 24 V
10
< 0.05%
65
THD+N Total harmonic distortion + noise
VCC = 24 V, f = 1 kHz, PO = 5 W (half-power)
µV
dBV
dB
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
VO = 1 VRMS, Gain = 20 dB, f = 1 kHz
–80
Crosstalk
–70
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SNR
fOSC
Signal-to-noise ratio
102
dB
Oscillator frequency
Thermal trip point
Thermal hysteresis
250
310
150
15
350
kHz
°C
°C
6.8 AC Characteristics: VCC = 12 V
TA = –40°C to 125°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, inputs AC-coupled to AGND
KSVR
Supply ripple rejection
–70
dB
PO
PO
Continuous output power
Continuous output power
THD+N ≤ 10%, f = 1 kHz , RL = 8 Ω
THD+N ≤ 0.1%, f = 1 kHz , RL = 4 Ω
10
10
W
W
<
THD+N Total harmonic distortion + noise
RL = 8 Ω, f = 1 kHz, PO = 5 W (half-power)
0.06%
65
–80
–70
µV
dBV
dB
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
Po = 1 W, Gain = 20 dB, f = 1 kHz
Crosstalk
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SNR
fOSC
Signal-to-noise ratio
102
dB
Oscillator frequency
Thermal trip point
Thermal hysteresis
250
310 350
kHz
°C
150
15
°C
6
Copyright © 2012–2015, Texas Instruments Incorporated
TPA3111D1-Q1
www.ti.com.cn
ZHCS790E –MARCH 2012–REVISED DECEMBER 2015
6.9 Typical Characteristics
All measurements taken at 1 kHz, unless otherwise noted, using the TPA3110D2EVM, which is available at ti.com.
10
10
1
1
P
O
= 1 W
0.1
0.1
P
O
= 1 W
0.01
0.001
0.01
0.001
P
= 10 W
O
P
= 5 W
O
P
O
= 5 W
P
O
= 2.5 W
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
G001
G002
Gain = 20 dB
VCC = 12 V
ZL = 8 Ω +66 µH
Gain = 20 dB
VCC = 24 V
ZL = 8 Ω +66 µH
Figure 1. Total Harmonic Distortion vs Frequency
Figure 2. Total Harmonic Distortion vs Frequency
10
10
1
1
P
O
= 5 W
f = 1 kHz
f = 20 Hz
P
O
= 10 W
0.1
0.01
0.1
0.01
P
O
= 1 W
f = 10 kHz
0.001
0.001
20
100
1k
10k 20k
0.01
0.1
1
10 20
f − Frequency − Hz
P
O
− Output Power − W
G003
G004
Gain = 20 dB
VCC = 12 V
ZL = 4 Ω +33 µH
Gain = 20 dB
VCC = 12 V
ZL = 8 Ω +66 µH
Figure 3. Total Harmonic Distortion vs Frequency
Figure 4. Total Harmonic Distortion + Noise vs Output
Power
10
10
1
1
f = 1 kHz
f = 20 Hz
f = 20 Hz
f = 1 kHz
0.1
0.1
0.01
0.01
f = 10 kHz
0.1
f = 10 kHz
0.001
0.001
0.01
0.1
1
10 20
0.01
1
10 20
P
O
− Output Power − W
P
O
− Output Power − W
G005
G006
Gain = 20 dB
VCC = 24 V
ZL = 8 Ω +66 µH
Gain = 20 dB
VCC = 12 V
ZL = 4 Ω +33 µH
Figure 5. Total Harmonic Distortion + Noise vs Output
Power
Figure 6. Total Harmonic Distortion + Noise vs Output
Power
Copyright © 2012–2015, Texas Instruments Incorporated
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TPA3111D1-Q1
ZHCS790E –MARCH 2012–REVISED DECEMBER 2015
www.ti.com.cn
Typical Characteristics (continued)
All measurements taken at 1 kHz, unless otherwise noted, using the TPA3110D2EVM, which is available at ti.com.
25
20
15
10
5
20
15
10
5
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
V
1.0
1.5
2.0
V
− PLIMIT Voltage − V
− PLIMIT Voltage − V
PLIMIT
PLIMIT
G007
G008
Gain = 20 dB
VCC = 24 V
ZL = 8 Ω +66 µH
Gain = 20 dB
VCC = 12 V
ZL = 4 Ω +33 µH
The dashed line represents thermally limited region.
The dashed line represents thermally limited region.
Figure 7. Maximum Output Power vs PLIMIT Voltage
Figure 8. Output Power vs PLIMIT Voltage
100
100
90
80
70
60
50
40
30
20
10
0
40
V
CC
= 12 V
35
30
25
20
15
10
5
50
Phase
Gain
V
CC
= 24 V
0
−50
−100
−150
−200
−250
−300
0
10
100
1k
f − Frequency − Hz
10k
100k
0
1
2
3
4
5
6
7
8
9
10
G009
P
O
− Output Power − W
G012
Gain = 20 dB
CI = 1 µF
VCC = 12 V
ZL = 8 Ω +66 µH
Gain = 20 dB
ZL = 8 Ω +66 µH
VI = 0.1 VRMS
Filter = Audio Precision AUX-0025
Figure 10. Efficiency vs Output Power
Figure 9. Gain/Phase vs Frequency
100
90
80
70
60
50
40
30
20
10
0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
CC
= 12 V
V
CC
= 24 V
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
P
O
− Output Power − W
P
O(Tot)
− Total Output Power − W
G013
G014
Gain = 20 dB
VCC = 12 V
ZL = 4 Ω +33 µH
Gain = 20 dB
ZL = 8 Ω +66 µH
Figure 11. Efficiency vs Output Power
Figure 12. Supply Current vs Total Output Power
8
Copyright © 2012–2015, Texas Instruments Incorporated
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Typical Characteristics (continued)
All measurements taken at 1 kHz, unless otherwise noted, using the TPA3110D2EVM, which is available at ti.com.
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
−20
−40
−60
−80
−100
−120
0
1
2
3
4
5
6
7
8
9
10
20
100
1k
10k 20k
P
O(Tot)
− Total Output Power − W
f − Frequency − Hz
G015
G016
Gain = 20 dB
VCC = 12 V
ZL = 4 Ω +33 µH
Gain = 20 dB
VCC = 12 V
ZL = 8 Ω +66 µH
Figure 13. Supply Current vs Total Output Power
Figure 14. Supply Ripple Rejection Ratio vs Frequency
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7 Detailed Description
7.1 Overview
The TPA3111D1-Q1 device is AEC-Q100 qualified with temperature grade 1 (–40°C to 125°C), HBM ESD
classification level H2, and CDM ESD classification level C2 (see the ESD Ratings table). This automotive audio
amplifier also features several protection mechanisms as follows:
•
•
DC-Current Detection:
–
The TPA3111D1-Q1 device protects speakers from DC current by reporting a fault on the FAULT pin and
turning the amplifier outputs to a Hi-Z state when a DC current is detected. The PVCC supply must be
cycled to clear this fault.
Short-Circuit Protection and Automatic Recovery:
–
The TPA3111D1-Q1 device has short circuit protection from the output pins to VCC, GND, or to each
other. If a short circuit is detected, it is reported on the FAULT pin and the amplifier outputs switch to a Hi-
Z state. The fault can be cleared by cycling the SD pin.
–
To recover automatically from this fault, connect the FAULT pin directly to the SD pin.
•
Thermal Protection:
–
When the die temperature exceeds 150°C (±15°C) the device enters the shutdown state and the amplifier
outputs are disabled. The TPA3111D1-Q1 device recovers automatically when the temperature decreases
by 15°C.
The functional modes of the TPA3111D1-Q1 device are as follows:
•
Gain setting:
–
The gain of the TPA3111D1-Q1 device is set to one of four options by the state of the GAIN0 and GAIN1
pins. Changing the gain setting also changes the input impedance of the TPA3111D1-Q1 device.
–
Refer to Table 2 for a list of the gain settings.
•
•
Shutdown Mode:
–
The SD pin can be used to enter the shutdown mode which mutes the amplifier and causes the
TPA3111D1-Q1 device to enter a low-current state. This mode can also be triggered to improve power-off
pop performance.
PLIMIT:
The PLIMIT pin limits the output peak-to-peak voltage based on the voltage supplied to the PLIMIT pin.
The peak output voltage is limited to four times the voltage at the PLIMIT pin.
The Feature Description and Device Functional Modes sections provide more details about these functions.
–
10
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7.2 Functional Block Diagram
GVDD
PVCC
BSP
OUTP FB
+
PVCC
OUTP FB
œ
œ
œ
INP
INN
+
+
Gain
Control
Gate
Drive
PWM
Logic
PLIMIT
OUTP
PGND
œ
œ
+
+
+
OUTN FB
œ
FAULT
SD
TTL
Buffer
GAIN0
GAIN1
Gain Control
Ramp
Generator
PLIMIT
Reference
PLIMIT
BSN
GVDD
PVCC
AVCC
GVDD
PVCC
LDO
Regulator
AVCC
GVDD
SC Detect
DC Detect
Gate
Drive
Startup
Protection
Logic
OUTN
PGND
Biases and
References
Thermal
Detect
OUTN FB
UVLO and
OVLO
AGND
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7.3 Feature Description
7.3.1 DC Detect
The TPA3111D1-Q1 circuitry protects the speakers from DC current which might occur because of defective
capacitors on the input or shorts on the printed circuit board at the inputs. A DC-detect fault is reported on the
FAULT pin as a low state. The DC-detect fault also causes the amplifier to shut down by changing the state of
the outputs to Hi-Z. To clear the DC detect, cycle the PVCC supply. Cycling SD does NOT clear a DC-detect
fault.
A DC-detect fault is issued when the output differential duty-cycle exceeds 14% (for example, 57%, –43%) for
more than 420 ms at the same polarity. This feature helps protect the speaker from large DC currents or AC
currents less than 2 Hz. To avoid nuisance faults because of the DC detect circuit, hold the SD pin low at power-
up until the signals at the inputs are stable. Also, match the impedance at the positive and negative input to
avoid nuisance DC-detect faults.
Table 1 lists the minimum differential input voltages required to trigger the DC detect. The inputs must remain at
or above the voltage listed in the table for more than 420 ms to trigger the DC detect.
Table 1. DC Detect Threshold
AV (dB)
20
VIN (mV, DIFFERENTIAL)
112
56
26
32
28
36
17
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7.3.2 Short-Circuit Protection and Automatic Recovery Feature
The TPA3110D2-Q1 device has protection from overcurrent conditions caused by a short circuit on the output
stage. The short-circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are
switched to a Hi-Z state when the short circuit-protection latch is engaged. The latch is cleared by cycling the SD
pin through the low state.
If automatic recovery from the short-circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This allows the FAULT pin function to automatically drive the SD pin low, which clears the short-circuit
protection latch.
7.3.3 Thermal Protection
Thermal protection on the TPA3111D1-Q1 device prevents damage to the device when the internal die
temperature exceeds 150°C. This trip point has a ±15°C tolerance from device to device. When the die
temperature exceeds the thermal set point, the device enters the shutdown state and the outputs are disabled.
This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The
device begins normal operation at this point with no external system interaction.
Thermal protection faults are NOT reported on the FAULT pin.
7.3.4 GVDD Supply
The GVDD supply powers the gates of the output full bridge transistors. The GVDD supply can also supply the
PLIMIT voltage divider circuit. Add a 1-μF capacitor to ground at this pin.
7.4 Device Functional Modes
7.4.1 Gain Setting Through Gain0 and Gain1 Inputs
The gain of the TPA3111D1-Q1 device is set by two input pins, GAIN0 and GAIN1. The voltage slew rate of
these gain pins, along with pins 1 and 14, must be restricted to no more than 10 V/ms. For higher slew rates, use
a 100-kΩ resistor in series with the pins.
The gains listed in Table 2 are realized by changing the taps on the input resistors inside the amplifier which
causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by
ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part
at the same gain may shift by ±20% because of shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the Input Resistance section) should be designed
assuming an input impedance of 7.2 kΩ, which is the absolute minimum input impedance of the TPA3111D1-Q1
device. At the lower gain settings, the input impedance could increase as high as 72 kΩ.
Table 2. Gain Setting
AMPLIFIER GAIN (dB)
INPUT IMPEDANCE (kΩ)
GAIN1
GAIN0
TYPICAL
TYPICAL
0
0
1
1
0
1
0
1
20
26
32
36
60
30
15
9
12
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7.4.2 SD Operation
The TPA3111D1-Q1 device employs a shutdown mode of operation designed to reduce supply current (ICC) to
the absolute minimum level during periods of non-use for power conservation. The SD input pin should be held
high (see the AC Characteristics: VCC = 24 V and AC Characteristics: VCC = 12 V tables for the trip point values)
during normal operation when the amplifier is in use. Pulling the SD pin low causes the outputs to mute and the
amplifier to enter a low-current state. Never leave the SD pin unconnected. Amplifier operation is unpredictable if
the SD pin is not connected.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply voltage.
7.4.3 PLIMIT
The voltage at the PLIMIT pin (pin 10) can limit the power to levels below that which is possible based on the
supply rail. Add a resistor divider from the GVDD pin to ground to set the voltage at the PLIMIT pin. An external
reference can also be used if tighter tolerance is required. Also add a 1-μF capacitor from the PLIMIT pin to
ground.
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. This limit can be thought of as a virtual
voltage rail, which is lower than the supply connected to PVCC. This virtual rail is four times the voltage at the
PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input
voltage and speaker impedance.
TPA3111D1-Q1 PLIMIT Operation
PVCC = 12 V, RL = 4 Ω, VIN = 0.67 VRMS
PLIMIT = 6.95 V (GVDD), PO = 10 W
PLIMIT = 1.87 V P = 8 W
PLIMIT = 1.5 V POO = 6 W
PLIMIT = 1.16 V P = 4 W
PLIMIT = 0.77 V OPO = 2 W
Figure 15. PLIMIT Circuit Operation
The PLIMIT circuits sets a limit on the output peak-to-peak voltage. The limiting occurs by limiting the duty cycle
to the fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply
connected to PVCC. This virtual rail is four times the voltage at the PLIMIT pin. This output voltage can be used
to calculate the maximum output power for a given maximum input voltage and speaker impedance. Use
Equation 1 to calculate the maximum power output (POUT).
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æ
ö2
æ
ç
è
ö
÷
ø
RL
´ V
ç
÷
P
ç
÷
RL + 2´RS
è
ø
POUT
=
for unclipped power
2´RL
where
•
•
•
•
•
RS is the total series resistance including RDS(on), and any resistance in the output filter.
RL is the load resistance.
VP is the peak amplitude of the output possible within the supply rail.
VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP
POUT(10%THD) = 1.25 × POUT(unclipped)
(1)
Table 3. PLIMIT Typical Operation
OUTPUT VOLTAGE
TEST CONDITIONS
PLIMIT VOLTAGE
OUTPUT POWER (W)
AMPLITUDE (VP-P
)
PVCC = 24 V, VIN = 1 VRMS
RL = 4 Ω, Gain = 20 dB
,
,
,
,
1.92
1.24
1.75
1.20
10
5
15
PVCC = 24 V, VIN = 1 VRMS
RL = 4 Ω, Gain = 20 dB
10
PVCC = 12 V, VIN = 1 VRMS
RL = 4 Ω, Gain = 20 dB
10
5
15.3
10.3
PVCC = 12 V, VIN = 1 VRMS
RL = 4 Ω, Gain = 20 dB
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPA3111D1-Q1 device is an automotive class-D audio amplifier. The device accepts either a single ended
or differential analog input, amplifies the signal, and drives up to 10 W across a bridge tied load, usually a
speaker. Because an analog input is required, this device is often paired with a codec or audio DAC if the audio
source is digital.
The four digital I/O pins, GAIN0, GAIN1, SD, and FAULT, can be pulled up to the PVCC supply. When
connecting these pins to the PVCC supply, a 100-kΩ resistor must be put in series to limit the slew rate. For
more information, see Maximum Slew Rate on High-Voltage Pins for TPA3111D1 (SLUA626). One of four gain
settings is used depending on the configuration of GAIN0 and GAIN1. The SD pin is used to put the device in
shutdown or normal mode. The FAULT pin is used to indicate if a DC detect or short circuit fault was detected.
See the Typical Application section for design considerations and how to select external components.
8.2 Typical Application
PVCC
0.1 μF
1000 pF
100 μF
100 kΩ
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
Control
System
SD
PVCC
PVCC
BSN
1 kΩ
FAULT
GND
3
0.47 μF
4
GND
OUTN
PGND
OUTN
BSN
5
GAIN0
GAIN1
AVCC
FB
6
AVCC
1000 pF
1000 pF
7
PVCC
10 Ω
TPA3111D1-Q1
1 µF
8
AGND
GVDD
PLIMIT
INN
BSP
1 µF
9
OUTP
PGND
OUTP
BSP
FB
10
11
12
13
0.47 μF
1 µF
Audio
Source
INP
1 µF
100 kΩ
NC
PVCC
0.1 μF
14
15
AVCC
PVCC
AVCC
1000 pF
GND
29
100 μF
PowerPAD
PVCC
Figure 16. Mono Class-D Amplifier With BTL Output
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Typical Application (continued)
8.2.1 Design Requirements
The typical requirements for designing the external components around the TPA3111D1-Q1 device include
efficiency, EMI performance, and EMC performance. For most applications, only a ferrite bead is required to filter
unwanted emissions. The ripple current is low enough that an LC filter is typically not needed. As the output
power is increased, causing the ripple current to increase, an LC filter can be added to improve efficiency. An LC
filter can also be added in cases where additional EMI suppression is needed.
In addition to discussing how to select a ferrite bead and when to use an LC filter, the Detailed Design Procedure
section also discusses the input filter and power supply decoupling. The input filter must be selected with the
input impedance of the amplifier in mind. The cut-off frequency should be selected so that bass performance is
not impacted. Power supply decoupling is important to ensure that noise from the power line does not impact the
audio quality of the amplifier output.
8.2.2 Detailed Design Procedure
8.2.2.1 Class-D Operation
This section focuses on the Class-D operation of the TPA3111D1-Q1 device.
8.2.2.2 TPA3111D1-Q1 Modulation Scheme
The TPA3111D1-Q1 device uses a modulation scheme that allows operation without the classic LC
reconstruction filter when the amplifier is driving an inductive load. Each output is switching from 0 V to the
supply voltage. The OUTP and OUTN pins are in phase with each other with no input so that there is little or no
current in the speaker. The duty cycle of the OUTP pin is greater than 50% and the duty cycle of the OUTN pin
is less than 50% for positive output voltages. The duty cycle of the OUTP pin is less than 50% and the duty cycle
of the OUTN pin is greater than 50% for negative output voltages. The voltage across the load sits at 0 V
throughout most of the switching period, greatly reducing the switching current, which reduces any I2R losses in
the load. See Figure 20 for a plot of the output waveforms.
8.2.2.3 Ferrite Bead Filter Considerations
Using the advanced emissions suppression technology in the TPA3111D1-Q1 amplifier, designing a high
efficiency Class-D audio amplifier is possible while minimizing interference to surrounding circuits. This design
can also be accomplished with only a low-cost ferrite bead filter. In this case, the ferrite bead used in the filter
must be carefully selected.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, therefore select a material that is effective in the 10-MHz to 100-MHz range which is key to the
operation of the Class-D amplifier. Many of the specifications regulating consumer electronics have emissions
limits as low as 30 MHz. Use the ferrite bead filter to block radiation in the 30-MHz and above range from
appearing on the speaker wires and the power supply lines which are good antennas for these signals. The
impedance of the ferrite bead can be used along with a small capacitor with a value in the range of 1000 pF to
reduce the frequency spectrum of the signal to an acceptable level. For best performance, the resonant
frequency of the ferrite bead and capacitor filter should be less than 10 MHz.
Also, ensure that the ferrite bead is large enough to maintain the impedance at the peak currents expected for
the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this
case, ensure that the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier
sees. If these specifications are not available, estimate the bead current handling capability by measuring the
resonant frequency of the filter output at very low power and at maximum power. A change of resonant
frequency of less than 50% under this condition is desirable. Examples of tested ferrite beads that work well with
the TPA3110D2-Q1 device include 28L0138-80R-10 and HI1812V101R-10 from Steward and the 742792510
from Wurth Electronics.
A high-quality ceramic capacitor is also required for the ferrite bead filter. A low-ESR capacitor with good
temperature and voltage characteristics works best.
16
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Typical Application (continued)
Additional EMC improvements can be obtained by adding snubber networks from each of the Class-D outputs to
ground. The suggested values for a simple RC series snubber network is a 10-Ω resistor in series with a 330-pF
capacitor, although the design of the snubber network is specific to every application and must consider the
parasitic reactance of the printed circuit board as well as the audio amplifier. Take care to evaluate the stress on
the component in the snubber network especially if the amplifier is running at a high PVCC supply. Also, ensure
the layout of the snubber network is tight and returns directly to the PGND pin or the PowerPAD beneath the
chip.
8.2.2.4 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional Class-D amplifier needs an output filter is because the switching waveform
results in maximum current flow, which causes more loss in the load resulting in lower efficiency. The ripple
current is large for the traditional modulation scheme, because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is
half the period for the traditional modulation scheme. An ideal LC filter is required to store the ripple current from
each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA3111D1-Q1 modulation scheme has little loss in the load without a filter because the pulses are short
and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making
the ripple current larger. Ripple current can be filtered with an LC filter for increased efficiency, but for most
applications the filter is not required.
An LC filter with a cutoff frequency less than the Class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
8.2.2.5 When to Use an Output Filter for EMI Suppression
The TPA3111D1-Q1 device has been tested with a simple ferrite bead filter for a variety of applications including
long speaker wires up to 125 cm and high power. The TPA3111D1EVM passes FCC Class-B specifications
under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
A few circuit instances may require the addition of a complete LC reconstruction filter. These circumstances
might occur if nearby circuits are very sensitive to noise. In these cases a classic second order Butterworth filter
similar to those shown in the following figures can be used.
33 mH
OUTP
C2
L1
1 mF
33 mH
OUTN
C3
L2
1 mF
Figure 17. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
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Typical Application (continued)
15 mH
OUTP
C2
L1
2.2 mF
15 mH
OUTN
C3
2.2 mF
L2
Figure 18. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 19. Typical Ferrite Chip Bead Filter (Chip Bead Example: Steward HI0805R800R-10)
8.2.2.6 Input Resistance
Changing the gain setting can vary the input resistance of the amplifier from the smallest value, 9 kΩ ±20%, to
the largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the –3 dB or
cutoff frequency may change when changing gain steps.
Z
f
C
i
Z
i
IN
Input
Signal
Use Equation 2 to calculate the –3-dB frequency . Use the values listed in Table 2 for ZI.
1
f =
2p Zi Ci
(2)
18
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Typical Application (continued)
8.2.2.7 Input Capacitor, CI
In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper DC level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a high-
pass filter with the corner frequency determined in Equation 3.
-3 dB
1
fc
=
2p Zi Ci
f
c
(3)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 3 is
reconfigured as Equation 4.
1
Ci =
2p Zi fc
(4)
In this example, CI is 0.13 µF; so, one would likely choose a value of 0.15 μF as this value is commonly used. If
the gain is known and is constant, use ZI from Table 2 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network (CI) and the feedback network to the load. This
leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best selection. If a
ceramic capacitor is used, use a high quality capacitor with good temperature and voltage coefficient. An X7R-
type capacitor works well and, if possible, use a higher voltage rating than required which provides a better C-
versus-voltage characteristic. When polarized capacitors are used, the positive side of the capacitor should face
the amplifier input in most applications as the DC level there is held at 3 V, which is likely higher than the source
DC level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder
can create DC offset voltages. Ensure that boards are cleaned properly.
8.2.2.8 BSN and BSP Capacitors
The full H-bridge output stage uses only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 470-nF ceramic capacitor, rated for at least 16 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 470-nF capacitor must be
connected from OUTP to BSP, and one 470-nF capacitor must be connected from OUTN to BSN. See the
simplified application circuit diagram in the 说明 section.
The bootstrap capacitors connected between the BSx pins and corresponding output function as a floating power
supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle,
the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.
8.2.2.9 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3111D1-Q1 device with a differential source, connect the positive lead of the audio source to the INP
input and the negative lead from the audio source to the INN input. To use the TPA3111D1-Q1 device with a
single-ended source, AC-ground the INP or INN input through a capacitor equal in value to the input capacitor on
INN or INP and apply the audio source to either input. In a single-ended input application, the unused input
should be AC-grounded at the audio source instead of at the device input for best noise performance. For good
transient performance, the impedance seen at each of the two differential inputs should be the same.
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Typical Application (continued)
The impedance at the inputs should be limited to an RC time constant of 1 ms or less if possible. Limiting the
impedance allows the input DC blocking capacitors to become completely charged during the 14-ms power-up
time. If the input capacitors are not allowed to completely charge, some additional sensitivity to component
matching can occur which can result in a pop if the input components are not well matched.
8.2.2.10 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this application. A real (as opposed to ideal) capacitor can be
modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the
beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the
real capacitor behaves like an ideal capacitor.
8.2.3 Application Curve
OUTP
OUTN
Output = 0 V
Differential
+12 V
Voltage
0 V
Across
-12 V
Load
Current
OUTP
OUTN
Output > 0 V
Differential
Voltage
Across
Load
+12 V
0 V
-12 V
Current
Figure 20. The TPA3111D1-Q1 Output Voltage and Current Waveforms into an Inductive Load
20
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9 Power Supply Recommendations
The TPA3111D1-Q1 device is a high-performance CMOS audio amplifier that requires adequate power supply
decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply
decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker.
Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of
noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond
wire and copper trace inductances as well as lead frame capacitance, a good quality low equivalent-series-
resistance (ESR) ceramic capacitor with a value between 220 pF and 1000 pF works well. This capacitor should
be placed as close to the device PVCC pins and system ground (either PGND pins or PowerPAD) as possible.
For mid-frequency noise because of filter resonances or PWM switching transients as well as digital hash on the
line, place another good quality capacitor, with a typical value of 0.1 µF to 1 μF, as close as possible to the
PVCC pins which works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor
with a value of 220 µF or greater placed near the audio power amplifier is recommended. The 220-µF capacitor
also serves as a local storage capacitor for supplying current during large signal transients on the amplifier
outputs. The PVCC pins provide the power to the output transistors, so a 220-μF or larger capacitor should be
placed on each PVCC pin. A 10-μF capacitor on the AVCC pin is adequate. Also, a small decoupling resistor
between the AVCC and PVCC pins can be used to keep high frequency Class-D noise from entering the linear
input amplifiers.
10 Layout
10.1 Layout Guidelines
The TPA3111D1-Q1 device can be used with a small, inexpensive ferrite bead output filter for most applications.
However, because the Class-D switching edges are very fast, carefully planning the layout of the printed circuit
board is important. Use the guidelines that follow to help meet the EMC requirements:
•
The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC pins as
possible. Large (220 μF or greater) bulk power-supply decoupling capacitors should be placed near the
TPA3111D1-Q1 device on the PVCC supplies. Local, high-frequency bypass capacitors should be placed as
close to the PVCC pins as possible. These capacitors can be connected to the thermal pad directly for an
excellent ground connection. Consider adding a small, good-quality low-ESR ceramic capacitor with a value
between 220 pF and 1000 pF and a larger good-quality mid-freqency capacitor with a value between 0.1 µF
and 1 µF to the PVCC connections at each end of the chip.
•
•
•
Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
PGND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
The ferrite EMI filter (Figure 19) should be placed as close to the output pins as possible for the best EMI
performance. The LC filter (Figure 17 and Figure 18) should be placed close to the outputs. The capacitors
used in both the ferrite and LC filters should be grounded to power ground.
The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The
dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35 mm. Seven rows of solid vias
(three vias per row, 0.33 mm or 13 mils diameter) should be equally spaced underneath the thermal land. The
vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The
vias must be solid vias, not thermal relief or webbed vias. See PowerPAD™ Thermally Enhanced Package
(SLMA002) for more information on using the thermal pad of the package. For recommended PCB footprints,
see the mechanical pages in the 机械、封装和可订购信息 section.
Copyright © 2012–2015, Texas Instruments Incorporated
21
TPA3111D1-Q1
ZHCS790E –MARCH 2012–REVISED DECEMBER 2015
www.ti.com.cn
10.2 Layout Example
Smaller high
Large bulk
decoupling
capacitor
frequency
decoupling
capacitors
To the PVCC
supply
PVCC
PVCC
BSN
SD
FAULT
GND
GND
OUTN
PGND
OUTN
BSN
Thermal Pad
Speaker
Ferrite Bead
GAIN0
GAIN1
AVCC
AGND
GVDD
PLIMIT
INN
Vias to the
ground plane
BSP
OUTP
PGND
OUTP
BSP
Connect together
and connect to
the AVCC supply
Ferrite Bead
INP
NC
PVCC
PVCC
Via
AVCC
Copper trace (pour)
Thermal pad
Connect to ground
plane layer
To the PVCC
supply
Large bulk
decoupling
capacitor
Smaller high
frequency
decoupling
capacitors
Figure 21. Recommended Layout
22
版权 © 2012–2015, Texas Instruments Incorporated
TPA3111D1-Q1
www.ti.com.cn
ZHCS790E –MARCH 2012–REVISED DECEMBER 2015
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
相关文档请参阅以下部分：
•
•
•
•
•
•
•
•
《AN-1737 管理 D 类音频 应用中的 EMI》，SNAA050
《AN-1849 音频放大器电源设计》，
《音频功率放大器性能测量指南》，SLOA068
《TPA3111D1 的高电压引脚上的最大转换率》，SLUA626
《PowerPAD™ 耐热增强型封装》(，SLMA002
《TPA3111D1EVM 音频放大器评估板》，SLOU270
《TPA3110D2EVM 音频放大器评估板》，SLOU263
《对模拟组件使用热计算工具》，SLUA566
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
SpeakerGuard, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2012–2015, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPA3111D1QPWPRQ1
ACTIVE
HTSSOP
PWP
28
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPA3111Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3111D1QPWPRQ1 HTSSOP PWP
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 28
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TPA3111D1QPWPRQ1
2000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 28
4.4 x 9.7, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/B
www.ti.com
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相关型号：
TPA3111D1PWP
10-W mono, 8- to 26-V supply, analog input Class-D audio amplifier w/ filter free & SpeakerGu 28-HTSSOP -40 to 85
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