TPA3126D2DAD [TI]
50W 立体声、100W 单声道、4.5V 至 26V、模拟输入 D 类音频放大器，低空闲电流 | DAD | 32 | -40 to 85;
| 型号： | TPA3126D2DAD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 50W 立体声、100W 单声道、4.5V 至 26V、模拟输入 D 类音频放大器，低空闲电流 | DAD | 32 | -40 to 85 放大器 光电二极管 商用集成电路 音频放大器 |
| 文件： | 总41页 (文件大小：3455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TPA3126D2
ZHCSHZ1 –APRIL 2018
具有 15mA 低空闲电流和 AM 抑制功能的 TPA3126D2 50W 立体声、模拟
输入 D 类音频放大器
1 特性
2 应用
1
•
电池使用时间更长：
超低空闲电流：12V 时为 15mA
•
•
•
•
•
扬声器底座
Bluetooth®和 Wi-Fi 扬声器
声控扬声器或智能扬声器
条形音箱
–
•
21V 电压、10% THD+N、4Ω 负载条件下的功率为
2 × 50W
•
•
宽电压范围：4.5V 至 26V
高效 D 类运行模式
书架立体声系统
3 说明
–
–
混合调制方案可动态降低功率损耗
TPA3126D2 是一款采用热增强型封装的 50W 立体声
低空闲电流 D 类放大器。TPA3126D2 采用了 TI 专有
的混合调制方案，可在低功率水平下动态降低空闲电
流，从而延长便携式音频系统（如蓝牙扬声器）的电池
寿命。
低至 90mΩ 的 Rds(on) 可确保效率 > 90%
•
•
•
噗声和嘀哒声噪声抑制
支持立体声、单声道 BTL 和单声道 PBTL
多种开关频率：
–
–
–
AM 抑制
主从同步
为了进一步简化设计，该 D 类放大器集成了全面的保
护 特性 ，包括短路、热关断、过压、欠压和直流扬声
器保护。在过载情况下，器件会将故障情况报告给处理
器，从而避免自身遭到损坏。
300kHz 至 1.2MHz 开关频率
•
•
•
•
可选增益：20dB、26dB、32dB、36dB
可编程功率限制
支持单电源和双电源
器件信息(1)
带错误报告的综合保护功能：
器件型号
TPA3126D2
封装
封装尺寸（标称值）
–
过压、欠压、过热、直流检测和短路
HTSSOP (32)
11.00mm x 6.20mm
•
•
热增强型封装
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
–
DAD（32 引脚 HTSSOP PowerPAD™封装，
焊盘朝上）
性能在 TPA3116D2 基础上升级
–
空闲电流降低 70%；引脚对引脚兼容
TPA3126 和 TPA3116 空闲电流
空白
简化应用电路
80
70
60
50
40
30
20
10
0
TPA3116 (BD Mode)
TPA3126 (Hybrid Mode)
TPA3126D2
LC
Filter
MONO
DETECT
RIGHT
Audio
Source
And Control
PBTL
DETECT
LEFT
LC
Filter
SDZ
MUTE
FAULTZ
Power Supply
4.5V t 26V
PVCC
AVCC
AM2,1,0
AM Avoidance Control
Mode Select
MODSEL
GAIN/SLV
PLIMIT
GAIN control and Master/Slave setting
Power Limit
Separate Power
Supply (Optional)
4.5V-26V
Gain = 26dB, TA = 25èC, RL = 8W
Capable of synchronizaing to other devices
SYNC
5
10
15
20
25
Supply Voltage (V)
D002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS942
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 22
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
1
2
3
4
5
6
7
特性.......................................................................... 1
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings ............................................................ 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 DC Electrical Characteristics .................................... 7
7.6 AC Electrical Characteristics..................................... 8
7.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
10 Power Supply Recommendations ..................... 26
10.1 Power Supply Mode.............................................. 26
11 Layout................................................................... 27
11.1 Layout Guidelines ................................................. 27
11.2 Layout Example .................................................... 28
11.3 Heat Sink Used on the EVM................................. 30
12 器件和文档支持 ..................................................... 31
12.1 器件支持 ............................................................... 31
12.2 接收文档更新通知 ................................................. 31
12.3 相关文档................................................................ 31
12.4 社区资源................................................................ 31
12.5 商标....................................................................... 31
12.6 静电放电警告......................................................... 31
12.7 Glossary................................................................ 31
13 机械、封装和可订购信息....................................... 31
8
4 修订历史记录
日期
修订版本
说明
2018 年 4 月
*
最初发布版本。
2
Copyright © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
5 Device Comparison Table
THERMAL
PAD
LOCATION
MODULATION
SCHEME
TPA3126 PIN-
COMPATIBLE
PRODUCT
DESCRIPTION
TPA3116D2
TPA3118D2
50-W Stereo, Analog-Input Class D Amplifier
30-W Stereo, Analog-Input Class D Amplifier
BD, 1SPW
BD, 1SPW
Top
Y
Y
Bottom
30-W Stereo, Analog-Input Class D Amplifier with Low Idle Power
Dissipation
TPA3128D2
TPA3156D2
BD, 1SPW, Hybrid
BD, 1SPW, Hybrid
Bottom
Top
Y
Y
70-W Stereo, Analog-Input Class D Amplifier with Low Idle Power
Dissipation
Copyright © 2018, Texas Instruments Incorporated
3
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
6 Pin Configuration and Functions
DAD Package
32-Pin HTSSOP With PowerPAD™ Up
Top View
MODSEL
SDZ
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVCC
PVCC
BSPR
OUTPR
GND
2
FAULTZ
RINP
3
4
RINN
5
PLIMIT
GVDD
GAIN/SLV
GND
6
OUTNR
BSNR
GND
7
8
Thermal
Pad
9
BSPL
LINP
10
11
12
13
14
15
16
OUTPL
GND
LINN
MUTE
AM2
OUTNL
BSNL
PVCC
PVCC
AVCC
AM1
AM0
SYNC
Not to scale
Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
Mode selection logic input (LOW = Hybrid Mode, HIGH = BD Mode). TTL logic levels with compliance to
AVCC. Refer to: Device Modulation Scheme
1
MODSEL
SDZ
I
I
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with
compliance to AVCC. Refer to: Startup and Shutdown Operation
2
3
General fault reporting including Over-temp, DC Detect. Open drain. Refer to: Device Protection System
FAULTZ = High, normal operation
FAULTZ
DO
FAULTZ = Low (an external 100 kΩ pull-up resistor required), fault condition
4
5
RINP
RINN
I
I
Positive audio input for right channel. Connect to GND for MONO mode.
Negative audio input for right channel. Connect to GND for MONO mode.
Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly
to GVDD for no power limit. Refer to: PLIMIT Operation
6
PLIMIT
I
Internally generated gate voltage supply. Not to be used as a supply or connected to any component other
than a 1 µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers. Refer to:
GVDD Supply
7
GVDD
PO
Selects Gain and selects between Master and Slave mode depending on pin voltage divider. Refer to:
Gain Setting and Master and Slave
8
9
GAIN/SLV
GND
I
G
Ground
(1) DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap.
4
Copyright © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
PIN
ZHCSHZ1 –APRIL 2018
Pin Functions (continued)
TYPE(1)
DESCRIPTION
NO.
10
NAME
LINP
LINN
I
I
Positive audio input for left channel. Connect to GND for PBTL mode.
Negative audio input for left channel. Connect to GND for PBTL mode.
11
Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic
levels with compliance to AVCC.
12
MUTE
I
13
14
15
AM2
AM1
AM0
I
I
I
AM Avoidance Frequency Selection
AM Avoidance Frequency Selection
AM Avoidance Frequency Selection
Clock input/output for synchronizing multiple Class-D devices. Direction determined by GAIN/SLV terminal.
Refer to: Gain Setting and Master and Slave
16
SYNC
DIO
17
18
19
20
21
22
23
AVCC
PVCC
PVCC
BSNL
P
P
Analog Supply
Power supply
P
Power supply
BST
PO
G
Boot strap for negative left channel output, connect to 220 nF X5R, or better ceramic cap to OUTPL
OUTNL
GND
Negative left channel output
Ground
OUTPL
PO
Positive left channel output
Boot strap for positive left channel output, connect to 220 nF X5R, or better ceramic cap to OUTNL Refer
to: BSPx and BSNx Capacitors
24
25
26
BSPL
GND
BST
G
Ground
Boot strap for negative right channel output, connect to 220 nF X5R, or better ceramic cap to OUTNR.
Refer to: BSPx and BSNx Capacitors
BSNR
BST
27
28
29
OUTNR
GND
PO
G
Negative right channel output
Ground
OUTPR
PO
Positive right channel output
Boot strap for positive right channel output, connect to 220 nF X5R or better ceramic cap to OUTPR. Refer
to: BSPx and BSNx Capacitors
30
BSPR
BST
31
32
PVCC
PVCC
P
P
G
Power supply
Power supply
PowerPAD™
Connect to GND for best system performance. If not connected to GND, leave floating.
Copyright © 2018, Texas Instruments Incorporated
5
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
30
UNIT
V
Supply voltage, VCC
Input voltage, VI
PVCC, AVCC
INPL, INNL, INPR, INNR
6.3
V
PLIMIT, GAIN/SLV, SYNC
AM0, AM1, AM2, MUTE, SDZ, MODSEL
AM0, AM1, AM2, MUTE, SDZ, MODSEL
GVDD+0.3
PVCC+0.3
10
V
V
Slew rate, maximum(2)
V/ms
°C
Operating free-air temperature, TA
Operating junction temperature , TJ
Storage temperature, Tstg
–40
–40
–40
85
150
°C
125
°C
(1) Stresses beyond those listed under absolute maximum ratings can cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
(2) 100-kΩ series resistor is required if maximum slew rate is exceeded.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
2
NOM
MAX
UNIT
VCC
VIH
VIL
Supply voltage
PVCC, AVCC
26
V
V
V
V
High-level input voltage
Low-level input voltage
Low-level output voltage
AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL
AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL
FAULTZ, RPULL-UP = 100 kΩ, PVCC = 26 V
0.8
0.8
VOL
AM0, AM1, AM2, MUTE, SDZ, MODSEL
(VI = 2 V, VCC = 18 V)
IIH
High-level input current
Minimum load Impedance
Output-filter Inductance
50
µA
Ω
RL(BTL)
Output filter: L = 10 µH, C = 680 nF
Output filter: L = 10 µH, C = 1 µF
3.2
1.6
4
2
RL(PBTL)
Minimum output filter inductance under short-
circuit condition
Lo
1
µH
6
Copyright © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
7.4 Thermal Information
TPA3126D2
DAD(2)
32 PINS
N/A
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
°C/W
°C/W
°C/W
°C/W
1.2
1.2
ψJB
21
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) For the PCB layout, see the TPA3126D2EVM user guide.
7.5 DC Electrical Characteristics
TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω, fs = 400 kHz, hybrid mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Class-D output offset voltage
(measured differentially)
| VOS
ICC
|
VI = 0 V
1.5
5
mV
mA
SDZ = 2 V, With load and filter, PVCC = 12 V
SDZ = 2 V, With load and filter, PVCC = 24 V
SDZ = 0.8 V, With load and filter, PVCC = 12 V
SDZ = 0.8 V, With load and filter, PVCC = 24 V
15
23
20
30
Quiescent supply current
Quiescent supply current in
shutdown mode
ICC(SD)
rDS(on)
µA
mΩ
dB
Drain-source on-state resistance,
measured pin to pin
PVCC = 21 V, Iout = 500 mA, TJ = 25°C
90
R1 = 5.6 kΩ, R2 = Open
R1 = 20 kΩ, R2 = 100 kΩ
R1 = 39 kΩ, R2 = 100 kΩ
R1 = 47 kΩ, R2 = 75 kΩ
R1 = 51 kΩ, R2 = 51 kΩ
R1 = 75 kΩ, R2 = 47 kΩ
R1 = 100 kΩ, R2 = 39 kΩ
R1 = 100 kΩ, R2 = 16 kΩ
SDZ = 2 V
19
25
31
35
19
25
31
35
20
26
32
36
20
26
32
36
40
2
21
27
33
37
21
27
33
37
G
G
Gain (BTL)
Gain (SLV)
dB
dB
dB
ton
Turn-on time
ms
µs
V
tOFF
GVDD
Turn-off time
SDZ = 0.8 V
Gate drive supply
IGVDD < 200 µA
5.1
5.6
6.3
Output voltage maximum under
PLIMIT control
VO
V(PLIMIT) = 2 V; VI = 1 Vrms
6.75
8.2
8.75
V
Copyright © 2018, Texas Instruments Incorporated
7
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
7.6 AC Electrical Characteristics
TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200 mVPP ripple at 1 kHz, Gain = 26 dB,
Inputs
KSVR
Power supply ripple rejection
–70
dB
AC-coupled to GND
THD+N = 10%, f = 1 kHz, PVCC = 14.4 V
THD+N = 10%, f = 1 kHz, PVCC = 21 V
25
50
PO
Continuous output power
Total harmonic distortion + noise
Output integrated noise
W
VCC = 21 V, f = 1 kHz, PO = 15 W (half-
power)
THD+N
Vn
0.1%
65
–80
µV
dBV
dB
20 Hz to 22 kHz, A-weighted filter, Gain = 20
dB
Crosstalk
VO = 1 Vrms, Gain = 20 dB, f = 1 kHz
–100
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SNR
Signal-to-noise ratio
102
dB
AM2=0, AM1=0, AM0=0
AM2=0, AM1=0, AM0=1
AM2=0, AM1=1, AM0=0
AM2=0, AM1=1, AM0=1
AM2=1, AM1=0, AM0=0
AM2=1, AM1=0, AM0=1
376
470
400
500
424
530
564
600
636
940
1000
1200
300
1060
1278
318
fOSC
Oscillator frequency
kHz
1128
282
AM2=1, AM1=1, AM0=0
Modulation scheme Fixed in 1SPW Mode
282
300
318
AM2=1, AM1=1, AM0=1, Reserved
Thermal trip point
≥150
15
°C
°C
A
Thermal hysteresis
Over current trip point
7.5
8
版权 © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
7.7 Typical Characteristics
fs = 400 kHz, Hybrid Mode, TPA3126D2EVM Tested With AP2722. (unless otherwise noted)
30
20
10
0
10
Gain=26dB
TA=25èC
RL=4W
Gain=26dB
PVcc=12V
TA=25èC
RL=8W
P O=1W
PO =2.5W
PO=5W
1
0.1
0.01
FPWM = 400 kHz
20 25
0.001
5
10
15
20
100
1k
10k 20k
Supply Voltage (V)
Frequency (Hz)
D0021
D005
图 1. Idle Current vs PVCC
图 2. Total Harmonic Distortion + Noise (BTL) vs Frequency
10
1
10
Gain=26dB
PVcc=24V
TA=25èC
RL=8W
P O=1W
PO =5W
PO=10W
Gain=26dB
PVCC=6V
TA=25èC
RL=4W
1
0.1
0.1
0.01
0.01
f= 20Hz
f= 1kHz
f= 6KHz
0.001
0.001
20
100
1k
10k 20k
0.01
0.1
Output Power (W)
1
10
Frequency (Hz)
D006
D007
图 3. Total Harmonic Distortion + Noise (BTL) vs Frequency
图 4. Total Harmonic Distortion + Noise (BTL) vs Output
Power
10
10
Gain=26dB
PVCC=12V
TA=25èC
Gain=26dB
PVCC=24V
TA=25èC
RL=4W
RL=4W
1
0.1
1
0.1
0.01
0.01
f= 20Hz
f= 20Hz
f= 1kHz
f= 6KHz
f= 1kHz
f= 6KHz
0.001
0.001
0.01
0.1
1
10
40
0.01
0.1
1
10
100
Output Power (W)
Output Power (W)
D008
D009
图 5. Total Harmonic Distortion + Noise (BTL) vs Output
图 6. Total Harmonic Distortion + Noise (BTL) vs Output
Power
Power
版权 © 2018, Texas Instruments Incorporated
9
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
Typical Characteristics (接下页)
fs = 400 kHz, Hybrid Mode, TPA3126D2EVM Tested With AP2722. (unless otherwise noted)
10
10
Gain=26dB
PVCC=24V
TA=25èC
RL=8W
Gain=26dB
PVCC=12V
TA=25èC
RL=8W
1
1
0.1
0.1
0.01
0.01
f= 20Hz
f= 20Hz
f= 1kHz
f= 6KHz
f= 1kHz
f= 6KHz
0.001
0.001
0.01
0.1
1
10
50
0.01
0.1
1
10
50
Output Power (W)
Output Power (W)
D010
D011
图 7. Total Harmonic Distortion + Noise (BTL) vs Output
图 8. Total Harmonic Distortion + Noise (BTL) vs Output
Power
Power
50
30
20
300
200
100
0
Gain=26dB
TA=25èC
PVCC=24V
RL=4W
40
30
20
10
0
10
0
-10
-20
-30
-40
-50
-100
-200
-300
-400
-500
Gain=26dB
PVCC=12V
TA=25èC
RL=4W
Gain
Phase
1
2
3
4
5
20
100
1k
10k 20k
100k
PLIMIT Voltage(V)
Frequency (Hz)
D0012
D0225
图 9. Output Power (BTL) vs PLIMIT Voltage
图 10. Gain/Phase (BTL) vs Frequency
100
90
80
70
60
50
40
30
20
10
0
50
45
40
35
30
25
20
15
10
5
Gain=26dB
TA=25èC
RL=4W
Gain=26dB
TA=25èC
RL=8W
THD+N=1%
THD+N=10%
THD+N=1%
THD+N=10%
0
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
D014
D037
15
D037
图 11. Maximum Output Power (BTL) vs Supply Voltage
图 12. Maximum Output Power (BTL) vs Supply Voltage
10
版权 © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
Typical Characteristics (接下页)
fs = 400 kHz, Hybrid Mode, TPA3126D2EVM Tested With AP2722. (unless otherwise noted)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Gain=26dB
TA=25èC
RL=8W
Gain=26dB
TA=25èC
RL=4W
PVCC = 6V
PVCC = 12 V
PVCC = 24 V
PVCC = 6V
PVCC = 12 V
PVCC = 24 V
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
Output Power (W)
Output Power (W)
D016
D017
图 13. Power Efficiency (BTL) vs Output Power
图 14. Power Efficiency (BTL) vs Output Power
0
0
-20
Gain=26dB
PVCC=24V
TA=25èC
RL=8W
Gain=26dB
PVCC=12V
TA=25èC
RL=4W
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
Right to Left
Left to Right
Right to Left
Left to Right
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
D010318
D00139
图 15. Crosstalk vs Frequency
图 16. Crosstalk vs Frequency
0
-20
10
Gain=26dB
PVCC=12VDC+200mVP-P
TA=25èC
Gain=26dB
PVcc=12V
TA=25èC
RL=2W
P O=1W
PO =5W
PO=10W
RL=8W
1
0.1
-40
-60
0.01
-80
Left Channel
Right Channel
-100
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
D020
D021
图 17. Supply Ripple Rejection Ratio (BTL) vs Frequency
图 18. Total Harmonic Distortion + Noise (PBTL) vs
Frequency
版权 © 2018, Texas Instruments Incorporated
11
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
Typical Characteristics (接下页)
fs = 400 kHz, Hybrid Mode, TPA3126D2EVM Tested With AP2722. (unless otherwise noted)
180
160
140
120
100
80
10
Gain=26dB
TA=25èC
RL=2W
Gain=26dB
PVCC=12V
TA=25èC
RL=2W
1
0.1
60
0.01
40
f= 20Hz
f= 1kHz
f= 6KHz
THD+N=1%
THD+N=10%
20
0.001
0
0.01
0.1
1
10
40
4
6
8
10
12
14
16
18
20
22
Output Power (W)
Supply Voltage (V)
D022
D023
图 19. Total Harmonic Distortion + Noise (PBTL) vs Output
图 20. Maximum Output Power (PBTL) vs Supply Voltage
Power
100
90
80
70
60
50
40
30
20
0
Gain=26dB
PVCC=12VDC+200mVP-P
TA=25èC
RL=2W
-20
-40
-60
-80
Gain = 26dB
TA = 25èC
RL = 3W
PVCC = 6V
PVCC = 12 V
PVCC = 24 V
10
0
-100
20
0
10
20
30
40
50
60
70
80
90 100
100
1k
10k 20k
Output Power (W)
Frequency (Hz)
D001
D025
图 21. Power Efficiency (PBTL) vs Output Power
图 22. Supply Ripple Rejection Ratio (PBTL) vs Frequency
10
140
Gain = 26dB
PVCC = 24V
Gain = 26dB
TA = 25èC
130
120
110
100
90
5
2
1
TA = 25èC
RL = 3W
RL = 3W
0.5
0.2
0.1
80
70
60
0.05
50
0.02
0.01
40
30
f = 20Hz
f = 1kHz
f = 6KHz
0.005
20
THD+N=1%
THD+N=10%
0.002
0.001
10
0
0.01
0.1
1
10
50 100 200
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
Output Power (W)
D002
D004
图 23. Total Harmonic Distortion + Noise (PBTL) vs Output
图 24. Maximum Output Power (PBTL) vs Supply Voltage
Power
12
版权 © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
8 Detailed Description
8.1 Overview
The analog-input Class-D amplifier TPA3126D2 is a performance upgrade to the prior generation TPA3116D2. It
features a more efficient, 90-mΩ MOSFET, and has an extremely-low idle current of < 23 mA (24 V) in the
standard LC filter configuration. The device can operate from the ultra-low-idle-loss modulation scheme, which
enables low power dissipation in both idle condition and while playing music, optimized for battery-powered audio
systems.
The TPA3126D2 supports both stereo and mono BTL modes, as well as mono PBTL mode. Comparing to the
conventional Class-D amplifiers, in the mono BTL mode, the idle channel of the TPA3126D2 is not in the
switching mode; therefore, it saves nearly half of the power loss, enabling low-power operation in single channel
applications.
The device may be configured for either master or slave operation by using the SYNC pin. This configuration
helps prevent the audible beats noise.
8.2 Functional Block Diagram
GVDD
PVCC
BSPR
SDZ
PVCC
TTL
Buffer
Modulation and
PBTL Select
MUTE
Gain
Control
OUTPR_FB
Gate
Drive
OUTPR
GAIN
+
OUTPR_FB
–
–
–
–
GND
RINP
RINN
+
+
PWM
Logic
Gain
Control
PLIMIT
GVDD
–
PVCC
–
+
BSNR
+
PVCC
OUTPNR_FB
OUTNR_
FB
+
FAULTZ
Gate
Drive
OUTNR
GND
Input
Sense
MONO
Select
SC Detect
DC Detect
SYNC
GAIN/SLV
Ramp
Generator
Startup Protection
Logic
Biases and
References
Thermal
Detect
AM<2:0>
PLIMIT
Reference
PLIMIT
PVCC
UVLO/OVLO
PVCC
GVDD
PVCC
BSNL
AVDD
PVCC
LDO
Regulator
AVCC
GVDD
GVDD
Gate
Drive
OUTNL
–
OUTNL_FB
OUTNL_
FB
–
+
+
–
LINP
LINN
GND
+
+
Gain
Control
PWM
Logic
PLIMIT
–
GVDD
–
PVCC
+
+
BSPL
PVCC
OUTPL_FB
–
Gate
Drive
OUTPL
GND
Input
Sense
PBTL
Select
Modulation and
PBTL Select
OUTPL_FB
GND
Thermal
Pad
版权 © 2018, Texas Instruments Incorporated
13
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
8.3 Feature Description
8.3.1 Gain Setting and Master and Slave
The gain of the TPA3126D2 is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave
mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four states
set the GAIN in Master mode with gains of 20, 26, 32, and 36 dB respectively, while the next four states set the
GAIN in Slave mode with gains of 20, 26, 32, and 36 dB respectively. The gain setting is latched during power-
up and cannot be changed while the device is powered on. 表 1 lists the recommended resistor values for
different state settings.
表 1. Gain and Master/Slave
MASTER / SLAVE
GAIN
R1 (to GND)(1)
R2 (to GVDD)(1)
INPUT IMPEDANCE
MODE
Master
Master
Master
Master
Slave
20 dB
26 dB
32 dB
36 dB
20 dB
26 dB
32 dB
36 dB
5.6 kΩ
20 kΩ
39 kΩ
47 kΩ
51 kΩ
75 kΩ
100 kΩ
100 kΩ
OPEN
100 kΩ
100 kΩ
75 kΩ
51 kΩ
47 kΩ
39 kΩ
16 kΩ
60 kΩ
30 kΩ
15 kΩ
9 kΩ
60 kΩ
30 kΩ
15 kΩ
9 kΩ
Slave
Slave
Slave
(1) Resistor tolerance should be 5% or better.
5
6
INNR
2
1
PLIMIT
GVDD
1
C5 1 µF
2
7
2
1
R2
8
51 k
GAIN/SLV
GND
9
R1 51 k
10
图 25. Gain, Master/Slave
In Master mode, the SYNC terminal is an output, while in Slave mode, the SYNC terminal is an input for a clock.
TTL logic levels with compliance to GVDD.
8.3.2 Input Impedance
The TPA3126D2 input stage is a fully differential input stage and the input impedance changes with the gain
setting from 7.3 kΩ at 36 dB gain to 50 kΩ at 20 dB gain. 表 1 lists the values from min to max gain. The
tolerance of the input resistor value is ±20% so that the minimum value will be higher than 5.9 kΩ. The inputs
must be AC-coupled to minimize the output DC-offset and ensure correct ramping of the output voltages during
power-ON and power-OFF. The input AC-coupling capacitor along with the input impedance forms a high-pass
filter with the following cut-off frequency:
1
ƒ
=
2pZiCi
(1)
If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz. 表 2
lists the recommended AC-coupling capacitors for each gain setting. If a –3-dB frequency response is accepted
at 20 Hz, 10 times lower capacitors (for example, a 1-µF capacitor) can be used.
14
版权 © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
表 2. Recommended Input AC-Coupling Capacitors
GAIN
20 dB
26 dB
32 dB
36 dB
INPUT IMPEDANCE
50 kΩ
INPUT CAPACITANCE
HIGH-PASS FILTER
2.1 Hz
1.5 µF
3.3 µF
5.6 µF
10 µF
25 kΩ
1.9 Hz
12.5 kΩ
2.3 Hz
7.3 kΩ
2.2 Hz
Z
f
C
i
Z
i
IN
Input
Signal
图 26. Input Impedance
The input capacitors should be a type of low leakage, such as quality electrolytic, tantalum, or ceramic
capacitors. If a polarized type is used the positive connection should face the input pins which are biased to 3
Vdc.
8.3.3 Startup and Shutdown Operation
The TPA3126D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of non-use for power conservation. The SDZ input terminal should be held high
(see specification table for trip point) during normal operation when the amplifier is in use. Pulling SDZ low puts
the outputs to mute and the amplifier to enter a low-current state. Do not leave SDZ unconnected, because the
amplifier operation is unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply. The gain setting is selected at the end of the start-up cycle, and cannot be changed until the next power-
up.
8.3.4 PLIMIT Operation
The TPA3126D2 has a built-in voltage limiter that can be used to limit the output voltage level below the supply
rail. The amplifier operates as if it was powered by a lower supply voltage, and thereby, limits the output power.
Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also
be used if tighter tolerance is required. Add a 1-µF capacitor from pin PLIMIT to ground to ensure stability.
图 27. Power Limit Example
版权 © 2018, Texas Instruments Incorporated
15
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. This is done by limiting the duty cycle to a
fixed maximum value. The limit can be considered as a "virtual" voltage rail which is lower than the supply
connected to PVCC. The "virtual" rail is approximately four times the voltage at the PLIMIT pin. The output
voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker
impedance.
æ
ö2
æ
ç
è
ö
÷
ø
RL
´ V
ç
÷
P
ç
÷
RL + 2 ´ RS
è
ø
POUT
=
for unclipped power
2 ´ RL
where
•
•
•
•
POUT (10%THD) = 1.25 × POUT (unclipped)
RL is the load resistance.
RS is the total series resistance including RDS(on), and output filter resistance.
VP is the peak amplitude, which is limited by the "virtual" voltage rail.
(2)
表 3. Power Limit Example
PVCC (V)
24 V
PLIMIT VOLTAGE (V)(1)
R to GND
Open
R to GVDD
Short
OUTPUT VOLTAGE (Vrms)
GVDD
3.3
17.9
12.67
9
24 V
45 kΩ
24 kΩ
Open
51 kΩ
24 V
2.25
GVDD
2.25
1.5
51 kΩ
12 V
Short
10.33
9
12 V
24 kΩ
18 kΩ
51 kΩ
12 V
68 kΩ
6.3
(1) PLIMIT measurements taken with EVM gain set to 26 dB and input voltage set to 1 Vrms
.
8.3.5 GVDD Supply
The GVDD Supply is used to power the gates of the output full bridge transistors. The GVDD supply can also be
used to supply the PLIMIT and GAIN/SLV voltage dividers. Decouple GVDD with a X5R ceramic 1-µF capacitor
to GND. The GVDD supply is not intended to be used for external supply. The current consumption should be
limited by using resistor voltage dividers for GAIN/SLV and PLIMIT of 100 kΩ or more.
8.3.6 BSPx and BSNx Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor of quality X5R or better, rated for at
least 16 V, must be connected from each output to the corresponding bootstrap input. (See the application circuit
diagram in 图 34.) The bootstrap capacitors connected between the BSxx pins and corresponding output function
as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side
switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side
MOSFETs turned on.
8.3.7 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3126D2 with a differential source, connect the positive lead of the audio source to the RINP or LINP
input and the negative lead from the audio source to the RINN or LINN input. To use the TPA3126D2 with a
single-ended source, AC ground the negative input through a capacitor equal in value to the input capacitor on
positive and apply the audio source to either input. In a single-ended input application, the unused input should
be AC grounded at the audio source instead of at the device input for best noise performance. For good transient
performance, the impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible to allow
the input DC blocking capacitors to become completely charged during the 40-ms power-up time. If the input
capacitors are not allowed to completely charged, there will be some additional sensitivity to the component
matching which can result in pop if the input components are not well matched.
16
版权 © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
8.3.8 Device Protection System
The TPA3126D2 contains a complete set of protection circuits carefully designed to make system design efficient
as well as to protect the device against any kind of permanent failures due to short circuits, overload, over
temperature, and under-voltage. The FAULTZ pin signals if an error is detected according to 表 4:
表 4. Fault Reporting
TRIGGERING CONDITION
(typical value)
LATCHED/SELF-
CLEARING
FAULT
FAULTZ
ACTION
Over Current
Output short or short to PVCC or GND
Tj > 150°C
Low
Low
Low
Output high impedance
Output high impedance
Output high impedance
Latched
Latched
Latched
Over Temperature
Too High DC Offset
DC output voltage
Under Voltage on
PVCC
PVCC < 4.5V
PVCC > 27V
–
–
Output high impedance
Output high impedance
Self-clearing
Self-clearing
Over Voltage on
PVCC
8.3.9 DC Detect Protection
The TPA3126D2 has circuitry which protects the speakers from DC current which might occur due to defective
capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault is reported on the
FAULT pin as a low state. The DC Detect fault causes the amplifier to shutdown by changing the state of the
outputs to Hi-Z.
If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the
SDZ pin. Connecting the FAULTZ and SDZ pins allows the FAULTZ pin function to automatically drive the SDZ
pin low which clears the DC Detect protection latch.
A DC Detect Fault is issued when the output differential voltage of either channel exceeds DC protection
threshold level for more than 640 ms at the same polarity. 表 5 shows some examples of the typical DC Detect
Protection threshold for several values of the supply voltage. The Detect Protection Threshold feature protects
the speaker from large DC currents or AC currents less than 2 Hz. To avoid nuisance faults due to the DC detect
circuit, hold the SD pin low at power-up until the signals at the inputs are stable. Also, take care to match the
impedance seen at the positive and negative inputs to avoid nuisance DC detect faults.
表 5 lists the minimum output offset voltages required to trigger the DC detect. The outputs must remain at or
above the voltage listed in the table for more than 640 ms to trigger the DC detect.
表 5. DC Detect Threshold
PVCC (V)
VOS - OUTPUT OFFSET VOLTAGE (V)
4.5
6
1.35
1.8
12
18
3.6
5.4
8.3.10 Short-Circuit Protection and Automatic Recovery Feature
The TPA3126D2 has protection from over current conditions caused by a short circuit on the output stage. The
short circuit protection fault is reported on the FAULTZ pin as a low state. The amplifier outputs are switched to a
high impedance state when the short circuit protection latch is engaged. The latch can be cleared by cycling the
SDZ pin through the low state.
If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the
SDZ pin. Connecting the FAULTZ and SDZ pins allows the FAULTZ pin function to automatically drive the SDZ
pin low which clears the short-circuit protection latch.
版权 © 2018, Texas Instruments Incorporated
17
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
8.3.11 Thermal Protection
Thermal protection on the TPA3126D2 prevents damage to the device when the internal die temperature
exceeds 150°C. This trip point has a ±15°C tolerance from device to device. Once the die temperature exceeds
the thermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a latched
fault.
Thermal protection faults are reported on the FAULTZ terminal as a low state.
If automatic recovery from the thermal protection latch is desired, connect the FAULTZ pin directly to the SDZ
pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the thermal
protection latch.
8.3.12 Device Modulation Scheme
The TPA3126D2 has the option of running in either BD modulation or ultra-low idle current Hybrid Mode.
8.3.12.1 BD Modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amplifier
is driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
18
版权 © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
0V
-
OUTP OUTN
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
图 28. BD Mode Modulation
版权 © 2018, Texas Instruments Incorporated
19
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
8.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
Many traditional Class-D amplifiers are based on the AD modulation. Due to the out-of-phase nature of a BTL or
PBTL amplifier operating in the AD modulation, if no LC filter was present, the load sees the full PWM signal
across its terminals. This causes a high-frequency ripple current to pass through the load, which leads to high
power dissipation, poor efficiency, and potential speaker damage. The ripple current is large in the AD
modulation scheme, because it is proportional to voltage multiplied by the time at that voltage. The differential
voltage swing is 2 × VCC, and the time at each voltage is half the period for the AD modulation scheme. An ideal
LC filter is required to store the ripple current from each half cycle for the next half cycle, while any resistance
causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely
reactive.
The modulation schemes implemented in the TPA3126D2 have little loss in the load even without a filter because
the pulses are short and the change in voltage is VCC instead of 2 × VCC. As the output power increases and
the pulses widen, the ripple current can go up. In this case, the ripple current can be filtered with an LC filter for
increased efficiency. However, in most applications the filter is not required.
With an LC filter, specifically as the cut-off frequency of the LC filter is smaller than the PWM switching frequency
of the amplifier, the ripple current is reduced such that only a small residual ripple voltage is present after the LC
filter. The filter has less resistance but higher impedance at the switching frequency than the speaker, which
results in less power dissipation, hence increasing efficiency.
8.3.14 Ferrite Bead Filter Considerations
Using the Advanced Emissions Suppression Technology in the TPA3126D2, a high efficiency Class-D audio
amplifier can be designed while minimizing interference to the surrounding circuits. Designing the amplifier can
also be accomplished with only a low-cost ferrite bead filter. In this case the user must carefully select the ferrite
bead used in the filter. One important aspect of the ferrite bead selection is the type of material used in the ferrite
bead. Not all ferrite material is alike, therefore the user must select a material that is effective in the 10-MHz to
100-MHz range which is key to the operation of the Class-D amplifier. Many of the specifications regulating
consumer electronics have emissions limits as low as 30-MHz. The ferrite bead filter should be used to block
radiation in the 30-MHz and above range from appearing on the speaker wires and the power supply lines which
are good antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor
with a value in the range of 1000-pF to reduce the frequency spectrum of the signal to an acceptable level. For
best performance, the resonant frequency of the ferrite bead or capacitor filter should be less than 10-MHz.
Also, the ferrite bead must be large enough to maintain its impedance at the peak currents expected for the
amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this case
it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current the
amplifier will see. If these specifications are not available, the device can also estimate the bead current handling
capability by measuring the resonant frequency of the filter output at low power and at maximum power. A
change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite
beads which have been tested and work well with the TPA3136D2 can be seen in the TPA3136D2EVM user
guide SLOU444.
A high quality ceramic capacitor is also required for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the Class-D outputs to
ground. Suggested values for a simple RC series snubber network would be 18-Ω in series with a 330-pF
capacitor, although design of the snubber network is specific to different applications and must be designed with
the consideration of the parasitic reactance of the printed circuit board as well as the audio amp. Take care to
evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC.
Also, verify the layout of the snubber network is tight and returns directly to the GND pins on the IC.
图 29 and 图 30 are TPA3126D2 EN55022 Radiated Emissions results uses TPA3126D2EVM with 8-Ω
speakers.
20
版权 © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
图 29. TPA3126D2 Radiated Emissions-Horizontal
图 30. TPA3126D2 Radiated Emissions-Vertical
(PVCC=19V, PO=1W)
(PVCC=19V, PO=1W)
8.3.15 When to Use an Output Filter for EMI Suppression
A complete LC reconstruction filter should be added in some circuit instances. These circumstances might occur
if there are nearby circuits which are sensitive to noise. In these cases, a classic second order Butterworth filter
similar to those shown in 图 31 can be used.
Some systems have little power supply decoupling from the AC line but are also subject to line conducted
interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these
cases, LC reconstruction filters can be the lowest-cost methods to pass LCI tests. Common mode chokes using
low frequency ferrite material can also be effective in preventing line conducted interference.
10 µH
OUTP
C2
L1
0.68 µF
4 W - 8 W
10 µH
OUTN
C3
L2
0.68 µF
Ferrite
Chip Bead
OUTP
1 nF
4 W - 8 W
Ferrite
Chip Bead
OUTN
1 nF
图 31. Output Filters
版权 © 2018, Texas Instruments Incorporated
21
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
8.3.16 AM Avoidance EMI Reduction
表 6. AM Frequencies
US
EUROPEAN
SWITCHING FREQUENCY (kHz)
AM2
AM1
AM0
AM FREQUENCY (kHz)
AM FREQUENCY (kHz)
540-917
540-914
500
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
0
0
1
917-1125
1125-1375
1375-1547
914-1122
1122-1373
1373-1548
600 (or 400)
500
600 (or 400)
1547-1700
1548-1701
600 (or 500)
8.4 Device Functional Modes
TPA3126D2 can be configured in either a stereo BTL (Bridge Tied Load) mode, mono BTL mode (only one
output BTL channel active), or in a mono PBTL (Parallel Bridge Tied Load) mode.
8.4.1 Mono PBTL Mode
In mono PBTL mode, the device can deliver up to 100-W output power. Configuration steps for mono PBTL
mode are as follows:
•
•
•
Connect LINP and LINN directly to Ground (without capacitors), so the device is set in a mono PBTL mode
during power up.
Connect OUTPR and OUTNR together for the positive speaker terminal, and OUTNL and OUTPL together for
the negative speaker terminal.
Analog input signal is applied to RINP and RINN.
PVCC
TPA3156D2
TPA3126D2
TPA3128D2
RINP
Audio
Source
And Control
TPA3129D2
Power Supply
4.5V œ 26V
RINN
RIGHT
OUTPR
LINP
LINN
OUTNR
PBTL
DETECT
LC
Filter
OUTPL
OUTNL
Copyright © 2018, Texas Instruments Incorporated
图 32. Mono PBTL Mode
22
版权 © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
Device Functional Modes (接下页)
8.4.2 Mono BTL Mode (Single Channel Mode)
The TPA3126D2 can be connected in mono BTL mode while cutting the idle power-loss nearly by half.
•
Connect RINP and RINN directly to Ground (without capacitors), so the device is set in mono BTL mode
during power up.
•
•
Connect OUTPL to the positive speaker terminal, and OUTNL to the negative speaker terminal.
Analog input signal is applied to LINP and LINN.
TPA3156D2
TPA3126D2
TPA3128D2
TPA3129D2
RINP
MONO
DETECT
RIGHT
RINN
Power Supply
4.5V œ 26V
OUTPR
OUTNR
LINP
LINN
Audio
Source
LEFT
And Control
OUTPL
OUTNL
LC
Filter
Copyright © 2018, Texas Instruments Incorporated
图 33. Mono BTL Mode
版权 © 2018, Texas Instruments Incorporated
23
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Typical Application
This section describes a 2.1 Master and Slave application. The Master (U1 TPA3126D2) is configured as stereo
BTL outputs with 400-kHz switching frequency and no power limit implemented, and the Slave (U2) is configured
as a mono PBTL output. Both U1 and U2 are setup with a gain of 26-dB. Inputs are connected for differential
inputs.
39&&
39&&ꢌ'(&283/,1*
287387ꢌ/&ꢌ),/7(5
/
(0,ꢌ&ꢎ5&ꢌ618%%(5
39&&
*1'
&ꢁꢉ
ꢀꢃQ)
ꢂꢃ9
&ꢀ
ꢈꢈꢃ)
ꢇꢂ9
&ꢈ
&ꢇ
ꢃꢄꢀ)
ꢂꢃ9
ꢀꢃꢃꢃS)
ꢂꢃ9
ꢀꢃ
ꢅꢄꢉ$
&ꢈꢁ
ꢃꢄꢃꢀ
ꢂꢃ9
5ꢀ
&ꢀꢆ
&ꢈꢃ
ꢀꢃꢃꢃS) ꢂꢃ9
ꢀꢃꢃN
ꢃꢄꢆꢉ
ꢂꢃ9
ꢇꢄꢇꢈ
*1'
8ꢀ
02'6(/
ꢀ
ꢈ
ꢇꢈ
ꢇꢀ
ꢇꢃ
ꢈꢊ
ꢈꢉ
ꢈꢅ
ꢈꢆ
ꢈꢂ
ꢈꢁ
ꢈꢇ
ꢈꢈ
ꢈꢀ
ꢈꢃ
ꢀꢊ
ꢀꢉ
ꢀꢅ
*1'
39&&
39&&
%635
28735
*1'
*1'
*1'
6'=
ꢁ5
ꢋ6'B/5
&ꢊ
ꢇ
)$8/7=
5,13
5ꢉ
ꢇꢄꢇꢈ
&ꢁ ꢀ)
ꢃꢄꢈꢈ) ꢈꢂ9
*1'
*1'
,1B3B5,*+7
,1B1B5,*+7
ꢁ
&ꢀꢅ
&ꢈꢀ
ꢃꢄꢆꢉ
ꢂꢃ9
&ꢂ ꢀ)
ꢂ
ꢀꢃꢃꢃS) ꢂꢃ9
&ꢈꢂ
5,11
3/,0,7
*9''
*$,1ꢋ6/9
*1'
*1'
*1'
*1'
ꢃꢄꢃꢀ
ꢆ
ꢂꢃ9
28715
%615
*1'
ꢀꢃ
ꢅꢄꢉ$
5ꢈ
&ꢀꢃ
ꢅ
ꢀꢃꢃN
&ꢆ
ꢃꢄꢈꢈ) ꢈꢂ9
ꢉ
/ꢇ
ꢀ)
5ꢇ
ꢊ
&ꢀꢀ
%63/
ꢈꢃꢄꢃN
ꢃꢄꢈꢈ) ꢈꢂ9
ꢀꢃ
ꢅꢄꢉ$
&ꢈꢆ
ꢀꢃ
ꢀꢀ
ꢀꢈ
ꢀꢇ
ꢀꢁ
ꢀꢂ
ꢀꢆ
ꢃꢄꢃꢀ
ꢂꢃ9
/,13
2873/
*1'
*1'
&ꢅ ꢀ)
&ꢉ ꢀ)
&ꢀꢉ
&ꢈꢈ
/,11
,1B3B/()7
,1B1B/()7
39&&
ꢃꢄꢆꢉ
ꢂꢃ9
5ꢊ
ꢀꢃꢃꢃS) ꢂꢃ9
087(
$0ꢈ
2871/
%61/
39&&
39&&
$9&&
ꢇꢄꢇꢈ
5ꢂ
ꢀꢃꢃN
&ꢀꢈ
5ꢁ
ꢃꢄꢈꢈ) ꢈꢂ9
ꢁ5
ꢀꢃꢃN
$0ꢀ
5ꢀꢃ
ꢇꢄꢇꢈ
*1'
&ꢀꢊ
*1'&ꢈꢇ
ꢀꢃꢃꢃS) ꢂꢃ9
39&&ꢌ'(&283/,1*
39&&
ꢃꢄꢆꢉ
ꢂꢃ9
$0ꢃ
5ꢀꢉ
ꢀN
4ꢀ
087(B/5
&ꢈꢅ
ꢃꢄꢃꢀ
ꢂꢃ9
/ꢁ
6<1&
*1'
73$ꢇꢀꢀꢆ'ꢈ
&ꢀꢇ
&ꢀꢁ
&ꢀꢂ
ꢈꢈꢃ
ꢇꢂ9
ꢃꢄꢀ
ꢂꢃ9
ꢀꢃꢃꢃS)
ꢂꢃ9
ꢀꢃ
ꢅꢄꢉ$
*1'
39&&ꢌ'(&283/,1*
5ꢆ
ꢁꢄꢅꢃN
*1'
39&&
39&&
&ꢁꢈ
ꢈꢈꢃ)
ꢇꢂ9
&ꢁꢇ
&ꢁꢁ
ꢃꢄꢀ)
ꢂꢃ9
ꢀꢃꢃꢃS)
ꢂꢃ9
5ꢀꢀ
&ꢁꢊ
ꢀꢃQ)
ꢂꢃ9
ꢀꢃꢃN
*1'
8ꢈ
02'6(/
287387ꢌ/&ꢌ),/7(5
(0,ꢌ&ꢎ5&ꢌ618%%(5
ꢀ
ꢈ
ꢇꢈ
ꢇꢀ
ꢇꢃ
ꢈꢊ
ꢈꢉ
ꢈꢅ
ꢈꢆ
ꢈꢂ
ꢈꢁ
ꢈꢇ
ꢈꢈ
ꢈꢀ
ꢈꢃ
ꢀꢊ
ꢀꢉ
ꢀꢅ
*1'
39&&
39&&
%635
28735
*1'
*1'
6'=
/ꢂ
ꢋ6'B68%
,1B3B68%
,1B1B68%
&ꢈꢉ
&ꢈꢊ
ꢀ)
ꢀ)
&ꢇꢈ
ꢇ
)$8/7=
5,13
ꢃꢄꢈꢈ) ꢈꢂ9
ꢀꢃ
ꢀꢇꢄꢂ$
&ꢁꢃ
ꢃꢄꢃꢀ)
ꢂꢃ9
ꢁ
&ꢇꢆ
&ꢇꢉ
ꢂ
ꢃꢄꢆꢉ
ꢂꢃ9
ꢀꢃꢃꢃS)
ꢂꢃ9
5,11
3/,0,7
*9''
*$,1ꢋ6/9
*1'
*1'
*1'
*1'
5ꢀꢆ
ꢆ
28715
%615
*1'
ꢇꢄꢇꢈ
5ꢀꢈ
ꢁꢅN
&ꢇꢇ
ꢅ
&ꢇꢃ
ꢃꢄꢈꢈ) ꢈꢂ9
ꢉ
ꢈ5
ꢀ)
5ꢀꢇ
ꢅꢂN
ꢊ
&ꢇꢁ
%63/
ꢃꢄꢈꢈ) ꢈꢂ9
*1'
*1'
ꢀꢃ
ꢀꢀ
ꢀꢈ
ꢀꢇ
ꢀꢁ
ꢀꢂ
ꢀꢆ
/,13
2873/
*1'
ꢇꢄꢇꢈ
*1'
39&&
&ꢇꢅ
&ꢇꢊ
/,11
ꢃꢄꢆꢉ
ꢂꢃ9
ꢀꢃꢃꢃS)
ꢂꢃ9
5ꢀꢂ
ꢀꢃꢃN
&ꢁꢀ
ꢃꢄꢃꢀ)
ꢂꢃ9
/ꢆ
087(
$0ꢈ
2871/
%61/
39&&
39&&
$9&&
5ꢀꢁ
ꢀꢃꢃN
&ꢇꢂ
ꢃꢄꢈꢈ) ꢈꢂ9
ꢀꢃ
ꢀꢇꢄꢂ$
$0ꢀ
39&&ꢌ'(&283/,1*
39&&
5ꢀꢅ
ꢀN
4ꢀ
$0ꢃ
087(B68%
6<1&
73$ꢇꢀꢀꢆ'ꢈ
&ꢁꢂ
&ꢁꢆ
&ꢁꢅ
&ꢇꢀ
ꢈꢈꢃ)
ꢇꢂ9
ꢃꢄꢀ)
ꢂꢃ9
ꢀꢃꢃꢃS)
ꢂꢃ9
ꢁꢅS)
*1'
*1'
*1'
图 34. TPA3126D2 in a 2.1 Mode Application
24
版权 © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
Application Information (接下页)
9.1.1.1 Design Requirements
DESIGN PARAMETERS
Input voltage range PVCC
PWM output frequencies
Maximum output power
EXAMPLE VALUE
4.5 V to 26 V
300kHz, 400 kHz, 500 kHz, 600 kHz, 1 MHz or 1.2 MHz
2 × 50 W
9.1.1.2 Detailed Design Procedure
The TPA3126D2 devices are very flexible and easy-to-use Class D amplifiers; therefore, the design process is
straightforward. Before beginning the design, gather the following information regarding the audio system.
•
•
•
•
PVCC rail planned for the design
Speaker or load impedance
Maximum output power requirement
Desired PWM frequency
9.1.1.2.1 Select the PWM Frequency
Set the PWM frequency by using AM0, AM1 and AM2 pins.
9.1.1.2.2 Select the Amplifier Gain and Master/Slave Mode
To select the amplifier gain setting, the designer must determine the maximum power target and the speaker
impedance. Once these parameters have been determined, calculate the required output voltage swing which
delivers the maximum output power.
Choose the lowest analog gain setting that corresponds to produce an output voltage swing greater than the
required output swing for maximum power. The analog gain and master/slave mode can be set by selecting the
voltage divider resistors (R1 and R2) on the Gain/SLV pin.
9.1.1.2.3 Select Input Capacitance
Select the bulk capacitors at the PVCC inputs for proper voltage margin and adequate capacitance to support the
power requirements. In practice, with a well-designed power supply, two 100-μF, 50-V capacitors should be
sufficient. One capacitor should be placed near the PVCC inputs at each side of the device. PVCC capacitors
should be a low ESR type because they are being used in a fast-switching application.
9.1.1.2.4 Select Decoupling Capacitors
Good quality decoupling capacitors must be added at each of the PVCC inputs to provide good reliability, good
audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this
application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors.
Also, these decoupling capacitors should be located near the PVCC and GND connections to the device in order
to minimize series inductances.
9.1.1.2.5 Select Bootstrap Capacitors
Each of the outputs require bootstrap capacitors to provide gate drive for the high-side output FETs. For this
design, use 0.22-μF, 25-V capacitors of X5R quality or better.
版权 © 2018, Texas Instruments Incorporated
25
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
9.1.1.3 Application Curves
10
140
130
120
110
100
90
Gain = 26dB
PVCC = 24V
Gain = 26dB
TA = 25èC
5
2
1
TA = 25èC
RL = 3W
RL = 3W
0.5
0.2
0.1
80
70
60
0.05
50
0.02
0.01
40
30
f = 20Hz
f = 1kHz
f = 6KHz
0.005
20
THD+N=1%
THD+N=10%
0.002
0.001
10
0
0.01
0.1
1
10
50 100 200
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
Output Power (W)
D002
D004
图 35. Total Harmonic Distortion + Noise (PBTL) vs Output
图 36. Maximum Output Power (PBTL) vs Supply Voltage
Power
10 Power Supply Recommendations
The TPA3126D2 device requires an external power supply, between 4.5 V and 26 V, for the analog circuitry
(AVCC) and the power stage (PVCC) of the amplifier. Several on-chip regulators are included on the
TPA3126D2 to generate the voltages necessary for the internal circuitry of the audio path. The voltage regulators
which have been integrated are sized only to provide the current necessary to power the internal circuitry. The
external pins are provided only as a connection point for off-chip bypass capacitors to filter the supply.
Connecting external circuitry to these regulator outputs may result in reduced performance and damage to the
device. The AVCC supply feeds internal LDO including GVDD. This LDO output are connected to external pins
for filtering purposes, but should not be connected to external circuits. GVDD LDO output have been sized to
provide current necessary for internal functions but not for external loading.
10.1 Power Supply Mode
The TPA3126D2 supports both single and dual power supply modes. For dual power supply mode application,
when AVCC is supplied with 4.5-V power, PVCC is recommended to be lower than 20 V. When PVCC is
supplied with power greater than 20 V, AVCC is recommended to be higher than 6 V.
26
版权 © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
11 Layout
11.1 Layout Guidelines
The TPA3126D2 can be used with a small, inexpensive ferrite bead output filter in most applications. However,
because the Class-D switching edges are fast, the layout of the printed circuit board must be planned carefully.
The following suggestions helps to meet EMC requirements.
•
Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC terminals as possible. Large (100-μF or greater) bulk power supply decoupling capacitors should
be placed near the TPA3126D2 on the PVCC supplies. Local, high-frequency bypass capacitors should be
placed as close to the PVCC pins as possible. These caps can be connected to the IC GND pad directly for
an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between
220-pF and 1-nF, and a larger mid-frequency cap of value between 100-nF and 1-µF also of good quality to
the PVCC connections at each end of the chip.
•
•
•
Minimize the current loop from each of the outputs through the ferrite bead filter and back to GND. The size
of this current loop determines its effectiveness as an antenna.
Grounding — The PVCC decoupling capacitors should connect to GND. All ground should be connected at
the IC GND, which should be used as a central ground connection or star ground for the TPA3126D2.
Output filter — The ferrite EMI filter (see 图 31) should be placed as close to the output terminals as possible
for the best EMI performance. The LC filter should be placed close to the outputs. The capacitors used in
both the ferrite and LC filters should be grounded.
For an example layout, see the TPA3126D2 Evaluation Module (TPA3126D2EVM) User Guide (SLOU506). Both
the EVM user manual and the thermal pad application reports, SLMA002 and SLMA004, are available on the TI
Web site at http://www.ti.com.
版权 © 2018, Texas Instruments Incorporated
27
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
11.2 Layout Example
图 37. Layout Example Top
28
版权 © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
Layout Example (接下页)
图 38. Layout Example Bottom
版权 © 2018, Texas Instruments Incorporated
29
TPA3126D2
ZHCSHZ1 –APRIL 2018
www.ti.com.cn
11.3 Heat Sink Used on the EVM
The heat sink (part number ATS-TI 10 OP-521-C1-R1) used on the EVM is an 14x25x50 mm extruded aluminum
heat sink with three fins (see drawing below). For additional information on the heat sink, go to www.qats.com.
50.00 0.38
[1.969 .015]
SINK LENGTH
MACHINE THESE
3 EDGES AFTER
0.00
ANODIZATION
25.00
–0.60
3.00
[.118]
+.000
–.024
SINK HEIGHT
.984
1.00
[.118]
6.35
[.250]
3.00
[.118]
13.90 0.38
[.547 .015]
BASE WIDTH
6.95
[.274]
5.00
[.197]
40.00
[1.575]
2X 4-40 x 6.5
图 39. EVM Heat Sink
This size heat sink has shown to be sufficient for continuous output power. The crest factor of music and having
airflow will lower the requirement for the heat sink size and smaller types can be used.
30
版权 © 2018, Texas Instruments Incorporated
TPA3126D2
www.ti.com.cn
ZHCSHZ1 –APRIL 2018
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
《TPA3126D2 评估模块用户指南》
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.3 相关文档
如需相关文档，请参阅：
•
•
《D 类音频放大器系统级保护概述》
《借助 TPA3128D2 实现超低空闲电流》
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
PowerPAD, E2E are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
12.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请参阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
31
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
TPA3126D2DAD
TPA3126D2DADR
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
HTSSOP
HTSSOP
DAD
32
32
46
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
TPA
3126
D2
ACTIVE
DAD
2000 RoHS & Green
NIPDAU
-40 to 85
TPA
3126
D2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3126D2DADR
HTSSOP DAD
32
2000
330.0
24.4
8.6
11.5
1.6
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DAD 32
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TPA3126D2DADR
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DAD HTSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPA3126D2DAD
32
46
530
11.89
3600
4.9
Pack Materials-Page 3
PACKAGE OUTLINE
TM
DAD0032A
PowerPAD TSSOP - 1.15 mm max height
S
C
A
L
E
1
.
6
0
0
PLASTIC SMALL OUTLINE
C
8.3
7.9
SEATING PLANE
TYP
A
0.1 C
PIN 1 ID AREA
30X 0.65
32
1
EXPOSED
THERMAL PAD
11.1
10.9
NOTE 3
4.36
3.26
2X
9.75
16
17
0.30
32X
0.19
4.11
3.31
0.1
C A
B
6.2
6.0
B
(0.15) TYP
0.25
SEE DETAIL A
1.15
1.00
GAGE PLANE
0.75
0.50
0.15
0.05
0 - 8
DETAIL A
TYPICAL
4222646/B 02/2020
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DAD0032A
PowerPAD TMTSSOP - 1.15 mm max height
PLASTIC SMALL OUTLINE
32X (1.5)
SEE DETAILS
SYMM
1
32
32X (0.45)
30X (0.65)
SYMM
(R0.05) TYP
17
16
(7.5)
LAND PATTERN EXAMPLE
SCALE:8X
METAL UNDER
SOLDER MASK
SOLDER MASK
SOLDER MASK
OPENING
METAL
OPENING
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222646/B 02/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DAD0032A
PowerPAD TSSOP - 1.15 mm max height
PLASTIC SMALL OUTLINE
32X (1.5)
SYMM
1
32
32X (0.45)
30X (0.65)
SYMM
(R0.05) TYP
16
17
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4222646/B 02/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TPA3126D2DADR
50W 立体声、100W 单声道、4.5V 至 26V、模拟输入 D 类音频放大器，低空闲电流 | DAD | 32 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA3128D2
具有低空闲电流的 30W 立体声、60W 单声道、4.5V 至 26V、模拟输入 D 类音频放大器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA3128D2DAP
具有低空闲电流的 30W 立体声、60W 单声道、4.5V 至 26V、模拟输入 D 类音频放大器 | DAP | 32 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA3128D2DAPR
具有低空闲电流的 30W 立体声、60W 单声道、4.5V 至 26V、模拟输入 D 类音频放大器 | DAP | 32 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA3129D2
具有低空闲电流的 15W 立体声、30W 单声道、4.5V 至 26V、模拟输入 D 类音频放大器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA3129D2DAP
具有低空闲电流的 15W 立体声、30W 单声道、4.5V 至 26V、模拟输入 D 类音频放大器 | DAP | 32 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA3129D2DAPR
具有低空闲电流的 15W 立体声、30W 单声道、4.5V 至 26V、模拟输入 D 类音频放大器 | DAP | 32 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA3130D2
15W,30W,50W Filter-Free Class-D Stereo Amplifier Family with AM AvoidanceWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA3130D2DAP
15W,30W,50W Filter-Free Class-D Stereo Amplifier Family with AM AvoidanceWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA3130D2DAPR
15W,30W,50W Filter-Free Class-D Stereo Amplifier Family with AM AvoidanceWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA3131D2
4W, 25W Filter-Free Class-D Stereo Amplifier with AM AvoidanceWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA3131D2RHBR
支持无滤波器操作的 4W 立体声、8W 单声道、4.5V 至 26V 电源电压、模拟输入 D 类音频放大器 | RHB | 32 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明