TPA3144D2PWPR [TI]
6W 立体声、12W 单声道、4.5V 至 14.4V、模拟输入 D 类音频放大器，无电感器和 AGL | PWP | 28 | -40 to 85;
| 型号： | TPA3144D2PWPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 6W 立体声、12W 单声道、4.5V 至 14.4V、模拟输入 D 类音频放大器，无电感器和 AGL | PWP | 28 | -40 to 85 放大器 光电二极管 商用集成电路 音频放大器 电感器 |
| 文件： | 总42页 (文件大小：2511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPA3144D2
ZHCSDW8C –APRIL 2015–REVISED DECEMBER 2017
TPA3144D2 6W 无电感器立体声 (BTL) D 类音频放大器，具有超低 EMI和
AGL
1 特性
具有扩频控制和 1SPW 调制方案的高级 EMI 抑制技术
在满足 EMC 要求的同时支持在输出中使用价格低廉的
铁氧体磁珠滤波器，从而降低系统成本。TPA3144D2
不仅针对短路和过载提供全面的保护，而且
1
•
•
•
•
电源电压为 7V、THD+N 为 10%、负载为 4Ω 时的
功率为 2x6W/通道
电源电压为 9.5V、THD+N 为 10%、负载为 6Ω 时
的功率为 2x6W/通道
SpeakerGuard™扬声器保护电路还包括一个可调节自
动增益限制 (AGL)、一个可调节功率限制器和一个直流
检测电路，用于保护连接的扬声器。 AGL 可在不发生
信号削波的情况下调节最大输出电压，从而增强了扬声
器保护效果，提升了音频质量。直流检测及引脚至引
脚、引脚接地和引脚至电源短路保护电路可以防止扬声
器在生产过程中发生输出直流和引脚短路。同时充分保
护输出，防止 GND、PVCC、输出至输出短路。短路
保护和热保护具有自动恢复功能。
电源电压为 10V、THD+N 为 10%、负载为 8Ω 时
的功率为 2x6W/通道
高达 90% 的高效 D 类运行（负载为 8Ω），无需
散热器
•
•
•
1W/4Ω/1kHz 时的 THD+N < 0.05%
A 加权输出噪声 < 65µV
在宽电源电压范围内工作 SpeakerGuard™扬声器
保护电路的工作电压范围为 4.5V 至 14.4V
•
•
无电感运行
抗电磁干扰 (EMI) 性能增强，具备扩展频谱和
1SPW 运行能力
TPA3144D2 可驱动阻抗低至 4Ω 的立体声扬声器。
TPA3144D2 的效率在负载为 8Ω 时高达 90%，无需外
部散热器，而且 TPA3144D2 可在双层印刷电路板
(PCB) 上实现全功率输出。
•
•
SpeakerGuard™扬声器保护功能包括自动增益限
制、可调节功率限制器和直流保护
可靠的引脚至引脚、引脚接地以及引脚至电源短路
保护和热保护
器件信息(1)
器件型号
TPA3144D2
封装
封装尺寸（标称值）
•
•
•
4 个可选的固定增益设置
单端或差分模拟输入
HTSSOP (28)
9.70mm × 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
启动时无喀哒声和噼啪声
2 应用
简化原理图
•
•
•
•
•
•
电视
TPA3144D2
Ferrite
Bead
Filter
蓝牙 (BT) 扬声器
无线扬声器
迷你扬声器
USB 扬声器
消费类音频设备
RIGHT
DETECT
Audio
Source
And Control
PBTL
LEFT
Ferrite
Bead
Filter
SD
FAULT
1SPW
1SPW Modulation Scheme Select
4 Level Gain Select
Power Supply
4.5V-14.4V
3 说明
GAIN
SSCTRL
LIMRATE
LIMTHRES
Spread Spectrum Mode Select
AGL Speed Select / Voltage Limiter
AGL / Limiter Threshold
TPA3144D2 是一款高效的 D 类音频功率放大器，适
用于以高达 6W 的功率驱动阻抗为 6Ω 或 8Ω（每通
道）的桥接式立体声扬声器。
110VAC->240VAC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS907
TPA3144D2
ZHCSDW8C –APRIL 2015–REVISED DECEMBER 2017
www.ti.com.cn
目录
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 19
10 Application and Implementation........................ 21
10.1 Application Information.......................................... 21
10.2 Typical Applications ............................................. 21
11 Power Supply Recommendations ..................... 28
11.1 Power Supply Decoupling, CS ............................. 28
12 Layout................................................................... 29
12.1 Layout Guidelines ................................................. 29
12.2 Layout Example .................................................... 30
13 器件和文档支持 ..................................................... 31
13.1 器件支持................................................................ 31
13.2 文档支持................................................................ 31
13.3 社区资源................................................................ 31
13.4 商标....................................................................... 31
13.5 静电放电警告......................................................... 31
13.6 Glossary................................................................ 31
14 机械、封装和可订购信息....................................... 32
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 Switching Characteristics.......................................... 7
7.7 Typical Characteristics.............................................. 8
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 12
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (July 2015) to Revision C
Page
•
Changed the Supply Voltage (AVCC to GND, PVCC to GND) MAX value From: 16 V To: 20 V in the Absolute
Maximum Ratings .................................................................................................................................................................. 5
Changes from Revision A (June 2015) to Revision B
Page
•
•
•
•
•
•
Changed Figure 5 .................................................................................................................................................................. 8
Changed Figure 6 .................................................................................................................................................................. 8
Changed Figure 8 .................................................................................................................................................................. 8
Changed Figure 14 ................................................................................................................................................................ 9
Changed Figure 15 ................................................................................................................................................................ 9
Changed Figure 19 .............................................................................................................................................................. 15
Changes from Original (April 2015) to Revision A
Page
•
•
•
•
•
•
•
•
•
已更改 “宽电源电压范围”特性从“4.5V 至 13.2V”更改为“4.5V 至 14.4V”................................................................................. 1
Changed Continuous output power TYP from 10 W to 6 W .................................................................................................. 7
Changed Continuous output power TYP from 10 W to 6 W ................................................................................................. 7
Changed Continuous output power, PBTL (mono) TYP from 20 W to 12 W......................................................................... 7
Changed Figure 3................................................................................................................................................................... 8
Changed Figure 4................................................................................................................................................................... 8
Changed Figure 13 ................................................................................................................................................................ 9
Changed Figure 14 ................................................................................................................................................................ 9
Changed Figure 15 ................................................................................................................................................................ 9
2
版权 © 2015–2017, Texas Instruments Incorporated
TPA3144D2
www.ti.com.cn
ZHCSDW8C –APRIL 2015–REVISED DECEMBER 2017
5 Device Comparison Table
DEVICE NAME
DESCRIPTION
6-W Stereo Class-D Audio Power Amplifier with
TPA3113D2
TPA3131D2
TPA3130D2
TPA3110D2
SpeakerGuard™
7W Filter-Free Class-D Stereo Amplifier In
Space Saving QFN
15W Filter-Free Class D Stereo Amplifier with
AM Avoidance
15W Filter-Free Class D Stereo Amplifier with
SpeakerGuard™
6 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP
(Top View)
SD
FAULT
LINP
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PVCC
PVCC
BSPL
2
3
LINN
4
OUTPL
GND
LIMRATE
GAIN
5
6
OUTNL
BSNL
BSNR
OUTNR
GND
SSCTRL
LIMTHRES
GVDD
GND
7
8
9
10
11
12
13
14
RINN
OUTPR
BSPR
PVCC
PVCC
RINP
1SPW
AVCC
Copyright © 2015–2017, Texas Instruments Incorporated
3
TPA3144D2
ZHCSDW8C –APRIL 2015–REVISED DECEMBER 2017
www.ti.com.cn
Pin Functions
PIN
I/O/P(1)
DESCRIPTION
NAME
NUMBER
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels
with compliance to AVCC.
SD
1
I
Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC.
Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both
short circuit faults and dc detect faults must be reset by cycling PVCC.
FAULT
2
O
LINP
LINN
3
4
I
I
Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
Decay speed for clip free power limiter. Connect a resistor divider from GVDD to GND to set decay
speed. Connect directly to GND to disconnect limiter.
LIMRATE
GAIN
5
6
7
I
I
I
4-state Amplifier gain select. Connect a resistor divider from GVDD to GND to set closed loop gain.
Spread spectrum control. Connect a resistor divider from GVDD to GND to set mode. Connect to GND
for disable spread spectrum.
SSCTRL
LIMTHR
ES
Voltage limit level for AGL and power limiter. Connect a resistor divider from GVDD to GND to set limit.
Connect directly to GVDD to disconnect limiter
8
9
I
High-side FET gate drive supply. Nominal voltage is 7 V. Also should be used as supply for LIMTHRES
limit function
GVDD
O
GND
10
11
12
13
14
P
I
Analog signal ground.
RINN
RINP
1SPW
AVCC
Negative audio input for right channel. Biased at 3 V.
Positive audio input for right channel. Biased at 3 V.
Modulation scheme select. Low: BD mode, high: 1SPW mode.
Analog supply
I
I
P
Power supply for right channel H-bridge. Right channel and left channel power supply inputs are
connected internally.
PVCC
PVCC
15
16
P
P
Power supply for right channel H-bridge. Right channel and left channel power supply inputs are
connected internally.
BSPR
OUTPR
GND
17
18
19
20
21
22
23
24
25
26
I
Bootstrap I/O for right channel, positive high-side FET.
Class-D H-bridge positive output for right channel.
Power ground for the H-bridges.
O
P
O
I
OUTNR
BSNR
BSNL
Class-D H-bridge negative output for right channel.
Bootstrap I/O for right channel, negative high-side FET.
Bootstrap I/O for left channel, negative high-side FET.
Class-D H-bridge negative output for left channel.
Power ground for the H-bridges.
I
OUTNL
GND
O
P
O
I
OUTPL
BSPL
Class-D H-bridge positive output for left channel.
Bootstrap I/O for left channel, positive high-side FET.
Power supply for left channel H-bridge. Right channel and left channel power supply inputs are
connected internally.
PVCC
PVCC
27
28
P
Power supply for left channel H-bridge. Right channel and left channel power supply inputs are
connected internally.
P
P
Thermal Pad
Connect to GND for best thermal and electrical performance
(1) I = Input, O = Output, P = Power
4
Copyright © 2015–2017, Texas Instruments Incorporated
TPA3144D2
www.ti.com.cn
ZHCSDW8C –APRIL 2015–REVISED DECEMBER 2017
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
AVCC to GND, PVCC to GND
–0.3
20
Supply voltage
GVDD to GND
V
GND to GND
-0.3
–0.3
–0.3
0.3
10
V
Input current
Voltage
To any pin except supply pins
mA
V
AVCC + 0.3
10
SD, FAULT, 1SPW to GND(2)
V/ms
V
GVDD + 0.3
100
Voltage
Voltage
GAIN, LIMRATE, LIMTHRES, SSCTRL(3)
V/ms
V
RINN, RINP, LINN, LINP
BTL, PVCC > 12 V
BTL, PVCC ≤ 12 V
PBTL, PVCC > 12 V
PBTL, PVCC ≤ 12 V
–0.3
4.8
3.2
2.5
1.8
6.3
Minimum load resistance, RL
Ω
Continuous total power dissipation
Operating free-air temperature range, TA
Temperature range
See the Thermal Information Table
(4)
–40
–65
–65
85
°C
°C
°C
150
150
Storage temperature range, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100 kΩ resister in series
with the pins.
(3) The voltage slew rate of these pins must be restricted to no more than 100 V/ms. For higher slew rates, use a 100 kΩ resister in series
with the pins.
(4) The TPA3144D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
7.2 ESD Ratings
VALUE
±1000
±250
UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged device model (CDM), per JEDEC specification JESD22-C101
V(ESD) Electrostatic discharge
V
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2015–2017, Texas Instruments Incorporated
5
TPA3144D2
ZHCSDW8C –APRIL 2015–REVISED DECEMBER 2017
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Supply voltage
TEST CONDITIONS
MIN
4.5
2
MAX
UNIT
V
VCC
VIH
VIL
VOL
IIH
PVCC, AVCC
14.4
AVCC
0.8
High-level input voltage
SD, 1SPW
V
Low-level input voltage
SD, 1SPW
V
Low-level output voltage
High-level input current
FAULT, RPULL-UP=100 k, PVCC=14.4 V
SD, 1SPW, VI = 2 V, AVCC = 12 V
SD, 1SPW, VI = 0.8 V, AVCC = 12 V
0.8
V
50
µA
µA
°C
°C
IIL
Low-level input current
5
TA
Operating free-air temperature(1)
Operating junction temperature(1)
–40
-40
85
TJ
150
(1) The TPA3144D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
7.4 Thermal Information
TPA3144D2
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
28 PINS
37.5
19.4
16.6
0.6
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
16.4
2.8
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DC CHARACTERISTICS, TA = 25°C, AVCC = PVCC = 12 V, RL = 6 Ω, using the TPA3144D2 EVM which is available at ti.com. (unless otherwise noted)
Class-D output offset voltage (measured
differentially)
| VOS
|
VI = 0 V, Gain = 36 dB
1.5
15
mV
ICC
ICC(SD)
Quiescent supply current
Quiescent supply current in shutdown mode
SD = 2 V, no load, 10 µF + 680 nF Output Filter
SD = 0.8 V, no load
35
40
40
60
mA
µA
IO = 500 mA, TJ = 25°C High Side
240
240
rDS(on)
Drain-source on-state resistance
Excluding Metal and
mΩ
Low side
Bond Wire Resistance
GAIN = 0 V (GND)
GAIN = 2.3 V (1/3·GVDD)
GAIN = 4.6 V (2/3·GVDD)
GAIN = 6.9 V (GVDD)
SD = 2 V
19
25
31
35
20
26
21
27
33
37
G
Gain
dB
32
36
ton
Turn-on time
14
ms
µs
V
tOFF
Turn-off time
SD = 0.8 V
2.5
6.9
GVDD
Gate drive supply
IGVDD = 2 mA
6.4
7.4
VRINN = 3.1 V and VRINN = 2.9 V, or VRINN = 2.9 V and
VRINN = 3.1 V
tDCDET
DC detect time
950
ms
6
Copyright © 2015–2017, Texas Instruments Incorporated
TPA3144D2
www.ti.com.cn
ZHCSDW8C –APRIL 2015–REVISED DECEMBER 2017
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
AC CHARACTERISTICS, TA = 25°C, AVCC = PVCC = 12 V, RL = 6 Ω, using the TPA3144D2 EVM which is available at ti.com. (unless otherwise noted)
200-mVPP ripple at 1 kHz,
Gain = 20 dB, Inputs ac-coupled to GND
PSRR
Power supply ripple rejection
–65
dB
PO
Continuous output power
THD+N = 10%, f = 1 kHz
6
6
W
W
W
A
PO
Continuous output power
THD+N = 10%, f = 1 kHz, PVCC = 13 V, RL = 8 Ω
THD+N = 10%, f = 1 kHz, PVCC = 13 V, RL = 4 Ω
f = 1 kHz, RL=3 Ω
PO
Continuous output power, PBTL (mono)
Maximum output current
12
IO
3.1
THD+N
Total harmonic distortion + noise
f = 1 kHz, PO = 5 W (half-power)
0.06%
65
µV
dBV
dB
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB, Spread
Spectrum off
Vn
Output integrated noise
–80
–75
Crosstalk
VO = 1 Vrms, Gain = 20 dB, f = 1 kHz
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted, Spread Spectrum off
SNR
OTE
Signal-to-noise ratio
102
dB
Thermal trip point
150
15
°C
°C
°C
Thermal hysteresis
TFB
Thermal foldback trip point
125
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
250
255
NOM
MAX
350
UNIT
kHz
fOSC
Oscillator frequency
310
315
fOSC, SS
Oscillator frequency, Spread Spectrum ON
355
kHz
Copyright © 2015–2017, Texas Instruments Incorporated
7
TPA3144D2
ZHCSDW8C –APRIL 2015–REVISED DECEMBER 2017
www.ti.com.cn
7.7 Typical Characteristics
All Measurements taken at 20dB closed loop gain, 1-kHz audio, TA = 25°C unless otherwise noted. Measurements were
made with AES17 filter using the TPA3144D2 EVM, which is available at ti.com.
10
10
1W
1W
2.5W
5W
2.5W
5W
1
1
0.1
0.1
0.01
0.01
0.001
0.001
20
50 100 200
500 1k
2k
5k 10k 20k
20
50 100 200
500 1k
2k
5k 10k 20k
Frequency (Hz)
Frequency (Hz)
D001
D002
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH, 1 W, 2.5 W, 5 W
AVCC=PVCC = 13 V, Load = 8 Ω + 66 µH, 1 W, 2.5 W, 5 W
Figure 1. Total Harmonic Distortion vs Frequency, 1SPW
(BTL)
Figure 2. Total Harmonic Distortion vs Frequency, 1SPW
(BTL)
10
10
20 Hz
1 kHz
20 Hz
1 kHz
1
0.1
1
0.1
0.01
0.01
0.01
0.1
Output Power (W)
1
7
0.01
0.1
Output Power (W)
1
7
D001
D001
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH, 20 Hz, 1 kHz, 6.7 kHz
AVCC=PVCC = 13 V, Load = 8 Ω + 66 µH, 20 Hz, 1 kHz, 6.7 kHz
Figure 3. Total Harmonic Distortion + Noise vs Output
Power, 1SPW (BTL)
Figure 4. Total Harmonic Distortion + Noise vs Output
Power, 1SPW (BTL)
20
18
16
14
12
10
8
16
14
12
10
8
6
6
4
4
2
2
0
0
4
5
6
7
8
9
10 11 12 13 14 15
4
5
6
7
8
9
10 11 12 13 14 15
Supply Voltage (V)
Supply Voltage (V)
D005
D006
AVCC=PVCC = 4.5 V to 14.4 V, Load = 6 Ω + 47 µH, AGL + PLIM
AVCC=PVCC = 4.5 V to 14.4 V, Load = 8 Ω + 66 µH, AGL + PLIM
disable (LIMRATE = GND, LIMTHRES = GVDD)
disable (LIMRATE = GND, LIMTHRES = GVDD)
Figure 5. Output Power vs Supply Voltage, 1SPW (BTL)
Figure 6. Output Power vs Supply Voltage, 1SPW (BTL)
8
Copyright © 2015–2017, Texas Instruments Incorporated
TPA3144D2
www.ti.com.cn
ZHCSDW8C –APRIL 2015–REVISED DECEMBER 2017
Typical Characteristics (continued)
All Measurements taken at 20dB closed loop gain, 1-kHz audio, TA = 25°C unless otherwise noted. Measurements were
made with AES17 filter using the TPA3144D2 EVM, which is available at ti.com.
100
90
80
70
60
50
40
30
20
10
0
28
24
20
16
12
8
40
20
0
-20
-40
-60
PVcc = 6V
PVcc = 12V
PVcc = 14.4V
20
50 100 200
500 1k
Frequency
2k
5k 10k 20k
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Total Output Power (W)
D007
D008
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH (device pins)
AVCC=PVCC = 6 V, 12 V, 14.4 V, Load = 6 Ω + 47 µH, AGL +
PLIM disable (LIMRATE = GND, LIMTHRES = GVDD)
Figure 7. Gain/Phase vs Frequency (BTL)
Figure 8. Efficiency vs Output Power, 1SPW (BTL)
100
90
80
70
60
50
40
30
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
20
PVcc = 6V
PVcc = 13V
PVcc = 14.4V
-100
-110
Ch 1
Ch 2
10
0
-120
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Power (W)
20
50 100 200
500 1k
Frequency (Hz)
2k
5k 10k 20k
D009
D010
AVCC=PVCC= 6 V, 13 V, 14.4 V, Load = 8 Ω + 66 µH, AGL +
AVCC=PVCC = 12 V, 1 W, Load = 6 Ω + 47 µH
PLIM disable (LIMRATE = GND, LIMTHRES = GVDD)
Figure 10. Crosstalk vs Frequency, 1SPW (BTL)
Figure 9. Efficiency vs Output Power, 1SPW (BTL)
0
10
5
1 W
5 W
10 W
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
20
50 100 200
500 1k
2k
5k 10k 20k
20
50 100 200
500 1k
2k
5k 10k 20k
Frequency (Hz)
Frequency (Hz)
D011
D012
AVCC=PVCC = 12 V, Load = 4 Ω + 33 µH
AVCC=PVCC = 13 V, Load = 4 Ω + 33 µH, 1 W, 2.5 W, 10 W
Figure 11. Supply Ripple Rejection Ratio vs Frequency
(BTL)
Figure 12. Total Harmonic Distortion + Noise vs Frequency,
1SPW (PBTL)
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Typical Characteristics (continued)
All Measurements taken at 20dB closed loop gain, 1-kHz audio, TA = 25°C unless otherwise noted. Measurements were
made with AES17 filter using the TPA3144D2 EVM, which is available at ti.com.
10
15
12
9
20 Hz
1 kHz
1
6
0.1
0.01
3
0
0.01
0.1
Output Power (W)
1
7
4
5
6
7
8
9
10 11 12 13 14 15
Supply Voltage (V)
D001
D001
AVCC=PVCC = 13 V, Load = 4 Ω + 33 µH, 20 Hz, 1 kHz, 6.7 kHz
AVCC=PVCC = 4.5 V to 14.4 V, Load = 4 Ω + 33 µH, AGL + PLIM
disable (LIMRATE = GND, LIMTHRES = GVDD)
Figure 13. Total Harmonic Distortion + Noise vs Output
Power, 1SPW (PBTL)
Figure 14. Output Power vs Supply Voltage, 1SPW (PBTL)
100
90
80
70
60
50
40
30
20
10
0
PVcc = 6 V
PVcc = 13 V
PVcc = 14.4 V
0
1
2
3
4
5
6
7
8
9
10 11 12
Total Output Power (W)
D015
AVCC=PVCC = 6 V, 13 V, 14.4 V, Load = 4 Ω + 33 µH, AGL + PLIM disable (LIMRATE = GND, LIMTHRES =
GVDD)
Figure 15. Efficiency vs Output Power, 1SPW (PBTL)
8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications and Typical
Characteristics.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to
out of band noise present at the amplifier output. An AES-17 pre analyzer filter is recommended to use for Class-
D amplifier measurements. In absence of such filter, a 30-kHz low-pass filter (10 Ω + 47 nF) can be used to
reduce the out of band noise remaining on the amplifier outputs.
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9 Detailed Description
9.1 Overview
To facilitate system design, the TPA3144D2 needs only a single power supply between 4.5 V and 14.4 V for
operation. An internal voltage regulator provides suitable voltage levels for the gate driver, digital, and low-
voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, as in the high-side gate drive,
is accommodated by built-in bootstrap circuitry with integrated boot strap diodes requiring only an external
capacitor for each half-bridge.
The audio signal path, including the gate drive and output stage, is designed as identical, independent full-
bridges. All decoupling capacitors should be placed as close to their associated pins as possible. In general, the
physical loop with the power supply pins, decoupling capacitors and GND return path to the device pins must be
kept as short as possible and with as little area as possible to minimize induction (see reference board
documentation for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BSXX) to the power-stage output pin (OUTXX). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap
pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential
and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching
frequencies in the range of 310 kHz, use ceramic capacitors with at least 220-nF capacitance, size 0603 or 0805,
for the bootstrap supply. These capacitors ensure sufficient energy storage, even during clipped low frequency
audio signals, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of its
ON cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. For optimal electrical performance, EMI compliance, and system reliability, each PVCC
pin should be decoupled with ceramic capacitors that are placed as close as possible to each supply pin. It is
recommended to follow the PCB layout of the TPA3144D2 reference design. For additional information on
recommended power supply and required components, see the application diagrams in this data sheet.
The PVCC power supply should have low output impedance and low noise. The power-supply ramp and SD
release sequence is not critical for device reliability as facilitated by the internal power-on-reset circuit, but it is
recommended to release SD after the power supply is settled for minimum turn on audible artifacts.
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9.2 Functional Block Diagram
GVDD
PVCCL
BSPL
PVCCL
PBTL Select
OUTPL FB
Gate
Drive
OUTPL
OUTPL FB
GND
LINP
PWM
Logic
Gain
PLIMIT
Control
LINN
GVDD
PVCCL
BSNL
PVCCL
OUTNL FB
FAULT
OUTNL FB
OUTNL
Gate
Drive
SD
TTL
Buffer
SC Detect
DC Detect
GAIN
GND
Gain
Control
Biases and
References
Ramp
Generator
Startup Protection
Logic
Spread Spectrum
Thermal
Detect
SSCTRL
Control
UVLO/OVLO
LIMITER
Reference
LIMRES
GVDD
PVCCL
BSNR
AVDD
PVCCL
LDO
Regulator
AVCC
GVDD
Gate
Drive
OUTNR
GVDD
OUTNR FB
OUTNR FB
RINN
GND
PWM
Logic
Gain
PLIMIT
Control
RINP
GVDD
PVCCL
BSPR
PVCCL
OUTNR FB
Gate
Drive
OUTPR
PBTL Select
OUTPR FB
GND
9.3 Feature Description
9.3.1 Gain Setting via GAIN Pin
The gain of the TPA3144D2 is set by a voltage applied to the GAIN pin, which is set by a resistor voltage divider
with GVDD as supply voltage. The resistance of the voltage divider should be a minimum of 100 kΩ in order not
to overload the GVDD regulator of TPA3144D2.
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Feature Description (continued)
/SD
/FAULT
LINP
LINN
LIMRATE
GAIN
SSCTRL
LIMTHRES
GVDD
AGND
RINN
RINP
1SPW
AVCC
Figure 16. GAIN Pin Voltage Programming by GVDD Resistor Divider
The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside
the amplifier. This causes the input impedance (Zi) to be dependent on the gain setting. The actual gain settings
are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance
from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
The selected input gain is latched at device start up and cannot be changed when SD is high.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 7.2 kΩ, which is the absolute minimum input impedance of the TPA3144D2. At the lower gain
settings, the input impedance could increase as high as 72 kΩ.
Table 1. Gain Setting
AMPLIFIER GAIN (dB)
INPUT IMPEDANCE (kΩ)
GAIN PIN VOLTAGE
TYP
20
TYP
60
30
15
9
0 V (GND)
2.3 V (1/3·GVDD)
4.6 V (2/3·GVDD)
6.9 V (GVDD)
26
32
36
9.3.2 SD Operation
The TPA3144D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SD input pin should be held high (see
specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the
outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier
operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply voltage.
9.3.3 Gain Limit Control, LIMTHRES and LIMRATE
The TPA3144D2 has built-in gain limiters with two operation modes for load and system protection: Voltage
limiting and temperature limiting. The voltage limiting mode controls the TPA3144D2 voltage gain to limit the
output signal without signal clipping, and the temperature control mode limits the device power dissipation to
keep the die temperature within recommended operating conditions. Both voltage limiter and thermal limiter
attack and release speeds (time per 0.5dB gain step) are controlled by the LIMRATE pin:
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Table 2. Speaker Guard AGL Settings
LIMRATE
VOLTAGE
AGL ATTACK
TIME
AGL/TFB
RELEASE TIME
MODE
TFB ATTACK TIME
GVDD
2/3·GVDD
1/3·GVDD
GND
FAST
MEDIUM
SLOW
40 µs
80 µs
200 ms
400 ms
400 ms
800 ms
160 µs
800 ms
1600 ms
DISABLED
PLIMIT
DISABLED
DISABLED
LIMRATE accepts a 4-level input signal to setup operation. When LIMRATE is connected to GND, the voltage
limiter function is changed to a hard clip action to control the maximum output voltage.
9.3.4 SPEAKERGUARD Automatic Gain Limit, AGL
The TPA3144D2 has a built-in SpeakerGuard AGL to limit excessive output voltage to a non clipping output
signal. When an excessive level input signal is sent to TPA3144D2, the SpeakerGuard AGL will automatically
reduce the amplifier gain to maintain maximum unclipped output signal to preserve high audio quality and to
protect the attached speaker from excessive power. The AGL works with a fast attack speed and a slower
release speed to achieve maximum protection and a minimum number of audible artifacts.
input signal
attack level
release level
output signal
Figure 17. AGL Attack and Release Thresholds
When the input level multiplied by the TPA3144D2 closed loop gain exceeds the limiter threshold set by the
LIMTHRES pin voltage, the TPA3144D2 closed loop gain is reduced by a single or by multiple 0.5-dB steps until
the output signal voltage gets below the level set by the LIMTHRES pin voltage, or if a –12.0-dB gain reduction
limit is reached. When the output voltage gets below the release threshold, the TPA3144D2 closed loop gain is
increased by a single or by multiple 0.5-dB steps until the release threshold is reached, or the closed loop gain is
at its nominal closed loop gain level. The AGL gain adjustment is applied with a ramp speed selectable by the
LIMRATE pin setting.
14
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input signal
thermal
warning
attack time
release time
gain
release level
attack level
output signal
Figure 18. AGL Attack and Release Slopes
9.3.5 Thermal Foldback, TFB
The TPA3144D2 Thermal Foldback, TFB, is designed to protect the TPA3144D2 from excessive die temperature
in case the device is operated beyond the recommended temperature or power limit, or with a weaker thermal
system than recommended. The TFB works by reducing the on die power dissipation by reducing the
TPA3144D2 closed loop gain in steps of 0.5 dB if the temperature trig point is exceeded. Once the die
temperature drops below the TFB trig point, the TPA3144D2 closed loop gain is increased by a single or by
multiple 0.5-dB steps until either the TFB trig point is reached, the closed loop gain attains the nominal closed
loop gain level, or a maximum of 12-dB attenuation is reached, in which case the closed loop gain will be
decreased again. The TFB gain adjustment is applied with a ramp speed selectable by the LIMRATE pin setting
as shown in Table 2.
9.3.6 PLIMIT
The PLIMIT operation will, if selected, limit the output voltage level to a voltage level below the supply rail. In this
case the amplifier operates as if it was powered by a lower supply voltage, and thereby limiting the output power
by voltage clipping. PLIMIT threshold is set by the LIMTHRES pin voltage.
TPA3144D2
Figure 19. PLIMIT Circuit Operation
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9.3.7 LIMTHRES
The AGL and PLIMIT voltage threshold is set by the applied LIMTHRES voltage. The LIMTHRES voltage is set
by a voltage divider from GVDD to GND. The limiting is done by limiting the amplifier output voltage to a fixed
maximum value. This limit can be thought of as a "virtual" voltage rail, which is lower than the PVCC supply. This
virtual rail is 4 times the voltage at the LIMTHRES pin. This output voltage can be used to calculate the
maximum output voltage (unclipped using AGL and clipped using PLIMIT) and power for a given LIMTHRES
voltage and speaker impedance.
2
≈
∆
∆
«
’
÷
÷
◊
≈
’
RL
∆
∆
÷
÷
∂VP
RL + 2∂ RS
«
◊
P
=
,
forunclipped power
OUT
2∂ RL
(1)
Where:
RS is the total series resistance including RDS(on), and any resistance in the output filter.
RL is the load resistance.
VP is the peak amplitude of the output possible within the supply rail.
VP = 4 × LIMTHRES voltage if VP < PVCC
POUT = Maximum unclipped output power. 10%THD using PLIMIT: 1.25 × PMAX (unclipped)
Increasing the LIMTHRES voltage from a given value increases the maximum output voltage swing until it equals
PVCC. Adjusting LIMTHRES to a higher value will disable both the AGL and PLIMIT function and will offer
highest available output power, however it is always advised to use the LIMTHRES function if PVCC is higher
than the nominal value to prevent shutdown due to over current protection or to reduce frequency of thermal
foldback events. To disable the AGL or PLIMIT function, the LIMTHRES pin is simply connected to GVDD.
/SD
/FAULT
LINP
LINN
LIMRATE
GAIN
SSCTRL
LIMTHRES
GVDD
AGND
RINN
RINP
1SPW
AVCC
Figure 20. LIMHTRES Pin Voltage Programming by GVDD Resistor Divider
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Table 3. LIMTHRES Typical Operation
OUTPUT
OUTPUT
POWER (W),
10% THD,
PLIMIT
TEST
CONDITIONS
()
LIMTHRES
VOLTAGE (V)
POWER (W),
UNCLIPPED,
AGL
R to GND
R to GVDD
PVCC = 12 V,
RL = 4 Ω
1.6
1.9
2.2
22 kΩ
33 kΩ
39 kΩ
68 kΩ
82 kΩ
82 kΩ
4.75
4.75
4.75
6
6
6
PVCC = 12 V,
RL = 6 Ω
PVCC = 12 V,
RL = 8 Ω
space
3
2,5
2
3
AGL, UNCLIPPED, 8Ω
PLIMIT, 10% THD, 8Ω
AGL, UNCLIPPED, 6Ω
PLIMIT, 10% THD, 6Ω
2
1
1,5
1
0,5
0
0
0
0
1
2
3
4
5
6
7
2
4
6
C002
C003
Max Output Power [W]
Max Output Power [W]
Figure 22. Max Output Power vs LIMTHRES, 6 Ω, PVCC =
Figure 21. Max Output Power vs LIMTHRES, 8 Ω, PVCC =
12 V
12 V
9.3.8 Spread Spectrum and De-Phase Control
The TPA3144D2 has built-in spread spectrum control of the oscillator frequency and de-phase of the PWM
outputs to improve EMI performance. Two spread spectrum schemes can be selected, and for operation without
spread spectrum, de-phase can be turned off.
De-phase inverts the phase of the output PWM such that the idle output PWM waveforms of the two audio
channels are inverted. De-phase does not affect the audio signal, or its polarity.
Spread spectrum mode and de-phase is selected by the applied SSCTRL voltage.
Table 4. Gain Setting
SPREAD SPECTRUM
SSCTRL PIN VOLTAGE
DE-PHASE
MODULATION
0 V (GND)
OFF
OFF
ON
ON
ON
2.3 V (1/3·GVDD)
4.6 V (2/3·GVDD)
6.9 V (GVDD)
OFF
SS1 MODULATION
SS2 MODULATION
9.3.9 GVDD Supply
The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply
the voltage divider circuits for LIMRATE, LIMTHRES, GAIN, and SSCTRL programming voltages.. Add a 1-μF
capacitor to ground at this pin.
9.3.10 DC Detect
The TPA3144D2 has circuitry which will protect the speakers from DC current which might occur due to defective
capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on
the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the
state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVCC supply. Cycling SD will
NOT clear a DC detect fault.
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A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 14% (for example,
+57%, -43%) for more than 950 msec at the same polarity. This feature protects the speaker from large DC
currents or AC currents less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low
at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive
and negative inputs to avoid nuisance DC detect faults.
The minimum differential input voltages required to trigger the DC detect are show in Table 5. The inputs must
remain at or above the voltage listed in the table for more than 950 msec to trigger the DC detect.
Table 5. DC Detect Threshold, PVCC=12V
AV(dB)
20
Vin (mV, differential)
Vout (V, differential)
260
130
65
2.6
2.6
2.6
2.6
26
32
36
40
9.3.11 PBTL Select
The TPA3144D2 offers the feature of parallel BTL operation with two outputs of each channel connected directly.
If the LINP and LINN input pins (pin 3 and 4) are tied low, the positive and negative outputs of each channel (left
and right) are synchronized and in phase. To operate in this PBTL (mono) mode, tie LINP and LINN inputs low to
GND and apply the input signal to the RINP and RINN inputs and place the speaker between the LEFT and
RIGHT outputs with OUTPL connected to OUTNL and OUTPR connected to OUTNR to parallel the output half
bridges for highest power efficiency. For an example of the PBTL connection, see the schematic in the Typical
Applications section.
9.3.12 Short-Circuit Protection and Automatic Recovery Feature
The TPA3144D2 has protection from overcurrent conditions caused by a short circuit on the output stage. The
short circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a
Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin
through the low state.
If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the short-circuit
protection latch.
9.3.13 Thermal Protection
Thermal protection on the TPA3144D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a
latched fault.
Thermal protection faults are reported on the FAULT pin.
If automatic recovery from the thermal protection latch is desired, connect the FAULT pin directly to the SD pin.
This allows the FAULT pin function to automatically drive the SD pin low which clears the thermal protection
latch.
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9.4 Device Functional Modes
The TPA3144D2 has the option of running in either BD modulation or 1SPW modulation; this is set by the 1SPW
pin.
1SPW = GND: BD-modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
-
OUTP OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
Figure 23. BD Mode Modulation
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Device Functional Modes (continued)
1SPW = HIGH: 1SPW-modulation
The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty
in THD degradation and more attention required in the output filter selection. In 1SPW mode the outputs operate
at ~15% modulation during idle conditions. When an audio signal is applied one output will decrease and one will
increase. The decreasing output signal will quickly rail to GND at which point all the audio modulation takes place
through the rising output. The result is that only one output is switching during a majority of the audio cycle.
Efficiency is improved in this mode due to the reduction of switching losses. The THD penalty in 1SPW mode is
minimized by the high performance feedback loop. The resulting audio signal at each half output has a
discontinuity each time the output rails to GND. This can cause ringing in the audio reconstruction filter unless
care is taken in the selection of the filter components and type of filter used.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
-PVCC
OUTP
-OUTN
0
A
Speaker
Current
Figure 24. 1SPW Mode Modulation
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPA3144D2 is designed for use in inductor free applications with limited distance wire length) between
amplifier and speakers like in TV sets, sound docks and Bluetooth speakers. The TPA3144D2 can either be
configured in stereo or mono mode, depending on output power conditions. Depending on output power
requirements and necessity for (speaker) load protection, the built in AGL or PLIMIT circuit can be used to
control system power, see functional description of these features.
10.2 Typical Applications
PVCC
100µF
1nF 100nF
GND
FB
10k
SD
FAULT
LINP
PVCC
PVCC
BSPL
OUTPL
GND
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
/SHUTDOWN
IN_LEFT
1nF
1nF
2
1µF
1µF
220nF
3
LINN
4
GND
LIMRATE
GAIN
GND
5
GND
OUTNL
BSNL
BSNR
OUTNR
GND
6
FB
FB
39k
56k
33k
220nF
SSCTRL
LIMTHRES
GVDD
7
TPA3144D2
8
33k
33k
220nF
GND
9
GND
1µF
GND
10
11
12
13
14
1µF
RINN
OUTPR
BSPR
PVCC
PVCC
1nF
1nF
RINP
IN_RIGHT
1µF
220nF
1SPW
AVCC
GND
GND
1µF
GND
FB
10R
PVCC
1nF 100nF 100µF
GND
Figure 25. Stereo Class-D Amplifier with BTL Output and Single-Ended Inputs with Spread Spectrum
Modulation
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Typical Applications (continued)
PVCC
100µF
1nF 100nF
10k
SD
FAULT
LINP
PVCC
PVCC
BSPL
OUTPL
GND
GND
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
/SHUTDOWN
2
470nF
3
LINN
4
FB
GND
LIMRATE
GAIN
GND
5
OUTNL
BSNL
BSNR
OUTNR
GND
6
39k
33k
56k
33k
SSCTRL
LIMTHRES
GVDD
1nF
1nF
7
TPA3144D2
8
33k
GND
9
1µF
GND
GND
GND
10
11
12
13
14
1µF
RINN
OUTPR
BSPR
PVCC
PVCC
FB
RINP
IN
1µF
470nF
1SPW
AVCC
GND
1µF
GND
10R
PVCC
1nF 100nF 100µF
GND
(1) 100-kΩ resistor is needed if the PVCC slew rate is more than 10 V/ms.
Figure 26. Stereo Class-D Amplifier with PBTL Output and Single-Ended Input with Spread Spectrum
Modulation
10.2.1 Design Requirements
10.2.1.1 PCB Material Recommendation
FR-4 Glass Epoxy material with 1 oz. (35 µm) is recommended for use with the TPA3144D2. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance). It is recommended to use several GND underneath the device thermal pad for
thermal coupling to a bottom side copper GND plane for best thermal performance.
10.2.1.2 PVCC Capacitor Recommendation
The large capacitors used in conjunction with each full-bridge, are referred to as the PVCC Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 100 μF, 16 V will support most applications
with 12-V power supply. 25-V capacitor rating is recommended for power supply voltage higher than 12-V. For
The PVCC capacitors should be low ESR type because they are used in a circuit associated with high-speed
switching.
10.2.1.3 Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the ceramic capacitors that are placed on the power supply to each full-bridge. They must withstand
the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and
the ripple current created by high power output. A minimum voltage rating of 16 V is required for use with a 12-V
power supply.
22
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Typical Applications (continued)
10.2.2 Detailed Design Procedure
A rising-edge transition on SD input allows the device to start switching. It is recommended to ramp the PVCC
voltage to its desired value before releasing SD for minimum audible artefacts.
The device is non-inverting the audio signal from input to output.
The GVDD pin is not recommended to be used as a voltage source for external circuitry.
10.2.2.1 Ferrite Bead Filter Considerations
Using the Advanced Emissions Suppression Technology in the TPA3144D2 amplifier it is possible to design a
high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to
accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite
bead used in the filter.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to
the operation of the Class-D amplifier. Many of the specifications regulating consumer electronics have
emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz
and above range from appearing on the speaker wires and the power supply lines which are good antennas for
these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the
range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance,
the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz.
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In
this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak
current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead's
current handling capability by measuring the resonant frequency of the filter output at low power and at maximum
power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of
ferrite beads which have been tested and work well with the TPA3144D2 include NFZ2MSM series from Murata.
A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class D outputs to
ground. Suggested values for a simple RC series snubber network would be 10 Ω in series with a 330-pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the GND or the thermal pad beneath the
chip.
10.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3144D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
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Typical Applications (continued)
10.2.2.3 When to Use an Output Filter for EMI Suppression
The TPA3144D2 has been tested with a simple ferrite bead filter for a variety of applications including long
speaker wires up to 100 cm and high power. The TPA3144D2 EVM passes FCC Class B specifications under
these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic
second order Butterworth filter similar to those shown in the figures below can be used.
Some systems have little power supply decoupling from the AC line but are also subject to line conducted
interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these
cases, it LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using
low frequency ferrite material can also be effective at preventing line conducted interference.
33 mH
OUTP
C2
L1
1 mF
33 mH
OUTN
C3
L2
1 mF
Figure 27. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
C2
L1
2.2 mF
15 mH
OUTN
C3
2.2 mF
L2
Figure 28. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 6 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 29. Typical Ferrite Chip Bead Filter (Chip Bead Example: )
10.2.2.4 Input Resistance
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the
largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or
cutoff frequency may change when changing gain steps.
24
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ZHCSDW8C –APRIL 2015–REVISED DECEMBER 2017
Typical Applications (continued)
Z
f
C
i
Z
i
IN
Input
Signal
The -3-dB frequency can be calculated using Equation 2. Use the Zi values given in Table 1.
1
f =
2p Zi Ci
(2)
10.2.2.5 Input Capacitor, Ci
In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a high-
pass filter with the corner frequency determined in Equation 3.
-3 dB
1
2p Zi Ci
fc
=
f
c
(3)
The value of Ci is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where Zi is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 3 is
reconfigured as Equation 4.
1
Ci =
2p Zi fc
(4)
In this example, Ci is 0.13 µF; so, one would likely choose a value of 0.15 μF as this value is commonly used. If
the gain is known and is constant, use Zi from Table 1 to calculate Ci. A further consideration for this capacitor is
the leakage path from the input source through the input network (Ci) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.
10.2.2.6 BSN and BSP Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 0.22-μF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 0.22-μF capacitor must be
connected from OUTPx to BSPx, and one 0.22-μF capacitor must be connected from OUTNx to BSNx. (See the
application circuit diagram in Figure 25.)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
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Typical Applications (continued)
10.2.2.7 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3144D2 with a differential source, connect the positive lead of the audio source to the INP input and
the negative lead from the audio source to the INN input. To use the TPA3144D2 with a single-ended source, ac
ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply
the audio source to either input. In a single-ended input application, the unused input should be ac grounded at
the audio source instead of at the device input for best noise performance. For good transient performance, the
impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input dc blocking capacitors to become completely charged during the 14 ms power-up time. If the input
capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching
which can result in pop if the input components are not well matched.
10.2.2.8 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
26
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Typical Applications (continued)
10.2.3 Application Performance Curves
10.2.3.1 EN55013 Radiated Emissions Results
TPA3144D2 EVM, PVCC = 12 V, 8-Ω load, up to 1 meter speaker cable, Spread Spectrum enabled, PO = 1.25 W
60
50
40
30
60
50
40
30
20
10
0
20
10
0
Limit
Limit
Peaks
Peaks
-10
-10
0.03
0.1
Frequency (GHz)
1
0.03
0.1
Frequency (GHz)
1
CISPR Class B 3m 30-1000MHz Scan#7- TPA3144D2 EVM with
8R Load, Different ferrite choke, Murata 601FB+1nF, 1-meter
cable, Battery supply, SS-TRI, BD, 1.25W, Spkr Wire Config2
CISPR Class B 3m 30-1000MHz Scan#7- TPA3144D2 EVM with
8R Load, Different ferrite choke, Murata 601FB+1nF, 1-meter
cable, Battery supply, SS-TRI, BD, 1.25W, Spkr Wire Config2
Figure 30. Radiated Emission - Horizontal
Figure 31. Radiated Emission - Vertical
Table 6. Radiated Emission - Horizontal
Table 7. Radiated Emission - Vertical
TURN
TABLE
DEGREES
TURN
TABLE
DEGREES
FREQUENCY
MHz
LIMIT
dBµV/m
PEAKS
dBµV/m
Q-PEAK MARGIN
TOWER
cm
FREQUENCY
MHz
LIMIT
dBµV/m
PEAKS
dBµV/m
Q-PEAK MARGIN
TOWER
cm
dBµV/m
dB
dBµV/m
dB
166.246
237.372
40.457
47.457
21.781
29.330
21.975
29.186
–18.482
–18.271
44.9
100
100
56.841
241.9
40.457
47.457
26.213
19.429
27.058
20.430
–13.399
–27.027
54
100
100
326.9
–0.1
space
10.2.3.2 EN55022 Conducted Emissions Results
TV (40 inch) from the major TV manufacturer, TPA3144D2 EVM, PVCC = 12 V, 8-Ω speakers, Spread Spectrum enabled, PO
= 1.25 W
80
70
60
80
70
60
50
40
30
20
10
Quasi Peak Limit
Average Limit
Peak Readings
Quasi Peak Limit
Average Limit
Peak Readings
50
40
30
20
10
0.15
1
10
30
0.15
1
10
30
Frequency (MHz)
Frequency (MHz)
CISPR Class B 0.150-30MHz Idle Mode. SS0, Triangular, BD,
1.25 Watt
CISPR Class B 0.150-30MHz Idle Mode. SS0, Triangular, BD,
1.25 Watt
Figure 32. Conducted Emission - Line
Figure 33. Conducted Emission - Neutral
Table 8. Conducted Emission - Line
Table 9. Conducted Emission - Neutral
QP
LIMIT
dBµV
AVE
LIMIT
dBµV
AVE
AVE
QP
QP
QP
LIMIT
dBµV
AVE
LIMIT
dBµV
AVE
AVE
QP
QP
FREQUENCY
MHz
FREQUENCY
MHz
READINGS MARGIN READINGS MARGIN
READINGS MARGIN READINGS MARGIN
dBµV
33.774
28.872
21.341
22.678
22.622
20.952
dB
dBµV
45.956
39.164
29.585
31.471
31.082
29.849
dB
dBµV
34.022
29.574
22.652
22.699
23.264
28.006
dB
dBµV
45.398
40.485
32.52
dB
0.156
0.552
0.806
0.95
65.83
56
55.83
46
–22.056
–17.128
–24.659
–23.322
–23.378
–25.048
–19.873
–16.836
–26.415
–24.529
–24.918
–26.151
0.158
0.554
0.735
0.918
1.402
7.806
65.785
56
55.785
46
–21.763
–16.426
–23.348
–23.301
–22.736
–21.994
–20.387
–15.515
–23.48
56
46
56
46
56
46
56
46
31.849
32.173
35.214
–24.151
–23.827
–24.786
1.485
1.976
56
46
56
46
56
46
60
50
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11 Power Supply Recommendations
11.1 Power Supply Decoupling, CS
The TPA3144D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. Optimum decoupling is
achieved by using a network of capacitors of different types that target specific types of noise on the power
supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper
trace inductances as well as lead frame capacitance, a good quality low equivalent-series-resistance (ESR)
ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be placed as close to
the device PVCC pins and system ground (either GND pins or thermal pad) as possible. For mid-frequency noise
due to filter resonances or PWM switching transients as well as digital hash on the line, another good quality
capacitor typically 0.1 μF to 1 µF placed as close as possible to the device PVCC leads works best. For filtering
lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 μF or greater placed near the audio
power amplifier is recommended. The 220-μF capacitor also serves as a local storage capacitor for supplying
current during large signal transients on the amplifier outputs. The PVCC pins provide the power to the output
transistors, so a 220-µF or larger capacitor should be placed on each PVCC pin. A 10-µF capacitor on the AVCC
pin is adequate. Also, a small decoupling resistor between AVCC and PVCC can be used to keep high frequency
class-D noise from entering the linear input amplifiers.
28
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12 Layout
12.1 Layout Guidelines
The TPA3144D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the printed
circuit board. The following suggestions will help to meet EMC requirements.
•
Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC pins as possible. Large (220 µF or greater) bulk power supply decoupling capacitors should be
placed near the TPA3144D2 on the PVCCL and PVCCR supplies. Local, high-frequency bypass capacitors
should be placed as close to the PVCC pins as possible. These caps can be connected to the thermal pad
directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor
between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1μF and 1μF also of good
quality to the PVCC connections at each end of the chip.
•
•
Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
Grounding—The AVCC (pin 14) decoupling capacitor should be connected to ground (GND). The PVCC
decoupling capacitors should connect to GND. Analog ground and power ground should be connected at the
thermal pad, which should be used as a central ground connection or star ground for the TPA3144D2.
•
•
Output filter—The ferrite EMI filter (Figure 29) should be placed as close to the output pins as possible for the
best EMI performance. The LC filter (Figure 27 and Figure 28) should be placed close to the outputs. The
capacitors used in both the ferrite and LC filters should be grounded to power ground.
Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35 mm. Seven rows
of solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application
Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB
footprints, see figures at the end of this data sheet.
For an example layout, see the TPA3144D2 Evaluation Module (TPA3144D2 EVM) User Manual. Both the EVM
user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com.
Copyright © 2015–2017, Texas Instruments Incorporated
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www.ti.com.cn
12.2 Layout Example
100mF
100nF
FB
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
1nF
1nF
1nF
0.22mF
FB
FB
0.22mF
0.22mF
21
20
19
18
17
10
1nF
1nF
1mF
11
12
0.22mF
13
14
16
15
1nF
FB
1mF
100nF
100mF
Top Layer Ground and Thermal Pad
Pad to Top Layer Ground Pour
Via to Bottom Ground Plane
Top Layer Signal Traces
Figure 34. BTL Layout Example
30
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ZHCSDW8C –APRIL 2015–REVISED DECEMBER 2017
13 器件和文档支持
13.1 器件支持
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.2 文档支持
13.2.1 相关文档
《PowerPAD™ 耐热增强型封装应用报告》（文献编号：SLMA002）
13.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.4 商标
SpeakerGuard, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
32
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPA3144D2PWP
TPA3144D2PWPR
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
28
28
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
TPA3144D2
TPA3144D2
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3144D2PWPR
HTSSOP PWP
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 28
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TPA3144D2PWPR
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
PWP HTSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPA3144D2PWP
28
50
530
10.2
3600
3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW
PWP 28
4.4 x 9.7, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/B
www.ti.com
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