TPA3250D2DDW [TI]
70W 立体声、140W 单声道、12 至 38V 电源电压、模拟输入 D 类音频放大器，焊盘朝下 | DDW | 44 | 0 to 70;
| 型号： | TPA3250D2DDW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 70W 立体声、140W 单声道、12 至 38V 电源电压、模拟输入 D 类音频放大器，焊盘朝下 | DDW | 44 | 0 to 70 放大器 音频放大器 |
| 文件： | 总42页 (文件大小：1411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPA3250
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
TPA3250 70W 立体声、130W 峰值 PurePath™ 超高清 D 类放大器（焊盘
朝下）
1 特性
•
采用推荐的系统设计时，符合电磁干扰 (EMI) 标准
1
•
•
差分模拟输入
2 应用
总谐波失真+噪声 (THD+N) 为 10% 时的总输出功
率
•
•
•
•
高端条形音箱
微型 Combo 系统
蓝光光盘™/DVD 接收器
有源扬声器
–
70W（连续功率）/8Ω，桥接负载 (BTL) 立体声
配置（32V 时）
–
130W（峰值功率）/4Ω，BTL 立体声配置
（32V 时）
3 说明
•
•
总谐波失真+噪声 (THD+N) 为 1% 时的总输出功率
TPA3250 器件是一款高性能 D 类功率放大器，具有 D
类效率并且能够提供真正的高端音质。该器件 特有 高
级集成反馈设计和专有高速栅极驱动器错误校正功能
（PurePath™ 超高清）。该技术可使器件在整个音频
频带内保持超低失真，同时展现完美音质。该器件最多
可驱动 2 个 130W（峰值功率）/4Ω 负载和 2 个 70W
（连续功率）/8Ω 负载，并且 特有 一个 2 VRMS 模拟
输入接口，支持与高性能 DAC（例如 TI 的
–
60W（连续功率）/8Ω，桥接负载 (BTL) 立体声
配置（32V 时）
–
105W（峰值功率）/4Ω，BTL 立体声配置
（32V 时）
采用高级集成反馈设计，具有高速栅极驱动器错误
校正功能
（PurePath™超清）
–
–
–
高达 100kHz 的单宽带，用于高清 (HD) 源的高
频成分
PCM5242）无缝连接。除了出色的音频性能
超低 THD+N：1W/4Ω 时为 0.005%；削波时
<0.01%
外，TPA3250 还兼具高功率效率和超低功率级空闲损
耗（低于 1W）两大优点。这可以通过 60mΩ
电源抑制比 (PSRR) 为 60dB（BTL，无输入信
号）
MOSFET 以及优化的栅极驱动器方案来实现。该方案
相对于传统的分立实现方案可显著降低空闲损耗。
–
–
（A 加权）输出噪声 < 60µV
（A 加权）信噪比 (SNR) > 110dB
器件信息(1)
•
多种配置可供选择：
立体声、单声道、2.1 和 4xSE
器件型号
TPA3250
封装
封装尺寸（标称值）
–
HTSSOP (44)
6.10mm x 14.00mm
•
•
•
•
启动和停止时无喀哒声和噼啪声
92% 高效 D 类操作 (8Ω)
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
12V 至 36V 宽电源电压工作范围
具有错误报告功能的自保护设计（包括欠压、过
压、削波和短路保护）
简化电路原理图
总谐波失真
10
TPA3250
8W
LC
RIGHT
Filter
Audio
Source
And Control
1
0.1
LEFT
LC
Filter
/CLIP_OTW
/RESET
/FAULT
12V
M1:M2
Operation Mode Select
Switching Frequency Select
Master/Slave Synchronization
Power Supply
36V
FREQ_ADJ
OSC_IO
0.01
110VAC->240VAC
T A = 25èC
0.001
10m
100m
1
10
100
Po - Output Power - W
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASE99
TPA3250
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
目录
9.2 Functional Block Diagrams ..................................... 15
9.3 Feature Description................................................. 17
9.4 Device Functional Modes........................................ 17
10 Application and Implementation........................ 21
10.1 Application Information.......................................... 21
10.2 Typical Applications .............................................. 21
11 Power Supply Recommendations ..................... 28
11.1 Power Supplies ..................................................... 28
11.2 Powering Up.......................................................... 28
11.3 Powering Down..................................................... 29
11.4 Thermal Design..................................................... 30
12 Layout................................................................... 33
12.1 Layout Guidelines ................................................. 33
12.2 Layout Examples................................................... 34
13 器件和文档支持 ..................................................... 37
13.1 文档支持................................................................ 37
13.2 社区资源................................................................ 37
13.3 商标....................................................................... 37
13.4 静电放电警告......................................................... 37
13.5 Glossary................................................................ 37
14 机械、封装和可订购信息....................................... 37
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Audio Characteristics (BTL) ...................................... 8
7.7 Audio Characteristics (SE) ....................................... 9
7.8 Audio Characteristics (PBTL) ................................... 9
7.9 Typical Characteristics, BTL Configuration............. 10
7.10 Typical Characteristics, SE Configuration............. 12
7.11 Typical Characteristics, PBTL Configuration ........ 13
Parameter Measurement Information ................ 14
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
8
9
4 修订历史记录
Changes from Original (December 2015) to Revision A
Page
•
已将数据表器件编号由“TPS3250D2”改为“TPA3250” ............................................................................................................. 1
2
Copyright © 2015–2016, Texas Instruments Incorporated
TPA3250
www.ti.com.cn
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
5 Device Comparison Table
DEVICE NAME
TPA3251
DESCRIPTION
175-W Stereo Class-D PurePath™ Ultra-HD Analog Input Audio Power Amplifier
50W Filter-Free Class-D Stereo Amplifier Family with AM Avoidance
30W Filter-Free Class-D Stereo Amplifier Family with AM Avoidance
TPA3116D2
TPA3118D2
6 Pin Configuration and Functions
The TPA3250 is available in a thermally enhanced TSSOP package.
The package type contains a PowerPad™ that is located on the bottom side of the device for thermal connection
to the PCB.
DDV Package
HTSSOP 44-Pin
(Top View)
BST_D
BST_C
GND
GVDD_CD
CLIP_OTW
VBG
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
3
GND
FAULT
4
OUT_D
OUT_D
PVDD_CD
PVDD_CD
PVDD_CD
OUT_C
GND
RESET
INPUT_D
INPUT_C
C_START
AVDD
5
6
7
8
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
Thermal
Pad
GND
DVDD
OUT_B
PVDD_AB
PVDD_AB
PVDD_AB
OUT_A
OUT_A
GND
OSC_IOP
OSC_IOM
FREQ_ADJ
OC_ADJ
INPUT_A
INPUT_B
M2
GND
M1
BST_B
BST_A
VDD
GVDD_AB
Copyright © 2015–2016, Texas Instruments Incorporated
3
TPA3250
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
9
AVDD
P
P
P
P
P
O
O
P
O
O
P
Internal voltage regulator, analog section
BST_A
BST_B
BST_C
BST_D
23
24
43
44
2
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
Clipping warning and Over-temperature warning; open drain; active low
Startup ramp, requires a charging capacitor to GND
CLIP_OTW
C_START
DVDD
8
12
4
Internal voltage regulator, digital section
FAULT
Shutdown signal, open drain; active low
FREQ_ADJ
15
Oscillator frequency programming pin
10, 11, 25, 26,
33, 34, 41, 42
GND
Ground
GVDD_AB
GVDD_CD
INPUT_A
INPUT_B
INPUT_C
INPUT_D
M1
22
P
P
I
Gate-drive voltage supply; AB-side, requires 0.1 µF capacitor to GND
Gate-drive voltage supply; CD-side, requires 0.1 µF capacitor to GND
Input signal for half bridge A
1
17
18
I
Input signal for half bridge B
7
I
Input signal for half bridge C
6
I
Input signal for half bridge D
20
I
Mode selection 1 (LSB)
M2
19
I
Mode selection 2 (MSB)
OC_ADJ
OSC_IOM
OSC_IOP
OUT_A
16
I/O
I/O
O
O
O
O
O
P
P
I
Over-Current threshold programming pin
Oscillator synchronization interface
Oscillator synchronization interface
Output, half bridge A
14
13
27, 28
OUT_B
32
Output, half bridge B
OUT_C
35
Output, half bridge C
OUT_D
39, 40
Output, half bridge D
PVDD_AB
PVDD_CD
RESET
29, 30, 31
PVDD supply for half-bridge A and B
PVDD supply for half-bridge C and D
Device reset Input; active low
36, 37, 38
5
21
3
VDD
P
P
P
Power supply for internal voltage regulator requires a 10-µF capacitor with a 0.1-µF capacitor to GND for decoupling.
Internal voltage reference requires a 0.1-µF capacitor to GND for decoupling.
VBG
PowerPAD™
Ground, connect to PCB copper pour. Placed on bottom side of device.
Table 1. Mode Selection Pins
MODE PINS
OUTPUT
CONFIGURATION
INPUT MODE
DESCRIPTION
M2
0
M1
0
2N + 1
2N/1N + 1
2N + 1
2 × BTL
1 x BTL + 2 x SE
1 x PBTL
Stereo BTL output configuration
0
1
2.1 BTL + SE mode
1
0
Parallelled BTL configuration. Connect INPUT_C and INPUT_D to GND.
Single ended output configuration
1
1
1N +1
4 x SE
4
Copyright © 2015–2016, Texas Instruments Incorporated
TPA3250
www.ti.com.cn
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
-0.3
MAX
50
UNIT
V
BST_X to GVDD_X(2)
VDD to GND
GVDD_X to GND(2)
13.2
13.2
50
V
V
Supply voltage
PVDD_X to GND(2)
V
DVDD to GND
4.2
8.5
4.2
50
V
AVDD to GND
V
VBG to GND
V
OUT_X to GND(2)
BST_X to GND(2)
–0.3
–0.3
–0.3
–0.3
–0.3
V
62.5
4.2
4.2
7
V
OC_ADJ, M1, M2, OSC_IOP, OSC_IOM, FREQ_ADJ, C_START, to GND
RESET, FAULT, CLIP_OTW, CLIP to GND
INPUT_X to GND
V
Interface pins
V
V
Continuous sink current, RESET, FAULT, CLIP_OTW, CLIP, RESET to
GND
9
mA
TJ
Operating junction temperature range
Storage temperature range
0
150
150
°C
°C
Tstg
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins
±2000
V
(1)
VESD
Electrostatic discharge
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2015–2016, Texas Instruments Incorporated
5
TPA3250
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
PVDD_x
GVDD_x
Half-bridge supply
DC supply voltage
DC supply voltage
DC supply voltage
12
32
38
13.2
13.2
V
Supply for logic regulators and gate-drive
circuitry
10.8
12
V
V
VDD
Digital regulator supply voltage
10.8
2.7
1.5
1.6
5
12
4
RL(BTL)
RL(SE)
Output filter inductance within
recommended value range
Load impedance
3
Ω
RL(PBTL)
LOUT(BTL)
LOUT(SE)
LOUT(PBTL)
2
Output filter inductance
Minimum output inductance at IOC
5
μH
kHz
kΩ
5
Nominal
430
475
575
29.7
19.8
9.9
450
500
600
30
470
525
PWM frame rate selectable for AM
interference avoidance; 1% Resistor
tolerance
FPWM
AM1
AM2
625
Nominal; Master mode
AM1; Master mode
AM2; Master mode
30.3
20.2
10.1
R(FREQ_ADJ)
PWM frame rate programming resistor
20
10
CPVDD
ROC
PVDD close decoupling capacitors
Over-current programming resistor
1.0
μF
kΩ
kΩ
Resistor tolerance = 5%
Resistor tolerance = 5%
22
47
30
64
ROC(LATCHED) Over-current programming resistor
Voltage on FREQ_ADJ pin for slave
mode operation
V(FREQ_ADJ)
Slave mode
3.3
V
TJ
Junction temperature
0
125
°C
7.4 Thermal Information
TPA3250
THERMAL METRIC(1)
DDV 44-PINS HTSSOP
UNIT
JEDEC STANDARD 4 LAYER PCB
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
26.0
10.2
6.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
6.5
RθJC(bot)
1.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6
Copyright © 2015–2016, Texas Instruments Incorporated
TPA3250
www.ti.com.cn
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
7.5 Electrical Characteristics
PVDD_X = 32 V, GVDD_X = 12 V, VDD = 12 V, TA (Ambient temperature) = 25°C, fS = 450 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
DVDD
VDD = 12 V
3
3.3
7.8
3.6
V
V
node
Voltage regulator, only used as reference
node
AVDD
VDD = 12 V
Operating, 50% duty cycle
Idle, reset mode
40
13
25
3
IVDD
VDD supply current
mA
mA
50% duty cycle
IGVDD_X
Gate-supply current per full-bridge
PVDD idle current per full bridge
Reset mode
50% duty cycle with 10µH Output Filter Inductors
Reset mode, No switching
12.5
1
mA
mA
IPVDD_X
ANALOG INPUTS
RIN
Input resistance
24
20
kΩ
V
VIN
Maximum input voltage swing
Maximum input current
Inverting voltage Gain
7
1
IIN
mA
dB
G
VOUT/VIN
OSCILLATOR
Nominal, Master Mode
AM1, Master Mode
2.58
2.85
3.45
1.86
2.7
3
2.82
3.15
3.75
fOSC(IO+)
FPWM × 6
MHz
AM2, Master Mode
3.6
VIH
VIL
High level input voltage
Low level input voltage
V
V
1.45
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
60
60
100
100
mΩ
mΩ
TJ = 25°C, Includes metallization resistance,
GVDD = 12 V
RDS(on)
Drain-to-source resistance, high side (HS)
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
VDD
Vuvp,VDD,GVDD
9.5
V
(1)
Vuvp,VDD, GVDD,hyst
OTW
0.6
V
Overtemperature warning, CLIP_OTW(1)
115
145
125
135
165
°C
Temperature drop needed below OTW
temperature for CLIP_OTW to be inactive
after OTW event.
(1)
OTWhyst
25
°C
OTE(1)
Overtemperature error
OTE-OTW differential
155
30
°C
°C
OTE-OTW(differential)
(1)
A reset needs to occur for FAULT to be
released following an OTE event
(1)
OTEhyst
25
2.3
14
°C
ms
A
OLPC
IOC
Overload protection counter
Overcurrent limit protection
fPWM = 450 kHz
Resistor – programmable, nominal peak current in
1Ω load, ROCP = 22 kΩ
Resistor – programmable, peak current in 1Ω load,
ROCP = 47kΩ
IOC(LATCHED)
IDCspkr
Overcurrent limit protection
14
1.5
150
A
A
DC Speaker Protection Current Threshold
Overcurrent response time
BTL current imbalance threshold
Time from switching transition to flip-state induced
by overcurrent.
IOCT
ns
Connected when RESET is active to provide
bootstrap charge. Not used in SE mode.
IPD
Output pulldown current of each half
3
mA
(1) Specified by design.
Copyright © 2015–2016, Texas Instruments Incorporated
7
TPA3250
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
Electrical Characteristics (continued)
PVDD_X = 32 V, GVDD_X = 12 V, VDD = 12 V, TA (Ambient temperature) = 25°C, fS = 450 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC DIGITAL SPECIFICATIONS
VIH
VIL
Ilkg
High level input voltage
Low level input voltage
Input leakage current
1.9
V
V
M1, M2, OSC_IOP, OSC_IOM, RESET
0.8
100
μA
OTW/SHUTDOWN (FAULT)
Internal pullup resistance, CLIP_OTW to
RINT_PU
20
3
26
32
kΩ
DVDD, FAULT to DVDD
High level output voltage
Low level output voltage
CLIP_OTW, FAULT
VOH
Internal pullup resistor
IO = 4 mA
3.3
200
30
3.6
V
VOL
500
mV
Device fanout
No external pullup
devices
7.6 Audio Characteristics (BTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 32 V,
GVDD_X = 12 V, RL = 8 Ω, fS = 450 kHz, ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00,
AES17 + AUX-0025 measurement filters,unless otherwise noted.
PARAMETER
TEST CONDITIONS
RL = 8 Ω, 10% THD+N
MIN
TYP MAX UNIT
70
RL = 4 Ω, 10% THD+N, 3 seconds Peak
130
Power(1)
RL = 4 Ω, 10% THD+N, Single Channel, 300
W
130
seconds duration(1)
PO
Power output per channel
RL = 8 Ω, 1% THD+N
RL = 4 Ω, 1% THD+N
60
40
RL = 4 Ω, 1% THD+N, 6 seconds Peak
105
105
Power(1)
RL = 4 Ω, 1% THD+N, Single Channe(1)
l
THD+N Total harmonic distortion + noise
1 W
0.005%
A-weighted, AES17 filter, Input Capacitor
Grounded
Vn
Output integrated noise
60
μV
|VOS
|
Output offset voltage
Signal-to-noise ratio(2)
Inputs AC coupled to GND
20
112
112
0.6
60
mV
dB
dB
W
SNR
DNR
Pidle
Dynamic range
Power dissipation due to Idle losses (IPVDD_X
)
PO = 0, 4 channels switching(3)
(1) Peak Power rating using TPA3250 EVM
(2) SNR is calculated relative to 1% THD+N output level.
(3) Actual system idle losses also are affected by core losses of output inductors.
8
Copyright © 2015–2016, Texas Instruments Incorporated
TPA3250
www.ti.com.cn
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
7.7 Audio Characteristics (SE)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 32 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 15 μH, CDEM = 1 µF, MODE = 11,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
TEST CONDITIONS
RL = 4 Ω, 10% THD+N
MIN
TYP MAX UNIT
33
RL = 3 Ω, 10% THD+N
RL = 4 Ω, 1% THD+N
RL = 3 Ω, 1% THD+N
1 W
42
PO
Power output per channel
W
27
34
THD+N Total harmonic distortion + noise
0.015%
A-weighted, AES17 filter, Input Capacitor
Grounded
Vn
Output integrated noise
111
μV
SNR
DNR
Pidle
Signal to noise ratio(1)
A-weighted
100
100
0.5
dB
dB
W
Dynamic range
A-weighted
PO = 0, 4 channels switching(2)
Power dissipation due to idle losses (IPVDD_X)
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
7.8 Audio Characteristics (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 32 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, MODE = 10,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
TEST CONDITIONS
RL = 8 Ω, 10% THD+N
MIN
TYP MAX UNIT
75
RL = 4 Ω, 10% THD+N
RL = 3 Ω, 10% THD+N
RL = 8 Ω, 1% THD+N
RL = 4 Ω, 1% THD+N
RL = 3 Ω, 1% THD+N
1 W
145
189
W
PO
Power output per channel
60
115
150
THD+N Total harmonic distortion + noise
0.015%
A-weighted, AES17 filter, Input Capacitor
Grounded
Vn
Output integrated noise
62
μV
SNR
DNR
Pidle
Signal to noise ratio(1)
A-weighted
112
107
0.6
dB
dB
W
Dynamic range
A-weighted
PO = 0, 4 channels switching(2)
Power dissipation due to idle losses (IPVDD_X)
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
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7.9 Typical Characteristics, BTL Configuration
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 32 V, GVDD_X = 12 V, RL = 8 Ω, fS = 450 kHz, ROC = 22 kΩ,
TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise
noted.
10
5
10
1
T A = 25èC
1W
T A = 25èC
1W
10W
40W
10W
40W
2
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.005
0.01
0.001
0.002
0.001
0.0005
0.0003
20
100
1k
10k
20k
20
100
1k
10k
40k
f - Frequency - Hz
f - Frequency - Hz
D001
D002
RL = 8 Ω
P = 1W, 10W, 40W
TA = 25°C
RL = 8 Ω
P = 1W, 10W, 40W
TA = 25°C
AUX-0025 filter, 80 kHz analyzer BW
Figure 1. Total Harmonic Distortion+Noise vs Frequency
Figure 2. Total Harmonic Distortion+Noise vs Frequency
125
4W
8W
10
8W
100
1
0.1
75
50
0.01
25
THD+N = 10%
TA = 25èC
T A = 25èC
0
0.001
10
15
20
25
30
35
40
10m
100m
1
10
100
PVDD - Supply Voltage - V
Po - Output Power - W
D004
D0030
RL = 4 Ω, 8 Ω
THD+N = 10%
TA = 25°C
RL = 8 Ω
TA = 25°C
Figure 4. Output Power vs Supply Voltage
Figure 3. Total Harmonic Distortion + Noise vs Output
Power
120
100
10
1
4W
8W
4W
8W
100
80
60
40
20
THD+N = 1%
TA = 25èC
TA = 25èC
0
10
15
20
25
30
35
40
10m
100m
1
10
100
PVDD - Supply Voltage - V
2 Channel Output Power - W
D005
D006
RL = 4 Ω, 8 Ω
THD+N = 1%
TA = 25°C
RL = 4 Ω, 8 Ω
THD+N = 10%
TA = 25°C
Figure 5. Output Power vs Supply Voltage
Figure 6. System Efficiency vs Output Power
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Typical Characteristics, BTL Configuration (continued)
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 32 V, GVDD_X = 12 V, RL = 8 Ω, fS = 450 kHz, ROC = 22 kΩ,
TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise
noted.
0
30
T A = 25èC
8W
4W
8W
V ref = 22.627 V
FFT size = 16384
-20
-40
25
20
15
10
5
-60
-80
-100
-120
-140
-160
TA = 25èC
0
0
5k
10k
15k
20k
25k
30k
35k
40k
45k 48k
0
50
100
150
200
f - Frequency - Hz
2 Channel Output Power - W
D008
D007
8 Ω, VREF = 25.46 V (1% Output power)
FFT = 16384
TA = 25°C
RL = 4 Ω, 8 Ω
THD+N = 10%
TA = 25°C
AUX-0025 filter, 80 kHz analyzer BW
Figure 8. Noise Amplitude vs Frequency
Figure 7. System Power Loss vs Output Power
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7.10 Typical Characteristics, SE Configuration
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 32 V, GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ,
TA = 25°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, MODE = 11, AES17 + AUX-0025 measurement filters, unless
otherwise noted.
10
1
10
1
TA = 25èC
1W
5W
15W
3W
4W
0.1
0.1
0.01
0.01
TA = 25èC
0.001
0.001
20
100
1k
10k 20k
10m
RL = 3Ω, 4Ω
100m
1
10
100
f - Frequency - Hz
D010
Po - Output Power - W
D009
RL = 4Ω
P = 1W, 10W, 25W
TA = 25°C
TA = 25°C
Figure 10. Total Harmonic Distortion+Noise vs Frequency
Figure 9. Total Harmonic Distortion+Noise vs Output Power
70
10
3W
4W
TA = 25èC
1W
5W
60
15W
50
40
30
20
1
0.1
0.01
10
THD+N = 10%
TA = 25èC
0
10
15
20
25
30
35
40
PVDD - Supply Voltage - V
0.001
D012
20
100
1k
10k
40k
RL = 3Ω, 4Ω
THD+N = 10%
TA = 25°C
f - Frequency - Hz
D011
RL = 4Ω
P = 1W, 10W, 25W
TA = 25°C
AUX-0025 filter, 80 kHz analyzer BW
Figure 12. Output Power vs Supply Voltage
Figure 11. Total Harmonic Distortion+Noise vs Frequency
60
3W
4W
50
40
30
20
10
0
THD+N = 1%
TA = 25èC
10
15
20
25
30
35
40
PVDD - Supply Voltage - V
D013
RL = 3Ω, 4Ω
THD+N = 1%
TA = 25°C
Figure 13. Output Power vs Supply Voltage
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7.11 Typical Characteristics, PBTL Configuration
All Measurements taken at audio frequency = 1kHz, PVDD_X = 32 V, GVDD_X = 12 V, RL = 4Ω, fS = 450 kHz, ROC = 22 kΩ,
TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, MODE = 10, AES17 + AUX-0025 measurement filters, unless otherwise
noted.
10
5
10
1
TA = 25èC
1W
20W
75W
4W
8W
2
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.005
0.01
0.002
0.001
0.0005
0.0003
TA = 25èC
0.001
10m
100m
1
10
100
20
100
1k
10k 20k
Po - Output Power - W
f - Frequency - Hz
D014
D015
RL = 4Ω, 8Ω
TA = 25°C
RL = 4Ω
P = 1W, 20W, 75W
TA = 25°C
Figure 14. Total Harmonic Distortion+Noise vs Output
Power
Figure 15. Total Harmonic Distortion+Noise vs Frequency
275
10
3W
250
TA = 25èC
1W
4W
20W
75W
225
200
175
150
125
100
75
1
0.1
0.01
50
THD+N = 10%
TA = 25èC
25
0
0.001
10
15
20
25
30
35
40
20
100
1k
10k
40k
PVDD - Supply Voltage - V
D017
f - Frequency - Hz
D016
RL = 3Ω, 4Ω
THD+N = 10%
TA = 25°C
RL = 4Ω
P = 1W, 20W, 75W
TA = 25°C
AUX-0025 filter, 80 kHz analyzer BW
Figure 17. Output Power vs Supply Voltage
Figure 16. Total Harmonic Distortion+Noise vs Frequency
225
3W
4W
200
175
150
125
100
75
50
25
THD+N = 1%
TA = 25èC
0
10
15
20
25
30
35
40
PVDD - Supply Voltage - V
D018
RL = 3Ω, 4Ω
THD+N = 1%
TA = 25°C
Figure 18. Output Power vs Supply Voltage
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Recommended Operating Conditions,
Typical Characteristics, BTL Configuration, Typical Characteristics, SE Configuration and Typical Characteristics,
PBTL Configuration sections.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to
out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to
use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can
be used to reduce the out of band noise remaining on the amplifier outputs.
9 Detailed Description
9.1 Overview
To facilitate system design, the TPA3250 needs only a 12-V supply in addition to the (typical) 32-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry, AVDD and DVDD. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate
drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
The audio signal path including gate drive and output stage is designed as identical, independent half-bridges.
For this reason, each half-bridge has separate bootstrap pins (BST_X). Power-stage supply pins (PVDD_X) and
gate drive supply pins (GVDD_X) are separate for each full bridge. Although supplied from the same 12-V
source, separating to GVDD_AB, GVDD_CD, and VDD on the printed-circuit board (PCB) by RC filters (see
application diagram for details) is recommended. These RC filters provide the recommended high-frequency
isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as
possible. In general, the physical loop with the power supply pins, decoupling capacitors and GND return path to
the device pins must be kept as short as possible and with as little area as possible to minimize induction (see
reference board documentation for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. It is recommended to use 33-
nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient
energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully
turned on during the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X node is
decoupled with 1-μF ceramic capacitor placed as close as possible to the supply pins. It is recommended to
follow the PCB layout of the TPA3250 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36-V power-
stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit, but it is recommended to release RESET after the power
supply is settled for minimum turn on audible artefacts. Moreover, the TPA3250 is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-
critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
14
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9.2 Functional Block Diagrams
/CLIP_OTW
VDD
VBG
VREG
AVDD
DVDD
GND
POWER-UP
RESET
/FAULT
UVP
M1
M2
TEMP
SENSE
GVDD_A
GVDD_B
GVDD_C
GND
GVDD_D
/RESET
DIFFOC
CB3C
STARTUP
CONTROL
C_START
OVER-LOAD
PROTECTION
CURRENT
SENSE
OC_ADJ
OSC_IOM
OSC_IOP
PVDD_X
OUT_X
GND
OSCILLATOR
PPSC
FREQ_ADJ
GVDD_AB
BST_A
PWM
ACTIVITY
DETECTOR
PVDD_AB
OUT_A
GND
-
PWM
RECEIVER
TIMING
CONTROL
CONTROL
GATE-DRIVE
GATE-DRIVE
GATE-DRIVE
GATE-DRIVE
INPUT_A
ANALOG
+
LOOP FILTER
GVDD_AB
BST_B
PVDD_AB
OUT_B
GND
-
PWM
RECEIVER
TIMING
CONTROL
INPUT_B
ANALOG
CONTROL
CONTROL
CONTROL
+
LOOP FILTER
GVDD_CD
BST_C
PVDD_CD
OUT_C
GND
-
PWM
RECEIVER
TIMING
CONTROL
INPUT_C
ANALOG
+
LOOP FILTER
GVDD_CD
BST_D
PVDD_CD
OUT_D
GND
-
PWM
RECEIVER
TIMING
CONTROL
INPUT_D
ANALOG
+
LOOP FILTER
FunctionalBlockDiagram.vsd
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Functional Block Diagrams (continued)
Capacitor for
External
Filtering
&
System
microcontroller or
Analog circuitry
Startup/Stop
BST_A
BST_B
OSC_IOP
OSC_IOM
Oscillator
Synchronization
Bootstrap
Capacitors
2nd Order
L-C Output
Filter for
each
OUT_A
OUT_B
Output
H-Bridge 1
INPUT_A
Input DC
Blocking
Caps
ANALOG_IN_A
ANALOG_IN_B
Input
H-Bridge 1
INPUT_B
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
Hardwire PWM
Frame Adjust
& Master/Slave
Mode
FREQ_ADJ
2nd Order
L-C Output
Filter for
each
OUT_C
OUT_D
INPUT_C
INPUT_D
Input DC
Blocking
Caps
ANALOG_IN_C
ANALOG_IN_D
Input
H-Bridge 2
Output
H-Bridge 2
H-Bridge
BST_C
BST_D
M1
M2
Hardwire
Mode
Control
Bootstrap
Capacitors
GVDD, VDD,
DVDD &
AVDD
Power Supply
Decoupling
Hardwire
PVDD
GND
PVDD
Power Supply
Decoupling
36V
Over-
Current
Limit
SYSTEM
Power
Supplies
GND
12V
GVDD (12V)/VDD (12V)
VAC
*NOTE1: Logic AND in or outside microcontroller
Figure 19. System Block Diagram
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9.3 Feature Description
9.3.1 Error Reporting
The FAULT, and CLIP_OTW, pins are active-low, open-drain outputs. The function is for protection-mode
signaling to a system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low. Also, CLIP_OTW goes low when
the device junction temperature exceeds 125°C (see Table 2).
Table 2. Error Reporting
FAULT
CLIP_OTW
DESCRIPTION
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) Junction
temperature higher than 125°C (overtemperature warning)
0
0
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 125°C
(overtemperature warning)
0
0
0
1
1
1
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature lower than 125°C
Junction temperature higher than 125°C (overtemperature warning)
Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)
Note that asserting either RESET low forces the FAULT signal high, independent of faults being present. TI
recommends monitoring the CLIP_OTW signal using the system microcontroller and responding to an
overtemperature warning signal by, that is, turning down the volume to prevent further heating of the device
resulting in device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and
CLIP_OTW outputs.
9.4 Device Functional Modes
9.4.1 Device Protection System
The TPA3250 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TPA3250 responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other
than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has
been removed, that is, the supply voltage has increased.
The device will function on errors, as shown in Table 3.
Table 3. Device Protection
BTL
MODE
PBTL
MODE
SE
MODE
LOCAL
ERROR IN
LOCAL
ERROR IN
LOCAL
ERROR IN
TURNS OFF
TURNS OFF
TURNS OFF
A
B
C
D
A
B
C
D
A
B
C
D
A+B
C+D
A+B
C+D
A+B+C+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching,
does not assert FAULT).
9.4.1.1 Overload and Short Circuit Current Protection
TPA3250 has fast reacting current sensors with a programmable trip threshold (OC threshold) on all high-side
and low-side FETs. To prevent output current to increase beyond the programmed threshold, TPA3250 has the
option of either limiting the output current for each switching cycle (Cycle By Cycle Current Control, CB3C) or to
perform an immediate shutdown of the output in case of excess output current (Latching Shutdown). CB3C
prevents premature shutdown due to high output current transients caused by high level music transients and a
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drop of real speaker’s load impedance, and allows the output current to be limited to a maximum programmed
level. If the maximum output current persists, i.e. the power stage being overloaded with too low load impedance,
the device will shut down the affected output channel and the affected output is put in a high-impedance (Hi- Z)
state until a RESET cycle is initiated. CB3C works individually for each half bridge output. If an over current
event is triggered, CB3C performs a state flip of the half bridge output that is cleared upon beginning of next
PWM frame.
PWM_X
RISING EDGE PWM
SETS CB3C LATCH
HS PWM
LS PWM
OC EVENT RESETS
CB3C LATCH
OC THRESHOLD
OUTPUT CURRENT
OCH
HS GATE-DRIVE
LS GATE-DRIVE
Figure 20. CB3C Timing Example
During CB3C an over load counter increments for each over current event and decrease for each non-over
current PWM cycle. This allows full amplitude transients into a low speaker impedance without a shutdown
protection action. In the event of a short circuit condition, the over current protection limits the output current by
the CB3C operation and eventually shut down the affected output if the overload counter reaches its maximum
value. If a latched OC operation is required such that the device shuts down the affected output immediately
upon first detected over current event, this protection mode should be selected. The over current threshold and
mode (CB3C or Latched OC) is programmed by the OC_ADJ resistor value. The OC_ADJ resistor needs to be
within its intentional value range for either CB3C operation or Latched OC operation.
I_OC
IOC_max
IOC_min
Not Defined
ROC_ADJ
Figure 21. OC Threshold versus OC_ADJ Resistor Value Example
OC_ADJ values outside specified value range for either CB3C or latched OC operation will result in minimum OC
threshold.
18
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Table 4. Device Protection
OC_ADJ Resistor Value
Protection Mode
CB3C
OC Threshold
16.3A
22kΩ
24kΩ
27kΩ
30kΩ
47kΩ
51kΩ
56kΩ
64kΩ
CB3C
15.1A
CB3C
13.5A
CB3C
12.3A
Latched OC
Latched OC
Latched OC
Latched OC
16.3A
15.1A
13.5A
12.3A
9.4.1.2 DC Speaker Protection
The output DC protection scheme protects a connected speaker from excess DC current caused by a speaker
wire accidentally shorted to chassis ground. Such a short circuit results in a DC voltage of PVDD/2 across the
speaker, which potentially can result in destructive current levels. The output DC protection detects any
unbalance of the output and input current of a BTL output, and in the event of the unbalance exceeding a
programmed threshold, the overload counter increments until its maximum value and the affected output channel
is shut down. DC Speaker Protection is disabled in PBTL and SE mode operation.
9.4.1.3 Pin-to-Pin Short Circuit Protection (PPSC)
The PPSC detection system protects the device from permanent damage in the case that a power output pin
(OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent
after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup that is, when VDD is supplied, consequently a short to either GND_X or PVDD_X after
system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on
the output, all half bridges are kept in a Hi-Z state until the short is removed; the device then continues the
startup sequence and starts switching. The detection is controlled globally by a two step sequence. The first step
ensures that there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from
OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC
filter. The typical duration is < 15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the
device will not react to changes applied to the RESET pin. If no shorts are present the PPSC detection passes,
and FAULT is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL
and PBTL output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC
detection system it is recommended not to insert a resistive load to GND_X or PVDD_X.
9.4.1.4 Overtemperature Protection OTW and OTE
TPA3250 has a two-level temperature-protection system that asserts an active-low warning signal (CLIP_OTW)
when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds
155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-
impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch,
RESET must be asserted. Thereafter, the device resumes normal operation.
9.4.1.5 Undervoltage Protection (UVP) and Power-on Reset (POR)
The UVP and POR circuits of the TPA3250 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and FAULT being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
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9.4.1.6 Fault Handling
If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and
will assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires
resetting the device by toggling RESET. Toggling RESET should never be allowed with excessive system
temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET
(RESET high) if the OTW signal is cleared (high). A channel fault results in shutdown of the PWM activity of the
affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults being
present. TI recommends monitoring the OTW signal using the system micro controller and responding to an over
temperature warning signal by, that is, turning down the volume to prevent further heating of the device resulting
in device shutdown (OTE).
Table 5. Error Reporting
Fault/Event
Description
Global or
Channel
Reporting
Method
Latched/Self
Clearing
Action needed
to Clear
Fault/Event
Output FETs
HI-Z
PVDD_X UVP
VDD UVP
Increase affected
supply voltage
Voltage Fault
Global
FAULT pin
Self Clearing
AVDD UVP
Allow DVDD to
rise
POR (DVDD UVP)
Power On Reset Global
FAULT pin
None
Self Clearing
Self Clearing
Self Clearing
HI-Z
Allow BST cap to
recharge (lowside HighSide off
ON, VDD 12V)
Channel (Half
Bridge)
BST_X UVP
Voltage Fault
Cool below OTW
threshold
OTW
OTE
Thermal Warning Global
OTW pin
Normal operation
Thermal
Global
FAULT pin
FAULT pin
Latched
Latched
Toggle RESET
Toggle RESET
HI-Z
HI-Z
Shutdown
OLP (CB3C>1.7ms) OC Shutdown
Channel
Channel
Latched OC
(47kΩ<ROC_ADJ<68 OC Shutdown
kΩ)
FAULT pin
None
Latched
Toggle RESET
HI-Z
CB3C
Reduce signal
level or remove
short
Flip state, cycle
by cycle at fs/3
(22kΩ<ROC_ADJ<30 OC Limiting
kΩ)
Channel
Global
Self Clearing
Self Clearing
No OSC_IO
activity in Slave
Mode
Resume OSC_IO
activity
Stuck at Fault(1)
None
HI-Z
(1) Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical Characteristics
table of this data sheet.
9.4.1.7 Device Reset
Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state after the ramp down
is complete. Output pull downs are active both in SE mode and BTL mode with RESET low.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs.
Asserting reset input low removes any fault information to be signaled on the FAULT output, that is, FAULT is
forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault.
To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of
FAULT.
20
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TPA3250
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
TPA3250 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1 mixed
1x BTL + 2x SE mode depending on output power conditions and system design.
10.2 Typical Applications
10.2.1 Stereo BTL Application
3R3
+12V
470uF
100nF
100nF
33nF
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
GVDD_AB
VDD
BST_A
BST_B
GND
10µH
10nF
33nF
M1
1nF
1nF
1µF
1µF
M2
GND
3w3
10µF
10µF
INPUT_A
INPUT_B
INPUT_A
INPUT_B
OC_ADJ
FREQ_ADJ
OSC_IOM
OSC_IOP
DVDD
OUT_A
OUT_A
PVDD_AB
PVDD_AB
PVDD_AB
OUT_B
GND
3R3
22k
10nF
1µF
10µH
30k
470uF
PVDD
GND
10
11
12
13
14
15
16
17
18
19
1µF
1µF
1µF
TPA3250
GND
GND
GND
OUT_C
PVDD_CD
PVDD_CD
PVDD_CD
OUT_D
OUT_D
GND
1µF
AVDD
10µH
10nF
C_START
INPUT_C
INPUT_D
/RESET
/FAULT
VBG
1µF 470uF
10nF
10µF
10µF
INPUT_C
INPUT_D
/RESET
/FAULT
1nF
1nF
1µF
1µF
3w3
26
25
24
23
3R3
100nF
20
21
22
10nF
GND
33nF
10µH
/CLIP_OTW
/CLIP_OTW
GVDD_CD
BST_C
BST_D
3R3
100nF
33nF
Figure 22. Typical Differential Input BTL Application
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www.ti.com.cn
Typical Applications (continued)
10.2.1.1 Design Requirements
For this design example, use the parameters in Table 6.
Table 6. Design Requirements, BTL Application
DESIGN PARAMETER
Low Power (Pull-up) Supply
Mid Power Supply 12 V
High Power Supply
EXAMPLE
3.3 V
12 V
12 - 32 V
M2 = L
Mode Selection
M1 = L
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ± 3.9V (peak, max)
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
Analog Inputs
Output Filters
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance
3-8 Ω
10.2.1.2 Detailed Design Procedures
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply nominally operating at a low rail adjusting to a higher supply rail.
The device is inverting the audio signal from input to output.
The DVDD and AVDD pins are not recommended to be used as a voltage sources for external circuitry.
10.2.1.2.1 Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 1μF that is placed on the power supply to each full-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 50 V is required for use with a 32V power
supply.
10.2.1.2.2 PVDD Capacitor Recommendation
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000 μF, 50 V supports most applications.
The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed
switching.
10.2.1.2.3 PCB Material Recommendation
FR-4 Glass Epoxy material with 2 oz. (70 μm) copper is recommended for use with the TPA3250. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
22
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10.2.1.2.4 Oscillator
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower values. These values should be chosen such that the nominal and the
lower value switching frequencies together results in the fewest cases of interference throughout the AM band.
The oscillator frequency can be selected by the value of the FREQ_ADJ resistor connected to GND in master
mode according to the description in the Recommended Operating Conditions table.
For slave mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to DVDD. This configures the
OSC_I/O pins as inputs to be slaved from an external differential clock. In a master/slave system inter channel
delay is automatically setup between the switching of the audio channels, which can be illustrated by no idle
channels switching at the same time. This will not influence the audio output, but only the switch timing to
minimize noise coupling between audio channels through the power supply to optimize audio performance and to
get better operating conditions for the power supply. The inter channel delay will be setup for a slave device
depending on the polarity of the OSC_I/O connection such that a slave mode 1 is selected by connecting the
master device OSC_I/O to the slave 1 device OSC_I/O with same polarity (+ to + and - to -), and slave mode 2 is
selected with the inverse polarity (+ to - and - to +).
10.2.2 Application Curves
Relevant performance plots for TPA3250 in BTL configuration are shown in Typical Characteristics, BTL
Configuration
Table 7. Relevant Performance Plots, BTL Configuration
PLOT TITLE
Total Harmonic Distortion+Noise vs Frequency
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Total Harmonic Distortion + Noise vs Output Power
Output Power vs Supply Voltage, 10% THD+N
Output Power vs Supply Voltage, 10% THD+N
System Efficiency vs Output Power
FIGURE NUMBER
Figure 1
Figure 2
Figure 3
Figure 4
Figure 6
Figure 6
System Power Loss vs Output Power
Figure 7
Output Power vs Case Temperature
Noise Amplitude vs Frequency
Figure 8
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10.2.3 Typical Application, Single Ended (1N) SE
TPA3250 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1 mixed
1x BTL + 2x SE mode depending on output power conditions and system design.
470uF
15µH
3R3
+12V
470uF
100nF
100nF
33nF
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
10nF
GVDD_AB
VDD
BST_A
BST_B
GND
1nF
1nF
1µF
1µF
3w3
33nF
M1
M2
GND
3R3
10µF
10µF
INPUT_A
INPUT_B
INPUT_A
INPUT_B
OC_ADJ
FREQ_ADJ
OSC_IOM
OSC_IOP
DVDD
OUT_A
OUT_A
PVDD_AB
PVDD_AB
PVDD_AB
OUT_B
GND
10nF
22k
1µF
470uF
15µH
30k
470uF
PVDD
GND
10
11
12
13
14
15
16
17
18
19
1µF
1µF
1µF
TPA3250
GND
GND
GND
OUT_C
PVDD_CD
PVDD_CD
PVDD_CD
OUT_D
OUT_D
GND
1µF
AVDD
470uF
15µH
470nF
C_START
INPUT_C
INPUT_D
/RESET
/FAULT
VBG
1µF 470uF
10µF
10µF
INPUT_C
INPUT_D
/RESET
/FAULT
10nF
1nF
1nF
1µF
1µF
26
25
24
23
3w3
100nF
20
21
22
GND
33nF
3R3
/CLIP_OTW
/CLIP_OTW
GVDD_CD
BST_C
BST_D
10nF
3R3
100nF
33nF
470uF
15µH
Figure 23. Typical Single Ended (1N) SE Application
10.2.3.1 Design Requirements
Refer to Stereo BTL Application for the Design Requirements.
Table 8. Design Requirements, SE Application
DESIGN PARAMETER
Low Power (Pull-up) Supply
Mid Power Supply 1 2V
High Power Supply
EXAMPLE
3.3 V
12 V
12 - 32 V
M2 = H
M1 = H
Mode Selection
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ±3.9 V (peak, max)
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
Analog Inputs
Output Filters
Inductor-Capacitor Low Pass FIlter (15 µH + 680 nF)
Speaker Impedance
2 - 8 Ω
10.2.3.2 Detailed Design Procedures
Refer to Stereo BTL Application for the Detailed Design Procedures.
24
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ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
10.2.3.3 Application Curves
Relevant performance plots for TPA3250 in PBTL configuration are shown in Typical Characteristics, SE
Configuration
Table 9. Relevant Performance Plots, SE Configuration
PLOT TITLE
FIGURE NUMBER
Figure 9
Total Harmonic Distortion+Noise vs Output Power
Total Harmonic Distortion+Noise vs Frequency
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Output Power vs Supply Voltage, 10% THD+N
Output Power vs Supply Voltage, 1% THD+N
Output Power vs Case Temperature
Figure 10
Figure 11
Figure 12
Figure 13
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10.2.4 Typical Application, Differential (2N) PBTL
TPA3250 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1 mixed
1x BTL + 2x SE mode depending on output power conditions and system design.
3R3
+12V
470uF
100nF
100nF
33nF
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
GVDD_AB
VDD
BST_A
BST_B
GND
10µH
33nF
M1
M2
GND
10µF
10µF
INPUT_A
INPUT_B
INPUT_A
INPUT_B
OC_ADJ
FREQ_ADJ
OSC_IOM
OSC_IOP
DVDD
OUT_A
OUT_A
PVDD_AB
PVDD_AB
PVDD_AB
OUT_B
GND
22k
PVDD
1µF
10µH
30k
470uF
10nF
1nF
1nF
10
11
12
13
14
15
16
17
18
19
680nF
680nF
1µF
1µF
1µF
3w3
TPA3250
GND
GND
3R3
GND
OUT_C
PVDD_CD
PVDD_CD
PVDD_CD
OUT_D
OUT_D
GND
10nF
1µF
AVDD
10µH
10nF
C_START
INPUT_C
INPUT_D
/RESET
/FAULT
VBG
1µF 470uF
GND
/RESET
/FAULT
26
25
24
23
100nF
20
21
22
GND
33nF
10µH
/CLIP_OTW
/CLIP_OTW
GVDD_CD
BST_C
BST_D
3R3
100nF
33nF
Figure 24. Typical Differential (2N) PBTL Application
10.2.4.1 Design Requirements
Refer to Stereo BTL Application for the Design Requirements.
Table 10. Design Requirements, PBTL Application
DESIGN PARAMETER
Low Power (Pull-up) Supply
Mid Power Supply 12 V
High Power Supply
EXAMPLE
3.3 V
12 V
12 - 32 V
M2 = H
M1 = L
Mode Selection
INPUT_A = ±3.9V (peak, max)
INPUT_B = ±3.9V (peak, max)
INPUT_C = Grounded
Analog Inputs
INPUT_D = Grounded
Output Filters
Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance
2 - 4 Ω
10.2.4.2 Detailed Design Procedures
Refer to Stereo BTL Application for the Detailed Design Procedures.
26
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10.2.4.3 Application Curves
Relevant performance plots for TPA3250 in PBTL configuration are shown in Typical Characteristics, PBTL
Configuration
Table 11. Relevant Performance Plots, PBTL Configuration
PLOT TITLE
FIGURE NUMBER
Figure 14
Total Harmonic Distortion+Noise vs Output Power
Total Harmonic Distortion+Noise vs Frequency
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW
Output Power vs Supply Voltage, 10% THD+N
Output Power vs Supply Voltage, 1% THD+N
Output Power vs Case Temperature
Figure 15
Figure 16
Figure 17
Figure 18
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11 Power Supply Recommendations
11.1 Power Supplies
The TPA3250 device requires two external power supplies for proper operation. A high-voltage supply called
PVDD is required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one
mid-voltage power supply for GVDD_X and VDD is required to power the gate-drive and other internal digital and
analog portions of the device. The allowable voltage range for both the PVDD and the GVDD_X/VDD supplies
are listed in the Recommended Operating Conditions table. Ensure both the PVDD and the GVDD_X/VDD
supplies can deliver more current than listed in the Electrical Characteristics table.
11.1.1 VDD Supply
The VDD supply required from the system is used to power several portions of the device. It provides power to
internal regulators DVDD and AVDD that are used to power digital and analog sections of the device,
respectively. Proper connection, routing, and decoupling techniques are highlighted in the TPA3250 device EVM
User's Guide SLVUAG8 (as well as the Application Information section and Layout Examples section) and must
be followed as closely as possible for proper operation and performance. Deviation from the guidance offered in
the TPA3250 device EVM User's Guide, which followed the same techniques as those shown in the Application
Information section, may result in reduced performance, errant functionality, or even damage to the TPA3250
device. Some portions of the device also require a separate power supply which is a lower voltage than the VDD
supply. To simplify the power supply requirements for the system, the TPA3250 device includes integrated low-
dropout (LDO) linear regulators to create these supplies. These linear regulators are internally connected to the
VDD supply and their outputs are presented on AVDD and DVDD pins, providing a connection point for an
external bypass capacitors. It is important to note that the linear regulators integrated in the device have only
been designed to support the current requirements of the internal circuitry, and should not be used to power any
additional external circuitry. Additional loading on these pins could cause the voltage to sag and increase noise
injection, which negatively affects the performance and operation of the device.
11.1.2 GVDD_X Supply
The GVDD_X supply required from the system is used to power the gate-drives for the output H-bridges. Proper
connection, routing, and decoupling techniques are highlighted in the TPA3250 device EVM User's Guide
SLVUAG8 (as well as the Application Information section and Layout Examples section) and must be followed as
closely as possible for proper operation and performance. Deviation from the guidance offered in the TPA3250
device EVM User's Guide, which followed the same techniques as those shown in the Application Information
section, may result in reduced performance, errant functionality, or even damage to the TPA3250 device.
11.1.3 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are
highlighted in the TPA3250 device EVM User's Guide SLVUAG8 (as well as the Application Information section
and Layout Examples section) and must be followed as closely as possible for proper operation and
performance. Due the high-voltage switching of the output stage, it is particularly important to properly decouple
the output power stages in the manner described in the TPA3250 device EVM User's Guide SLVUAG8. The lack
of proper decoupling, like that shown in the EVM User's Guide, can results in voltage spikes which can damage
the device, or cause poor audio performance and device shutdown faults.
11.2 Powering Up
The TPA3250 does not require a power-up sequence, but it is recommended to hold RESET low minimum
400ms after PVDD supply voltage is turned ON. The outputs of the H-bridges remain in a high-impedance state
until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP)
voltage threshold (see the Electrical Characteristics table of this data sheet). This allows an internal circuit to
charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output as well as
initiating a controlled ramp up sequence of the output voltage.
28
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TPA3250
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ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
Powering Up (continued)
të55
ë55
Dë55
5ë55
ꢀ
> 400ms
w9{9Ç delay
/w9{9Ç
!ë55
ꢀ
C 100µs
C 220ms
!ë55 ramp
/C!Ü[Ç
ëLb_ó
hÜÇ_ó
ꢀ
trecꢁarge
ëhÜÇ_ó
ꢀ
{ꢀarꢀup ramp
Figure 25. Startup Timing
When RESET is released to turn on TPA3250, FAULT signal will turn low and AVDD voltage regulator will be
enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold (see the
Electrical Characteristics table of this data sheet). After a precharge time to stabilize the DC voltage across the
input AC coupling capacitors, before the ramp up sequence starts.
11.3 Powering Down
The TPA3250 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks by
initiating a controlled ramp down sequence of the output voltage.
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11.4 Thermal Design
11.4.1 Thermal Performance
TPA3250 thermal performance is dependent on the thermal design of the PCB. As a result, the maximum
continuous output power attainable will be influenced by the PCB design. The continuous power rating is lower
than the peak output power capability of the device. TPA3250 peak power rating is based on the burst capability
of the device. The peak to average power ratio of TPA3250 is well suited to handle even demanding audio
playback without thermal shutdown. Thermal performance with typical audio content (burst) versus sine wave
content (continuous) should be considered when defining the thermal test requirements for the end product.
11.4.2 Thermal Performance with Continuous Output Power
It is recommended to operate TPA3250 below the OTW threshold, which in most systems will require the
average output power to be below the maximum peak output power. The maximum continuous power TPA3250
will deliver depends directly on the thermal design of the PCB and for the entire system (closed box with no air
flow, or a fanned system etc.). Thermal performance is also impacted by PVDD voltage and switching frequency.
The best configuration for a given application will often depend on the continuous output power requirements.
Table 12. Device and PCB Temperatures with 8-Ω Load, TA = 40°C
TA = 40°C, TPA3250 EVM, No Airflow. Steady State Temperatures.
Switching
Frequency
Device Top
Temperature
Maximum PCB
Temperature
PVDD
Continuous Power [W]
Comment
32V
32V
32V
32V
32V
32V
36V
36V
36V
450kHz
450kHz
450kHz
600kHz
600kHz
600kHz
450kHz
450kHz
450kHz
73W
18W
9W
10% THD
114°C
87°C
89°C
71°C
65°C
98°C
84°C
70°C
113°C
87°C
71°C
1/4 of 10% THD power
1/8 of 10% THD power
10% THD
77°C
72W
18W
9W
128°C
105°C
85°C
OTW after 236 seconds
OTW after 95 seconds
1/4 of 10% THD power
1/8 of 10% THD power
10% THD
92W
23W
11.5W
150°C
111°C
79°C
1/4 of 10% THD power
1/8 of 10% THD power
OTW after 3 seconds. Not
recommended.
36V
600kHz
91W
10% THD
OTE(1)
36V
36V
600kHz
600kHz
22.5W
11.5W
1/4 of 10% THD power
1/8 of 10% THD power
144°C
115°C
109°C
90°C
OTW after 152 seconds
(1) Steady state data is not available because device heats up to OTE in this condition.
Table 13. Device and PCB Temperatures with 4-Ω Load, TA = 40°C
TA = 40°C, TPA3250 EVM, No Airflow. Steady State Temperatures.
Switching
Frequency
Device Top
Temperature
Maximum PCB
Temperature
PVDD
32V
Continuous Power [W]
10% THD
Comment
OTW after 1 second.Not
recommended.
450kHz
130W
OTE
OTW after 92 seconds. Not
recommended.
32V
32V
32V
450kHz
450kHz
600kHz
32.5W
16W
1/4 of 10% THD power
1/8 of 10% THD power
10% THD
147°C
107°C
111°C
85°C
OTW after 1 second. Not
recommended.
130W
OTE(1)
OTW after 29 seconds. Not
recommended.
32V
32V
36V
36V
600kHz
600kHz
450kHz
450kHz
32.5W
16W
1/4 of 10% THD power
1/8 of 10% THD power
10% THD
OTE(1)
OTW after 92 seconds. Not
recommended.
147°C
99°C
OTW after 0 seconds. Not
recommended.
165W
41W
OTE(1)
OTE(1)
OTW after 11 seconds. Not
recommended.
1/4 of 10% THD power
(1) Steady state data is not available because device heats up to OTE in this condition.
30
Copyright © 2015–2016, Texas Instruments Incorporated
TPA3250
www.ti.com.cn
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
Table 13. Device and PCB Temperatures with 4-Ω Load, TA = 40°C (continued)
TA = 40°C, TPA3250 EVM, No Airflow. Steady State Temperatures.
OTW after 134 seconds. Not
recommended.
36V
36V
450kHz
600kHz
21W
1/8 of 10% THD power
142°C
108°C
Not recommended
11.4.3 Thermal Performance with Non-Continuous Output Power
As audio signals often have a peak to average ratio larger than one (average level below maximum peak output),
the thermal performance for audio signals can be illustrated using burst signals with different burst ratios.
Figure 26. Example of audio signal
A burst signal is characterized by the high-level to low-level ratio as well as the duration of the high level and low
level, e.g. a burst 1:4 stimuli is a single period of high level followed by 4 cycles of low level.
Iigh level
[ow level
1cycle : 4cycles
Figure 27. Example of 1:4 Burst Signal
The following analysis of thermal performance for TPA3250 is made with the TPA3250 EVM surrounded by still
air (no airflow) with a controlled air temperature of 40°C. For 32-V operation the system is not thermally limited
with 8Ω load, but depending on the burst stimuli for operation at 36V some thermal limitations may occur,
depending on switching frequency and average to maximum power ratio. Low to maximum power ratio of the
burst stimuli is given in the plots as for example P1:8 which equals 1 cycle of full power followed by 8 cycles of
low power.
Copyright © 2015–2016, Texas Instruments Incorporated
31
TPA3250
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
130
120
110
100
90
130
120
110
100
90
80
80
70
70
Device Top P1:8
PCB Max P1:8
Device Top P1:4
PCB Max P1:4
60
60
Device Top P1:8
PCB Max P1:8
Device Top P1:4
PCB Max P1:4
Device Top P1:2
PCB Max P1:2
50
50
1:8
1:4
1:2
1
1:8
1:4
Burst Ratio (High:Low)
PVDD = 32V, fs = 600kHz RL = 8Ω
1:2
1
Burst Ratio (High:Low)
PVDD = 32V, fs = 450kHz RL = 8Ω
D022
D021
TA = 40°C
TA = 40°C
Figure 28. Device and PCB Temperatures vs. Burst Ratio
130
Figure 29. Device and PCB Temperatures vs. Burst Ratio
130
120
110
100
90
120
110
100
90
80
80
70
70
Device Top P1:8
PCB Max P1:8
Device Top P1:4
PCB Max P1:4
60
60
Device Top P1:8
PCB Max P1:8
50
50
1:8
1:4
Burst Ratio (High:Low)
PVDD = 36V, fs = 450kHz RL = 8Ω
1:2
1
1:8
1:4
Burst Ratio (High:Low)
PVDD = 36V, fs = 600kHz RL = 8Ω
1:2
1
D023
D024
TA = 40°C
TA = 40°C
Figure 30. Device and PCB Temperatures vs. Burst Ratio
Figure 31. Device and PCB Temperatures vs. Burst Ratio
32
Copyright © 2015–2016, Texas Instruments Incorporated
TPA3250
www.ti.com.cn
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
12 Layout
12.1 Layout Guidelines
•
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply
for power and audio signals.
•
Maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as
many of the ground pins as possible, since the ground pins are the best conductors of heat in the package.
•
•
•
•
•
PCB layout, audio performance and EMI are linked closely together.
Routing the audio input should be kept short and together with the accompanied audio source ground.
The small bypass capacitors on the PVDD lines of the DUT be placed as close the PVDD pins as possible.
A local ground area underneath the device is important to keep solid to minimize ground bounce.
Orient the passive component so that the narrow end of the passive component is facing the TPA3250
device, unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads.
•
•
Avoid placing other heat producing components or structures near the TPA3250 device.
Avoid cutting off the flow of heat from the TPA3250 device to the surrounding ground areas with traces or via
strings, especially on output side of device.
Netlist for this printed circuit board is generated from the schematic in Figure 32.
Copyright © 2015–2016, Texas Instruments Incorporated
33
TPA3250
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
12.2 Layout Examples
12.2.1 BTL Application Printed Circuit Board Layout Example
ꢀad to top layer ground pour
.ottom [ayer {ignal Çraces
Çop [ayer {ignal Çraces
.ottom to top layer connection via
{ystem ꢀrocessor
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
Ç1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Ç2
Ç2
30
29
28
27
26
25
24
23
Ç1
A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide
traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or
traces should be blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors placed close to the pins.
D. Note T3: PowerPad™ needs to be soldered to PCB GND copper pour
Figure 32. BTL Application Printed Circuit Board - Composite
34
Copyright © 2015–2016, Texas Instruments Incorporated
TPA3250
www.ti.com.cn
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
Layout Examples (continued)
12.2.2 SE Application Printed Circuit Board Layout Example
ꢀad to top layer ground pour
.ottom [ayer {ignal Çraces
Çop [ayer {ignal Çraces
.ottom to top layer connection via
{ystem ꢀrocessor
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
Ç1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Ç2
Ç2
30
29
28
27
26
25
24
23
Ç1
A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide
traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or
traces should be blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed close to the pins.
D. Note T3: PowerPad™ needs to be soldered to PCB GND copper pour
Figure 33. SE Application Printed Circuit Board - Composite
Copyright © 2015–2016, Texas Instruments Incorporated
35
TPA3250
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
www.ti.com.cn
Layout Examples (continued)
12.2.3 PBTL Application Printed Circuit Board Layout Example
ꢀad to top layer ground pour
.ottom [ayer {ignal Çraces
Çop [ayer {ignal Çraces
.ottom to top layer connection via
{ystem ꢀrocessor
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
Ç1
3
4
5
6
Drounded for ꢀ.Ç[
Drounded for ꢀ.Ç[
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Ç2
Ç2
30
29
28
27
26
25
24
23
Ç1
A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide
traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or
traces should be blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed close to the pins.
D. ote T3: PowerPad™ needs to be soldered to PCB GND copper pour
Figure 34. PBTL Application Printed Circuit Board - Composite
36
版权 © 2015–2016, Texas Instruments Incorporated
TPA3250
www.ti.com.cn
ZHCSF33A –DECEMBER 2015–REVISED FEBRUARY 2016
13 器件和文档支持
13.1 文档支持
《TPA3250D2EVM 用户指南》，SLVUAG8
13.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 商标
PurePath, PowerPAD, E2E are trademarks of Texas Instruments.
蓝光光盘 is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
13.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015–2016, Texas Instruments Incorporated
37
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPA3250D2DDW
TPA3250D2DDWR
ACTIVE
ACTIVE
HTSSOP
HTSSOP
DDW
DDW
44
44
35
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
0 to 70
0 to 70
3250
3250
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DDW 44
6.1 x 14, 0.635 mm pitch
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224876/A
www.ti.com
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