TPA6130A2_17 [TI]
138-mW DIRECTPATH Stereo Headphone Amplifier with I2C Volume Control;
| 型号： | TPA6130A2_17 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 138-mW DIRECTPATH Stereo Headphone Amplifier with I2C Volume Control |
| 文件： | 总29页 (文件大小：1171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA6130A2
YZH
RTJ
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
138-mW DIRECTPATH™ STEREO HEADPHONE AMPLIFIER WITH I2C VOLUME CONTROL
FEATURES
•
DirectPath™ Ground-Referenced Outputs
•
Digital I2C Bus Control
Per Channel Mute and Enable
Software Shutdown
–
–
–
–
Eliminates Output DC Blocking Capacitors
Reduces Board Area
–
–
–
Reduces Component Height and Cost
Full Bass Response Without Attenuation
Multi-Mode Support: Stereo HP, Dual Mono
HP, and Single-Channel BTL Operation
–
Amplifier Status
•
•
•
Power Supply Voltage Range: 2.5 V to 5.5 V
64 Step Audio Taper Volume Control
•
Space Saving Lead-Free (Pb-Free) Packages
–
–
20 Pin, 4 mm x 4 mm QFN
16 ball, 2 mm x 2 mm WCSP
High Power Supply Rejection Ratio (>100 dB
PSRR)
•
Differential Inputs for Maximum Noise
Rejection (68 dB CMRR)
•
ESD Protection of 8 kV HBM and IEC Contact
APPLICATIONS
•
•
High-Impedance Outputs When Disabled
•
•
•
•
Mobile Phones
Advanced Pop and Click Suppression
Circuitry
Portable Media Players
Notebook Computers
High Fidelity Applications
DESCRIPTION
The TPA6130A2 is a stereo DirectPath™ headphone amplifier with I2C digital volume control. The TPA6130A2
has minimal quiescent current consumption, with a typical IDD of 4 mA, making it optimal for portable
applications. The I2C control allows maximum flexibility with a 64 step audio taper volume control, channel
independent enables and mutes, and the ability to configure the outputs into stereo, dual mono, or a single
receiver speaker BTL amplifier that drives 300 mW of power into 16 Ω loads.
The TPA6130A2 is a high fidelity amplifier with an SNR of 98 dB. A PSRR greater than 100 dB enables
direct-to-battery connections without compromising the listening experience. The output noise of 9 µVrms
(typical A-weighted) provides a minimal noise background during periods of silence. Configurable differential
inputs and high CMRR allow for maximum noise rejection in the noisy environment of a mobile device.
TPA6130A2 packaging includes a 2 by 2 mm chip-scale package, and a 4 by 4 mm QFN package.
SIMPLIFIED APPLICATION DIAGRAM
2
I C
GPIO
SD
Audio Source
SCL SDA
Left Out M
Left Out P
LEFTINM
HPLEFT
0.47 mF
0.47 mF
0.47 mF
0.47 mF
LEFTINP
Right Out M
Right Out P
RIGHTINM
RIGHTINP
TPA6130A2
HPRIGHT
GND
GND
CPP CPN CPVSS
VDD VDD
1 mF
1 mF
1 mF
1 mF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DirectPath is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
LEFTINM
Left
HPLEFT
LEFTINP
Gain
Control
De-Pop
RIGHTINM
RIGHTINP
HPRIGHT
Right
Current
Limit
Thermal
CPP
CPN
SD
Charge
Pump
Power
Management
I2C Interface
and Control
SDA
SCL
CPVSS
GND
VDD
VDD
GND
Headphone channels are independently enabled and muted. The I2C interface controls channel gain, device
modes, and charge pump activation. The charge pump generates a negative supply voltage for the output
amplifiers. This allows a 0 V bias at the outputs, eliminating the need for bulky output capacitors. The thermal
block detects faults and shuts down the device before damage occurs. The I2C register records thermal fault
conditions. The current limit block prevents the output current from getting high enough to damage the device.
The De-Pop block eliminates audible pops during power-up, power-down, and amplifier enable and disable
events.
2
TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
20
19
18
17
16
A1
A2
A3
A4
A4
A3
A2
A1
1
15
LEFTINM
CPVSS
CPN
CPP
GND
VDD
VDD
GND
CPP
CPN
2
3
4
14
13
12
LEFTINP
GND
HPLEFT
GND
B1
B2
B3
B4
B4
B3
B2
B1
HPLEFT
CPVSS
LEFTINP LEFTINM
C3 C4
RIGHTINP RIGHTINM
LEFTINM LEFTINP
C4 C3
RIGHTINM RIGHTINP
CPVSS
HPLEFT
T op View
C1
C2
C2
C1
RIGHTINP
VDD
GND
GND
VDD
VDD
5
11
RIGHTINM
HPRIGHT
D1
D2
D3
D4
SD
D4
SD
D3
D2
D1
6
7
8
9
10
HPRIGHT
SCL
SDA
SDA
SCL
HPRIGHT
Top (Symbol Side) View WCSP Package (YZH)
Bottom (Ball Side) View WCSP Package (YZH)
Top View QFN Package (RTJ)
TERMINAL FUNCTIONS
TERMINAL
INPUT/
OUTPUT/
POWER
(I/O/P)
DESCRIPTION
BALL
WCSP
NAME
PIN QFN
Charge pump voltage supply. VDD must be connected to the common VDD voltage
supply. Decouple to GND (pin 19 on the QFN) with its own 1 µF capacitor.
VDD
A4
A3
20
P
Charge pump ground. GND must be connected to common supply GND. It is
recommended that this pin be decoupled to the VDD of the charge pump pin (pin 20 on
the QFN).
GND
19
P
Charge pump flying capacitor positive terminal. Connect one side of the flying capacitor
to CPP.
CPP
A2
A1
B4
18
17
1
P
P
I
Charge pump flying capacitor negative terminal. Connect one side of the flying capacitor
to CPN.
CPN
Left channel negative differential input. Impedance must be matched to LEFTINP.
Connect the left input to LEFTINM when using single-ended inputs.
LEFTINM
Left channel positive differential input. Impedance must be matched to LEFTINM. AC
ground LEFTINP near signal source while maintaining matched impedance to LEFTINM
when using single-ended inputs.
LEFTINP
B3
2
I
Negative supply generated by the charge pump. Decouple to pin 19 on the QFN or a
GND plane. Use a 1 µF capacitor.
CPVSS
B2
B1
C4
15, 16
14
P
O
I
HPLEFT
RIGHTINM
Headphone left channel output. Connect to left terminal of headphone jack.
Right channel negative differential input. Impedance must be matched to RIGHTINP.
Connect the right input to RIGHTINM when using single-ended inputs.
5
Right channel positive differential input. Impedance must be matched to RIGHTINM. AC
ground RIGHTINP near signal source while maintaining matched impedance to
RIGHTINM when using single-ended inputs.
RIGHTINP
C3
4
I
Analog ground. Must be connected to common supply GND. It is recommended that this
pin be used to decouple VDD for analog. Use pin 13 to decouple pin 12 on the QFN
package.
3, 9, 10,
13
GND
VDD
C2
C1
P
P
Analog VDD. VDD must be connected to common VDD supply. Decouple with its own
1-µF capacitor to analog ground (pin 13 on the QFN).
12
SD
D4
D3
D2
D1
6
7
I
I/O
I
Shutdown. Active low logic. 5V tolerant input.
SDA - I2C Data. 5V tolerant input.
SCL - I2C Clock. 5V tolerant input.
SDA
SCL
8
HPRIGHT
11
O
Headphone light channel output. Connect to the right terminal of the headphone jack.
Thermal
pad
Solder the thermal pad on the bottom of the QFN package to the GND plane of the
PCB. It is required for mechanical stability and will enhance thermal performance.
N/A
Die Pad
P
3
TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range, TA = 25°C (unless otherwise noted)
VALUE / UNIT
Supply voltage, VDD
RIGHTINx, LEFTINx
–0.3 V to 6.0 V
–2.7 V to 3.6 V
–0.3 V to 7 V
See Dissipation Rating Table
–40°C to 85°C
–40°C to 125°C
–65°C to 150°C
260°C
VI
Input voltage
SD, SCL, SDA
Output continuous total power dissipation
Operating free-air temperature range
Operating junction temperature range
Storage temperature range
TA
TJ
Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
HBM Output Pins
ESD Protection
8 kV
HBM All Other Pins
3.5 kV
IEC Contact ESD Protection(2)
No External Protection
8 kV
V14MLA0603 Varistors Used for External Protection
15 kV
Minimum Load Impedance
12.8 Ω
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Tested to IEC 61000-4-2 standards on a TPA6130A2 EVM.
DISSIPATION RATINGS TABLE
T
A ≤ 25°C
DERATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
FACTOR(1)(2)
RTJ
YZH
4100 mW
41 mW/°C
9.7 mW/°C
2250 mW
530 mW
1640 mW
390 mW
970 mW
(1) Derating factor measured with JEDEC High K board: 1S2P - One signal layer and two plane layers.
(2) See JEDEC Standard 51-3 for Low-K board, JEDEC Standard 51-7 for High-K board, and JEDEC
Standard 51-12 for using package thermal information. Please see JEDEC document page for
downloadable copies: http://www.jedec.org/download/default.cfm.
AVAILABLE OPTIONS
TA
PACKAGED DEVICES(1)
20-pin, 4 mm × 4 mm QFN
16-ball, 2 mm × 2 mm WSCP
PART NUMBER
TPA6130A2RTJ(2)
TPA6130A2YZH
SYMBOL
BSG
–40°C to 85°C
BRU
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) The RTJ package is only available taped and reeled. To order, add the suffix “R” to the end of the part number for a reel of 3000, or add
the suffix “T” to the end of the part number for a reel of 250 (e.g., TPA6130A2RTJR).
RECOMMENDED OPERATING CONDITIONS
MIN
2.5
MAX UNIT
Supply voltage, VDD
5.5
V
V
VIH
VIL
TA
High-level input voltage
SCL, SDA, SD
SCL, SDA
SD
1.3
0.6
0.35
85
V
Low-level input voltage
V
Operating free-air temperature
–40
°C
4
TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
|VOS|
PSRR
Output offset voltage
VDD = 2.5 V to 5.5 V, inputs grounded
VDD = 2.5 V to 5.5 V, inputs grounded
VDD = 2.5 V to 5.5 V
150 400
µV
dB
dB
Power supply rejection ratio
–109 –90
CMRR Common mode rejection ratio
–68
SCL, SDA
SD
1
|IIH
|
High-level input current
Low-level input current
VDD = 5.5 V, VI = VDD
µA
10
1
|IIL|
VDD = 5.5 V, VI = 0 V
SCL, SDA, SD
µA
mA
µA
µA
VDD = 2.5 V to 5.5 V, SD = VDD
4
0.4
25
6
1
Shutdown mode, VDD = 2.5V to 5.5 V, SD = 0 V
SW Shutdown mode, VDD = 2.5V to 5.5 V, SWS = 1
IDD
Supply current
75
Both HP amps disabled, VDD = 2.5V to 5.5 V,
SWS = 0, Charge Pump enabled, SD = VDD
1.4
2.5
mA
TIMING CHARACTERISTICS(1)(2)
For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER
Frequency, SCL
TEST CONDITIONS
No wait states
MIN
TYP
MAX
400
UNIT
kHz
µs
fSCL
tw(H)
tw(L)
tsu1
th1
Pulse duration, SCL high
0.6
1.3
300
10
Pulse duration, SCL low
µs
Setup time, SDA to SCL
ns
Hold time, SCL to SDA
ns
t(buf)
tsu2
th2
Bus free time between stop and start condition
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
1.3
0.6
0.6
0.6
µs
µs
µs
tsu3
µs
(1) VPull-up = VDD
(2) A pull-up resistor ≤2 kΩ is required for a 5 V I2C bus voltage.
t
t
w(L)
w(H)
SCL
t
h1
t
su1
SDA
Figure 1. SCL and SDA Timing
5
TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
SCL
th2
t(buf)
tsu3
tsu2
SDA
Start Condition
Stop Condition
Figure 2. Start and Stop Conditions Timing
OPERATING CHARACTERISTICS
VDD = 3.6 V , TA = 25°C, RL = 16 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 2.5V
MIN
TYP
60
MAX UNIT
Stereo, Outputs out of phase,
THD = 1%, f = 1 kHz, Gain = 0.1 dB
VDD = 3.6V
VDD = 5V
127
138
PO
Output power
mW
VDD = 2.5V
VDD = 3.6V
VDD = 5V
110
Bridge-tied load,
THD = 1%, f = 1 kHz, Gain = 0.1 dB
230
290
f = 100 Hz
f = 1 kHz
0.0029%
0.0055%
0.0027%
-97
Total harmonic distortion
plus noise
THD+N
PO = 35 mW
f = 20 kHz
200 mVpp ripple, f = 217 Hz
200 mVpp ripple, f = 1 kHz
200 mVpp ripple, f = 20 kHz
-90
dB
kSVR
Supply ripple rejection ratio
-93
-76
∆Av
Gain matching
Slew rate
1%
0.3
V/µs
Vn
Noise output voltage
VDD = 3.6V, A-weighted, Gain = 0.1 dB
9
µVRMS
Charge pump switching
frequency
fosc
300
400
5
500
kHz
ms
Start-up time from shutdown
Differential input impedance See Figure 33
SNR
Signal-to-noise ratio
Po = 35 mW
Threshold
Hysteresis
98
180
35
dB
°C
°C
Thermal shutdown
Tri-state HP output
impedance
ZO
CO
HiZ left and right bits set. HP amps disabled. DC value.
25
80
MΩ
Output capacitance
pF
6
TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS
C(PUMP, DECOUPLE, ,BYPASS, CPVSS) = 1 µF, CI = 2.2µF.
All THD + N graphs taken with outputs out of phase (unless otherwise noted).
Table of Graphs
FIGURE
3–8
Total harmonic distortion + noise
Total harmonic distortion + noise
Supply voltage rejection ratio
Common mode rejection ratio
Output power
vs Output power
vs Frequency
vs Frequency
vs Frequency
vs Load
9–22
23-25
26-27
28-29
30-31
32
Output voltage
vs Load
Power Dissipation
vs Output power
vs Gain
Differential Input Impedance
Shutdown time
33
34
Startup time
35
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
NOISE
vs
NOISE
vs
NOISE
vs
OUTPUT POWER
OUTPUT POWER
OUTPUT POWER
10
10
1
10
1
R
= 16 W,
R = 16 W,
L
R
= 32 W,
L
Gain = 0.1 dB,
L
Gain = 0.1 dB,
Gain = 0.1 dB,
f = 1 kHz,
V
= 3.6 V,
V
= 3.6 V,
DD
= 1 kHz,
IN
Stereo
DD
= 1 kHz,
1
f
f
IN
Stereo
IN
Stereo
V
= 2.5 V
= 3 V
DD
In Phase
In Phase
V
DD
0.1
0.01
0.1
0.1
Out of Phase
Out of Phase
V
= 3.6 V
DD
0.01
0.01
V
= 5 V
DD
0.001
0.001
0.001
1m
10m
100m
1
1m
10m
100m
1
100m
100m
1m
10m
100m
1
100m
P
- Output Power - W
P
- Output Power - W
P
- Output Power - W
O
O
O
Figure 3.
Figure 4.
Figure 5.
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
NOISE
vs
NOISE
vs
NOISE
vs
OUTPUT POWER
OUTPUT POWER
OUTPUT POWER
10
1
10
1
10
1
R
= 16 W,
R = 32 W,
L
R
= 32 W,
V
= 5 V
L
L
DD
Gain = 6.1 dB,
= 1 kHz,
Gain = 6.1 dB,
= 1 kHz,
Gain = 0.1 dB,
= 1 kHz,
f
f
f
IN
BTL
IN
BTL
IN
Stereo
V
= 2.5 V
= 3 V
DD
V
= 2.5 V
V
= 3.6 V
DD
DD
V
DD
V
= 2.5 V
= 3 V
0.1
0.01
0.1
0.1
DD
V
= 3.6 V
DD
V
V
DD
= 5 V
V
= 5 V
DD
DD
0.01
0.01
V
= 3.6 V
DD
V
= 3 V
DD
0.001
0.001
0.001
100m
100m
1m
10m
100m
1
1m
10m
1
2
1m
10m
1 2
100m
100m
100m
P
- Output Power - W
P
- Output Power - W
P - Output Power - W
O
O
O
Figure 6.
Figure 7.
Figure 8.
7
TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
NOISE
vs
NOISE
vs
NOISE
vs
FREQUENCY
FREQUENCY
FREQUENCY
1
1
100
10
1
R
V
= 16 W,
R
V
= 16 W,
L
L
R
V
= 16 W,
L
= 3.6 V,
= 3 V,
DD
DD
= 2.5 V,
DD
Gain = 0.1 dB,
Stereo
Gain = 0.1 dB,
Stereo
Gain = 0.1 dB,
Stereo
0.1
0.1
P
= 70 mW
P
= 20 mW
O
O
P
= 40 mW
O
P
= 1 mW
P
= 35 mW
O
P
= 20 mW
O
O
0.1
P
= 5 mW
O
0.01
0.01
0.01
P
= 5 mW
O
P
= 4 mW
O
0.001
0.001
0.001
20
20
100
1k
10k 20k
20
100
1k
10k 20k
100
1k
10k 20k
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 9.
Figure 10.
Figure 11.
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
NOISE
vs
NOISE
vs
NOISE
vs
FREQUENCY
FREQUENCY
FREQUENCY
1
1
1
R
V
= 16 W,
R
V
= 32 W,
R
V
= 32 W,
L
L
L
= 5 V,
= 2.5 V,
= 3 V,
DD
DD
DD
Gain = 0.1 dB,
Stereo
Gain = 0.1 dB,
Stereo
Gain = 0.1 dB,
Stereo
P
= 50 mW
O
0.1
0.1
0.1
P
= 20 mW
O
P
= 20 mW
O
P
= 80 mW
O
P
= 1 mW
O
P
= 40 mW
O
0.01
0.01
0.01
P
= 5 mW
O
P
= 4 mW
O
P
= 5 mW
O
0.001
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
20
100
1k
10k 20k
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 12.
Figure 13.
Figure 14.
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
NOISE
vs
NOISE
vs
NOISE
vs
FREQUENCY
FREQUENCY
FREQUENCY
1
1
1
R
V
= 16 W,
R
V
= 32 W,
R
V
= 32 W,
L
= 5 V,
L
L
= 2.5 V,
= 3.6 V,
DD
DD
DD
Gain = 6.1 dB,
BTL
Gain = 0.1 dB,
Stereo
Gain = 0.1 dB,
Stereo
P
= 35 mW
0.1
0.1
O
0.1
P
= 100 mW
P
= 50 mW
O
O
P
= 5 mW
P = 70 mW
O
O
P
= 70 mW
O
0.01
0.01
0.01
P
= 5 mW
P
= 5 mW
O
O
P
= 25 mW
1k
O
0.001
0.001
0.001
20
100
10k 20k
20
100
1k
10k 20k
20
100
1k
10k 20k
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 15.
Figure 16.
Figure 17.
8
TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
NOISE
vs
NOISE
vs
NOISE
vs
FREQUENCY
FREQUENCY
FREQUENCY
1
1
1
R
V
= 16 W,
R
V
= 16 W,
R
V
= 32 W,
L
= 2.5 V,
DD
L
L
= 3.6 V,
= 5 V,
DD
DD
Gain = 6.1 dB,
BTL
Gain = 6.1 dB,
BTL
Gain = 6.1 dB,
BTL
0.1
0.1
0.1
P
= 200 mW
P
= 100 mW
O
O
P
= 200 mW
O
P
= 5 mW
O
P
= 25 mW
O
P
= 25 mW
O
0.01
0.01
0.01
P
= 25 mW
P
= 100 mW
P
= 100 mW
O
O
O
0.001
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
20
100
1k
10k 20k
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 18.
Figure 19.
Figure 20.
TOTAL HARMONIC DISTORTION +
TOTAL HARMONIC DISTORTION +
SUPPLY VOLTAGE REJECTION
NOISE
vs
NOISE
vs
RATIO
vs
FREQUENCY
FREQUENCY
FREQUENCY
1
1
0
R
V
= 32 W,
R
V
= 32 W,
L
= 5 V,
R
= 16 W,
L
L
= 3.6 V,
Gain = 0.1 dB,
Cp = 1 mF,
Stereo
DD
DD
-20
Gain = 6.1 dB,
BTL
Gain = 6.1 dB,
BTL
0.1
0.1
-40
-60
P
= 200 mW
O
P
= 200 mW
O
V
= 3.6 V
DD
V
= 2.5 V
P
= 25 mW
DD
O
P
= 25 mW
O
-80
0.01
0.01
-100
-120
V
= 5 V
DD
P
= 100 mW
P
= 100 mW
O
O
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
20
100
1k
10k 20k
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 21.
Figure 22.
Figure 23.
SUPPLY VOLTAGE REJECTION
SUPPLY VOLTAGE REJECTION
RATIO
vs
RATIO
vs
COMMON MODE REJECTION RATIO
vs
FREQUENCY
FREQUENCY
FREQUENCY
0
0
0
R
= 32 W,
R
= 16 W,
R = 16 W,
L
L
L
-10
-20
-30
-40
-50
-60
-70
-80
Gain = 0.1 dB,
Cp = 1 mF,
Stereo
Gain = 6.1 dB,
Cp = 1 mF,
BTL
Gain = 0.1 dB,
= 2.2 mF,
-20
-20
C
I
Stereo
-40
-60
-40
-60
V
= 3.6 V
DD
V
= 2.5 V
DD
V
= 2.5 V
V
= 3.6 V
DD
DD
-80
-80
V
= 3.6 V
V
= 2.5 V
DD
DD
-100
-120
-100
-120
V
= 5 V
DD
V
= 5 V
V
= 5 V
DD
DD
1k
20
100
1k
10k 20k
20
100
1k
10k 20k
20
100
10k 20k
f - Frequency - Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 24.
Figure 25.
Figure 26.
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TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
COMMON MODE REJECTION RATIO
OUTPUT POWER
OUTPUT POWER
vs
vs
vs
FREQUENCY
LOAD
LOAD
0
-10
-20
-30
-40
-50
-60
-70
-80
250
200
150
100
500
400
300
200
R
= 16 W,
f
= 1 kHz,
f
= 1 kHz,
L
IN
IN
Gain = 6.1 dB,
Gain = 6.1 dB,
= 2.2 mF,
Gain = 0.1 dB,
THD+N = 1%,
Stereo
THD+N = 1%,
BTL
C
I
BTL
V
= 5 V
V
= 5 V
DD
DD
V
= 3.6 V
DD
V
= 3.6 V
DD
V
= 3.6 V
V
= 2.5 V
DD
DD
50
0
100
0
V
= 2.5 V
DD
V
= 2.5 V
DD
V
= 5 V
DD
1k
20
100
10k 20k
10
100
1k
10
100
1k
f - Frequency - Hz
Load - W
Load - W
Figure 27.
Figure 28.
Figure 29.
OUTPUT VOLTAGE
OUTPUT VOLTAGE
POWER DISSIPATION
vs
OUTPUT POWER
vs
vs
LOAD
LOAD
1
0.8
0.6
0.4
6
13
R
= 16 W,
L
5.5
Gain = 0.1 dB,
Stereo
V
= 5 V
DD
11
9
5
V
= 5 V
4.5
DD
V
= 5 V
DD
4
3.5
3
7
V
= 2.5 V
DD
V
= 3.6 V
= 2.5 V
DD
5
V
= 3.6 V
V
DD
DD
V
= 3.6 V
DD
2.5
2
THD + N = 1%
Gain = 0.1 dB,
= 1 kHz,
THD + N = 1%
Gain = 6.1 dB,
= 1 kHz,
0.2
0
f
3
1
IN
Stereo
f
IN
BTL
1.5
1
V
= 2.5 V
DD
10
1000
100
Load - W
10
100
Load - W
1000
0
50 100 150 200 250 300 350 400
P
- Output Power - mW
O
Figure 30.
Figure 31.
Figure 32.
DIFFERENTIAL INPUT IMPEDANCE
vs
GAIN
100
90
80
70
60
50
40
30
V
= 3.6 V
DD
-60
-50
-40
-30
-20
-10
0
10
Gain - dB
Figure 33.
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TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
1
0.75
0.5
Output
SWS
Disable
0.25
0
-0.25
-0.5
-0.75
-1
0
200m
400m
600m
800m
1m
1.2m
1.4m
1.6m
1.8m
2m
t - Time - s
Figure 34. Shutdown Time
1
0.75
0.5
Output
SWS Enable
0.25
0
-0.25
-0.5
-0.75
-1
0
1m
2m
3m
4m
5m
6m
7m
8m
9m
10m
t - Time - s
Figure 35. Startup Time
11
TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
APPLICATION INFORMATION
SIMPLIFIED APPLICATIONS CIRCUIT
VDD
1 mF
1 mF
20
19 18 17
16
1 mF
LEFTINM
LEFTINP
GND
CPVSS
HPLEFT
GND
15
14
13
12
11
1
2
3
4
5
0.47 mF
0.47 mF
TPA6130A2
VDD
VDD
RIGHTINP
RIGHTINM
1 mF
0.47 mF
0.47 mF
HPRIGHT
6
7
8
9
10
Headphone Amplifiers
Single-supply headphone amplifiers typically require dc-blocking capacitors. The capacitors are required
because most headphone amplifiers have a dc bias on the outputs pin. If the dc bias is not removed, the output
signal is severely clipped, and large amounts of dc current rush through the headphones, potentially damaging
them. The top drawing in Figure 36 illustrates the conventional headphone amplifier connection to the
headphone jack and output signal.
DC blocking capacitors are often large in value. The headphone speakers (typical resistive values of 16 Ω or 32
Ω) combine with the dc blocking capacitors to form a high-pass filter. Equation 1 shows the relationship between
the load impedance (RL), the capacitor (CO), and the cutoff frequency (fC).
1
f +
c
2pR C
L
O
(1)
CO can be determined using Equation 2, where the load impedance and the cutoff frequency are known.
1
C
+
O
2pR f
c
L
(2)
If fc is low, the capacitor must then have a large value because the load resistance is small. Large capacitance
values require large package sizes. Large package sizes consume PCB area, stand high above the PCB,
increase cost of assembly, and can reduce the fidelity of the audio output signal.
Two different headphone amplifier applications are available that allow for the removal of the output dc blocking
capacitors. The Capless amplifier architecture is implemented in the same manner as the conventional amplifier
with the exception of the headphone jack shield pin. This amplifier provides a reference voltage, which is
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TPA6130A2
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SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
connected to the headphone jack shield pin. This is the voltage on which the audio output signals are centered.
This voltage reference is half of the amplifier power supply to allow symmetrical swing of the output voltages. Do
not connect the shield to any GND reference or large currents will result. The scenario can happen if, for
example, an accessory other than a floating GND headphone is plugged into the headphone connector. See the
second block diagram and waveform in Figure 36.
Conventional
VDD
CO
VOUT
GND
VDD/2
CO
Capless
VDD
VOUT
GND
VBIAS
VBIAS
DirectPathTM
VDD
GND
VSS
Figure 36. Amplifier Applications
The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump
to provide a negative voltage rail. Combining the user provided positive rail and the negative rail generated by
the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at
zero volts with the capability to swing to the positive rail or negative rail. The DirectPath™ amplifier requires no
output dc blocking capacitors, and does not place any voltage on the sleeve. The bottom block diagram and
waveform of Figure 36 illustrate the ground-referenced headphone architecture. This is the architecture of the
TPA6130A2.
Input-Blocking Capacitors
DC input-blocking capacitors block the dc portion of the audio source, and allow the inputs to properly bias.
Maximum performance is achieved when the inputs of the TPA6130A2 are properly biased. Performance issues
such as pop are optimized with proper input capacitors.
The dc input-blocking capacitors may be removed provided the inputs are connected differentially and within the
input common mode range of the amplifier, the audio signal does not exceed ±3 V, and pop performance is
sufficient.
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TPA6130A2
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SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
CIN is a theoretical capacitor used for mathematical calculations only. Its value is the series combination of the
dc input-blocking capacitors, C(DCINPUT-BLOCKING). Use Equation 3 to determine the value of C(DCINPUT-BLOCKING)
.
For example, if CIN is equal to 0.22 µF, then C(DCINPUT-BLOCKING) is equal to about 0.47 µF.
1
2
C
C
=
(DCINPUT-BLOCKING)
IN
(3)
The two C(DCINPUT-BLOCKING) capacitors form a high-pass filter with the input impedance of the TPA6130A2. Use
Equation 3 to calculate CIN, then calculate the cutoff frequency using CIN and the differential input impedance of
the TPA6130A2, RIN, using Equation 4. Note that the differential input impedance changes with gain. See
Figure 33 for input impedance values. The frequency and/or capacitance can be determined when one of the
two values are given.
1
1
fc
+
C
+
or
IN
IN
2p R
C
2p fc
R
IN IN
IN IN
(4)
If a high pass filter with a -3 dB point of no more than 20 Hz is desired over all gain settings, the minimum
impedance would be used in the above equation. Figure 33 shows this to be 37 kΩ. The capacitor value by the
above equation would be 0.215 µF. However, this is CIN, and the desired value is for C(DCINPUT-BLOCKING)
.
Multiplying CIN by 2 yields 0.43 µF, which is close to the standard capacitor value of 0.47 µF. Place 0.47 µF
capacitors at each input terminal of the TPA6130A2 to complete the filter.
Charge Pump Flying Capacitor and CPVSS Capacitor
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The CPVSS capacitor must be at least equal to the flying capacitor in order to allow maximum charge transfer.
Low ESR capacitors are an ideal selection, and a value of 1 µF is typical.
Decoupling Capacitors
The TPA6130A2 is a DirectPath™ headphone amplifier that requires adequate power supply decoupling to
ensure that the noise and total harmonic distortion (THD) are low. Use good low equivalent-series-resistance
(ESR) ceramic capacitors, typically 1.0 µF. Find the smallest package possible, and place as close as possible
to the device VDD lead. Placing the decoupling capacitors close to the TPA6130A2 is important for the
performance of the amplifier. Use a 10 µF or greater capacitor near the TPA6130A2 to filter lower frequency
noise signals. The high PSRR of the TPA6130A2 will make the 10 µF capacitor unnecessary in most
applications.
Layout Recommendations
Exposed Pad On TPA6130A2RTJ Package Option
Solder the exposed metal pad on the TPA6130A2RTJ QFN package to the a pad on the PCB. The pad on the
PCB may be grounded or may be allowed to float (not be connected to ground or power). If the pad is grounded,
it must be connected to the same ground as the GND pins (3, 9, 10, 13, and 19). See the layout and mechanical
drawings at the end of the datasheet for proper sizing. Soldering the thermal pad improves mechanical reliability,
improves grounding of the device, and enhances thermal conductivity of the package.
GND Connections
The GND pin for charge pump should be decoupled to the charge pump VDD pin, and the GND pin adjacent to
the Analog VDD pin should be separately decoupled to each other.
I2C CONTROL INTERFACE DETAILS
Addressing the TPA6130A2
The device operates only as a slave device whose address is 1100000 binary.
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TPA6130A2
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SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
GENERAL I2C OPERATION
The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte
(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions.
A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 37. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then wait for an acknowledge condition. The TPA6130A2 holds SDA low during acknowledge clock
period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share
the same signals via a bidirectional bus using a wired-AND connection.
An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. When
the bus level is 5 V, pull-up resistors between 1 kΩ and 2 kΩ in value must be used.
8- Bit Data for
Register (N)
8- Bit Data for
Register (N+1)
Figure 37. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the
last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence
is shown in Figure 37.
SINGLE-AND MULTIPLE-BYTE TRANSFERS
The serial control interface supports both single-byte and multi-byte read/write operations for all registers.
During multiple-byte read operations, the TPA6130A2 responds with data, a byte at a time, starting at the
register assigned, as long as the master device continues to respond with acknowledges.
The TPA6130A2 supports sequential I2C addressing. For write transactions, if a register is issued followed by
data for that register and all the remaining registers that follow, a sequential I2C write transaction has taken
place. For I2C sequential write transactions, the register issued then serves as the starting point, and the amount
of data subsequently transmitted, before a stop or start is transmitted, determines to how many registers are
written.
SINGLE-BYTE WRITE
As shown in Figure 38, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I2C
device address and the read/write bit, the TPA6130A2 responds with an acknowledge bit. Next, the master
transmits the register byte corresponding to the TPA6130A2 internal memory address being accessed. After
receiving the register byte, the TPA6130A2 again responds with an acknowledge bit. Next, the master device
transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the
TPA6130A2 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to
complete the single-byte data write transfer.
15
TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
A6 A5 A4
A3 A2 A1 A0
Stop
2
I C Device Address and
Read/Write Bit
Register
Data Byte
Condition
Figure 38. Single-Byte Write Transfer
MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the TPA6130A2 as shown in Figure 39. After receiving each data byte,
the TPA6130A2 responds with an acknowledge bit.
Register
Figure 39. Multiple-Byte Write Transfer
SINGLE-BYTE READ
As shown in Figure 40, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
After receiving the TPA6130A2 address and the read/write bit, the TPA6130A2 responds with an acknowledge
bit. The master then sends the internal memory address byte, after which the TPA6130A2 issues an
acknowledge bit. The master device transmits another start condition followed by the TPA6130A2 address and
the read/write bit again. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA6130A2
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
2
2
Stop
Condition
I C Device Address and
Read/Write Bit
Register
I C Device Address and
Read/Write Bit
Data Byte
Figure 40. Single-Byte Read Transfer
MULTIPLE-BYTE READ
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TPA6130A2 to the master device as shown in Figure 41. With the exception of the last
data byte, the master device responds with an acknowledge bit after receiving each data byte.
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TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
Repeat Start
Condition
Not
Start
Acknowledge
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
2
2
Register
Stop
Condition
I C Device Address and
Read/Write Bit
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Figure 41. Multiple-Byte Read Transfer
Register Map
Table 1. Register Map
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
2
3
4
5
6
7
8
HP_EN_L
Mute_L
Reserved
Reserved
RFT
HP_EN_R
Mute_R
Reserved
Reserved
RFT
Mode[1]
Volume[5]
Reserved
RFT
Mode[0]
Volume[4]
Reserved
RFT
Reserved
Volume[3]
Reserved
Version[3]
RFT
Reserved
Volume[2]
Reserved
Version[2]
RFT
Thermal
Volume[1]
HiZ_L
Version[1]
RFT
SWS
Volume[0]
HiZ_R
Version[0]
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
RFT
Bits labeled "Reserved" are reserved for future enhancements. They may not be written to. When read, they will
show a "0" value.
Bits labeled "RFT" are reserved for TI testing. Under no circumstances must any data be written to these
registers. Writing to these bits may change the function of the device, or cause complete failure. If read, these
bits may assume any value.
Control Register (Address: 1)
BIT
7
HP_EN_L
0
6
HP_EN_R
0
5
Mode[1]
0
4
Mode[0]
0
3
Reserved
0
2
Reserved
0
1
Thermal
0
0
SWS
0
Function
Reset Value
HP_EN_L
Enable bit for the left-channel amplifier. Amplifier is active when bit is high.
HP_EN_R Enable bit for the right-channel amplifier. Amplifier is active when bit is high.
Mode[1:0]
Reserved
Thermal
Mode bits Mode[1] and Mode[0] select one of three modes of operation. 00 is stereo headphone
mode. 01 is dual mono headphone mode. 10 is bridge-tied load mode.
These bits are reserved for future enhancements. They may not be written to. When read they
will read as zero.
A 1 on this bit indicates a thermal shutdown was initiated by the hardware. When the temperature
drops to safe levels, the device will start to operate again, regardless of bit status. This bit is
clear-on-read.
SWS
Software shutdown control. When the bit is one, the device is in software shutdown. When the bit
is low, the charge-pump is active. SWS must be low for normal operation.
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TPA6130A2
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SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
Volume and Mute Register (Address: 2)
BIT
7
Mute_L
1
6
Mute_R
1
5
Volume[5]
0
4
Volume[4]
0
3
Volume[3]
0
2
Volume[2]
0
1
Volume[1]
0
0
Function
Volume[0]
Reset
Value
0
Mute_L
Mute_R
Left channel mute. If this bit is High the left channel is muted.
Right channel mute. If this bit is High the right channel is muted.
Volume[5:0] Six bits for volume control. 111111 indicates the highest gain and 000000 indicates the lowest
gain.
Output Impedance Register (Address: 3)
BIT
7
Reserved
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
HiZ_L
0
0
HiZ_R
0
Function
Reset Value
Reserved These bits are reserved for future enhancements. They may not be written to. When read they will
read as zero. All writes to these bits will be ignored.
HiZ_L
HiZ_R
Puts left-channel amplifier output in tri-state high impedance mode.
Puts right-channel amplifier output in tri-state high impedance mode.
I2C address and Version Register (Address: 4)
BIT
7
Reserved
0
6
Reserved
0
5
RFT
0
4
RFT
0
3
Version[3]
0
2
Version[2]
0
1
Version[1]
0
0
Version[0]
0
Function
Reset Value
Reserved
These bits are reserved for future enhancements. They may not be written to. When read they
will read as zero.
Version[3:0] The version bits track the revision of the silicon. Valid values are 0010 for released TPA6130A2.
RFT Reserved for Test. Do NOT write to these registers.
Reserved for test registers (Addresses: 5-8)
BIT
7
RFT
x
6
RFT
x
5
RFT
x
4
RFT
x
3
RFT
x
2
RFT
x
1
RFT
x
0
RFT
x
Function
Reset Value
RFT
Reserved for Test. Do NOT write to these registers.
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TPA6130A2
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SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
Modes of Operation
The TPA6130A2 supports numerous modes of operation.
Hardware Shutdown
Hardware shutdown occurs when the SD pin is set to logic 0. The device is completely shutdown in this mode,
drawing minimal current. This mode overrides all other modes. All information programmed into the registers is
lost. When the device starts up again, the registers go back to their default state.
Software Shutdown
Software shutdown is set by placing a logic 1 in register 1, bit 0. That is the SWS bit. The software shutdown
places the device in a low power state, although the current draw is higher than that of hardware shutdown (see
the Electrical Characteristics Table for values). Engaging software shutdown turns off the charge pump and
disables the outputs. The device is awakened by placing a logic 0 in the SWS bit.
Note that when the device is in SWS mode, register 1, bits 7 and 6 will be cleared to reflect the disabled state of
the amplifier. All other registers maintain their values. Re-enable the amplibifer by placing a logic 0 in the SWS
bit. It is necessary to reset the entire register because a full word must be used when writing just one bit.
Charge Pump Enabled, HP Amplifiers Disabled
The output amplifiers of the TPA6130A2 are enabled by placing a logic 1 in register 1, bits 6 and 7. Place a logic
0 in register 1, bits 6 and 7 to disable the output amplifiers. The left and right outputs can be enabled and
disabled individually. When the output amplifiers are disabled, the charge-pump remains on.
HiZ State
HiZ is enabled by placing a logic 1 in register 3, bits 0 and 1. Place a logic 0 in register 3, bits 0 and 1 to disable
the HiZ state of the outputs. The left and right outputs can be placed into a HiZ state individually.
The HiZ state puts the outputs into a state of high impedance. Use this configuration when the outputs of the
TPA6130A2 share traces with other devices whose outputs may be active.
Note that to use the HiZ mode, the TPA6130A2 MUST be active (not in SWS or hardware shutdown).
Furthermore, the output amplifiers must NOT be enabled.
Stereo Headphone Drive
The device is in this mode when the MODE bits in register 1 are 00 and both headphone enable bits are
enabled. The two amplifier channels operate independently. This mode is appropriate for stereo playback.
Dual Mono Headphone Drive
The device is in this mode when the MODE bits in register 1 are 01 and both headphone enable bits are
enabled. The left channel is the active input. It is amplified and distributed to both the left and right headphone
outputs.
Bridge-Tied Load Receiver Drive
The device is in this mode when the MODE bits in register 1 are 10 and both headphone enable bits are
enabled. In this mode, the device will take the left channel input and drive a single load connected between
HPLEFT and HPRIGHT in a bridge-tied fashion. The minimum load for bridge-tied mode is the same as for
stereo mode (see table entitled "Absolute Maximum Ratings").
19
TPA6130A2
www.ti.com
SLOS488A–NOVEMBER 2006–REVISED DECEMBER 2006
Default Mode
The TPA6130A2 starts up with the following conditions:
•
•
•
•
•
SWS = Off, CHARGE PUMP = On
HP ENABLES = Off
HiZ = Off
MODE = Stereo
HP MUTES = On, VOLUME = -59.5 dB,
VOLUME CONTROL
The TPA6130A2 volume control is set through the I2C interface. The six volume control register bits are decoded
to 64 volume settings that employ an audio taper. See Table 2 for the gain table. The values listed in this table
are typical. Each gain step has a different input impedance. See Figure 33.
Table 2. Audio Taper Gain Values
Gain Control Word
(Binary) Mute [7:6],
V[5:0]
Nominal Gain (dB) Nominal Gain (V/V)
Gain Control Word
(Binary) Mute [7:6],
V[5:0]
Nominal Gain
(dB)
Nominal Gain (V/V)
11XXXXXX
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
–100
–59.5
–53.5
–50.0
–47.5
–45.5
–43.9
–41.4
–39.5
–36.5
–35.3
–33.3
–31.7
–30.4
–28.6
–27.1
–26.3
–24.7
–23.7
–22.5
–21.7
–20.5
–19.6
–18.8
–17.8
–17.0
–16.2
–15.2
–14.5
–13.7
–13.0
–12.3
–11.6
0.00001
0.001
0.002
0.003
0.004
0.005
0.007
0.009
0.012
0.015
0.018
0.022
0.026
0.031
0.037
0.043
0.050
0.057
0.065
0.074
0.084
0.093
0.104
0.116
0.129
0.142
0.156
0.172
0.188
0.205
0.223
0.242
0.262
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111
00111000
00111001
00111010
00111011
00111100
00111101
00111110
00111111
–10.9
–10.3
–9.7
–9.0
–8.5
–7.8
–7.2
–6.7
–6.1
–5.6
–5.1
–4.5
–4.1
–3.5
–3.1
–2.6
–2.1
–1.7
–1.2
–0.8
–0.3
0.1
0.283
0.305
0.329
0.353
0.379
0.405
0.433
0.462
0.493
0.524
0.557
0.591
0.627
0.664
0.702
0.742
0.783
0.825
0.870
0.915
0.962
1.010
1.061
1.112
1.165
1.220
1.277
1.335
1.395
1.456
1.520
1.585
0.5
0.9
1.4
1.7
2.1
2.5
2.9
3.3
3.6
4.0
20
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
PACKAGING INFORMATION
Orderable Device
TPA6130A2RTJR
TPA6130A2RTJRG4
TPA6130A2RTJT
TPA6130A2RTJTG4
TPA6130A2YZHR
TPA6130A2YZHT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RTJ
20
20
20
20
16
16
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
QFN
RTJ
RTJ
RTJ
YZH
YZH
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DSBGA
DSBGA
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
250 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
MLA
MLA
Reel
Diameter Width
(mm)
Reel
A0 (mm)
4.3
B0 (mm)
4.3
K0 (mm)
1.5
P1
W
Pin1
(mm) (mm) Quadrant
(mm)
TPA6130A2RTJR
TPA6130A2RTJT
TPA6130A2YZHT
RTJ
RTJ
YZH
20
20
330
12
12
12
4
12 PKGORN
T2TR-MS
P
180
177
12
8
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
16 UNITIVE
2.2
2.2
0.68
8
NONE
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TPA6130A2RTJR
TPA6130A2RTJT
TPA6130A2YZHT
RTJ
RTJ
YZH
20
20
16
MLA
MLA
346.0
190.0
187.0
346.0
212.7
187.0
29.0
31.75
25.6
UNITIVE
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
D: 1.93 mm + 30 µm
E: 1.93 mm + 30 µm
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