TPA6211T-Q1 [TI]
汽车类 3.1W 单声道模拟输入 AB 类音频放大器;
| 型号： | TPA6211T-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 3.1W 单声道模拟输入 AB 类音频放大器 放大器 音频放大器 |
| 文件： | 总35页 (文件大小：2729K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA6211T-Q1
ZHCSKV6A –MARCH 2020 –REVISED JULY 2021
TPA6211T-Q1 汽车类3.1W 单声道模拟输入AB 类音频放大器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
TPA6211A1-Q 器件是一款 3.1W 单声道全差分放大
器，用于驱动阻抗至少为 3Ω 的扬声器，而在大多数
应用中仅占用 20‑mm2 的总印刷电路板 (PCB) 面积。
此器件在 2.5V 至 5.5V 电压范围内运行，仅消耗 4mA
静态电源电流。TPA6211T-Q1 器件采用节省空间的 8
引脚HVSSOP 封装。
– 器件温度等级2：–40°C 至105°C
– 器件HBM ESD 分类等级3A
– 器件CDM ESD 分类等级C6
• 在THD = 10%（典型值）时
可利用5V 电源向3Ω 负载输送3.1W 功率
• 低电源电流：电压为5V 时为4mA（典型值）
• 关断电流：0.01µA（典型值）
• 快速启动，具有极小杂音
• 仅三个外部组件
该器件包含如下特性：80dB 的电源电压抑制比（20Hz
至 2KHz），改善的 RF 整流抗扰度以及较小的 PCB
占用面积。杂音超低的快速启动特性使得 TPA6211T-
Q1 器件成为了紧急呼叫应用的理想选择。此外，该器
件可满足信息娱乐系统与仪表组应用中（例如仪表组提
示音或驾驶员通知）的低功耗需求。
– 针对直接电池供电运行，改进了PSRR (80dB)
和宽电源电压（2.5V 至5.5V）
– 全差分设计简化了射频
整流
– 63dB CMRR 省去了两个输入
耦合电容
器件信息(1)
封装尺寸（标称值）
器件型号
封装
HVSSOP (8)
TPA6211T-Q1
3.00mm × 3.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 汽车音频
• 紧急呼叫
• 驾驶员通知
• 仪表组蜂鸣装置
5 V DC
a
A.
C(BYPASS) 是可选的
应用电路
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS496
TPA6211T-Q1
ZHCSKV6A –MARCH 2020 –REVISED JULY 2021
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................18
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Applications.................................................. 19
9 Power Supply Recommendations................................25
9.1 Power Supply Decoupling Capacitor........................ 25
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 Receiving Notification of Documentation Updates..27
11.2 Community Resources............................................27
11.3 Trademarks............................................................. 27
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Operating Characteristics........................................... 6
6.7 Dissipation Ratings..................................................... 6
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................13
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (March 2020) to Revision A (July 2021)
Page
• Updated Thermal Information table.................................................................................................................... 4
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5 Pin Configuration and Functions
1
2
3
4
8
7
6
5
SHUTDOWN
VO–
BYPASS
IN+
GND
VDD
VO+
Thermal
Pad
IN–
Not to scale
图5-1. DGN Package 8-Pin HVSSOP Top View
表5-1. Pin Functions
PIN
NAME
BYPASS
I/O
DESCRIPTION
NO.
2
I
I
I
I
I
Mid-supply voltage, adding a bypass capacitor improves PSRR
High-current ground
GND
IN–
IN+
7
4
Negative differential input
3
Positive differential input
SHUTDOWN
Thermal Pad
1
Shutdown pin (active low logic)
Connect to ground. Thermal pad must be soldered down in all applications to properly secure device on
the PCB.
—
—
VDD
VO+
VO–
6
5
8
I
Power supply
O
O
Positive BTL output
Negative BTL output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted(1)
MIN
–0.3
–0.3
MAX
UNIT
Supply voltage, VDD
6
V
Input voltage, VI
VDD + 0.3 V
See 节6.7
V
Continuous total power dissipation
Lead temperature 1.6 mm (1/16 Inch) from case for 10 s
Operating free-air temperature, TA
Junction temperature, TJ
DGN
260
105
150
150
°C
°C
°C
°C
–40
–40
–65
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under 节6.3.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
2.5
MAX
UNIT
V
VDD
VIH
VIL
TA
Supply voltage
5.5
High-level input voltage
Low-level input voltage
Operating free-air temperature
SHUTDOWN
SHUTDOWN
1.55
V
0.5
V
105
°C
–40
6.4 Thermal Information
TPA6211T-Q1
THERMAL METRIC(1)
DGN (HVSSOP)
UNIT
8 PINS
53.9
72.7
26.4
3.5
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
26.3
10.2
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
TA = 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
0.3
MAX UNIT
Output offset voltage (measured
differentially)
VOS
VI = 0-V differential, Gain = 1 V/V, VDD = 5.5 V
9
mV
–9
PSRR
VIC
Power supply rejection ratio
Common mode input range
VDD = 2.5 V to 5.5 V
dB
V
–85
–60
DD –0.8
–40
VDD = 2.5 V to 5.5 V
0.5
V
VDD = 5.5 V, VIC = 0.5 V to 4.7 V
VDD = 2.5 V, VIC = 0.5 V to 1.7 V
–63
–63
0.45
0.37
0.26
CMRR Common mode rejection ratio
dB
–40
VDD = 5.5 V
RL = 4 Ω, VIN+ = VDD, VIN+ = 0 V,
Gain = 1 V/V, VIN– = 0 V or VIN– = VDD
Low-output swing
VDD = 3.6 V
VDD = 2.5 V
VDD = 2.5 V
0.4
V
Low-output swing (only for
TPA6211HTDGNRQ1)
0.46
RL = 4 Ω, VIN+ = VDD, VIN+ = 0 V,
Gain = 1 V/V, VIN– = 0 V or VIN– = VDD
TA = 105°C
VDD = 5.5 V
VDD = 3.6 V
VDD = 2.5 V
VDD = 2.5 V
4.95
3.18
2.13
RL = 4 Ω, VIN+ = VDD, VIN– = VDD
,
High-output swing
Gain = 1 V/V, VIN– = 0 V or VIN+ = 0 V
2
V
High-output swing (only for
TPA6211HTDGNRQ1)
1.95
RL = 4 Ω, VIN+ = VDD, VIN– = VDD
Gain = 1 V/V, VIN– = 0 V or VIN+ = 0 V
TA = 105°C
,
| IIH
| IIH
| IIL
| IIL
IQ
|
|
High-level input current, shutdown
VDD = 5.5 V, VI = 5.8 V
58
3
100
115
100
115
5
µA
µA
µA
µA
mA
mA
µA
µA
High-level input current, shutdown (only
for TPA6211HTDGNRQ1)
VDD = 5.5 V, VI = 5.8 V
TA = 105°C
|
Low-level input current, shutdown
VDD = 5.5 V, VI = –0.3 V
Low-level input current, shutdown (only
for TPA6211HTDGNRQ1)
VDD = 5.5 V, VI = –0.3 V
TA = 105°C
|
Quiescent current
VDD = 2.5 V to 5.5 V, no load
4
Quiescent current (only for
TPA6211HTDGNRQ1)
VDD = 2.5 V to 5.5 V, no load
TA = 105°C
IQ
5.7
1
I(SD)
I(SD)
Supply current
0.01
V
SHUTDOWN ≤0.5 V, VDD = 2.5 V to 5.5 V, RL = 4 Ω
Supply current (only for
TPA6211HTDGNRQ1)
V
SHUTDOWN ≤0.5 V, VDD = 2.5 V to 5.5 V, RL = 4 Ω
1.25
TA = 105°C
38 kW
RI
40 kW
RI
42 kW
Gain
V/V
RL = 4 Ω
RI
44.4 kꢀ
RI
RL = 4 Ω
TA = 105°C
Gain (only for TPA6211HTDGNRQ1)
Resistance from shutdown to GND
V/V
100
kΩ
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MAX UNIT
6.6 Operating Characteristics
TA = 25°C, Gain = 1 V/V
PARAMETER
TEST CONDITIONS
VDD = 5 V
MIN
TYP
2.45
1.22
0.49
2.22
1.1
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
THD + N = 1%, f = 1 kHz, RL = 3 Ω
THD + N = 1%, f = 1 kHz, RL = 4 Ω
THD + N = 1%, f = 1 kHz, RL = 8 Ω
PO
Output power
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
W
0.47
1.36
0.72
0.33
0.045%
0.05%
0.06%
0.03%
0.03%
0.04%
0.02%
0.02%
0.03%
–80
–70
105
VDD = 3.6 V
VDD = 2.5 V
PO = 2 W, VDD = 5 V
PO = 1 W, VDD = 3.6 V
PO = 300 mW, VDD = 2.5 V
PO = 1.8 W, VDD = 5 V
PO = 0.7 W, VDD = 3.6 V
PO = 300 mW, VDD = 2.5 V
PO = 1 W, VDD = 5 V
f = 1 kHz, RL = 3 Ω
f = 1 kHz, RL = 4 Ω
f = 1 kHz, RL = 8 Ω
THD+N Total harmonic distortion plus noise
PO = 0.5 W, VDD = 3.6 V
PO = 200 mW, VDD = 2.5 V
f = 217 Hz
VDD = 3.6 V, Inputs AC-grounded with
CI = 2 µF, VRIPPLE = 200 mVpp
kSVR
SNR
Vn
Supply ripple rejection ratio
Signal-to-noise ratio
dB
dB
f = 20 Hz to 20 kHz
VDD = 5 V, PO = 2 W, RL = 4 Ω
No weighting
A weighting
f = 217 Hz
15
VDD = 3.6 V, f = 20 Hz to 20 kHz,
Inputs AC-grounded with CI = 2 µF
Output voltage noise
µVRMS
dB
12
CMRR Common mode rejection ratio
VDD = 3.6 V, VIC = 1 Vpp
–65
40
ZI
Input impedance
38
44
kΩ
µs
VDD = 3.6 V, No CBYPASS
4
Start-up time from shutdown
VDD = 3.6 V, CBYPASS = 0.1 µF
27
ms
6.7 Dissipation Ratings
DERATING
FACTOR(1)
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA ≤25°C
POWER RATING
PACKAGE
DGN
2.13 W
17.1 mW/°C
1.36 W
1.11 W
(1) Derating factor based on High-k board layout.
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Typical Characteristics
表6-1. Table of Graphs
FIGURE
vs Supply voltage
图6-1
Output power
vs Load resistance
vs Output power
图6-2
Power dissipation
图6-3, 图6-4
vs Output power
图6-5, 图6-6, 图6-7
Total harmonic distortion + noise
vs Frequency
图6-8, 图6-9, 图6-10, 图6-11, 图6-12
vs Common-mode input voltage
vs Frequency
图6-13
Supply voltage rejection ratio
Supply voltage rejection ratio
GSM Power supply rejection
GSM Power supply rejection
图6-14, 图6-15, 图6-16, 图6-17
vs Common-mode input voltage
vs Time
图6-18
图6-19
图6-20
图6-21
图6-22
图6-23
图6-24
图6-25
图6-26
图6-27
vs Frequency
vs Frequency
Common-mode rejection ratio
vs Common-mode input voltage
vs Frequency
Closed loop gain/phase
Open loop gain/phase
vs Frequency
vs Supply voltage
vs Shutdown voltage
vs Bypass capacitor
Supply current
Start-up time
3.5
3.5
3
f = 1 kHz
Gain = 1 V/V
3
f = 1 kHz
V
DD
= 5 V, THD 10%
P
O
= 3 Ω, THD 10%
Gain = 1 V/V
V
DD
= 5 V, THD 1%
P
O
= 4 Ω, THD 10%
2.5
P
= 3 Ω, THD 1%
2.5
2
O
V
DD
= 3.6 V, THD 10%
P
O
= 4 Ω, THD 1%
2
P
O
= 8 Ω, THD 10%
V
DD
= 3.6 V, THD 1%
P
O
= 8 Ω, THD 1%
1.5
1.5
1
V
DD
= 2.5 V, THD 10%
V
DD
= 2.5 V, THD 1%
1
0.5
0
0.5
0
2.5
3
3.5
4
4.5
5
3
8
13
18
23
28
V
DD
- Supply Voltage - V
R
L
- Load Resistance - Ω
图6-1. Output Power vs Supply Voltage
图6-2. Output Power vs Load Resistance
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1.4
1.2
0.8
4 Ω
V
DD
= 3.6 V
V
DD
= 5 V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4 Ω
1
0.8
8 Ω
0.6
0.4
0.2
8 Ω
0
0
0.3
0.6
0.9
1.2
1.5
1.8
0
0.3
0.6
P - Output Power - W
O
0.9
1.2
1.5
1.8
P
- Output Power - W
O
图6-3. Power Dissipation vs Output Power
图6-4. Power Dissipation vs Output Power
20
10
R
C
= 4 Ω
R
C
= 3 Ω
L
,
L
,
10
5
5
2
= 0 to 1 µF,
= 0 to 1 µF,
(BYPASS)
(BYPASS)
Gain = 1 V/V
Gain = 1 V/V
2
1
1
0.5
0.5
0.2
0.1
2.5 V
2.5 V
3.6 V
3.6 V
0.2
0.1
5 V
5 V
0.05
0.05
0.02
0.01
0.02
0.01
20m
50m 100m 200m 500m
- Output Power - W
1
2
3
10m 20m
50m 100m 200m 500m
P - Output Power - W
O
1
2 3
P
O
图6-5. Total Harmonic Distortion + Noise vs Output 图6-6. Total Harmonic Distortion + Noise vs Output
Power Power
20
10
5
V
= 5 V,
= 3 Ω,
R
C
= 8 Ω
DD
L
,
10
5
R
C
= 0 to 1 µF,
L
,
(BYPASS)
= 0 to 1 µF,
Gain = 1 V/V
(BYPASS)
Gain = 1 V/V,
C = 2 µF
2
1
I
2
1
0.5
1 W
2.5 V
0.5
0.2
0.1
3.6 V
0.2
0.1
2 W
5 V
0.05
0.05
0.02
0.01
0.02
0.01
0.005
10m 20m
50m 100m 200m 500m
- Output Power - W
1
2 3
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
P
O
图6-7. Total Harmonic Distortion + Noise vs Output
图6-8. Total Harmonic Distortion + Noise vs
Power
Frequency
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10
5
10
V
R
C
= 3.6 V,
V
= 5 V,
DD
DD
= 4 Ω,
R
C
= 4 Ω,
L
,
5
2
L
,
= 0 to 1 µF,
= 0 to 1 µF,
(BYPASS)
(BYPASS)
2
1
Gain = 1 V/V,
C = 2 µF
Gain = 1 V/V,
C = 2 µF
1 W
I
I
1
0.5
2 W
0.1 W
0.5 W
0.5
0.2
0.1
1.8 W
1 W
0.2
0.05
0.1
0.02
0.01
0.05
0.005
0.02
0.01
0.002
0.001
0.005
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
20
50 100 200 500
f - Frequency - Hz
1k 2k
5k 10k 20k
图6-10. Total Harmonic Distortion + Noise vs
图6-9. Total Harmonic Distortion + Noise vs
Frequency
Frequency
10
10
V
= 2.5 V,
V
= 3.6 V,
= 8 Ω,
DD
DD
5
5
R
C
= 4 Ω,
R
C
L
,
L
,
= 0 to 1 µF,
= 0 to 1 µF,
(BYPASS)
(BYPASS)
2
1
2
1
Gain = 1 V/V,
C = 2 µF
Gain = 1 V/V,
C = 2 µF
I
I
0.5
0.2
0.5
0.25 W
0.4 W
0.6 W
0.1 W
0.2
0.28 W
0.1
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20 50 100 200
500 1k 2k
5k 10k 20k
20 50 100 200
500 1k 2k
5k 10k 20k
f - Frequency - Hz
f - Frequency - Hz
图6-11. Total Harmonic Distortion + Noise vs
图6-12. Total Harmonic Distortion + Noise vs
Frequency
Frequency
0.06
+0
R
C
= 4 Ω,
L
,
f = 1 kHz
0.058
-10
-20
-30
-40
-50
-60
-70
-80
= 0.47 µF,
(BYPASS)
P
O
= 200 mW,
= 1 kHz
Gain = 1 V/V,
R
L
0.056
0.054
0.052
0.05
C = 2 µF,
I
Inputs ac Grounded
V
= 2.5 V
= 3.6 V
DD
V
DD
= 5 V
0.048
0.046
0.044
0.042
0.04
V
= 3.6 V
DD
V
DD
= 2.5 V
V
DD
-90
V
DD
= 5 V
-100
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
0
1
2
3
4
5
V
IC
- Common Mode Input Voltage - V
图6-13. Total Harmonic Distortion + Noise vs
图6-14. Supply Voltage Rejection Ratio vs
Common-Mode Input Voltage
Frequency
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+0
+0
R
C
= 4 Ω,
R
C
= 4 Ω,
L
,
L
,
-10
-20
-30
-40
-50
-60
-70
-80
-10
= 0.47 µF,
= 0.47 µF,
(BYPASS)
(BYPASS)
Gain = 5 V/V,
C = 2 µF,
I
-20
-30
-40
-50
-60
-70
-80
C = 2 µF,
I
Inputs ac Grounded
V
= 2.5 V to 5 V
Inputs Floating
DD
V
DD
= 3.6 V
V
DD
= 2.5 V
V
DD
= 5 V
-90
-90
-100
-100
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
图6-15. Supply Voltage Rejection Ratio vs
图6-16. Supply Ripple Rejection Ratio vs
Frequency
Frequency
+0
0
R
= 4 Ω,
L
C = 2 µF,
,
R
= 4 Ω,
L
C = 2 µF,
,
−10
−20
−30
−40
−50
−60
−70
−80
I
Gain = 1 V/V,
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
I
Gain = 1 V/V,
V
DD
= 3.6 V
C
= 0.47 µF
(BYPASS)
= 3.6 V,
V
DD
f = 217 Hz,
Inputs ac Grounded
V
DD
= 2.5 V
V
DD
= 3.6 V
C
= 0.1 µF
(BYPASS)
No C
(BYPASS)
V
DD
= 5 V
C
= 1 µF
(BYPASS)
−90
C
= 0.47 µF
(BYPASS)
−100
20
50 100 200 500 1k 2k
f − Frequency − Hz
5k 10k 20k
0
1
2
3
4
5
6
DC Common Mode Input − V
图6-17. Supply Voltage Rejection Ratio vs
图6-18. Supply Voltage Rejection Ratio vs DC
Frequency
Common-Mode Input
0
V
DD
C1
−50
Frequency
217 Hz
C1 − Duty
20%
−100
C1 Pk−Pk
500 mV
V
R
Shown in Figure 19,
= 8 Ω,
DD
−150
L
−100
−120
−140
C = 2.2 µF,
I
Inputs Grounded
R
= 8 Ω
L
C = 2.2 µF
I
V
OUT
C
= 0.47 µF
(BYPASS)
−160
−180
C
= 0.47 µF
(BYPASS)
2 ms/div
Ch1 100 mV/div
Ch4 10 mV/div
0
400
800
1200
1600
2000
t − Time − ms
f − Frequency − Hz
图6-19. GSM Power Supply Rejection vs Time
图6-20. GSM Power Supply Rejection vs
Frequency
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0
+0
R
L
= 4 Ω,
,
R
= 4 Ω,
L
Gain = 1 V/V,
,
-10
-20
-30
-40
-50
-60
-70
-80
V
IC
Gain = 1 V/V,
= 200 mV V
,
p-p
-10
dc Change in V
IC
-20
-30
-40
-50
-60
-70
V
DD
= 2.5 V
V
DD
= 2.5 V
V
DD
= 5 V
V
DD
= 3.5 V
V
DD
= 5 V
-80
-90
-90
-100
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
IC
- Common Mode Input Voltage - V
图6-21. Common-Mode Rejection Ratio vs
图6-22. Common-Mode Rejection Ratio vs
Frequency
Common-Mode Input Voltage
40
100
180
150
180
V
= 5 V,
DD
Phase
90
80
70
60
30
R
= 8 Ω
150
L
120
90
20
10
120
90
60
60
0
Gain
50
40
30
20
10
Gain
30
-10
30
0
-20
-30
-40
0
−30
−60
−90
−120
−150
−180
-30
-60
Phase
0
-50
-60
-70
-80
-90
−10
V
= 5 V
-120
DD
−20
R
= 8 Ω
= 1
L
−30
−40
-150
-180
A
V
100
1 k
10 k
f − Frequency − Hz
100 k
1 M
1
10
100
1 k 10 k 100 k 1 M 10 M
f - Frequency - Hz
图6-24. Open Loop Gain/Phase vs Frequency
图6-23. Closed Loop Gain/Phase vs Frequency
5
10
V
DD
= 5 V
T
= 125°C
= 25°C
A
4.5
V
DD
= 5 V
1
0.1
4
V
= 3.6 V
DD
T
3.5
A
V
= 2.5 V
DD
3
2.5
2
T
A
= -40°C
0.01
0.001
0.0001
0.00001
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1
0
2
3
4
5
V
DD
- Supply Voltage - V
Voltage on SHUTDOWN Terminal - V
图6-25. Supply Current vs Supply Voltage
图6-26. Supply Current vs Shutdown Voltage
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300
250
200
150
100
50
0
0
0.2
0.4
0.6
0.8
1
C
- Bypass Capacitor - µF
(Bypass)
图6-27. Start-up Time vs Bypass Capacitor
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7 Detailed Description
7.1 Overview
The TPA6211T-Q1 device is a fully differential amplifier with differential inputs and outputs. The fully differential
amplifier consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that
the amplifier outputs a differential voltage that is equal to the differential input times the gain. The common-mode
feedback ensures that the common-mode voltage at the output is biased around VDD / 2 regardless of the
common-mode voltage at the input.
7.2 Functional Block Diagram
5 V DC
A. C(BYPASS) is optional
7.3 Feature Description
7.3.1 Advantages of Fully Differential Amplifiers
Input coupling capacitors are not required. A fully differential amplifier with good CMRR, such as the TPA6211T-
Q1 device, allows the inputs to be biased at voltage other than mid-supply. For example, if a DAC has a lower
mid-supply voltage than that of the TPA6211T-Q1 device, the common-mode feedback circuit compensates, and
the outputs are still biased at the mid-supply point of the TPA6211T-Q1 device. The inputs of the TPA6211T-Q1
device can be biased from 0.5 V to VDD – 0.8 V. If the inputs are biased outside of that range, input coupling
capacitors are required.
A Mid-supply bypass capacitor, CBYPASS, is not required. The fully differential amplifier does not require a bypass
capacitor. Any shift in the mid-supply voltage affects both positive and negative channels equally, thus canceling
at the differential output. Removing the bypass capacitor slightly worsens power supply rejection ratio (kSVR), but
a slight decrease of kSVR can be acceptable when an additional component can be eliminated (see 图6-17).
The RF-immunity is improved. A fully differential amplifier cancels the noise from RF disturbances much better
than the typical audio amplifier.
7.3.2 Fully Differential Amplifier Efficiency and Thermal Information
Class-AB amplifiers are inefficient, primarily because of voltage drop across the output-stage transistors. The
two components of this internal voltage drop are the headroom or DC voltage drop that varies inversely to output
power, and the sinewave nature of the output. The total voltage drop can be calculated by subtracting the RMS
value of the output voltage from VDD. The internal voltage drop multiplied by the average value of the supply
current, IDD(avg), determines the internal power dissipation of the amplifier.
An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power
supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the
load and in the amplifier, the current and voltage waveform shapes must first be understood (see 图7-1).
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V
O
V
(LRMS)
I
DD
I
DD(avg)
图7-1. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are
different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified
shape, whereas in BTL the current waveform is a full-wave rectified waveform. This means RMS conversion
factors are different. Keep in mind that for most of the waveform both the push and pull transistors are not on at
the same time, which supports the fact that each amplifier in the BTL device only draws current from the supply
for half the waveform. 方程式1 to 方程式10 are the basis for calculating amplifier efficiency.
PL
hBTL
=
PSUP
(1)
where
BTL is the efficiency of a BTL amplifier
•
ŋ
• PL is the power delivered to load
• PSUP is the power drawn from power supply
PL is calculated with 方程式2, and VLRMS is calculated with 方程式3.
2
VLRMS
PL =
RL
(2)
where
• VLRMS = RMS voltage on BTL load
• RL is load resistance
VP
=
VLRMS
2
(3)
where
• VP is peak voltage on BTL load
Therefore, PL can be given as 方程式4.
2
VP
PL =
2´RL
(4)
(5)
PSUP is calculated with 方程式5.
PSUP = VDD × IDDavg
where
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• VDD is power supply voltge
• IDDavg is average current drawn from the power supply
IDDavg is calculated with 方程式6.
p VP
VP
RL
2´ VP
p´RL
1
1 ò0
IDDavg =
´ sin(t)´ dt = –
´
´cos(t)0p
=
p
RL
p
(6)
(7)
Therefore, PSUP can be given as 方程式7.
2´ VDD ´ VP
PSUP
=
p´RL
Substituting for PL and PSUP, 方程式1 becomes 方程式8
2
VP
p´ VP
2´RL
hBTL
=
=
2´VDD´VP
p´RL
4´ VDD
(8)
(9)
VP is calculated with 方程式9.
VP 2´PL ´RL
=
And substituting for VP, ŋBTL can be calculated with 方程式10
p 2´PL ´RL
hBTL
=
4´ VDD
(10)
A simple formula for calculating the maximum power dissipated (PDmax) can be used for a differential output
application:
2VD2D
PDmax
=
p2RL
(11)
表7-1. Efficiency and Maximum Ambient Temperature vs Output Power
OUTPUT POWER
5-V, 3-Ω SYSTEMS
0.5 W
EFFICIENCY
INTERNAL DISSIPATION
POWER FROM SUPPLY
MAX AMBIENT TEMPERATURE
27.2%
38.4%
60.2%
67.7%
1.34 W
1.6 W
1.84 W
2.6 W
54°C
35°C
34°C
44°C
1 W
2.45 W
1.62 W
1.48 W
4.07 W
4.58 W
3.1 W
5-V, 4-Ω BTL SYSTEMS
0.5 W
31.4%
44.4%
62.8%
74.3%
1.09 W
1.25 W
1.18 W
0.97 W
1.59 W
2.25 W
3.18 W
3.77 W
72°C
60°C
65°C
80°C
1 W
2 W
2.8 W
5-V, 8-Ω SYSTEMS
105°C (limited by maximum ambient
temperature specification)
0.5 W
1 W
44.4%
62.8%
0.625 W
0.592 W
1.13 W
1.6 W
105°C (limited by maximum ambient
temperature specification)
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表7-1. Efficiency and Maximum Ambient Temperature vs Output Power (continued)
OUTPUT POWER
EFFICIENCY
INTERNAL DISSIPATION
POWER FROM SUPPLY
MAX AMBIENT TEMPERATURE
105°C (limited by maximum ambient
temperature specification)
1.36 W
73.3%
0.496 W
1.86 W
105°C (limited by maximum ambient
temperature specification)
1.7 W
81.9%
0.375 W
2.08 W
方程式 10 is used to calculate efficiencies for four different output power levels, see 表 7-1. The efficiency of the
amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a
nearly flat internal power dissipation over the normal operating range. The internal dissipation at full output
power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper
power supply design. For a 2.8-W audio system with 4-Ω loads and a 5-V supply, the maximum draw on the
power supply is almost 3.8 W.
A final point to remember about Class-AB amplifiers is how to manipulate the terms in the efficiency equation to
the utmost advantage when possible. In 方程式 10, VDD is in the denominator. This indicates that as VDD goes
down, efficiency goes up.
The maximum ambient temperature depends on the heat sinking ability of the PCB system. Given Rθ JA
(junction-to-ambient thermal resistance), the maximum allowable junction temperature, and the internal
dissipation at 1-W output power with a 4-Ohm load, the maximum ambient temperature can be calculated with 方
程式12. The maximum recommended junction temperature for the TPA6211T-Q1 device is 150°C.
TA (Max) = TJ(Max) -RqJA ´PD = 150 - 71.7´1.25 = 60°C
(12)
方程式 12 shows that the maximum ambient temperature is 60°C at 1-W output power and 4-Ohm load with a 5-
V supply.
表 7-1 shows that the thermal performance must be considered when using a Class-AB amplifier to keep
junction temperatures in the specified range. The TPA6211T-Q1 device is designed with thermal protection that
turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. In addition,
using speakers with an impedance higher than 4 Ω dramatically increases the thermal performance by reducing
the output current.
7.3.3 Differential Output Versus Single-Ended Output
图 7-2 shows a Class-AB audio power amplifier (APA) in a fully differential configuration. The TPA6211T-Q1
amplifier has differential outputs driving both ends of the load. One of several potential benefits to this
configuration is power to the load. The differential drive to the speaker means that as one side is slewing up, the
other side is slewing down, and vice versa. This in effect doubles the voltage swing on the load as compared to
a ground-referenced load. Plugging 2 × VO(PP) into the power equation (方程式 13) yields four-times the output
power (as the voltage is squared) from the same supply rail and load impedance (see 方程式15 and 方程式16).
VO(PP)
V
=
(rms)
2 2
2
V
(rms)
Power =
RL
(13)
(14)
2
V
æ
ç
è
O(PP) ö
÷
2
2
V
VO(PP)
8RL
2 2
RL
(rms)
ø
Power
=
=
=
(S-E)
RL
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2
2 ´ V
O(PP) ö
æ
ç
è
÷
2
2
V
VO(PP)
2RL
2 2
RL
(rms)
ø
Power
=
=
=
(Diff)
RL
(15)
(16)
Power
= 4 ´ Power
(Diff)
(S-E)
V
DD
V
O(PP)
2x V
O(PP)
R
L
V
DD
-V
O(PP)
图7-2. Differential Output Configuration
In a typical automotive application operating at 5 V, bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 390 mW to 1.56 W. This is a 6-dB improvement in sound power, or
loudness of the sound. In addition to increased power, there are frequency-response concerns. Consider the
single-supply SE configuration shown in 图 7-3. A coupling capacitor (CC) is required to block the DC-offset
voltage from the load. This capacitor can be quite large (approximately 33 µF to 1000 µF) so it tends to be
expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting low-frequency
performance. This frequency-limiting effect is due to the high-pass filter network created with the speaker
impedance and the coupling capacitance. This is calculated with 方程式17.
1
fc =
2pRLCC
(17)
For example, a 68-µF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL
configuration cancels the DC offsets, which eliminates the need for the blocking capacitors. Low-frequency
performance is then limited only by the input network and speaker response. Cost and PCB space are also
minimized by eliminating the bulky coupling capacitor.
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V
DD
V
O(PP)
C
C
R
V
O(PP)
L
-3 dB
f
c
图7-3. Single-Ended Output and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increased
dissipation is understandable considering that the BTL configuration produces four-times the output power of the
SE configuration.
7.4 Device Functional Modes
The TPA6211T-Q1 device can be put in shutdown mode when asserting SHUTDOWN pin to a logic LOW. While
in shutdown mode, the device output stage is turned off and set into high impedance, making the current
consumption very low. The device exits shutdown mode when a HIGH logic level is applied to SHUTDOWN pin.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The TPA6211T-Q1 is a fully-differential amplifier designed to drive a speaker with at least 3-Ω impedance while
consuming only 20-mm2 total printed-circuit board (PCB) area in most applications.
8.2 Typical Applications
图 8-1 shows a typical application circuit for the TPA6211T-Q1 with a speaker, input resistors, and supporting
power supply decoupling capacitors.
8.2.1 Typical Differential Input Application
5 V DC
Copyright © 2016, Texas Instruments Incorporated
A. C(BYPASS) is optional
图8-1. Typical Differential Input Application Schematic
Typical values are shown in 表8-1.
表8-1. Typical Component Values
COMPONENT
VALUE
RI
40 kΩ
(1)
CBYPASS
0.22 µF
1 µF
CS
CI
0.22 µF
(1) CBYPASS is optional.
8.2.1.1 Design Requirements
For this design example, use the parameters listed in 表8-2 as the input parameters.
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表8-2. Design Parameters
PARAMETER
EXAMPLE VALUE
2.5 V to 5.5 V
4 mA to 5 mA
High > 1.55 V
Low < 0.5 V
Power supply voltage
Current
Shutdown
Speaker
3 Ω, 4 Ω, or 8 Ω
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Resistors (RI)
The input resistor (RI) can be selected to set the gain of the amplifier according to 方程式18.
RF
Gain =
RI
(18)
The internal feedback resistors (RF) are trimmed to 40 kΩ.
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and the cancellation of the second harmonic
distortion diminishes if resistor mismatch occurs. Therefore, TI recommends 1%-tolerance resistors or better to
optimize performance.
8.2.1.2.2 Bypass Capacitor (CBYPASS) and Start-Up Time
The internal voltage divider at the BYPASS pin of this device sets a mid-supply voltage for internal references
and sets the output common mode voltage to VDD / 2. Adding a capacitor filters any noise into this pin,
increasing kSVR. CBYPASS also determines the rise time of VO+ and VO– when the device exits shutdown. The
larger the capacitor, the slower the rise time.
8.2.1.2.3 Input Capacitor (CI)
The TPA6211T-Q1 device does not require input coupling capacitors when driven by a differential input source
biased from 0.5 V to VDD – 0.8 V. Use 1% tolerance or better gain-setting resistors if not using input coupling
capacitors.
In the single-ended input application, an input capacitor (CI) is required to allow the amplifier to bias the input
signal to the proper DC level. In this case, CI and RI form a high-pass filter with the corner frequency defined in
方程式19.
1
fc =
2pRICI
(19)
-3 dB
f
c
图8-2. Input Filter Cutoff Frequency
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The value of CI is an important consideration, as it directly affects the bass (low frequency) performance of the
circuit. Consider the example where RI is 10 kΩ and the specification calls for a flat bass response down to
100 Hz. 方程式19 is reconfigured as 方程式20.
1
CI =
2pRIfc
(20)
In this example, CI is 0.16 µF, so the likely choice ranges from 0.22 µF to 0.47 µF. TI recommends the use of
ceramic capacitors because they are the best choice in preventing leakage current. When polarized capacitors
are used, the positive side of the capacitor faces the amplifier input in most applications. The input DC level is
held at VDD / 2, typically higher than the source DC level. Confirming the capacitor polarity in the application is
important.
8.2.1.2.4 Band-Pass Filter (RI, CI, and CF)
Having signal filtering beyond the one-pole high-pass filter formed by the combination of CI and RI can be
desirable. A low-pass filter can be added by placing a capacitor (CF) between the inputs and outputs, forming a
band-pass filter.
An example of when this technique might be used would be in an application where the desirable pass-band
range is between 100 Hz and 10 kHz, with a gain of 4 V/V. 方程式 21 to 方程式 28 allow the proper values of CF
and CI to be determined.
8.2.1.2.4.1 Step 1: Low-Pass Filter
1
fc(LPF)
=
2pRFCF
(21)
(22)
1
fc(LPF)
=
2p40kWCF
Therefore,
1
CF =
2p40 kW fc(LPF)
(23)
(24)
Substituting 10 kHz for fc(LPF) and solving for CF:
CF = 398 pF
8.2.1.2.4.2 Step 2: High-Pass Filter
1
fc(HPF)
=
2pRICI
(25)
(26)
Because the application in this case requires a gain of 4 V/V, RI must be set to 10 kΩ.
Substituting RI into 方程式25.
1
fc(HPF)
=
2p10 kW CI
Therefore,
1
CI =
2p10 kW fc(HPF)
(27)
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Substituting 100 Hz for fc(HPF) and solving for CI:
CI = 0.16 µF
(28)
At this point, a first-order band-pass filter has been created with the low-frequency cutoff set to 100 Hz and the
high-frequency cutoff set to 10 kHz.
The process can be taken a step further by creating a second-order high-pass filter. This is accomplished by
placing a resistor (Ra) and capacitor (Ca) in the input path. Ra must be at least 10 times smaller than RI;
otherwise its value has a noticeable effect on the gain, as Ra and RI are in series.
8.2.1.2.4.3 Step 3: Additional Low-Pass Filter
Ra must be at least ten-times smaller than RI. Set Ra = 1 kΩ
1
fc(LPF)
=
2pRaCa
(29)
Therefore,
1
Ca =
2p 1kW fc(LPF)
(30)
(31)
Substituting 10 kHz for fc(LPF) and solving for Ca:
Ca = 160 pF
图 8-3 is a bode plot for the band-pass filter in the previous example. 图 8-8 shows how to configure the
TPA6211T-Q1 device as a band-pass filter.
AV
12 dB
9 dB
−20 dB/dec
+20 dB/dec
−40 dB/dec
f
= 100 Hz
f
= 10 kHz
c(LPF)
c(HPF)
f
图8-3. Bode Plot
8.2.1.2.5 Decoupling Capacitor (CS)
The TPA6211T-Q1 device is a high-performance CMOS audio amplifier that requires adequate power supply
decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling
also prevents oscillations for long lead lengths between the amplifier and the speaker. For higher frequency
transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor,
typically 0.1 µF to 1 µF, placed as close as possible to the device VDD lead works best. For filtering lower
frequency noise signals, a 10-µF or greater capacitor placed near the audio power amplifier also helps, but is not
required in most applications because of the high PSRR of this device.
8.2.1.2.6 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
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8.2.1.3 Application Curves
3.5
3.5
3
PO = 8 W, THD 1%
VDD = 2.5 V, THD 1%
VDD = 2.5 V, THD 10%
VDD = 3.6 V, THD 1%
VDD = 3.6 V, THD 10%
VDD = 5 V, THD 1%
VDD = 5 V, THD 10%
PO = 8 W, THD 10%
3
PO = 4 W, THD 1%
PO = 3 W, THD 1%
PO = 4 W, THD 10%
PO = 3 W, THD 10%
2.5
2.5
2
2
1.5
1
1.5
1
0.5
0
0.5
0
2.5
3
3.5 4
Supply Voltage (V)
4.5
5
3
8
13
18
23
28
33
Load Resistance (W)
D002
D001
图8-4. Output Power vs Supply Voltage
图8-5. Output Power vs Load Resistance
8.2.2 Other Application Circuits
图8-6, 图8-7, and 图8-8 show example circuits using the TPA6211T-Q1 device.
5 V DC
C
C
Copyright © 2016, Texas Instruments Incorporated
A. C(BYPASS) is optional
图8-6. Differential Input Application Schematic Optimized With Input Capacitors
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5 V DC
C
C
Copyright © 2016, Texas Instruments Incorporated
A. C(BYPASS) is optional
图8-7. Single-Ended Input Application Schematic
C
F
C
F
5 V DC
C
C
C
C
Copyright © 2016, Texas Instruments Incorporated
A. C(BYPASS) is optional
图8-8. Differential Input Application Schematic With Input Bandpass Filter
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9 Power Supply Recommendations
The TPA6211T-Q1 device is designed to operate from an input voltage supply range between 2.5 V and 5.5 V.
Therefore, the output voltage range of power supply must be within this range and well regulated. The current
capability of upper power should not exceed the maximum current limit of the power switch.
9.1 Power Supply Decoupling Capacitor
The TPA6211T-Q1 device requires adequate power supply decoupling to ensure a high efficiency operation with
low total harmonic distortion (THD). Place a low equivalent series resistance (ESR) ceramic capacitor, typically
0.1 µF, as close as possible of the VDD pin. This choice of capacitor and placement helps with higher frequency
transients, spikes, or digital hash on the line. TI recommends placing a 2.2-µF to 10-µF capacitor on the VDD
supply trace. This larger capacitor acts as a charge reservoir, providing energy faster than the board supply, thus
helping to prevent any droop in the supply voltage.
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10 Layout
10.1 Layout Guidelines
Place all the external components close to the TPA6211T-Q1 device. The input resistors need to be close to the
device input pins so noise does not couple on the high impedance nodes between the input resistors and the
input amplifier of the device. Placing the decoupling capacitors, CS and CBYPASS, close to the TPA6211T-Q1
device is important for the efficiency of the amplifier. Any resistance or inductance in the trace between the
device and the capacitor can cause a loss in efficiency.
10.2 Layout Example
图10-1. TPA6211T-Q1 8-Pin HVSSOP (DGN) Board Layout
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
11.3 Trademarks
所有商标均为其各自所有者的财产。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPA6211TDGNRQ1
ACTIVE
HVSSOP
DGN
8
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
6211Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA6211TDGNRQ1
HVSSOP DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HVSSOP DGN
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
TPA6211TDGNRQ1
8
2500
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.846
1.646
4225480/B 12/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
(1.89)
9
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225480/B 12/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(1.89)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
0.125
0.15
0.175
1.33 X 1.60
4225480/B 12/2022
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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