TPA6304QDDVRQ1 [TI]
45W、2.1MHz 模拟输入 4 通道汽车 D 类 Burr-Brown™ 音频放大器 | DDV | 44 | -40 to 125;
| 型号： | TPA6304QDDVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 45W、2.1MHz 模拟输入 4 通道汽车 D 类 Burr-Brown™ 音频放大器 | DDV | 44 | -40 to 125 放大器 音频放大器 |
| 文件： | 总122页 (文件大小：3634K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA6304-Q1
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
TPA6304-Q1 具有负载突降保护和I2C 诊断功能的45W、2.1MHz 模拟输入4 通道
汽车用D 类Burr-Brown™ 音频放大器
1 特性
2 应用
• 高效率D 类
• 汽车音响主机
• 汽车外部放大器模块
– 效率显著高于AB 类
– 改善了散热解决方案，与AB 类相比，热耗散降
低75%
• 启动/停止操作低至4.5V
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1：–40°C 至125°C TA
– HBM ESD 分类等级2
3 说明
TPA6304-Q1 器件是一款采用 2.1MHz PWM 开关频率
的四通道模拟输入 D 类 Burr-Brown™ 音频放大器，可
实现经成本优化的解决方案，PCB 尺寸非常小，仅为
2.7cm2，具有高阻抗单端输入，启动/停止过程中可在
低至4.5V 的电压下全面运行。
– CDM ESD 分类等级C2B
• 在4Ω 负载、14.4V 电源电压的条件下，输出功率
为27W，THD 为10%
– 驱动4Ω 和2Ω 负载
• 负载诊断功能
TPA6304-Q1 D 类音频放大器的设计十分出色，可适
用于入门级汽车音响主机，以作为系统设计的一部分提
供模拟音频输入信号。与传统的线性放大器解决方案相
比，D 类拓扑技术显著提高了器件效率。
– 开路和短路输出负载
– 输出至电池短路或接地短路
– 连接高频扬声器
输出开关频率既可以设置为高于 AM 频带，以便消除
AM 频带干扰并降低输出滤波器尺寸及成本；也可以设
置为低于AM 频带，以便进一步优化效率。
• 采用高级栅极驱动设计以满足CISPR25-L5 EMC
规范
该器件采用带外露散热焊盘的 44 引脚 HTSSOP 封
装。
– D 类音频放大器，2.1MHz 开关频率，无AM 干
扰
– 扩频模式、相位偏移、压摆率控制
• 保护功能
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPA6304-Q1
HTSSOP (44)
14.00mm x 6.10mm
– 40V 负载突降保护
– 输出短路保护
– 直流失调电压和过热保护
– 意外接地开路和电源开路保护
• 音频输入
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 四通道单端模拟输入
– 10dB、16dB、22dB 或28dB 增益选项
• 支持通道并联驱动(PBTL)
• 在4Ω 负载和14.4V、1kHz 条件下的音频性能
– THD+N < 0.006%
– 42µVRMS 输出噪声
– 80dB PSRR
– 效率> 80%
• 特性
参考板
– 可编程削波探测
– 负载电流限制器
– 热增益和热折返
– 快速、自动启动诊断功能
– 在负载电流< 10mA 的条件下进行
交流负载阻抗测量
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEP6
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
Table of Contents
7.5 Programming............................................................ 43
7.6 Register Maps...........................................................47
8 Application Information Disclaimer...........................104
8.1 Application Information........................................... 104
8.2 Typical Applications................................................ 106
9 Power Supply Recommendations..............................109
10 Layout.........................................................................110
10.1 Layout Guidelines................................................. 110
10.2 Layout Example.....................................................111
10.3 Thermal Considerations........................................112
11 Device and Documentation Support........................ 114
11.1 Documentation Support.........................................114
11.2 接收文档更新通知..................................................114
11.3 支持资源................................................................ 114
11.4 Trademarks........................................................... 114
11.5 静电放电警告.........................................................114
11.6 术语表....................................................................114
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics.............................................. 11
7 Detailed Description......................................................23
7.1 Overview...................................................................23
7.2 Functional Block Diagram.........................................23
7.3 Feature Description...................................................24
7.4 Device Functional Modes..........................................35
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (September 2019) to Revision B (December 2020)
Page
• 将器件状态从预告信息更改为量产数据.............................................................................................................1
• Changed From: Single-Ended Analog input with 3 gain option To: Single-Ended Analog input with 4 gain
options in the Functional Block Diagram ......................................................................................................... 23
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
5 Pin Configuration and Functions
PVDD
PVDDQ
VBAT
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
BST_4P
OUT_4P
GND
2
3
GVDD_RET
GVDD
AVDD
4
OUT_4M
BST_4M
BST_3P
OUT_3P
GND
5
6
AVDD_RET
IN_REF
IN_4
7
8
9
OUT_3M
BST_3M
PVDD
IN_3
10
11
12
13
14
15
16
17
18
19
20
21
22
IN_2
Thermal
Pad
IN_1
PVDD
DVSS
BST_2P
OUT_2P
GND
DVDD
SCL
SDA
OUT_2M
BST_2M
BST_1P
OUT_1P
GND
STANDBY
FAULT
GPIO1
GPIO2
GND
OUT_1M
BST_1M
PVDD
Not to scale
图5-1. DDV Package, 44-Pin HTSSOP, Top View
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Voltage regulator bypass, derived from VBAT input pins. Connect 1 µF capacitor from AVDD
(pin 6) to AVDD_RET (pin 7).
AVDD
6
PWR
AVDD_RET
BST_1M
BST_1P
BST_2M
BST_2P
BST_3M
BST_3P
7
GND
PWR
PWR
PWR
PWR
PWR
PWR
AVDD voltage regulator return. Connect to ground.
23
27
28
32
35
39
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
BST_4M
BST_4P
DVDD
NO.
40
PWR
PWR
PWR
GND
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
DVDD supply input. Connect 1 µF capacitor from DVDD to DVSS (pin 13).
DVDD ground reference. Connect to ground.
44
14
DVSS
13
Reports a fault (active low, open drain), external pullup resistor determines I2C address during
power on reset.
FAULT
GND
18
DI/O
GND
21, 25, 30,
37, 42
Ground
GPIO1
GPIO2
19
20
DI/O
DI/O
General purpose IO, function set by register programming.
General purpose IO, function set by register programming.
Gate drive voltage regulator bypass for all output channels, derived from VBAT input pins.
Connect 2.2µF capacitor to GVDD_RET (pin 4).
GVDD
5
PWR
GVDD_RET
IN_1
4
GND
AI
Gate drive voltage regulator return. Connect to ground.
12
11
10
9
Non-inverting input channel. Internally biased to AVDD/2. Connect to AC coupling capacitor.
Non-inverting input channel. Internally biased to AVDD/2. Connect to AC coupling capacitor.
Non-inverting input channel. Internally biased to AVDD/2. Connect to AC coupling capacitor.
Non-inverting input channel. Internally biased to AVDD/2. Connect to AC coupling capacitor.
IN_2
AI
IN_3
AI
IN_4
AI
Reference input voltage for IN_1, IN_2, IN_3, IN_4. Internally biased to AVDD/2. Connect to
AC coupling capacitor.
IN_REF
8
AI
OUT_1M
OUT_1P
OUT_2M
OUT_2P
OUT_3M
OUT_3P
OUT_4M
OUT_4P
PVDD
24
26
29
31
36
38
41
43
NO
PO
Negative output for the channel
Positive output for the channel
NO
Negative output for the channel
PO
Positive output for the channel
NO
Negative output for the channel
PO
Positive output for the channel
NO
Negative output for the channel
PO
Positive output for the channel
1, 22, 33, 34
PWR
PWR
DI
PVDD voltage input carrying load currents (can be connected to battery).
PVDD voltage input not loaded with load currents (can be connected to battery).
I2C clock input
PVDDQ
SCL
2
15
16
17
3
SDA
DI/O
DI
I2C data input and output
STANDBY
VBAT
Enables low power standby state (active Low), 100-kΩinternal pulldown resistor.
Battery voltage input
PWR
GND
Thermal Pad
Provides thermal connection for the device. Heatsink must be connected to GND.
—
(1) AI = analog input, GND = ground, PWR = power, PO = positive output, NO = negative output, DI = digital input, DO = digital output,
DI/O = digital input and output, NC = No Connection
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6 Specifications
6.1 Absolute Maximum Ratings
MIN
–0.3
–1
MAX UNIT
PVDD, VBAT DC supply-voltage range relative to GND
30
40
V
V
VMAX
VRAMP
VIN
Transient supply-voltage range - PVDD, VBAT
Supply-voltage ramp rate - PVDD, VBAT
Audio input pins - IN_x, IN_Ref
t ≤400 ms exposure
75 V/ms
5.5
3.5
V
V
–0.3
–0.3
DVDD
DC supply voltage range relative to GND
Maximum current per pin - PVDD, VBAT, OUTxP,
OUT xM, GND
IMAX
Peak Audio Current, t < 25ms
7.5
A
V
Input voltage for logic pins - SCL, SDA, FAULT,
STANDBY, GPIOx
DVDD +
0.5
VLOGIC
–0.3
VGND
TJ
Maximum voltage between GND pins
Maximum operating junction temperature range
Storage temperature range
±0.3
175
150
V
°C
°C
–55
–55
Tstg
6.2 ESD Ratings
VALUE
UNIT
Human-body model
Human-body model (HBM), per AEC
V(ESD)
Electrostatic discharge
(HBM), per AEC
±2000
V
Q100-002(1)
Q100-002(1)
Charged-device model (CDM), per AEC
Q100-011
V(ESD)
V(ESD)
Electrostatic discharge
Electrostatic discharge
All pins
±750
±750
V
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (1, 22, 23 and
44)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
4.5
TYP
14.4
14.4
3.3
MAX UNIT
PVDD
VBAT
DVDD
TA
Output FET Supply Voltage Range
Battery Supply Voltage Range
Digital Logic Supply
Relative to GND
Relative to GND
Relative to GND
18
18
V
V
4.5
3.0
3.5
125
V
Ambient temperature
°C
–40
An adequate thermal design is
required
TJ
Junction temperature
160
°C
–40
RL
Nominal speaker load impedance
Nominal speaker load impedance
I2C pullup resistance on SDA and SCL pins
External capacitance on bypass pins
External capacitance on GVDD pin
BTL Mode
2
1.75
1
4
2
Ω
Ω
RL
PBTL Mode
RPU_I2C
CBypass
CGVDD
4.7
1
10
kΩ
µF
µF
Pin 1, 3, 6, 14
Pin 5
2.2
Limit set by DC-diagnostic
timing
COUT
External capacitance to GND on OUT pins
1
3.3
µF
Minimum output filter
inductance at ISD current
levels. Applies to short to
ground or short to power
protection.
LO
Output filter inductance - ISD
0.5
µH
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.3 Recommended Operating Conditions (continued)
MIN
TYP
MAX UNIT
Minimum output filter
inductance at ILIMIT current
levels. Applies to current
limiting.
LO
Output filter inductance - ILIMIT
1
µH
6.4 Thermal Information
THERMAL METRIC(1)
TPA6304-Q1(2)
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
Junction-to-ambient thermal resistance
–
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
0.6
17.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
16.8
–
ψJT
ψJB
RθJC(bot)
(1) For more information about traditional and new thermalmetrics, see the SPRA953 application report.
(2) JEDEC Standard 4 Layer PCB.
6.5 Electrical Characteristics
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒout = 1
kHz, Fsw = 2.1 MHz, Gain = 22 dB, BD Mode, AES17 Filter, LC reconstruction filter: 3.3μH - ASWPA4035S3R3MT in 4Ω,
ASWPA6055S3R3MT in 2Ωconfiguration and 1μF, default I2C settings, see application diagrams in Typical Applications
section.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CURRENT
IPVDD_IDLE
IVBAT_IDLE
IDVDD
PVDD idle current
All channels playing, no audio input
All channels playing, no audio input
All channels playing, -60 dB Signal
STANDBY active, DVDD = 0 V
STANDBY active, DVDD = 0 V
60
115
4
70
130
4.5
10
mA
mA
mA
µA
VBAT idle current
DVDD supply current
PVDD standby current
VBAT standby current
IPVDD_STBY
IVBAT_STBY
OUTPUT POWER
Output power per
1.5
1
2
µA
4 Ω, PVDD = 14.4 V, THD+N = 1%,
TC = 75°C
PO_BTL
PO_BTL
PO_BTL
PO_BTL
PO_BTL
20
25
22
27
27
37
45
W
W
W
W
W
channel, BTL
Output power per
channel, BTL
4 Ω, PVDD = 14.4 V, THD+N = 10%,
TC = 75°C
Output power per
channel, BTL
4 Ω, PVDD = 14.4 V, THD+N = 10%,
TC = 75°C, Inductor DCR = 25mΩ
Output power per
channel, BTL
2 Ω, PVDD = 14.4 V, THD+N = 1%,
TC = 75°C
32
40
Output power per
channel, BTL
2 Ω, PVDD = 14.4 V, THD+N = 10%,
TC = 75°C
Output power per
channel with square
wave, BTL
4 Ω, PVDD = 14.4 V, 2 VRMS Input
Square Wave
PO_BTL_SQ
PO_BTL_SQ
PO_PBTL
45
55
43
W
W
W
Output power per
channel with square
wave, BTL
4 Ω, PVDD = 16 V, 2 VRMS Input
Square Wave
Output power per
channel in parallel mode,
PBTL
2 Ω, PVDD = 14.4 V, THD+N = 1%,
TC = 75°C
38
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.5 Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒout = 1
kHz, Fsw = 2.1 MHz, Gain = 22 dB, BD Mode, AES17 Filter, LC reconstruction filter: 3.3μH - ASWPA4035S3R3MT in 4Ω,
ASWPA6055S3R3MT in 2Ωconfiguration and 1μF, default I2C settings, see application diagrams in Typical Applications
section.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output power per
channel in parallel mode,
PBTL
2 Ω, PVDD = 14.4 V, THD+N = 10%,
TC = 75°C
PO_PBTL
47
53
W
4 channels operating, 25 W output
power per channel, RL = 4 Ω, PVDD =
14.4 V, TC = 25°C; (includes device
and LC filter losses)
EFFP
Power efficiency
88
%
PWM OUTPUT STAGE
FET drain-to-source
25°C, Including bond wire and
package resistance
RDS(on)
100
80
mΩ
mΩ
resistance
FET drain-to-source
resistance
25°C, Not including bond wire and
package resistance
RDS(on)
AUDIO PERFORMANCE
Vn
Vn
Vn
Vn
Output noise voltage
Zero input, A-weighting, 10 dB gain
Zero input, A-weighting, 16 dB gain
Zero input, A-weighting, 22 dB gain
Zero input, A-weighting, 28 dB gain
35
42
60
75
µV
µV
µV
µV
Output noise voltage
Output noise voltage
Output noise voltage
Total harmonic distortion
+ noise
THD+N
0.013
%
G
G
G
G
Gain
Gain
Gain
Gain
Level 1
Level 2
Level 3
Level 4
9
15
21
27
10
16
22
28
10.5
16.5
22.5
28.5
dB
dB
dB
dB
Channel-to-channel gain
variation
GCH
0
–90
80
0.5
dB
dB
dB
–0.5
Crosstalk
PSRR
Channel crosstalk
Power-supply rejection
ratio
PVDD = 14.4 Vdc + 1 VRMS, ƒ= 1 kHz
Assert MUTE and compare to amp
playing 1W audio into 4 Ω
GMUTE
VCLICK
Vn_LINEOUT
Output attenuation
Click and Pop
100
117
7
dB
Zero input, ITU-filter, 28dB gain
mV
Zero input, A-weighting, channel set to
Line Output, RL = 600 Ω, Gain = 16
dB
Line output noise voltage
42
µV
%
Line output Total
harmonic distortion +
noise
VOUT = 2 VRMS , channel set to Line
Output
THD+N
0.01
ANALOG INPUT PINS
RIN
RIN
Input impedance
IN_1, IN_2, IN_3, IN_4
IN_REF
80
20
kΩ
kΩ
Input impedance
Maximum input voltage
swing
VIN AC coupled through capacitor.
Pins IN_1, IN_2, IN_3, IN_4
VIN
1
5
VRMS
Maximum input voltage
swing
VIN
IIN
IN_REF
mV
mA
Maximum input current
IN_1, IN_2, IN_3, IN_4, IN_REF
10
DIGITAL INPUT PINS
VIH
Input logic level high
70
%DVDD
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.5 Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒout = 1
kHz, Fsw = 2.1 MHz, Gain = 22 dB, BD Mode, AES17 Filter, LC reconstruction filter: 3.3μH - ASWPA4035S3R3MT in 4Ω,
ASWPA6055S3R3MT in 2Ωconfiguration and 1μF, default I2C settings, see application diagrams in Typical Applications
section.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
%DVDD
µA
VIL
IIH
IIL
Input logic level low
Input logic current
Input logic current
30
VI = DVDD
33
50
VI = 0
µA
–50
–33
DIGITAL OUTPUT PINS
Output voltage for logic
level high
VOH
VOL
I = ±2 mA
I = ±2 mA
90
%DVDD
%DVDD
Output voltage for logic
level low
10
BYPASS VOLTAGES
Gate drive bypass pin
VGVDD
5
5
V
V
voltage
Analog bypass pin
voltage
VAVDD
OVERVOLTAGE (OV) PROTECTION
PVDD overvoltage
VPVDD_OV_SET
18.5
18.5
20
0.5
20
22
22
V
V
V
V
shutdown set
PVDD overvoltage
VPVDD_OV_HYS
recovery hysteresis
VBAT overvoltage
VVBAT_OV_SET
shutdown set
VBAT overvoltage
VVBAT_OV_HYS
0.5
recovery hysteresis
UNDERVOLTAGE (UV) PROTECTION
VBAT undervoltage
VBATUV_SET
3.7
3.7
4.5
4.5
V
V
V
V
shutdown set
VBAT undervoltage
VBATUV_HYS
0.3
0.3
recovery hysteresis
PVDD undervoltage
PVDDUV_SET
shutdown set
PVDD undervoltage
PVDDUV_HYS
recovery hysteresis
POWER-ON RESET (POR)
VPOR_SET
VPOR_HYS
DVDD power on reset set Increasing DVDD
1.9
0.5
V
V
DVDD power on reset
recovery hysteresis
DVDD power off
Decreasing DVDD
threshold
VPOR_OFF
1.5
2.4
V
OVERTEMPERATURE (OT) PROTECTION
Per channel over-
OTW(i)
160
175
130
160
15
°C
°C
°C
°C
°C
temperature warning
Per channel over-
OTSD(i)
temperature shutdown
Global junction over-
OTW
Default value (see Misc Control
Register 1)
temperature warning
Global junction over-
OTSD
temperature shutdown
Over-temperature
OTHYS
recovery hysterisis
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.5 Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒout = 1
kHz, Fsw = 2.1 MHz, Gain = 22 dB, BD Mode, AES17 Filter, LC reconstruction filter: 3.3μH - ASWPA4035S3R3MT in 4Ω,
ASWPA6055S3R3MT in 2Ωconfiguration and 1μF, default I2C settings, see application diagrams in Typical Applications
section.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOAD OVERCURRENT PROTECTION
ILIMIT
ILIMIT
ILIMIT
ILIMIT
Load Overcurrent limit
Load Overcurrent limit
Load Overcurrent limit
Load Overcurrent limit
OC level 1, load current (default)
OC level 2, load current
OC level 3, load current
OC level 4, load current
3.0
3.5
5.0
6.0
3.4
4
A
A
A
A
5.8
6.5
OC level 1, any short to supply,
ground, or other channels (default)
ISD
ISD
ISD
Overcurrent shutdown
Overcurrent shutdown
Overcurrent shutdown
Overcurrent shutdown
4.7
5.5
8.0
9.0
6
7
A
A
A
A
OC level 2, any short to supply,
ground, or other channels
OC level 3, any short to supply,
ground, or other channels
10
11
OC level 4, any short to supply,
ground, or other channels
ISD
DC DETECT
DCFAULT
SYNC
Output DC fault
protection
1
1.75
2.5
V
Misc Control 2 Register,
PWM_FREQUENCY: 00, fsw
2.1MHz
Supported SYNC
frequency, master mode
fsync
=
=
8.4
9.2
MHz
MHz
%
Misc Control 2 Register,
PWM_FREQUENCY: 01, fsw
2.3MHz
Supported SYNC
frequency, master mode
fsync
SYNC frequency
deviation from nominal,
master mode
10
Δfsync
–10
Supported SYNC
frequency, slave mode
fsync
fsync
fsw = 2.1MHz
fsw = 2.3 MHz
8.4
9.2
MHz
MHz
Supported SYNC
frequency, slave mode
Supported SYNC
frequency deviation,
slave mode
10
56
%
%
Δfsync
–10
Supported SYNC duty
cycle, slave mode
Dsync
44
50
LOAD DIAGNOSTICS
Maximum resistance to
S2P
detect a short from OUT
pin(s) to PVDD
8000
Ω
Ω
Maximum resistance to
detect a short from OUT
pin(s) to ground
S2G
SL
300
Shorted load detection
tolerance
One channel, other channels in Hi-Z
±12.5%
Minimum impedance
detected as open load
OL
Other channels in Hi-Z
4 channels, no faults
110
174
Ω
TDC_DIAG
DC diagnostic time
ms
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.5 Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒout = 1
kHz, Fsw = 2.1 MHz, Gain = 22 dB, BD Mode, AES17 Filter, LC reconstruction filter: 3.3μH - ASWPA4035S3R3MT in 4Ω,
ASWPA6055S3R3MT in 2Ωconfiguration and 1μF, default I2C settings, see application diagrams in Typical Applications
section.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Maximum detectable
impedance for line output
mode
LO
12
kΩ
Line output diagnostic
time
TLINE_DIAG
150
ms
ƒ= 18.5 kHz, RL = 4 Ω, Impedance at
output pins
ACIMP
TAC_DIAG
FAC
AC impedance accuracy
AC diagnostic time
±0.75
217
Ω
ms
4 channels, ƒ= 18.5 kHz
AC diagnostic test
frequency
Default frequency
18.5
kHz
I2C CONTROL PORT
Bus free time between
tBUS
1.3
0
µs
ns
µs
start and stop conditions
tH1
Hold Time, SCL to SDA
Hold Time, start condition
to SCL
tH2
0.6
I2C Startup Time After
DVDD Power On Reset
tSTART
10
ms
(1)
tRISE
tFALL
tSU1
Rise Time, SCL and SDA
Fall Time, SCL and SDA
Setup, SDA to SCL
300
300
ns
ns
ns
(1)
100
0.6
Setup, SCL to Start
Condition
tSU2
tSU3
tW(H)
tW(L)
µs
µs
µs
µs
Setup, SCL to Stop
Condition
0.6
0.6
1.3
Required Pulse Duration
SCL High
Required Pulse Duration
SCL Low
(1) Specified by design.
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.6 Typical Characteristics
6.6.1 Bridge-Tied Load (BTL), BD
TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒOUT = 1 kHz, FSW = 2.1 MHz, Gain = 22 dB, BD
Mode, AES17 Filter, default I2C settings, LC reconstruction filter: 3.3 μH - ASWPA4035S3R3MT in 4Ω,
ASWPA6055S3R3MT in 2 Ωconfiguration and 1 μF (unless otherwise noted). See application diagram in 图8-2
10
5
10
5
2 W Load
4 W Load
2 W Load
4 W Load
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.02
0.01
0.05
0.02
0.01
0.005
0.002
0.001
0.005
10m
100m
1
Output Power(W)
10
50
0.002
0.001
PVDD = 14.4V
BTL
10m
100m
1
Output Power(W)
10
50
图6-1. THD+N vs Power - 2 Ω, 4 Ω- 14.4 V
PVDD = 18V
图6-2. THD+N vs Power - 2 Ω, 4 Ω- 18 V
BTL
10
45
2 W Load
4 W Load
2 W 1%THD+N
2 W 10%THD+N
4 W 1%THD+N
4 W 10%THD+N
5
40
35
30
25
20
15
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
20
100
1k
10k 20k
Supply Voltage (V)
Frequency (Hz)
TC = 75 °C
BTL
PO = 1 W
BTL
图6-4. Output Power vs Supply Voltage - 2 Ω1%, 2 Ω10%, 4 Ω
1%, 4 Ω10%
图6-3. THD+N vs Frequency - 2 Ω, 4 Ω
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
PVDD
PVDD
10
0
PVDD + VBAT
PVDD + VBAT
0
20
40
60
80
100 120
0.3 0.50.7 1
2
3
4 5 67 10
20 30 50 70100 200
Output Power (W)
Output Power (W)
TC = 75 °C
图6-5. Efficiency vs Output Power - 4 Ω
BTL
TC = 75 °C
图6-6. Efficiency vs Output Power - 4 Ω(Zoomed)
BTL
4 Ω
4 Ω
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.6.1 Bridge-Tied Load (BTL), BD (continued)
TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒOUT = 1 kHz, FSW = 2.1 MHz, Gain = 22 dB, BD
Mode, AES17 Filter, default I2C settings, LC reconstruction filter: 3.3 μH - ASWPA4035S3R3MT in 4Ω,
ASWPA6055S3R3MT in 2 Ωconfiguration and 1 μF (unless otherwise noted). See application diagram in 图8-2
20
18
16
14
12
10
8
100
90
80
70
60
50
40
30
20
10
0
6
4
PVDD (Device only)
PVDD+VBAT (Device only)
PVDD+VBAT (Device + LC)
PVDD
2
PVDD + VBAT
0
0
10 20 30 40 50 60 70 80 90 100 110
Output Power (W)
0
20
40
60
80
100 120 140 160 180
Output Power (W)
TC = 75 °C
BTL
TC = 75 °C
BTL
BTL
BTL
4 Ω
2 Ω
图6-7. Power Dissipation vs Output Power - 4 Ω
图6-8. Efficiency vs Output Power - 2 Ω
100
90
80
70
60
50
40
30
20
50
45
40
35
30
25
20
15
10
5
PVDD (Device only)
PVDD+VBAT (Device only)
PVDD+VBAT (Device + LC)
PVDD
PVDD + VBAT
10
0
0.3 0.5
0
1
5
10
50
100 200
0
20
40
60
80 100 120 140 160 180
Output Power (W)
Output Power (W)
TC = 75 °C
BTL
TC = 75 °C
2 Ω
2 Ω
图6-9. Efficiency vs Output Power - 2 Ω(Zoomed)
图6-10. Power Dissipation vs Output Power - 2 Ω
100
90
80
70
60
50
40
30
20
10
0
140
120
100
80
60
40
20
0
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
4
6
8
10
12
14
16
18
Supply Voltage (V)
Supply Voltage (V)
BTL
图6-11. PVDD Idle vs Supply Voltage
图6-12. VBAT Idle Current vs Supply Voltage
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.6.1 Bridge-Tied Load (BTL), BD (continued)
TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒOUT = 1 kHz, FSW = 2.1 MHz, Gain = 22 dB, BD
Mode, AES17 Filter, default I2C settings, LC reconstruction filter: 3.3 μH - ASWPA4035S3R3MT in 4Ω,
ASWPA6055S3R3MT in 2 Ωconfiguration and 1 μF (unless otherwise noted). See application diagram in 图8-2
140
120
100
80
0
Gain = 10 dB
Gain = 16 dB
Gain = 22 dB
Gain = 28 dB
CH 1 to CH 2
CH 1 to CH 3
CH 1 to CH 4
-20
-40
-60
60
-80
40
-100
20
0
-120
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
20
100
1k
10k 20k
Supply Voltage (V)
Frequency(Hz)
A-Weighted
图6-13. Noise vs Supply Voltage
BTL
BTL
BTL
BTL
图6-14. Crosstalk vs Frequency
0
-10
0
-10
PVDD
VBAT
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
PO = 1 W
PVDD = 14.4 V + 1 V RMS
BTL
PO = 1 W
VBAT = 14.4 V + 1 V RMS
图6-15. PSRR vs Frequency - PVDD Only
图6-16. PSRR vs Frequency - VBAT Only
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
PVDD + VBAT
-120
20
100
1k
Frequency (Hz)
10k 20k
PO = 1 W
PVDD = VBAT = 14.4 V + 1 V RMS
图6-17. PSRR vs Frequency - PVDD+VBAT
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.6.2 Parallel Bridge-Tied Load (PBTL)
TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 2 Ω, Pout = 1 W/ch, ƒOUT = 1 kHz, FSW = 2.1 MHz, Gain = 22 dB, BD
Mode, AES17 Filter, default I2C settings, LC reconstruction filter: 3.3 μH - ASWPA6055S3R3MT in 2 Ωconfiguration and 1
μF (unless otherwise noted). See application diagram in 节8.2.2
10
5
10
5
2 W Load
2 W Load
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
10m
100m
1
10
100
10m
100m
1
10
100
Output Power (W)
Output Power(W)
PVDD = 14.4 V
PBTL
PBTL
PBTL
PVDD = 18 V
PBTL
PBTL
PBTL
图6-18. THD+N vs Power - PBTL, 2 Ω, 14.4 V
图6-19. THD+N vs Power - PBTL, 2 Ω, 18 V
10
90
2 W Load
2 W 1%THD+N
2 W 10%THD+N
5
80
2
1
70
60
50
40
30
20
10
0
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
20
100
1k
10k 20k
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Frequency (Hz)
Supply Voltage (V)
P O = 1 W
图6-20. THD+N vs Frequency - PBTL, 2 Ω
TC = 75 °C
2 Ω
图6-21. Ouput Power vs Supply Voltage - PBTL, 2 Ω
100
20
18
16
14
12
10
8
80
60
40
20
0
6
4
PVDD (Device only)
PVDD+VBAT (Device only)
PVDD+VBAT (Device + LC)
PVDD
PVDD + VBAT
2
0
0
20
40
60
80
100
120
0
10 20 30 40 50 60 70 80 90 100 110
Output Power (W)
Output Power (W)
TC = 75 °C
TC = 75 °C
2 Ω
2 Ω
图6-22. Efficiency vs Output Power - PBTL, 2 Ω
图6-23. Power Dissipation vs Output Power - PBTL, 2 Ω
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.6.2 Parallel Bridge-Tied Load (PBTL) (continued)
TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 2 Ω, Pout = 1 W/ch, ƒOUT = 1 kHz, FSW = 2.1 MHz, Gain = 22 dB, BD
Mode, AES17 Filter, default I2C settings, LC reconstruction filter: 3.3 μH - ASWPA6055S3R3MT in 2 Ωconfiguration and 1
μF (unless otherwise noted). See application diagram in 节8.2.2
140
Gain = 10 dB
Gain = 16 dB
120
100
Gain = 22 dB
Gain = 28 dB
80
60
40
20
0
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Supply Voltage (V)
A-Weighted
图6-24. Noise vs Supply Voltage - PBTL, 2 Ω
PBTL
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.6.3 Bridge-Tied Load (BTL), 1SPW
TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒOUT = 1 kHz, FSW = 2.1 MHz, Gain = 22 dB,
1SPW Mode, AES17 Filter, default I2C settings, LC reconstruction filter: 3.3 μH - ASWPA4035S3R3MT in 4Ω,
ASWPA6055S3R3MT in 2 Ωconfiguration and 1 μF (unless otherwise noted). See application diagram in 图8-2
10
5
10
5
2 W Load
4 W Load
2 W Load
4 W Load
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
10m
100m
1
10
50
10m
100m
1
10
50
Output Power (W)
Output Power (W)
PVDD = 14.4 V
BTL
PVDD = 18 V
BTL
图6-25. THD+N vs Power - BTL, 2 Ω, 4 Ω, 14.4 V, 1SPW
图6-26. THD+N vs Power - BTL, 2 Ω, 4 Ω, 18 V, 1SPW
10
50
2 W Load
4 W Load
2 W 1%THD+N
5
45
2 W 10%THD+N
2
4 W 1%THD+N
4 W 10%THD+N
40
1
35
0.5
30
25
20
15
10
5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0
20
100
1k
10k 20k
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Frequency (Hz)
Supply Voltage (V)
P O = 1 W
BTL
TC = 75 °C
BTL
图6-27. THD+N vs Frequency - BTL, 2 Ω, 4 Ω, 14.4 V, 1SPW
图6-28. Ouput Power vs Supply Voltage - BTL, 2 Ω, 4 Ω, 1SPW
100
90
80
70
60
50
40
30
20
20
18
16
14
12
10
8
6
4
PVDD (Device only)
PVDD+VBAT (Device only)
PVDD+VBAT (Device + LC)
PVDD + VBAT
PVDD
10
0
2
0
0
20
40
60
80
100
120
0
10 20 30 40 50 60 70 80 90 100 110
Output Power (W)
Output Power (W)
TC = 75 °C
BTL
TC = 75 °C
BTL
4 Ω
4 Ω
图6-29. Efficiency vs Output Power - BTL, 4 Ω, 14.4 V, 1SPW
图6-30. Power Dissipation vs Output Power - BTL, 4 Ω, 14.4 V,
1SPW
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.6.3 Bridge-Tied Load (BTL), 1SPW (continued)
TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒOUT = 1 kHz, FSW = 2.1 MHz, Gain = 22 dB,
1SPW Mode, AES17 Filter, default I2C settings, LC reconstruction filter: 3.3 μH - ASWPA4035S3R3MT in 4Ω,
ASWPA6055S3R3MT in 2 Ωconfiguration and 1 μF (unless otherwise noted). See application diagram in 图8-2
100
90
80
70
60
50
40
30
20
10
0
50
45
40
35
30
25
20
15
10
5
PVDD (Device only)
PVDD+VBAT (Device only)
PVDD+VBAT (Device + LC)
PVDD
PVDD + VBAT
0
0
20
40
60
80
100 120 140 160 180
0
20
40
60
80
Output Power (W)
100 120 140 160 180
Output Power (W)
TC = 75 °C
BTL
TC = 75 °C
BTL
2 Ω
2 Ω
图6-31. Efficiency vs Output Power - BTL, 2 Ω, 14.4 V, 1SPW
图6-32. Power Dissipation vs Output Power - BTL, 2 Ω, 14.4 V,
1SPW
100
90
80
70
60
50
40
30
20
10
0
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Supply Voltage (V)
Supply Voltage (V)
BTL
BTL
图6-33. PVDD Idle Current vs Supply Voltage - BTL, 1SPW
图6-34. VBAT Idle Current vs Supply Voltage - BTL, 1SPW
100
140
BD
Gain = 10 dB
Gain = 16 dB
130
120
90
1SPW
Gain = 22 dB
80
70
60
50
40
30
20
10
0
110
Gain = 28 dB
100
90
80
70
60
50
40
30
20
10
0
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Supply Voltage (V)
Supply Voltage(V)
F SW = 384 kHz
BTL
A-Weighted
图6-36. Noise vs Supply Voltage - BTL, 1SPW
BTL
图6-35. PVDD Idle Current vs Supply Voltage - BTL, 1SPW, 384
kHz
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.6.4 Bridge-Tied Load (BTL), 384 kHz, BD
TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒOUT = 1 kHz, FSW = 384 kHz, Gain = 22 dB, BD
Mode, AES17 Filter, default I2C settings, LC reconstruction filter: 10 μH Sagami 7G14C-100M in 4 Ω/2 Ωconfiguration and
1 μF (unless otherwise noted). See application diagram in 图8-2
10
5
10
5
2 W Load
4 W Load
2 W Load
4 W Load
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
10m
100m
1
10
50
10m
100m
1
10
50
Output Power (W)
Output Power (W)
PVDD = 14.4V
BTL
PVDD = 18V
BTL
图6-37. THD+N vs Power - 2 Ω, 4 Ω- 14.4 V
图6-38. THD+N vs Power - 2 Ω, 4 Ω- 18 V
10
50
2 W Load
4 W Load
2 W 1%THD+N
5
45
2 W 10%THD+N
2
4 W 1%THD+N
4 W 10%THD+N
40
1
35
0.5
30
25
20
15
10
5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0
20
100
1k
10k 20k
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Frequency (Hz)
Supply Voltage (V)
PO = 1 W
图6-39. THD+N vs Frequency - 2 Ω, 4 Ω
BTL
TC = 75 °C
BTL
图6-40. Output Power vs Supply Voltage - 2 Ω1%, 2 Ω10%, 4
Ω1%, 4 Ω10%
100
100
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
10
0
PVDD
PVDD
PVDD + VBAT
10
PVDD + VBAT
0
0.02 0.05 0.1 0.2 0.5
Output Power (W)
0
10 20 30 40 50 60 70 80 90 100 110 120
1
2 3 45 7 10 2030 50 100 200
Output Power (W)
TC = 75 °C
BTL
TC = 75 °C
图6-42. Efficiency vs Output Power - 4 Ω(Zoomed)
BTL
4 Ω
4 Ω
图6-41. Efficiency vs Output Power - 4 Ω
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.6.4 Bridge-Tied Load (BTL), 384 kHz, BD (continued)
TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒOUT = 1 kHz, FSW = 384 kHz, Gain = 22 dB, BD
Mode, AES17 Filter, default I2C settings, LC reconstruction filter: 10 μH Sagami 7G14C-100M in 4 Ω/2 Ωconfiguration and
1 μF (unless otherwise noted). See application diagram in 图8-2
20
18
16
14
12
10
8
100
90
80
70
60
50
40
30
20
10
0
PVDD (Device only)
PVDD+VBAT (Device only)
PVDD+VBAT (Device + LC)
6
4
PVDD
2
PVDD + VBAT
0
0
10 20 30 40 50 60 70 80 90 100 110
Output Power (W)
0
20
40
60
80
100 120 140 160 180
Output Power (W)
TC = 75 °C
BTL
BTL
BTL
TC = 75 °C
BTL
BTL
BTL
4 Ω
2 Ω
图6-43. Power Dissipation vs Output Power - 4 Ω
图6-44. Efficiency vs Output Power - 2 Ω
100
90
80
70
60
50
40
30
20
50
PVDD (Device only)
PVDD+VBAT (Device only)
PVDD+VBAT (Device + LC)
45
40
35
30
25
20
15
10
5
PVDD
PVDD + VBAT
10
0
0.02 0.05 0.1 0.2 0.5
Output Power (W)
0
1
2
3 45 7 10 2030 50 100 200
0
20
40
60
80 100 120 140 160 180
Output Power (W)
TC = 75 °C
TC = 75 °C
2 Ω
2 Ω
图6-45. Efficiency vs Output Power - 2 Ω(Zoomed)
图6-46. Power Dissipation vs Output Power - 2 Ω
100
100
90
80
70
60
50
40
30
20
10
0
BD
90
1SPW
80
70
60
50
40
30
20
10
0
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Supply Voltage (V)
Supply Voltage (V)
图6-47. PVDD Idle vs Supply Voltage
图6-48. VBAT Idle Current vs Supply Voltage
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.6.5 Bridge-Tied Load (BTL), 384 kHz, 1SPW
TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒOUT = 1 kHz, FSW = 384 kHz, Gain = 22 dB,
1SPW Mode, AES17 Filter, default I2C settings, LC reconstruction filter: 10 μH Sagami 7G14C-100M in 4 Ω/2 Ω
configuration and 1 μF (unless otherwise noted). See application diagram in 图8-2
10
5
10
5
2 W Load
4 W Load
2 W Load
4 W Load
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
10m
100m
1
Output Power(W)
10
50
10m
100m
1
10
50
Output Power (W)
PVDD = 18V
BTL
PVDD = 14.4V
BTL
图6-50. THD+N vs Power - 2 Ω, 4 Ω- 18 V
图6-49. THD+N vs Power - 2 Ω, 4 Ω- 14.4 V
10
50
2 W Load
4 W Load
2 W 1%THD+N
5
45
2 W 10%THD+N
2
4 W 1%THD+N
4 W 10%THD+N
40
1
35
0.5
30
25
20
15
10
5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0
20
100
1k
10k 20k
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Frequency (Hz)
Supply Voltage (V)
PO = 1 W
图6-51. THD+N vs Frequency - 2 Ω, 4 Ω
BTL
TC = 75 °C
BTL
图6-52. Output Power vs Supply Voltage - 2 Ω1%, 2 Ω10%, 4
Ω1%, 4 Ω10%
100
100
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
10
0
PVDD
PVDD
PVDD + VBAT
10
PVDD + VBAT
0
0.02 0.05 0.1 0.2 0.5
Output Power (W)
0
10 20 30 40 50 60 70 80 90 100 110 120
1
2 3 45 7 10 2030 50 100 200
Output Power (W)
TC = 75 °C
BTL
TC = 75 °C
图6-54. Efficiency vs Output Power - 4 Ω(Zoomed)
BTL
4 Ω
4 Ω
图6-53. Efficiency vs Output Power - 4 Ω
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
6.6.5 Bridge-Tied Load (BTL), 384 kHz, 1SPW (continued)
TC = 25°C, PVDD = VBAT = 14.4 V, DVDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒOUT = 1 kHz, FSW = 384 kHz, Gain = 22 dB,
1SPW Mode, AES17 Filter, default I2C settings, LC reconstruction filter: 10 μH Sagami 7G14C-100M in 4 Ω/2 Ω
configuration and 1 μF (unless otherwise noted). See application diagram in 图8-2
20
18
16
14
12
10
8
100
90
80
70
60
50
40
30
20
10
0
PVDD (Device only)
PVDD+VBAT (Device only)
PVDD+VBAT (Device + LC)
6
4
PVDD
2
PVDD + VBAT
0
0
10 20 30 40 50 60 70 80 90 100 110
Output Power (W)
0
20
40
60
80
100 120 140 160 180
Output Power (W)
TC = 75 °C
BTL
TC = 75 °C
BTL
4 Ω
2 Ω
图6-55. Power Dissipation vs Output Power - 4 Ω
图6-56. Efficiency vs Output Power - 2 Ω
100
90
80
70
60
50
40
30
20
50
PVDD (Device only)
PVDD+VBAT (Device only)
PVDD+VBAT (Device + LC)
45
40
35
30
25
20
15
10
5
PVDD
PVDD + VBAT
10
0
0.02 0.05 0.1 0.2 0.5
Output Power (W)
0
1
2
3 45 7 10 2030 50 100 200
0
20
40
60
80
Output Power (W)
100 120 140 160 180
TC = 75 °C
BTL
TC = 75 °C
BTL
2 Ω
2 Ω
图6-57. Efficiency vs Output Power - 2 Ω(Zoomed)
图6-58. Power Dissipation vs Output Power - 2 Ω
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
Parameter measurement information
The parameters for the TPA6304-Q1 device were measured using the circuit in 图8-2.
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7 Detailed Description
7.1 Overview
The TPA6304-Q1 device is a four-channel analog input Class-D audio amplifier, specifically designed for use in
the automotive industry. The device is designed for vehicle battery operation. The ultra-efficient Class-D
technology allows for reduced power consumption, PCB area, heat, and peak currents in the electrical system.
The device realizes an audio sound system design with smaller size and lower weight than traditional Class-AB
solutions.
The core design blocks are:
• Single-ended analog inputs
• Clock management
• Pulse width modulator (PWM) with output stage feedback
• Gate drive
• Power FETs
• Diagnostics
• Protection
• Power supply
• I2C serial communication bus
7.2 Functional Block Diagram
DVDD
VBAT
GVDD
AVDD
PVDD
Analog Supply
Regulator
Gate Drive
Regulator
STANDBY
FAULT
Digital Core
GPIO1
Closed Loop Class-D Amplifier
Channel 1
Powerstage
GPIO2
OUT_1P
OUT_1M
Spread Spectrum
Timer
Channel 2
Powerstage
OUT_2P
OUT_2M
IN_1
IN_2
PWM
modulators
Gate
Drives
Channel 3
Powerstage
OUT_3P
OUT_3M
Single-Ended Analog input
with 4 gain options
IN_3
IN_4
Clip
Detection
Channel 4
Powerstage
OUT_4P
OUT_4M
IN_REF
Protection
Over-Current Limit/SD
Diagnostics
DC Short to GND
DC Short to Power
DC Open Load
Thermal Gain Foldback
Over Temperature
Over/Under Voltage
DC Detection
SCL
SDA
I2C Control
DC Shorted Load
AC Diagnostics
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.3 Feature Description
7.3.1 Single-Ended Analog Inputs
The TPA6304-Q1 features single-ended analog audio inputs in combination with a reference ground input.
Single-ended outputs available in the system are connected via AC coupling capacitors to the TPA6304-Q1 input
pins. The TPA6304-Q1 IN_REF pin is connected via AC coupling capacitor and a separate line back to the
ground reference point of the source of the single-ended audio signals.
Class-D Amplifier
Input Stage
System DAC
Single-Ended Outputs
PCB Traces
IN_1
CH1
CH2
CH3
CH4
0.47 …F
IN_2
OUT1
OUT2
0.47 …F
IN_3
DAC
OUT3
OUT4
0.47 …F
IN_4
GND
0.47 …F
IN_REF
2.2 …F
图7-1. Single-Ended Analog Input Connections
7.3.2 Gain Control
The gain of the TPA6304-Q1 is configurable in the Miscellaneous Control Register 2 through I2C. There are four
gain settings of 10 dB, 16 dB, 22 dB, and 28 dB. 28 dB is the default setting. It is recommended to select the
lowest possible gain for the expected PVDD operation and input voltage range to optimize dynamic range
performance.
The combination of input voltage range and supply voltage sets the requirement for the chosen gain setting. In a
typical application with maximum input signal amplitude of 0.5 Vrms and 14.4 V supply voltage the default gain of
28 dB allows for full output power of the device.
The input impedance for the IN_1, IN_2, IN_3 and IN_4 pins is typically 80 kΩ and independent of the gain
setting. The input impedance for the IN_REF input is typically 20 kΩ.
The inputs need to be AC-coupled to minimize the output DC-offset and ensure correct ramping of the output
voltages during power-ON and power-OFF. Time constants for all inputs, IN_1, IN_2, IN_3, IN_4 and IN_REF
need to match. The input AC-coupling capacitor together with the input impedance forms a high-pass filter.
If a flat frequency response is required down to 20 Hz the recommended cut-off frequency is a fifth of that, 4 Hz.
This can be achieved with a 0.47 µF ac-coupling capacitor.
It is recommenced to use AC-coupling capacitors with low leakage current, like ceramic-, film- or quality
electrolytic-capacitors.
The TPA6304-Q1 has an output DC detection built in to protect the attached speaker in case an input AC-
coupling capacitor fails or has too high leakage current.
7.3.3 Class-D Operation and Spread Spectrum Control
7.3.3.1 High Frequency Pulse Width Modulator (PWM)
The PWM converts the input audio data into a switched signal of varying duty cycle. The PWM modulator is an
advanced design with high bandwidth, low noise, low distortion, and excellent stability.
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
The TPA6304-Q1, by default, generates its own internal clock signals. This mode of operation is called clock
primary mode. The output switching rate is selectable via I2C, Miscellaneous Control Register 2. If desired, an
external frequency source can be used to drive the switching output. This signal can be sent to the device using
a GPIO Pin. The source frequency is 4x the selected switching frequency. By default, the four channels switches
out of phase with a phase offset of 90 degrees between each channel. With 90 degree phase shift and 2.1 MHz
switching frequency, the combined ripple current of all output channels are combined such that the effective
ripple current has its fundamental at 8.4 MHz This enables the use of smaller and lower cost external filtering
components due to lower power supply ripple.
For best EMI results the high frequency clock signals support spread spectrum control.
7.3.3.2 Clock Synchronization
The TPA6304-Q1 supports clock synchronization. During clock synchronization, one device is clock primary
(Device A) sending out a synchronization clock and one device is clock secondary (Device B), receiving the
synchronization clock. For Device A, set one of the GPIO Pins 'Sync Out'. By default Device A is in clock primary
mode. The Sync Pin Control Register allows to set up Device B as clock secondary. Finally one GPIO Pin of
Device B is set to 'Sync In' and the corresponding GPIO pins need to be connected on the PCB board.
Device B is frequency locked to one fourth of the received synchronization clock frequency. Device B creates an
Invalid Clock Fault Event if the clock signal fed to the GPIO configured as clock sync input is out of nominal
range.
GPIOx
Device A
GPIOx
Device B
图7-2. Clock Synchronization Diagram
7.3.3.3 Spread Spectrum Control
The TPA6304-Q1 offers spread spectrum control. Controlling the spectrum of the clock signal translates into an
optimized behavior of higher frequency signal components which are visible during EMI testing. By default
spread spectrum control is turned on and can be turned off in Spread Spectrum Control Register 2.
The four parameters SSC1, SSC2, SSC3 and SSC4 determine the spread spectrum behavior. The following
predefined profiles determine allowed and supported combinations of SSCx settings and in addition define
settings for the PWM Phase Control Register 1 and PWM Phase Control Register 2.
There are two Spread Spectrum profiles recommend in the TPA6304-Q1:
• Default Profile - optimized for best audio performance and efficiency with EMI performance that can meet
most systems specifications.
• Low EMI - optimized for the lowest EMI for systems with stringent EMI system specficiations.
表7-1. Spread Spectrum Profiles
SSC1[7:0]
SSC2[3:0]
SSC3[5:4]
SSC4[5:4]
PWM Phase
Control 1
PWM Phase
Control 2
Default
0x22
0x22
0x0
0x0
0x0
0x2
0x0
0x2
0x40
0x40
0x62
0x62
Low EMI
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.3.4 Gate Drive
The gate driver accepts the low-voltage PWM signal and level shifts it to drive the high-current, full-bridge,
power-FET stage. The device uses proprietary techniques to optimize EMI and audio performance.
The gate driver power supply voltage, GVDD, is internally generated and a decoupling capacitor must be
connected at pin 5.
7.3.5 Power FETs
The BTL output for each channel comprises four N-channel 80 mΩ FETs for high efficiency and maximum power
transfer to the load. These FETs are designed to handle large voltage transients during load dump.
7.3.6 Load Diagnostics
The device incorporates both DC- and AC- load diagnostics which are used to determine the status of the load.
The DC-diagnostics are turned on by default. The AC-load diagnostics is turned off by default.
7.3.6.1 DC Load Diagnostics
The DC load diagnostics are used to verify the load is connected properly.
In order to support fast system level start up requirements to play audio:
• The diagnostics are available as soon as the device power supplies are within the recommended operating
range.
• The diagnostics do not rely on external audio input signals or clock and sync frequencies to be available.
DC Diagnostics pass and allow a channel to enter MUTE or PLAY mode if the following tests pass on the output
pins:
• No short to ground
• No short to power
• No shorted load
• No open load
On completion of the diagnostic routine where no fault is reported, the respective CH(i) LDG STATE REPORT bit
of Channel State Report CH1, CH2 Register or Channel State Report CH3, CH4 Register is set high.
Any of the following conditions start the DC Load Diagnostics:
• Automatic DC load diagnostics at device initialization. Automatically on all four channels at device
initialization: After DVDD power on reset (POR) and when STANDBY Pin transitions from low to high.
• Automatic DC load diagnostics during Hi-Z to MUTE or PLAY transition. When any channel is directed to
leave the Hi-Z state and enter the MUTE or PLAY state.
• Manual start of DC load diagnostics. DC diagnostics can be enabled manually to run on any or all channels at
any time.
7.3.6.1.1 Automatic DC Load Diagnostics at Device Initialization
The TPA6304-Q1 supports automatic and autonomous DC load diagnostics at device start up. With power
stable, the device starts the internal power-on-reset. After completion of power-on-reset, the FAULT pin will be
pulled high. The next low to high transition on STANDBY pin starts an automatic DC load diagnostics on all four
channels.
No I2C configuration nor any audio signals are necessary for the TPA6304-Q1 to perform short-to-power (S2P),
short-to-ground (S2G), open load (OL), and shorted load (SL) based on default configuration. Systems can
benefit from this autonomous operation as it is possible to run the load diagnostics while bringing up the digital
part of the audio chain.
For each channel that yields a successful diagnostics test the CH(i) LDG STATE REPORT bit is set. For these
channels, once the system is ready to set the channel status to PLAY mode, no further delay is introduced.
Copyright © 2022 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
If the default values of automatic DC load diagnostics are not desired, the STANDBY pin can be held low until
the device is fully configured via I2C.
7.3.6.1.2 Automatic DC Load Diagnostics During Hi-Z to MUTE or PLAY Transition
By default, the LDG BYPASS bit in DC Load Diagnostics Control Register 1 is not set and the device starts the
DC load diagnostics when STANDBY is high and a channel is leaving HiZ state before entering MUTE or PLAY
state. If the automatic DC load diagnostics at device initialization already tested that channel with no faults
reported then DC load diagnostics is bypassed.
If DC load diagnostics identifies a fault, the CH(i) LDG STATE REPORT bit in Channel State Report CH1, CH2
Register or Channel State Report CH3, CH4 Register stays low indicating 'DC Load Diagnostic did not complete
without faults'. Details of the fault is reported in DC Load Diagnostic Report CH1, CH2 Register and DC Load
Diagnostic Report CH3, CH4 Register. The channel is retested after approximately 750 ms until either the fault
has been eliminated or the diagnostics function is turned off by I2C control.
If DC load diagnostics completed successfully CH(i) LDG STATE REPORT bit is set high.
7.3.6.1.3 Manual Start of DC Load Diagnostics
Automatic DC load diagnostics may not be a desired function at power up. Setting the LDG ABORT bit in DC
Load Diagnostics Control Register 1 disables automatic DC load diagnostics when pulling the STANDBY high.
This register must be written before the STANDBY pin is pulled high.
Before a channel can enter PLAY mode, DC load diagnostics need to be started manually.
To run manual DC load diagnostics:
1. Set audio channel into Hi-Z mode by setting CH(i) STATE CONTROL of Channel State Control Register to
'01'.
2. Write any desired control parameters for DC load diagnostics in DC Load Diagnostics Control Register 1, DC
Load Diagnostics Control Register 2, DC Load Diagnostics Control Register 3, DC Load Diagnostics Control
Register 4 and DC Load Diagnostics Control Register 5.
3. Set audio channel into Diag mode to start DC Diagnostics. For that, set CH(i) STATE CONTROL of Channel
State Control Register to '11'.
4. Monitor (read) CH(i) STATE REPORT bits in Channel State Report CH1, CH2 Register and Channel State
Report CH3, CH4 Register continuously until they change to '001'.
5. The DC load diagnostics results are stored in DC Load Diagnostic Report CH1, CH2 Register and DC Load
Diagnostic Report CH3, CH4 Register.
6. For each channel that yields a successful diagnostics test the CH(i) LDG STATE REPORT bit is set in
Channel State Report CH1, CH2 Register and Channel State Report CH3, CH4 Register. Once the system
is ready to set the channel status to PLAY mode, no further delay is introduced.
7.3.6.1.4 Short-to-Ground
The short-to-ground (S2G) tests triggers a fault condition if there is a conductive path from output pin OUT_(i)M
or OUT_(i)P of the tested channel (i) to GND with an impedance below that specified in the Specifications
section.
7.3.6.1.5 Short-to-Power
The short-to-power (S2P) tests triggers a fault condition if there is a conductive path from output pin OUT_(i)M or
OUT_(i)P of the tested channel (i) to a power rail with an impedance below that specified in the Specifications
section. The diagnostic also detects a short to vehicle battery when the supply is boosted.
7.3.6.1.6 Shorted Load and Open Load
The shorted load (SL) test triggers a fault condition if the conductive path between the OUT_(i)M pin and
OUT_(i)P pin of the tested channel (i) has an impedance below the threshold set in DC Load Diagnostics Control
Register 4 and DC Load Diagnostics Control Register 5. The SL test has a configurable threshold depending on
the expected load to be connected. Because the speakers and cable impedance connected to each channel
might be different, each channel can be assigned a unique threshold value.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
The open load (OL) test triggers a fault condition if the conductive path between the OUT_(i)M pin and OUT_(i)P
pin of the tested channel (i) has an impedance higher than that specified in the Specifications section.
Open Load
Open Load Detected
OL Maximum
Open Load (OL)
Detection Threshold
Normal or Open Load
May Be Detected
OL Minimum
SL Maximum
SL Minimum
Normal Load
Play Mode
Shorted Load (SL)
Detection Threshold
Normal or Shorted Load
May Be Detected
Shorted Load
Shorted Load Detected
图7-3. DC Load Diagnostic Reporting Thresholds
7.3.6.1.7 Line Output Diagnostics
The device also includes an optional test to detect a line output load (LO). DC Load Diagnostics Control Register
2 configures the channels that are enabled for LO testing. A line output load is a high-impedance load that is
above the open load (OL) threshold such that the DC-load diagnostics report an OL condition. If the line output
detection bit is set high, when an OL condition is detected during the DC Diagnostic test, the system also checks
if a line output load is present. This test may not be pop free, so if an external amplifier is connected it should be
muted.
7.3.6.2 AC Load Diagnostics
The AC load diagnostic is used to determine the proper connection of a capacitive coupled speaker or tweeter
when used with a passive crossover. The AC load diagnostic is controlled through I2C. The TPA6304-Q1
provides a required signal source to determine the AC impedance and reports the tweeter detection result back
to I2C registers. The I2C selected test frequency should create current flow through the desired speaker for
proper detection.
备注
If a fault occurs during AC diagnostics, the AC diagnostics is stopped. AC Diagnostics is not allowed
to be performed again until the DC Diagnostics are performed. This is to ensure the fault is not
potentially a hazard during AC diagnostics.
7.3.6.2.1 Operating Principal
The AC Load Diagnostic circuit of TPA6304-Q1 provides an internally generated stimulus to the load, captures
the response of the load, provides real and imaginary parts of the captured complex load impedance and offers
a magnitude estimator and tweeter detection comparator.
7.3.6.2.2 Stimulus
The frequency of the stimulus is set in AC Load Diagnostic Frequency Control Register. The device drives a low
level, 10 mA output current through the load which does not create any significant sound pressure levels from
the speaker.
7.3.6.2.3 Load Impedance
The load impedance as seen by the device is simply the ratio of voltage across the output pins and current
flowing through the load.
Copyright © 2022 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
Typically the load has a frequency dependent magnitude and causes current and voltage to have a phase shift.
The TPA6304-Q1 internally captures the load impedance as a complex value consisting of a real and imaginary
part. Expressing a load impedance in magnitude and phase or in real and imaginary part is mathematically
equivalent. Both forms can be transformed into each other without loss of information. After AC load diagnostics
has finished the real and imaginary parts of the complex impedance are available for readout in I2C registers
starting with the AC Load Diagnostic Report Real Part CH1 Register.
7.3.6.2.4 Tweeter Detection
In most cases, it is sufficient to use the TPA6304-Q1 built-in magnitude estimator and tweeter detection report to
perform the desired tweeter detection test. If a tweeter is properly connected in the system the magnitude of the
load impedance is close to the nominal impedance of the speaker , for example 4 Ω. Once AC load diagnostics
is finished, the magnitude of the load impedance is calculated and compared against a threshold set in the
Tweeter Detection Threshold Register. If the measured impedance is lower than the set threshold, the tweeter is
detected and marked accordingly in the Tweeter Detection Register.
7.3.6.2.5 Operation
To perform AC load diagnostics on TPA6304-Q1:
1. Use the Channel State Control Register to set the desired set of channels into Hi-Z mode.
2. Start the AC diagnostics by marking the channels in AC Load Diagnostic Control Register 1.
3. Poll the channel state from Channel State Report CH1, CH2 Register or Channel State Report CH3, CH4
Register. Once CH(i) STATE REPORT returns to 'Hi-Z' the AC load diagnostics results are ready for read
out.
7.3.7 Power Supply
The device has three power supply inputs:
• DVDD –This pin is a 3.3 V supply pin that provides power to the digital circuitry.
• VBAT –This pin is a higher voltage supply that can be connected to the vehicle battery or the regulated
voltage rail in a boosted system within the recommended limits. For best performance, this rail should be 10
V or higher. See the Recommended Operating Conditions table for the maximum supply voltage. This supply
rail is used for higher voltage analog circuits but not the output FETs.
• PVDD –This pin is a high-voltage supply that can either be connected to the vehicle battery or to another
voltage rail in a boosted system. The PVDD pin supplies the power to the output FETs and can be within the
recommended operating limits, even if that is below the VBAT supply, to allow for dynamic voltage systems.
An on-chip regulator is included generating the GVDD voltage necessary for the gate drive circuitry. The GVDD
supply pin is provided only for bypass capacitors to filter the supply and should not be used to power other
circuits.
The device can withstand fortuitous open ground and power conditions within the Absolute Maximum Ratings for
the device. Fortuitous open ground usually occurs when a speaker wire is shorted to ground, allowing for a
second ground path through the body diode in the output FETs.
7.3.7.1 Power-Supply Sequence
The device can accept any sequence of VBAT, PVDD and DVDD supply.
In a typical system, the VBAT and PVDD supplies are both connected to the vehicle battery and power up at the
same time.
7.3.7.1.1 Power-Up Sequence
At power-up, the STANDBY pin is recommended to be kept low till all three power supply rails (VBAT, PVDD,
DVDD) are within the Recommended Operating Conditions.
7.3.7.1.2 Power-Down Sequence
To power-down the device, first set the STANDBY pin low for at least 10ms before removing PVDD, VBAT or
DVDD. After 10ms, the power supplies can be removed.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.3.8 Device Initialization and Power-On-Reset (POR)
When the system first powers up, or when the DVDD voltage momentarily drops below the POR threshold, the
devices initializes.
• During device initialization all I2C registers are be set to default values.
• The FAULT Pin is activated and taken low.
• The I2C device address is determined from the pull-up resistor on the FAULT pin. See I2C Address Selection
for details.
• Once the device finished initialization, the open drain FAULT pin is released.
图 7-4 shows the time from DVDD voltage crossing the POR threshold to release of the FAULT pin is
approximately 10 ms.
After the initialization, bit 4 of the Power Fault Memory Register indicates that the device went through a POR
cycle. Reading this I2C register clears the fault signaling bit.
PVDD
VBAT
5.0V
4.2V
GVDD
VPOR_SET
DVDD
POR
/FAULT
I2C Ready
I2C
/STANDBY
AVDD
tSTART
POR
STANDBY
WAIT
20ms
DC DIAG
TDC_DIAG
AC DIAG
PLAY
TAC_DIAG
(Disabled by default)
图7-4. Typical Initialization Sequence and Timing
Copyright © 2022 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.3.9 Protection and Monitoring
7.3.9.1 Over Current Protection
If the output load current reaches over current shutdown threshold, ISD, such as during an output short to GND
or power supply, then an Over Current Shut Down (OCSD) Event occurs which limits the peak current and shuts
down the affected channel. There are four programmable OC levels that determine ISD. These can be set in
Miscellaneous Control Register 1. The time to shutdown the channel varies depending on the severity of the
short condition. The channel is placed into the PROTECTIVE SHUTDOWN State, the output stage is high
impedance.
Based on the default configuration a fault signal is generated which by default generates an active low signal at
the FAULT Pin.
7.3.9.2 DC Detect
The device monitors the DC offset continuously during normal operation at the output of the amplifier. If a
channel's DC offset exceeds the DCFAULT threshold, that channel triggers a DC Fault Event and is placed in the
PROTECTIVE SHUTDOWN State. This puts the output stage in high impedance.
By default, when a DC Fault Event occurs, a fault signal generates an active low signal on the FAULT Pin.
7.3.9.3 Load Current Limit
Under normal operation, during high level music playback, it is possible that dynamic load currents can rise
beyond the maximum load current, ILIM, of the device. In these cases, the device dynamically limits the current
into the load.
Each channel is independently monitored and limited. For each of the four over current (OC) levels that can be
set in Miscellaneous Control Register 1, there is a corresponding ILIM as shown in Specifications.
If the load current limit is active for at least 50% of a 200 ms window, the device generates a Load Current
Warning Event for the affected channel.
In case the load current warning event is active continuously for 800 ms the device generates a Load Current
Fault Event and the channel is placed in the PROTECTIVE SHUTDOWN State. This puts the output stage is
high impedance.
If OC level 4 is configured in Miscellaneous Control Register 1, the device will also generate a Load Current
Fault Event in case the load current limiter is active consecutively for more than 10 ms.
By default, a fault signal generates an active low signal on the FAULT Pin for when an OC event occurs.
7.3.9.4 Clip Detect
Each channel of the device monitors the output signal for situations at which the output voltage saturates and in
response can create a Clip Warning Event. Configuring the Clip Detect Signal Configuration Register can enable
clip detect, set the threshold at which clipping is detected to either 1%, 2%, 5% or 10%, and allows for mapping
channel groups to signals. Setting up GPIO Configuration Register or FAULT Pin Configuration Register to
output either Clip Detect Signal Group 1 or Clip Detect Signal Group 2 routes the signal through either Fault,
GPIO1 or GPIO2 of the TPA6304-Q1.
7.3.9.5 Temperature Protection and Monitoring
The device monitors temperature with five temperature sensors. Every output channel has one temperature
sensor in close proximity to monitor the temperature of it's respective channel. An additional sensor is located in
a global position on the die, so it better represents the actual die junction temperature. Based on these sensors
warning and fault signals can be generated. A Thermal Gain Foldback scheme is available that autonomously
regulates audio gain and consequently limit die temperature.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
FETs
OT1
OT2
OT3
OT4
CH1
CH2
CH3
CH4
FETs
FETs
FETs
OTGlobal
图7-5. Temperature Sensor Locations Within the Device
7.3.9.5.1 Over Temperature Shutdown (OTSD)
The temperature threshold for global OTSD and the threshold for over temperature shutdown generated by the
output channels, OTSD(i), are set to fixed values. Refer to Specifications for nominal temperature and recovery
hysteresis values.
If the global junction temperature rises above the OTSD threshold, all channels are placed into a protective
shutdown state. If the junction temperature of a channel rises above the OTSD threshold the affected channel is
put into a protective shutdown state. and an Over Temperature Shut Down (OTSD) Event is created. If over
temperature auto recovery is enabled, the effected channels recover the state they were in before OTSD
occurred once temperatures have cooled down below respective thresholds. The tolerance of the warning levels
and OTSD temperatures track each other.
By default, a fault signal generates an active low signal on the FAULT Pin for when an OTSD even occurs.
7.3.9.5.2 Over Temperature Warning (OTW)
The temperature threshold for global OTW has four levels and can be configured in Miscellaneous Control
Register 1. The OTW generated by the output channels, OTW(i), are set to a fixed value. Refer to Specifications
for nominal temperature and recovery hysteresis values.
During operation when the device heats up and crosses the threshold a global Over Temperature Warning Event
is generated. Similarly, if the temperature at a channel raises above the threshold an Over Temperature Warning
Event for that channel is generated. While the device continues to operate, the OTW information enables higher
level software to make decisions to optimize thermal system performance.
Based on the default configuration a Warning Signal is generated. As described in the Warning Signal section
the signal can either be polled via I2C register or a hardware signal can be generated by use of a GPIO Pin or
FAULT Pin.
7.3.9.5.3 Thermal Gain Foldback (TGFB)
The TGFB circuitry is designed to protect the TPA6304-Q1 from reaching excessive die temperatures. By
default, the TGFB is enabled and the device automatically reduces the gain and thereby output power when
either the global Over Temperature Warning Event (OTW) or any channel Over Temperature Warning Event,
OTW(i) is active. Simultaneously on all channels, the gain is stepped down in 0.5 dB steps with a max
attenuation of 12 dB. The gain increases as the temperature is reduced by the same gain step. The attack and
release time of the TGFB can be programmed.
The Thermal Gain Foldback Control Register controls whether TGFB is enabled, the rate of gain reduction
(attack) and the rate of gain increase or recovery (release). Pop free gain changes are controlled by enabling a
zero crossing detector. The zero crossing has a wait time before the gain can change. By default, TGFB and
zero crossing detector are enabled with a wait time of 20 µs. Zero Crossing behavior can be adjusted in the
Thermal Gain Foldback Control Register. When Thermal Gain Foldback is engaged, that is when the gain is
lower than 0 dB a Thermal Gain Foldback Warning Event is created.
Copyright © 2022 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
input signal
attack time
release time
output signal
图7-6. Thermal Foldback Attack and Release
7.3.9.6 Power Failures
The power supplies VBAT and PVDD are monitored for under-voltage and over-voltage events as described in
section Power Fault Events. This automatically engages shutdown and protects the device. VBAT and PVDD
safe operating voltage ranges can be found in the Recommended Operating Conditions table.
The device will shutdown if DVDD supply falls below VPOR_OFF. The DVDD POR fault event is described in
section Power Fault Events.
7.3.9.7 Load Dump Protection
When supply voltages at the VBAT and PVDD pins rise, over voltage shutdown as described in section Power
Fault Events engages and protects the device. The device can withstand 40 V load dump voltage spikes.
7.3.10 Hardware Control Pins
In addition to a STANDBY control pin and a FAULT status pin the device features the two general purpose IO
pins GPIO1 and GPIO2. Each GPIO Pin can be configured as WARNING status pin, MUTE control pin, Sync
Out or Sync In pin. For a complete list of pin configuration options please see Fault Pin Configuration Options
and GPIO Pin Options.
7.3.10.1 FAULT Pin
By default, the FAULT pin is configured to output the Fault Signal as active low signal under any of the following
conditions:
• Immediately following a power on reset (POR) until the device is ready to communicate via I2C
• DC fault
• Over current shutdown
• Load current fault
• Over temperature shutdown
Configuration of the Fault Signal in Fault Signal Configuration Register 1 and Fault Signal Configuration Register
2 allows the fine tuning of the device response to fault events.
After power up, once I2C communication is established the FAULT pin can be reconfigured to have different
behavior. This does not affect the reporting register content of faults or the protection of the device.
表7-2. Fault Pin Configuration Options
Name
Fault
Description
Setup Code
0000
FAULT pin outputs Fault Signal, active low
(default)
Warning
FAULT pin outputs Warning Signal, active low
0001
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
表7-2. Fault Pin Configuration Options (continued)
Name
Description
Setup Code
Clip Detect Group 1
Clip Detect Group 2
FAULT pin outputs Clip Detect Signal Group 1, active high
FAULT pin outputs Clip Detect Signal Group 2, active high
0010
0011
7.3.10.2 STANDBY Pin
The STANDBY pin is active low. The device is in a low current mode on the PVDD and VBAT pins while the
output pins are placed into a Hi-Z state. All internal analog biases disabled. In STANDBY and while DVDD is
present, the I2C bus is active and the internal registers are active.
Internally this pin is connected to DVSS with a 100 kΩpull-down resistor.
By default, the pin is configured in three level standby mode (TLSBY).
It is possible to communicate via I2C while STANDBY pin is low and the STANDBY pin functionality can be set to
two level mode by updating the TLSBY value of Micellaneous Control Register 4 during power up sequence.
表7-3. Two Level Mode
Input voltage at STANDBY pin
Device mode
Standby
Play
GND
DVDD
表7-4. Three Level Mode
Input voltage at STANDBY pin
Voltage Threshold
Device mode
Standby
Mute
GND
<0.5V
DVDD/2
DVDD
DVDD/2 +/- 0.5V
DVDD - 0.5V
Play
7.3.10.3 GPIO Pins
By default the two GPIO pins of the TPA6304-Q1 are in Hi-Z mode. During the initialization period of the system,
when the device gets configured via GPIO Configuration Register, the function of the GPIO can be configured.
表7-5. GPIO Pin Options
Functionality
Hi-Z
Mode
Off
Description
Setup Code
0000
Pin continuously is in Hi-Z mode
(default)
WARNING
FAULT
Open Drain Output
Open Drain Output
Output Buffer
Output Buffer
Output Buffer
Output Buffer
Output Buffer
Input
Warning Signal drives active low output
Fault Signal drives active low output
Clip Detect Signal Group 1 drives output
Clip Detect Signal Group 2 drives output
Modulator frequency drives output
Pin continuously drives logic high output
Pin continuously drives logic low output
Input signal drives modulator
0001
0010
0011
0100
0101
0110
0111
1000
1001
Clip Detect Group 1
Clip Detect Group 2
Sync Output
H
L
Sync Input
MUTE
Input
Active low input mutes the device
7.3.10.4 WARNING
The device does not have a dedicated WARNING status pin. Either GPIO1 or GPIO2 can be configured as
WARNING pin via GPIO Configuration Register. Once configured, the GPIO outputs the warning signal as active
low signal.
Copyright © 2022 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
The Warning Signal section holds details on configuration options and default settings of the warning signal.
7.3.10.5 MUTE
The device does not have a dedicated MUTE control pin. Either GPIO1 or GPIO2 can be configured as MUTE
pin via GPIO Configuration Register. Once configured the GPIO is active low input and is used for hardware
control of the mute and un-mute function for all channels. When the input signal is set low, all channels stop
switching and are set to Hi-Z mode. All internal analog circuitry is biased and enabled, and the input ac-coupling
capacitors are charged.
The hardware MUTE function is ORed with the I2C MUTE function. If either function is set, the MUTE function is
asserted.
7.4 Device Functional Modes
7.4.1 Internal Reporting Signals
To support software driver development, the TPA6304-Q1 allows the flexible configuration of internal fault,
warning, and clip detect signals. These signals, where applicable, can be configured based on current device
status registers or events stored in memory registers. Finally, these signals can be configured and routed to the
Fault, GPIO1, or GPIO2 pins for signaling purposes. For details on configuration and routing, see the Fault,
Warning and Clip Detect Signal Creation and Configuration section.
7.4.1.1 Fault Signal
Automotive systems have a high demand on gathering device information in case of unexpected conditions. The
Fault Signal Configuration Register 1 and Fault Signal Configuration Register 2 of the TPA6304-Q1 allow for a
flexible configuration of information necessary for higher level system software to effectively control the system.
The Fault Signal can be configured to be active in response to the following Fault Events:
• Over current shutdown, typically caused by shorts to power or short to ground (latched)
• Shutdown due to DC detection (latched)
• Load current failures, typically caused by shorted load (latched)
• Power failures (latched or non-latched)
• Over-temperature failures (latched or non-latched)
• Clock sync failures, if the device is in clock slave mode (latched or non-latched)
• Channel 1, 2, 3 or 4 in protective shutdown state
• Incomplete diagnostics
• Warning Signal being active
The Fault Signal, by default, gets routed to a GPIO Pin to create a HW signal. Its state can be polled by I2C read
at any time from OTSD CS Fault Status Register.
7.4.1.2 Warning Signal
The Warning Signal can be configured to be active in response to following Warning Events:
• Over-temperature warning (latched or non-latched)
• Thermal Gain Foldback being activated (latched or non-latched)
• Load current warning (latched)
• Power failures (latched or non-latched)
• Over temperature failures (latched or non-latched)
• Clip Detect (latched or non-latched)
• Incomplete diagnostics
• Clock sync failures, if the device is in clock secondary mode (latched or non-latched)
By default, the Warning Signal is active in response to latched over temperature warning events.
The Warning Signal can be routed to a GPIO Pin to create a HW signal or its state can be polled by I2C read at
any time from OTSD CS Fault Status Register.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.4.1.3 Clip Detect Signal
The clip detect signal can be routed out of the TPA6304-Q1 to support hardware control loops that limit THD in
the event of excessively large audio signals. Two independent clip detect signals can be generated. The clip
detect signal is based on clip detect warning events.
Section Clip Detect describes the circumstances under which the device creates clip detect warning signals.
Each output channel independently creates a clip detect warning signal.
Clip Detect Signal Group 1 can be configured in the Clip Detect Signal Configuration Register to be active when
either CH1 or CH2 create a clip detect warning, CH3 or CH4 create a clip detect warning, or any of the four
channels creates a clip detect warning.
Clip Detect Signal Group 2 can be configured in the same way as Clip Detect Signal Group 1.
Copyright © 2022 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
From channel status (cleared by ”clear fault‘)
Any ”101‘ channel state
0x1Db6
Channel Over Current
and DC Detection Fault
Memory
Any OC Fault latched
0x1Db1
4
4
0xF, 7:4
0xF, 3:0
Any DC Fault latched
0x1Db2
Any Power Fault latched
0x1Fb3
Power Fault Memory
0x10, 5:0
Any Power Fault latched
0x1Db3
6
Any Power Fault
0x20b3
Power Fault Status
0x11, 7:5, 3:0
Any Power Fault
0x1Eb3
7
5
Any OT Fault latched
0x1Fb4
Temperature (OTSD)
and Clock Sync Fault
Memory
Any OT Fault latched
0x1Db4
0x12, 4:0
0x12, 5
Sync Clock Fault latched
0x1Db5
Sync Clock Fault latched
0x1Fb5
13
12
Any OT Fault
0x20b4
Temperature (OTSD)
and Clock Sync Fault
Status
Any OT Fault
0x1Eb4
5
0x13, 4:0
0x13, 5
Sync Clock Fault
0x1Eb5
Sync Clock Fault
0x20b5
Channel Load Current
Fault Memory
Any DC Diag Fault
0x20b0
Any DC Diag Fault
0x1Eb0
4
0x14, 3:0
0x13b6
Any Load Current
Fault latched
0x1Db0
Fault Signal
Channel Load Current
Warning Memory
Any Load Current
Warning latched
0x1Fb0
4
5
0x15, 3:0
Warning Signal active
0x1Eb6
Temperature (OTW) and
Thermal Gain Foldback
Warning Memory
Any OT Warning latched
0x1Fb2
0x16, 4:0
FaultZ
GPIO1
0x16, 5
0x13b7
Thermal Foldback
activation latched
0x1Fb1
Warning Signal
Temperature (OTW) and
Thermal Gain Foldback
Warning Status
PIN
MUX
Any OT Warning
0x20b2
5
0x17, 4:0
Fault Signal Configuration
Register 1: 0x1D
Register 2: 0x1E
GPIO2
0x17, 5
Thermal Foldback active
0x20b1
Channel Clip Detect
Warning Memory
0x21b0
0x21b2
0x21b1
0x21b3
4
Clip Detect Signal Group 1
0x18, 3:0
Any Clip detect latched
0x1Fb6
Channel Clip Detect
Warning Status
CH1 0x19, 3
CH2 0x19, 2
CH3 0x19, 1
CH4 0x19, 0
Clip Detect Signal Group 2
Warning Signal Configuration
Register 1: 0x1F
Register 2: 0x20
Clip Detect Configuration
Register: 0x21
图7-7. Fault, Warning and Clip Detect Signal Creation and Configuration
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.4.2 Device States and Flags
7.4.2.1 Audio Channel States
Every audio channel has its set of states that carefully control the set up and shut down procedure of an audio
path from source to load. These states are listed in Audio Channel States, Channel states get reported in
Channel State Report CH1, CH2 Register and Channel State Report CH3, CH4 Register.
表7-6. Audio Channel States
STATE NAME
DIAG
OUTPUT FETS
OSCILLATOR
Stopped
Active
I2C
Hi-Z
Active
Active
Active
Active
Active
Active
Hi-Z
Hi-Z
MUTE
Hi-Z
Switching with audio
Hi-Z
Active
PLAY
Active
PSD
Active
PSD_AR
Hi-Z
Active
7.4.2.1.1 PROTECTIVE SHUTDOWN with AUTO RECOVERY State
If one or more channels of the device are in PLAY state the device may need to take protective actions and
shutdown one or more audio channels. The output FETs of the affected channels are turned off and the output
pins are high impedance. Once the cause for the protective shutdown is no longer present, the device resumes
back to PLAY. The reported state for affected channels is PROTECTIVE SHUTDOWN with AUTO RECOVERY
Possible reason for individual channels to enter this state is:
• Channel over temperature shutdown (OTSD(i))
Possible reasons for all channels to enter this state are:
• Power failures
• Invalid Clock
• Global over temperature shutdown (OTSD)
The following registers hold all information necessary to identify the reason for the device being in this state:
• Temperature (OTSD) and Clock Sync Fault Status Register
• Power Fault Status Register
7.4.2.1.2 PROTECTIVE SHUTDOWN State
If one or more channels of the device are in PLAY state the device may need to take protective actions and
shutdown one or more audio channels. The output FETs of the affected channels is turned off and the output
pins are high impedance. The reported state for affected channels is PROTECTIVE SHUTDOWN
Possible reasons for individual channels to enter this state are:
• Over Current Shutdown
• Load Current Fault
• DC fault
• Channel over temperature shutdown (OTSD(i))
Possible reason for all channels to enter this state is:
• Global over temperature shutdown (OTSD)
The following registers hold all information necessary to identify the reason for the device being in this state:
• Temperature (OTSD) and Clock Sync Fault Status Register
• Channel Over Current and DC Detection Fault Memory Register
• Channel Load Current Fault Memory Register
Copyright © 2022 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.4.2.1.2.1 Clear Fault
备注
If one or more channels are in PROTECTIVE SHUTDOWN State, the channel faults only recover after
setting the CLEAR FAULT bit in the Miscellaneous Control Register 3.
This clears the faults and set channels into Hi-Z mode.
7.4.2.2 Status and Memory Registers
7.4.2.2.1 Status Registers
The device reports device states and environmental information by means of status and reporting registers. The
following set of registers, at any time, hold the full set of device status:
• Channel State Report CH1, CH2 Register
• Channel State Report CH3, CH4 Register
• Power Fault Status Register
• Temperature (OTSD) and Clock Sync Fault Status Register
• Temperature (OTW) and Thermal Gain Foldback Warning Status Register
• Thermal Gain Foldback Status Register
Interrupt driven signaling to the controlling host device is supported by creation of events. Events can be
configured to create Warning Signal and Fault Signal.
Alternatively software can routinely read this set of registers to gather device status (polling mode).
7.4.2.2.2 Memory Registers
The device provides a set of memory registers which latch events. This allows software drivers to properly
analyze fault situations.
The following set of memory registers is available:
• Channel Over Current and DC Detection Fault Memory Register
• Power Fault Memory Register
• Temperature (OTSD) and Clock Sync Fault Memory Register
• Channel Load Current Fault Memory Register
• Channel Load Current Warning Memory Register
• Temperature (OTW) and Thermal Gain Foldback Warning Memory Register
• Channel Clip Detect Warning Memory Register
The memory registers, for example, support the following scenarios:
• The output pin of the device gets shorted to ground, the device reacts immediately and goes into
PROTECTIVE SHUTDOWN State. The software device driver may want to identify why the device is in
protective shutdown mode and reads the registers described in the PROTECTIVE SHUTDOWN State
section.
• The digital power rail just came up or dropped below POR levels. The device resets all settings and indicates
that in the Power Fault Memory Register with the DVDD POR STORED bit set.
• The device heated up and temporarily reducing audio gain. Software can check whether this situation has
happened since the last read of Temperature (OTW) and Thermal Gain Foldback Warning Memory Register.
备注
Memory registers only provide information to the controlling host. Reading the memory register clears
the content. The status of the device does not change by reading the memory registers.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.4.3 Fault Events
7.4.3.1 Overview
The device creates fault events as outlined in Details On Generated Fault Events.
表7-7. Details On Generated Fault Events
Channel
Required User
Response
Current status (non-
latched) reported in
Event latched and
Fault Event
Typical Reason
Status
reported in 2
Reporting 1
VBAT Over
Voltage Fault
Apply VBAT within
spec
VBAT above limit
VBAT below limit
PVDD above limit
'100'
VBAT Under
Voltage Fault
Apply VBAT within
spec
PROTECTIVE
SHUTDOWN
with AUTO
RECOVERY
State
Power Fault Status
Register
PVDD Over
Voltage Fault
Apply PVDD within
spec
Power Fault Memory
Register
PVDD Under
Voltage Fault
Apply PVDD within
spec
PVDD below limit
GVDD Fault
GVDD regulator fault
DVDD voltage
dropped below POR
limit or initial device
startup
'001'
Hi-Z State
Write initial device
DVDD POR
N/A
configuration via I2C
Over
Temperature SD
- Channel
Channel temperature
above limit
'101'
Temperature (OTSD) and Temperature (OTSD) and
PROTECTIVE
SHUTDOWN
State
Clear Fault
Clear Fault
Clock Sync Fault Status
Register
Clock Sync Fault Memory
Register
Over
Temperature SD
- Global
Die temperature
above limit
Over Current
Shut Down
(OCSD) Event
Short to ground or
short to power
Channel Over Current and
DC Detection Fault
Memory Register
'101'
PROTECTIVE
SHUTDOWN
State
DC voltage at device
input
N/A
DC Fault Event
Load Current
Fault Event
Channel Load Current
Fault Memory Register
Shorted load
'100'
PROTECTIVE
SHUTDOWN Apply sync clock signal
with AUTO
RECOVERY
State
Missing clock signal
while device set up
as clock slave
Temperature (OTSD) and Temperature (OTSD) and
Invalid Clock
Fault Event
Clock Sync Fault Status
Register
Clock Sync Fault Memory
Register
within nominal range
If 'OTSD auto recovery' is enabled in Miscellaneous Control Register 3:
Over
Temperature
SD- Channel
'100'
Channel temperature
above limit
PROTECTIVE
SHUTDOWN
with AUTO
RECOVERY
State
Temperature (OTSD) and Temperature (OTSD) and
Cool down device
Clock Sync Fault Status
Register
Clock Sync Fault Memory
Register
Over
Temperature SD
- Global
Die temperature
above limit
7.4.3.2 Power Fault Events
Current status of power fault events is reported in Power Fault Status Register and latched events are reported
in Power Fault Memory Register
1
See Channel State Report CH1, CH2 Register and Channel State Report CH3, CH4 Register for details.
Reading the memory register clears its content. This does not clear fault conditions.
2
Copyright © 2022 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.4.3.2.1 DVDD POR
When DVDD falls below VPOR_OFF the device shuts down. All channels are brought into Hi-Z State and I2C
communication terminates. When DVDD comes back up above VPOR_SET or when the device gets first powered
up and DVDD rises above VPOR_SET the device initiates a Power-On-Reset routine. During this routine all
registers and device states are set to default values. It is intended behavior that Power Fault Memory Register
reports "DVDD power on reset event stored" after power up.
As DVDD POR is a transient event it is not reported in the Power Fault Status register.
7.4.3.2.2 VBAT Over Voltage Fault
When the VBAT supply rail rises above nominal range a VBAT Over Voltage Fault event is created and the
device enters into PROTECTIVE SHUTDOWN with AUTO RECOVERY State. Once VBAT falls back down into
nominal range, the fault event is cleared.
7.4.3.2.3 VBAT Under Voltage Fault
When the VBAT supply rail falls below nominal range a VBAT Over Voltage Fault event is created and the device
enters into PROTECTIVE SHUTDOWN with AUTO RECOVERY State. Once VBAT rises back up into nominal
range, the fault event is cleared.
7.4.3.2.4 PVDD Over Voltage Fault
When the PVDD supply rail rises above nominal range a PVDD Over Voltage Fault event is created and the
device enters into PROTECTIVE SHUTDOWN with AUTO RECOVERY State. Once PVDD falls back down into
nominal range, the fault event is cleared.
7.4.3.2.5 PVDD Under Voltage Fault
When the VBAT supply rail falls below nominal range a PVDD Under Voltage Fault event is created and the
device enters into PROTECTIVE SHUTDOWN with AUTO RECOVERY State. Once PVDD rises back up into
nominal range, the fault event is cleared.
7.4.3.2.6 GVDD Fault
This fault indicates a fault condition of the internal gate drive circuitry.
7.4.3.3 Over Temperature Shut Down (OTSD) Event
Section Over Temperature Shutdown describes the circumstances under which the device creates an OTSD
event.
Current status of over termperature is reported in Temperature (OTSD) and Clock Sync Fault Status Register
and latched events are reported in Temperature (OTSD) and Clock Sync Fault Memory Register
By default, if temperatures rise above the OTSD threshold the device is in PROTECTIVE SHUTDOWN State.
Setting the 'OTSD auto recovery' bit in Miscellaneous Control Register 3 configures the device to be in
PROTECTIVE SHUTDOWN with AUTO RECOVERY State while temperatures are above OTSD thresholds.
7.4.3.4 Over Current Shut Down (OCSD) Event
Section Over current protection describes the circumstances under which the device creates an OCSD event.
As Over Current Shut Down (OCSD) Event is a transient event it is not reported in a status register. The latched
OCSD events are reported in Channel Over Current and DC Detection Fault Memory Register. Affected
channels are in PROTECTIVE SHUTDOWN State.
Over Current Shut Down (OCSD) Event also triggers when Load Current Fault Event triggers.
7.4.3.5 DC Fault Event
The DC Detect section describes the circumstances under which the device creates a DC fault event.
As DC Fault Event is a transient event it does not report in a status register. The latched DC fault events are
reported in Channel Over Current and DC Detection Fault Memory Register. Affected channels are in
PROTECTIVE SHUTDOWN State.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.4.3.6 Load Current Fault Event
The Load Current Limit section describes the circumstances under which the device creates a load current fault
event. This is a transient event that only lasts for a limited time. The device latches the event in Channel Load
Current Fault Memory Register.
7.4.3.7 Invalid Clock Fault Event
The Clock Synchronization section describes how two devices operate with synchronized clocks. The device in
clock slave mode receives a sync clock. If this sync clock is out of nominal frequency range or suddenly stops,
an Invalid Clock Fault Event is created and the device gracefully tranistions to the PROTECTIVE SHUTDOWN
with AUTO RECOVERY State. Once sync clock comes back into nominal frequency range the fault events are
cleared and the device auto recovers.
Current status is reported in Temperature (OTSD) and Clock Sync Fault Status Register and the latched event is
reported in Temperature (OTSD) and Clock Sync Fault Memory Register.
7.4.4 Warning Events
7.4.4.1 Overview
The device creates warning events as outlined in 表7-8.
表7-8. Details On Generated Warning Events
Current status (non-latched)
Warning Event
Typical Reason
Event latched and reported in
reported in
Over Temperature -
Channel
Channel temperature above
warning threshold
Over Temperature -
Global
Die temperature above warning Temperature (OTW) and Thermal Gain Temperature (OTW) and Thermal Gain
threshold
Foldback Warning Status Register
Foldback Warning Memory Register
Thermal Gain Foldback Die temperature above
active
threshold and TGFB enabled
Peak current into load reaches
maximum
Channel Load Current Warning
Memory Register
Load Current - Channel
N/A
Channel Clip Detect Warning Status
Register
Channel Clip Detect Warning Memory
Register
Clip Warning Event
Output voltage saturation
7.4.4.2 Over Temperature Warning Event
Section Over Temperature Shutdown describes the circumstances under which the device creates an Over
Temperature Warning event.
Thermal Gain Foldback, when enabled, responds to over temperature warning events.
Current status is reported in Temperature (OTW) and Thermal Gain Foldback Warning Status Register and
latched events are reported in Temperature (OTW) and Thermal Gain Foldback Warning Memory Register.
7.4.4.3 Thermal Gain Foldback Warning Event
When Thermal Gain Foldback is enabled and if it has reduced the gain below 0 dB due to high temperature, the
device creates a thermal gain foldback warning event. Once the temperature decreases and the gain foldback
circuitry releases the gain back up to 0 dB, this warning is cleared. Current status is reported in Temperature
(OTW) and Thermal Gain Foldback Warning Status Register and latched events are reported in Temperature
(OTW) and Thermal Gain Foldback Warning Memory Register.
7.4.4.4 Load Current Warning Event
Section Load current limit describes the circumstances under which the device creates a load current warning
event. The device latches the event in Channel Load Current Warning Memory Register. As this is a transient
event it is not reported in a status register.
7.4.4.5 Clip Warning Event
Section Clip Detect describes the circumstances under which the device creates a clip warning event.
Copyright © 2022 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
Current clip warning status is reported in Channel Clip Detect Warning Status Register and latched events are
reported in Channel Clip Detect Warning Memory Register.
7.5 Programming
7.5.1 I2C Serial Communication Bus
The device communicates with the system processor via the I2C serial communication bus as an I2C slave-only
device. The processor can poll the device via I2C to determine the operating status, configure settings, or run
diagnostics. For a complete list and description of all I2C controls, see the Register Maps section.
7.5.1.1 I2C Address Selection
The device supports two I2C addresses, so up to two devices can be used together in a system with no
additional bus switching hardware. The pull up resistor connected to the device FAULT pin and DVDD
determines the I2C address during power up. If two devices are present in a system their FAULT pin outputs
must not be shared in order for the I2C address detection circuitry to operate correctly. The slave addresses of
the device are listed in I2C Addresses.
表7-9. I2C Addresses
FAULT pin pull up
resistor value
I2C Write
I2C Read
DESCRIPTION
Device 0
Device 1
0x58
0x5A
0x59
0x5B
Floating
47k
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.5.2 I2C Bus Protocol
The device has a bidirectional serial control interface that is compatible with the Inter IC (I2C) bus protocol and
supports 100 and 400-kbps data transfer rates for random and sequential write and read operations. This is a
slave-only device that does not support a multimaster bus environment or wait-state insertion. The control
interface is used to program the registers of the device and to read device status.
The I2C bus uses two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-
bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop
conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. The master generates the 7-bit
slave address and the read/write (R/W) bit to open communication with another device and then wait for an
acknowledge condition. The device holds SDA LOW during the acknowledge-clock period to indicate an
acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals
via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and
SCL signals to set the HIGH level for the bus. There is no limit on the number of bytes that can be transmitted
between start and stop conditions. When the last word transfers, the master generates a stop condition to
release the bus.
R/
W
8-Bit Register Data for
Address (N)
8-Bit Register Data for
Address (N)
7-Bit Slave Address
A
8-Bit Register Address (N)
A
A
A
SDA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
Start
Stop
图7-8. Typical I2C Sequence
t
t
t
r
t
f
w(H)
w(L)
SCL
t
t
h1
su1
SDA
图7-9. SCL and SDA Timing
Use the I2C ADDRx pins to program the device slave address. Read and write data can be transmitted using
single-byte or multiple-byte data transfers.
7.5.2.1 Random Write
As shown in Random Write Transfer, a single-byte data-write transfer begins with the master device transmitting
a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the
direction of the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C
device address and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits
the address byte or bytes corresponding to the internal memory address being accessed. After receiving the
Copyright © 2022 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
address byte, the device again responds with an acknowledge bit. Next, the master device transmits the data
byte to be written to the memory address being accessed. After receiving the data byte, the device again
responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-
byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
ACK
A4
R/W
A7
ACK
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5
ACK
A6 A5
A3 A2 A1 A0
D4 D3 D2 D1 D0
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
Data Byte
图7-10. Random Write Transfer
7.5.2.2 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master to the device as shown in . After receiving each data byte, the device responds with an
acknowledge bit and the I2C subaddress is automatically incremented by one.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A5
A0
R/W ACK
A4 A3
A0
ACK
ACK
ACK
ACK
D0
A6
A1
A7
A6
A5
A1
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte
Other Data Byte
Last Data Byte
图7-11. Sequential Write Transfer
7.5.2.3 Random Read
As shown in , a single-byte data-read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. For the data-read transfer, both a write followed by a
read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory
address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the
device responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes,
the master device transmits another start condition followed by the address and the read/write bit again. This
time the read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the
device again responds with an acknowledge bit. Next, the device transmits the data byte from the memory
address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a
stop condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
D0 D6
A6 A5
A1 A0
A7 A6 A5 A4
Subaddress
A0
A6 A5
A1 A0
D7 D6
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Data Byte
图7-12. Random Read Transfer
7.5.2.4 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the device to the master device as shown in . Except for the last data byte, the master device
responds with an acknowledge bit after receiving each data byte and automatically increments the I2C
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
subaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge followed
by a stop condition to complete the transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
ACK
ACK
D0
A6
A0
A7 A6 A5
A0
A6
A0
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte Other Data Byte Last Data Byte
图7-13. Sequential Read Transfer
Copyright © 2022 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6 Register Maps
7.6.1 Registers
表 7-10 lists all registers, their functionality and default values. All register offset addresses not listed in 表 7-10
should be considered as reserved locations and the register contents should not be modified.
表7-10. Register Map
Offset
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
Acronym
Register Name
Section
节7.6.1.2
节7.6.1.3
节7.6.1.4
节7.6.1.5
节7.6.1.6
节7.6.1.7
节7.6.1.8
节7.6.1.9
节7.6.1.10
节7.6.1.11
节7.6.1.12
节7.6.1.13
Mode Control
Mode Control Register
Misc Control 1
Misc Control 2
Channel State Control
DC LDG Ctrl 1
DC LDG Ctrl 2
DC LDG Ctrl 3
DC LDG Ctrl 4
DC LDG Ctrl 5
DC LDG Rprt CH12
DC LDG Rprt CH34
DC LDG Rprt LO
Miscellaneous Control Register 1
Miscellaneous Control Register 2
Channel State Control Register
DC Load Diagnostics Control Register 1
DC Load Diagnostic Control Register 2
DC Load Diagnostic Control Register 3
DC Load Diagnostic Control Register 4
DC Load Diagnostic Control Register 5
DC Load Diagnostic Report CH1, CH2 Register
DC Load Diagnostic Report CH3, CH4 Register
DC Load Diagnostic Report Lineout Loads
Register
0xD
0xE
0xF
Channel State Rprt CH12
Channel State Rprt CH34
Ch OC DC Fault Mem
Channel State Report CH1, CH2 Register
Channel State Report CH3, CH4 Register
节7.6.1.14
节7.6.1.15
节7.6.1.16
Channel Over Current and DC Detection Fault
Memory Register
0x10
0x11
0x12
Power_Fault_Mem
Power Fault Status
OTSD CS Fault Mem
Power Fault Memory Register
Power Fault Status Register
节7.6.1.17
节7.6.1.18
节7.6.1.19
Temperature (OTSD) and Clock Sync Fault
Memory Register
0x13
OTSD CS Fault Status
Temperature (OTSD) and Clock Sync Fault Status
Register
节7.6.1.20
0x14
0x15
0x16
Ch Current Fault Mem
Ch Current Warn Mem
OTW TGFB Warn Mem
Channel Load Current Fault Memory Register
Channel Load Current Warning Memory Register
节7.6.1.21
节7.6.1.22
节7.6.1.23
Temperature (OTW) and Thermal Gain Foldback
Warning Memory Register
0x17
OTW TGFB Warn Status
Temperature (OTW) and Thermal Gain Foldback
Warning Status Register
节7.6.1.24
0x18
0x19
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
Ch ClipDet Warn Mem
Ch ClipDet Warn Status
TGFB Status
Channel Clip Detect Warning Memory Register
Channel Clip Detect Warning Status Register
Thermal Gain Foldback Status Register
Fault Signal Configuration Register 1
Fault Signal Configuration Register 2
Warning Signal Configuration Register 1
Warning Signal Configuration Register 2
Clip Detect Signal Configuration Register
Fault Pin Configuration Register
节7.6.1.25
节7.6.1.26
节7.6.1.27
节7.6.1.28
节7.6.1.29
节7.6.1.30
节7.6.1.31
节7.6.1.32
节7.6.1.33
节7.6.1.34
节7.6.1.35
节7.6.1.36
Fault Sig Conf 1
Fault Sig Conf 2
Warn Sig Conf 1
Warn Sig Conf 2
Clip Det Sig Conf
Fault Pin Conf
GPIO Conf
GPIO Pin Configuration Register
AC LDG Ctrl 1
AC Load Diagnostic Control Register 1
AC Load Diagnostic Control Register 2
AC LDG Ctrl 2
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
表7-10. Register Map (continued)
Offset
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
Acronym
Register Name
Section
TWEETER DET THRESH
AC LDG Rprt CH1 R
AC LDG Rprt CH1 I
AC LDG Rprt CH2 R
AC LDG Rprt CH2 I
AC LDG Rprt CH3 R
AC LDG Rprt CH3 I
AC LDG Rprt CH4 R
AC LDG Rprt CH4 I
TWEETER DET
Misc Control 3
Tweeter Detection Threshold
AC Load Diagnostic Report R CH1
AC Load Diagnostic Report I CH1
AC Load Diagnostic Report R CH2
AC Load Diagnostic Report I CH2
AC Load Diagnostic Report R CH3
AC Load Diagnostic Report I CH3
AC Load Diagnostic Report R CH4
AC Load Diagnostic Report I CH
Tweeter Detection
节7.6.1.37
节7.6.1.38
节7.6.1.39
节7.6.1.40
节7.6.1.41
节7.6.1.42
节7.6.1.43
节7.6.1.44
节7.6.1.45
节7.6.1.46
节7.6.1.47
节7.6.1.48
节7.6.1.49
节7.6.1.50
节7.6.1.51
节7.6.1.52
节7.6.1.53
节7.6.1.54
节7.6.1.55
节7.6.1.56
Miscellaneous Control Register 3
Revision ID
REVID
TGFB Ctrl
Thermal Gain Foldback Control Register
AC Load Diagnostic Frequency Control Register
Sync Pin Control Register
AC LDG FREQ Ctrl
SYNC Ctrl
Misc Control 4
Miscellaneous Control Register 4
Spread Spectrum Control Register 1
Spread Spectrum Control Register 2
PWM Phase Control Register 1
PWM Phase Control Register 2
SS Control 1
SS Control 2
PWM Phase Ctrl 1
PWM Phase Ctrl 2
Copyright © 2022 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.1 Mode Control Register (Offset = 0x1) [reset = 0x00]
Return to the 表7-10.
图7-14. Mode Control Register
7
6
5
4
3
2
1
0
RESET
W-0b
PWM MODE
R/W-0b
PBTL_34
R/W-0b
PBTL_12
R/W-0b
CH1 LO MODE CH2 LO MODE CH3 LO MODE CH4 LO MODE
R/W-0b R/W-0b R/W-0b R/W-0b
表7-11. Mode Control Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESET
W
0b
0: Normal Operation
1: Soft reset, will auto clear
6
5
4
3
2
1
0
PWM MODE
PBTL_34
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0b
0: BD Mode
1: 1SPW Mode
0: BTL mode
1: PBTL mode of Channel 3 and Channel 4
PBTL_12
0: BTL mode
1: PBTL mode of Channel 1 and Channel 2
CH1 LO MODE
CH2 LO MODE
CH3 LO MODE
CH4 LO MODE
0: Channel 1 is in normal / speaker mode
1: Channel 1 is in line output mode
0: Channel 2 is in normal / speaker mode
1: Channel 1 is in line output mode
0: Channel 3 is in normal / speaker mode
1: Channel 1 is in line output mode
0: Channel 4 is in normal / speaker mode
1: Channel 1 is in line output mode
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.2 Misc Control 1 Register (Offset = 0x2) [reset = 0x10]
Return to the 表7-10.
图7-15. Misc Control 1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0b
PI Control
R/W-0b
OTW CONTROL
R/W-1b
OC CONTROL
R/W-0b
RESERVED
R/W-0b
表7-12. Misc Control 1 Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
Description
0b
6
PI Control
0b
0: Disable Pulse Injection Mode
1: Enable Pulse Injection Mode
5-4
3-2
OTW CONTROL
R/W
1b
00: Global over temperature warning set to 140 °C
01: Global over temperature warning set to 130 °C
10: Global over temperature warning set to 120 °C
11:Global over temperature warning set to 110 °C
OC CONTROL
RESERVED
R/W
0b
See electrical characteristics table for details
00: OC Level 1
01: OC Level 2
10: OC Level 3
11: OC Level 4
1-0
R/W
0b
Copyright © 2022 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.3 Misc Control 2 Register (Offset = 0x3) [reset = 0xFF]
Return to the 表7-10.
图7-16. Misc Control 2 Register
7
6
5
4
3
2
1
0
CH1 GAIN
R/W-11b
CH2 GAIN
R/W-11b
CH3 GAIN
R/W-11b
CH4 GAIN
R/W-11b
表7-13. Misc Control 2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-4
3-2
1-0
CH1 GAIN
R/W
11b
00: 10dB
01: 16dB
10: 22dB
11: 28dB
CH2 GAIN
CH3 GAIN
CH4 GAIN
R/W
R/W
R/W
11b
11b
11b
00: 10dB
01: 16dB
10: 22dB
11: 28dB
00: 10dB
01: 16dB
10: 22dB
11: 28dB
00: 10dB
01: 16dB
10: 22dB
11: 28dB
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.4 Channel State Control Register (Offset = 0x4) [reset = 0x55]
Return to the 表7-10.
图7-17. Channel State Control Register
7
6
5
4
3
2
1
0
CH1 STATE CONTROL
R/W-1b
CH2 STATE CONTROL
R/W-1b
CH3 STATE CONTROL
R/W-1b
CH4 STATE CONTROL
R/W-1b
表7-14. Channel State Control Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
CH1 STATE CONTROL
R/W
1b
00: Set channel state to PLAY
01: Set channel state to HI-Z
10: Set channel state to MUTE
11: Set channel to start DC load diagnostic
5-4
3-2
1-0
CH2 STATE CONTROL
CH3 STATE CONTROL
CH4 STATE CONTROL
R/W
R/W
R/W
1b
1b
1b
00: Set channel state to PLAY
01: Set channel state to HI-Z
10: Set channel state to MUTE
11: Set channel to start DC load diagnostic
00: Set channel state to PLAY
01: Set channel state to HI-Z
10: Set channel state to MUTE
11: Set channel to start DC load diagnostic
00: Set channel state to PLAY
01: Set channel state to HI-Z
10: Set channel state to MUTE
11: Set channel to start DC load diagnostic
Copyright © 2022 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.5 DC LDG Ctrl 1 Register (Offset = 0x5) [reset = 0x00]
Return to the 表7-10.
图7-18. DC LDG Ctrl 1 Register
7
6
5
4
3
2
1
0
LDG ABORT
LDG BUFFER WAIT TIME
RESERVED
R/W-0b
LDG WAIT
BYPASS
LDG SLOL
DISABLE
LDG BYPASS
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表7-15. DC LDG Ctrl 1 Register Field Descriptions
Bit
Field
LDG ABORT
Type
Reset
Description
7
R/W
0b
0: Normal operation
1: Abort DC load diagnostic
6-5
LDG BUFFER WAIT TIME R/W
0b
00: Buffer wait time 1ms
01: Buffer wait time 2ms
10: Buffer wait time 5ms
11: Buffer wait time 10ms
4-3
2
RESERVED
R/W
R/W
0b
0b
LDG WAIT BYPASS
0: Enable the waiting loop at the end of shorted / open load
detection
1: Bypass the waiting loop at the end of shorted / open load
detection
1
0
LDG SLOL DISABLE
LDG BYPASS
R/W
R/W
0b
0b
0: Shorted load and open load detection are enabled
1: Shorted load, open load and line out out detection are disabled
0: Automatic DC diagnostic when leaving Hi-Z mode and after
channel fault
1: DC diagnostic will not run automatically
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.6 DC LDG Ctrl 2 Register (Offset = 0x6) [reset = 0x00]
Return to the 表7-10.
图7-19. DC LDG Ctrl 2 Register
7
6
5
4
3
2
1
0
RESERVED
LDG S2PS2G
AVG TIME
LDG SLOL AVG TIME
R/W-0b
LDG LO
ENABLE CH1
LDG LO
ENABLE CH2
LDG LO
ENABLE CH3
LDG LO
ENABLE CH4
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表7-16. DC LDG Ctrl 2 Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R/W
0b
6
LDG S2PS2G AVG TIME R/W
0b
Averaging time for Short-to-Power and Short-to-Ground
measurement
0: 0.2 ms
1: 0.7 ms
5-4
LDG SLOL AVG TIME
R/W
0b
Averaging time for shorted load and open load measurements:
00: Same averaging time as selected for Short-to-Power and
Short-to-Ground in bit 6 of this register
01: 10.7 ms
10: 21.3 ms
11: 42.7 ms
3
2
1
0
LDG LO ENABLE CH1
LDG LO ENABLE CH2
LDG LO ENABLE CH3
LDG LO ENABLE CH4
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0: Disable DC Load Diagnostics to check for line-out load on
CH1
1: Enable DC Load Diagnostics to check for line-out load on CH1
0: Disable DC Load Diagnostics to check for line-out load on
CH2
1: Enable DC Load Diagnostics to check for line-out load on CH2
0: Disable DC Load Diagnostics to check for line-out load on
CH3
1: Enable DC Load Diagnostics to check for line-out load on CH3
0: Disable DC Load Diagnostics to check for line-out load on
CH4
1: Enable DC Load Diagnostics to check for line-out load on CH4
Copyright © 2022 Texas Instruments Incorporated
54
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.7 DC LDG Ctrl 3 Register (Offset = 0x7) [reset = 0x00]
Return to the 表7-10.
图7-20. DC LDG Ctrl 3 Register
7
6
5
4
3
2
1
0
LDG RAMP 2
R/W-0b
LDG SETTLING 2
R/W-0b
LDG RAMP 1
R/W-0b
LDG SETTLING 1
R/W-0b
表7-17. DC LDG Ctrl 3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-4
3-2
1-0
LDG RAMP 2
R/W
0b
Ramp time, shorted load and open load diagnostics
00: 15 ms
01: 30 ms
10: 10 ms
11: 20 ms
LDG SETTLING 2
LDG RAMP 1
R/W
R/W
R/W
0b
0b
0b
Settling time, shorted load and open load diagnostics
00: 10 ms
01: 5 ms
10: 20 ms
11: 15 ms
Ramp time, short-to-power and short-to-ground diagnostics
00: 5 ms
01: 2.5 ms
10: 10 ms
11: 15 ms
LDG SETTLING 1
Settling time, short-to-power and short-to-ground diagnostics
00: 10ms
01: 5 ms
10: 20 ms
11: 30 ms
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.8 DC LDG Ctrl 4 Register (Offset = 0x8) [reset = 0x11]
Return to the 表7-10.
图7-21. DC LDG Ctrl 4 Register
7
6
5
4
3
2
1
0
CH1 DC LDG SL
R/W-1b
CH2 DC LDG SL
R/W-1b
表7-18. DC LDG Ctrl 4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH1 DC LDG SL
R/W
1b
Channel 1 DC load diagnostic shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
3-0
CH2 DC LDG SL
R/W
1b
Channel 2 DC load diagnostic shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
Copyright © 2022 Texas Instruments Incorporated
56
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.9 DC LDG Ctrl 5 Register (Offset = 0x9) [reset = 0x11]
Return to the 表7-10.
图7-22. DC LDG Ctrl 5 Register
7
6
5
4
3
2
1
0
CH3 DC LDG SL
R/W-1b
CH4 DC LDG SL
R/W-1b
表7-19. DC LDG Ctrl 5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH3 DC LDG SL
R/W
1b
Channel 3 DC load diagnostic shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
3-0
CH4 DC LDG SL
R/W
1b
Channel 4 DC load diagnostic shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.10 DC LDG Rprt CH12 Register (Offset = 0xA) [reset = 0x00]
Return to the 表7-10.
图7-23. DC LDG Rprt CH12 Register
7
6
5
4
3
2
1
0
CH1 S2G
R-0b
CH1 S2P
R-0b
CH1 OL
R-0b
CH1 SL
R-0b
CH2 S2G
R-0b
CH2 S2P
R-0b
CH2 OL
R-0b
CH2 SL
R-0b
表7-20. DC LDG Rprt CH12 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1 S2G
CH1 S2P
CH1 OL
CH1 SL
R
0b
0: No short-to-GND detected on channel 1
1: Short-to-GND detected on channel 1
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
0: No short-to-power detected on channel 1
1: Short-to-power detected on channel 1
0: No open load detected on channel 1
1: Open load detected on channel 1
0: No shorted load detected on channel 1
1: Shorted load detected on channel 1
CH2 S2G
CH2 S2P
CH2 OL
CH2 SL
0: No short-to-GND detected on channel 2
1: Short-to-GND detected on channel 2
0: No short-to-power detected on channel 2
1: Short-to-power detected on channel 2
0: No open load detected on channel 2
1: Open load detected on channel 2
0: No shorted load detected on channel 2
1: Shorted load detected on channel 2
Copyright © 2022 Texas Instruments Incorporated
58
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.11 DC LDG Rprt CH34 Register (Offset = 0xB) [reset = 0x00]
Return to the 表7-10.
图7-24. DC LDG Rprt CH34 Register
7
6
5
4
3
2
1
0
CH3 S2G
R-0b
CH3 S2P
R-0b
CH3 OL
R-0b
CH3 SL
R-0b
CH4 S2G
R-0b
CH4 S2P
R-0b
CH4 OL
R-0b
CH4 SL
R-0b
表7-21. DC LDG Rprt CH34 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH3 S2G
CH3 S2P
CH3 OL
CH3 SL
R
0b
0: No short-to-GND detected on channel 3
1: Short-to-GND detected on channel 3
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
0: No short-to-power detected on channel 3
1: Short-to-power detected on channel 3
0: No open load detected on channel 3
1: Open load detected on channel 3
0: No shorted load detected on channel 3
1: Shorted load detected on channel 3
CH4 S2G
CH4 S2P
CH4 OL
CH4 SL
0: No short-to-GND detected on channel 4
1: Short-to-GND detected on channel 4
0: No short-to-power detected on channel 4
1: Short-to-power detected on channel 4
0: No open load detected on channel 4
1: Open load detected on channel 4
0: No shorted load detected on channel 4
1: Shorted load detected on channel 4
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.12 DC LDG Rprt LO Register (Offset = 0xC) [reset = 0x00]
Return to the 表7-10.
图7-25. DC LDG Rprt LO Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH1 LO LDG
R-0b
CH2 LO LDG
R-0b
CH3 LO LDG
R-0b
CH4 LO LDG
R-0b
表7-22. DC LDG Rprt LO Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
CH1 LO LDG
R
0b
R
0b
0: No line output detected on channel 1
1: Line output detected on channel 1
2
1
0
CH2 LO LDG
CH3 LO LDG
CH4 LO LDG
R
R
R
0b
0b
0b
0: No line output detected on channel 2
1: Line output detected on channel 2
0: No line output detected on channel 3
1: Line output detected on channel 3
0: No line output detected on channel 4
1: Line output detected on channel 4
Copyright © 2022 Texas Instruments Incorporated
60
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.13 Channel State Rprt CH12 Register (Offset = 0xD) [reset = 0x24]
Return to the 表7-10.
图7-26. Channel State Rprt CH12 Register
7
6
5
4
3
2
1
0
CH1 STATE REPORT
CH2 STATE REPORT
CH1 LDG
STATE
CH2 LDG
STATE
REPORT
REPORT
R-1b
R-1b
R-0b
R-0b
表7-23. Channel State Rprt CH12 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
CH1 STATE REPORT
R
1b
Channel 1 is in state:
101: PSD (protective shutdown)
100: PSD_AR (protective shutdown, will auto recover)
011: DIAG
010: MUTE
001: HI-Z
000: PLAY
4-2
CH2 STATE REPORT
R
1b
Channel 2 is in state:
101: PSD (protective shutdown)
100: PSD_AR (protective shutdown, will auto recover)
011: DIAG
010: MUTE
001: HI-Z
000: PLAY
1
0
CH1 LDG STATE
REPORT
R
R
0b
0b
0: DC Load Diagnostic did not complete without faults on
channel 1
1: DC Load Diagnostic completed without faults on channel 1
CH2 LDG STATE
REPORT
0: DC Load Diagnostic did not complete without faults on
channel 2
1: DC Load Diagnostic completed without faults on channel 2
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.14 Channel State Rprt CH34 Register (Offset = 0xE) [reset = 0x24]
Return to the 表7-10.
图7-27. Channel State Rprt CH34 Register
7
6
5
4
3
2
1
0
CH3 STATE REPORT
CH4 STATE REPORT
CH3 LDG
STATE
CH4 LDG
STATE
REPORT
REPORT
R-1b
R-1b
R-0b
R-0b
表7-24. Channel State Rprt CH34 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
CH3 STATE REPORT
R
1b
Channel 3 is in state:
101: PSD (protective shutdown)
100: PSD_AR (protective shutdown, will auto recover)
011: DIAG
010: MUTE
001: HI-Z
000: PLAY
4-2
CH4 STATE REPORT
R
1b
Channel 4 is in state:
101: PSD (protective shutdown)
100: PSD_AR (protective shutdown, will auto recover)
011: DIAG
010: MUTE
001: HI-Z
000: PLAY
1
0
CH3 LDG STATE
REPORT
R
R
0b
0b
0: DC Load Diagnostic did not complete without faults on
channel 3
1: DC Load Diagnostic completed without faults on channel 3
CH4 LDG STATE
REPORT
0: DC Load Diagnostic did not complete without faults on
channel 4
1: DC Load Diagnostic completed without faults on channel 4
Copyright © 2022 Texas Instruments Incorporated
62
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.15 Ch OC DC Fault Mem Register (Offset = 0xF) [reset = 0x00]
Register clears to 0x0 upon reading.
For channel restart, DC and/or OC fault needs to be cleared by writing to register 0x30.
Return to the 表7-10.
图7-28. Ch OC DC Fault Mem Register
7
6
5
4
3
2
1
0
CH1 OC FAULT CH2 OC FAULT CH3 OC FAULT CH4 OC FAULT CH1 DC FAULT CH2 DC FAULT CH3 DC FAULT CH4 DC FAULT
STORED
STORED
STORED
STORED
STORED
STORED
STORED
STORED
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表7-25. Ch OC DC Fault Mem Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1 OC FAULT STORED
CH2 OC FAULT STORED
CH3 OC FAULT STORED
CH4 OC FAULT STORED
CH1 DC FAULT STORED
CH2 DC FAULT STORED
CH3 DC FAULT STORED
CH4 DC FAULT STORED
R
0b
0: No channel 1 over current fault event stored
1: Channel 1 over current fault event stored
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
0: No channel 2 over current fault event stored
1: Channel 2 over current fault event stored
0: No channel 3 over current fault event stored
1: Channel 3 over current fault event stored
0: No channel 4 over current fault event stored
1: Channel 4 over current fault event stored
0: No channel 1 DC fault event stored
1: Channel 1 DC fault event stored
0: No channel 2 DC fault event stored
1: Channel 2 DC fault event stored
0: No channel 3 DC fault event stored
1: Channel 3 DC fault event stored
0: No channel 4 DC fault event stored
1: Channel 4 DC fault event stored
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.16 Power_Fault_Mem Register (Offset = 0x10) [reset = 0x00]
Register clears to 0x0 upon reading.
Return to the 表7-10.
图7-29. Power_Fault_Mem Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
GVDD FAULT
STORED
DVDD POR
STORED
PVDD OV
STORED
VBAT OV
STORED
PVDD UV
STORED
VBAT UV
STORED
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表7-26. Power_Fault_Mem Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0b
GVDD FAULT STORED
R
0b
0: No GVDD regulator fault event stored
1: GVDD regulator fault event stored
4
3
2
1
0
DVDD POR STORED
PVDD OV STORED
VBAT OV STORED
PVDD UV STORED
VBAT UV STORED
R
R
R
R
R
0b
0b
0b
0b
0b
0: No DVDD power on reset event stored
1: DVDD power on reset event stored
0: No PVDD over voltage event stored
1: PVDD over voltage event stored
0: No VBAT over voltage event stored
1: VBAT over voltage event stored
0: No PVDD under voltage event stored
1: PVDD under voltage event detected and stored
0: No VBAT under voltage event stored
1: VBAT under voltage event stored
Copyright © 2022 Texas Instruments Incorporated
64
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.17 Power Fault Status Register (Offset = 0x11) [reset = 0x00]
Return to the 表7-10.
图7-30. Power Fault Status Register
7
6
5
4
3
2
1
0
GLOBAL
WARNING
GLOBAL
FAULT
GVDD FAULT
RESERVED
PVDD OV
VBAT OV
PVDD UV
VBAT UV
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表7-27. Power Fault Status Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GLOBAL WARNING
R
0b
0: No warning
1: If any warning active in device, regardless of warning signal
configuration
6
5
GLOBAL FAULT
GVDD FAULT
R
R
0b
0b
0: No fault
1: If any fault active in device, regardless of fault signal configuration
0: No GVDD regulator fault detected
1: GVDD regulator fault detected
4
3
RESERVED
PVDD OV
R
R
0b
0b
0: PVDD supply voltage is not above OV threshold
1: PVDD supply voltage is above OV threshold
2
1
0
VBAT OV
PVDD UV
VBAT UV
R
R
R
0b
0b
0b
0: VBAT supply voltage is not above OV threshold
1: VBAT supply voltage is above OV threshold
0: PVDD supply voltage is not below UV threshold
1:PVDD supply voltage is below UV threshold
0: VBAT supply voltage is not below UV threshold
1: VBAT supply voltage is below UV threshold
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.18 OTSD CS Fault Mem Register (Offset = 0x12) [reset = 0x00]
Return to the 表7-10.
图7-31. OTSD CS Fault Mem Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
INVALID
CLOCK
STORED
OTSD STORED
CH1 OTSD
STORED
CH2 OTSD
STORED
CH3 OTSD
STORED
CH4 OTSD
STORED
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表7-28. OTSD CS Fault Mem Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0b
INVALID CLOCK
STORED
R
0b
Only applies if device is configured in clock slave mode:
0: No clock synchronization fault event stored
1:Clock synchronization fault event stored
4
3
2
1
0
OTSD STORED
R
R
R
R
R
0b
0b
0b
0b
0b
0: No global over temperature shutdown event stored
1:Global over temperature shutdown event stored
CH1 OTSD STORED
CH2 OTSD STORED
CH3 OTSD STORED
CH4 OTSD STORED
0: No channel 1 over temperature shutdown event stored
1: Channel 1 over temperature shutdown event stored
0: No channel 2 over temperature shutdown event stored
1: Channel 2 over temperature shutdown event stored
0: No channel 3 over temperature shutdown event stored
1: Channel 3 over temperature shutdown event stored
0: No channel 4 over temperature shutdown event stored
1: Channel 4 over temperature shutdown event stored
Copyright © 2022 Texas Instruments Incorporated
66
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.19 OTSD CS Fault Status Register (Offset = 0x13) [reset = 0x00]
Return to the 表7-10.
图7-32. OTSD CS Fault Status Register
7
6
5
4
3
2
1
0
WARNING
SIGNAL
FAULT SIGNAL
INVALID
CLOCK
OTSD
CH1 OTSD
CH2 OTSD
CH3 OTSD
CH4 OTSD
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表7-29. OTSD CS Fault Status Register Field Descriptions
Bit
Field
Type
Reset
Description
7
WARNING SIGNAL
R
0b
0: If internal warning signal is not active
1: If internal warning signal is active (configured by warning signal
configuration registers)
6
5
FAULT SIGNAL
INVALID CLOCK
R
R
0b
0b
0: If internal fault signal is not active
1: If internal fault signal is active (configured by fault signal
configuration registers)
Only applies if device is configured in clock slave mode:
0: No Synchronization clock error detected
1: Synchronization clock error detected
4
3
2
1
0
OTSD
R
R
R
R
R
0b
0b
0b
0b
0b
0: Global die temperature is not above OTSD threshold
1: Global die temperature is above OTSD threshold
CH1 OTSD
CH2 OTSD
CH3 OTSD
CH4 OTSD
0: Channel 1 temperature is not above OTSD threshold
1: Channel 1 temperature is above OTSD threshold
0: Channel 2 temperature is not above OTSD threshold
1: Channel 2 temperature is above OTSD threshold
0: Channel 3 temperature is not above OTSD threshold
1: Channel 3 temperature is above OTSD threshold
0: Channel 4 temperature is not above OTSD threshold
1: Channel 4 temperature is above OTSD threshold
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
67
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.20 Ch Current Fault Mem Register (Offset = 0x14) [reset = 0x00]
Register clears to 0x0 upon reading.
To restart the channel, the load current faults need to be cleared by writing to Register 0x30.
Return to the 表7-10.
图7-33. Ch Current Fault Mem Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH1 I-LIMIT
FAULT
STORED
CH2 I-LIMIT
FAULT
STORED
CH3 I-LIMIT
FAULT
STORED
CH4 I-LIMIT
FAULT
STORED
R-0b
R-0b
R-0b
R-0b
表7-30. Ch Current Fault Mem Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
R
0b
CH1 I-LIMIT FAULT
STORED
R
0b
0: No channel 1 load current fault event stored
1: Channel 1 load current fault event stored
2
1
0
CH2 I-LIMIT FAULT
STORED
R
R
R
0b
0b
0b
0: No channel 2 load current fault event stored
1: Channel 2 load current fault event stored
CH3 I-LIMIT FAULT
STORED
0: No Channel 3 load current fault event stored
1: Channel 3 load current fault event stored
CH4 I-LIMIT FAULT
STORED
0: No channel 4 load current fault event stored
1: Channel 4 load current fault event stored
Copyright © 2022 Texas Instruments Incorporated
68
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.21 Ch Current Warn Mem Register (Offset = 0x15) [reset = 0x00]
Register clears to 0x0 upon reading.
Return to the 表7-10.
图7-34. Ch Current Warn Mem Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH1 I-LIMIT
WARN
STORED
CH2 I-LIMIT
WARN
STORED
CH3 I-LIMIT
WARN
STORED
CH4 I-LIMIT
WARN
STORED
R-0b
R-0b
R-0b
R-0b
表7-31. Ch Current Warn Mem Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
R
0b
CH1 I-LIMIT WARN
STORED
R
0b
0: No channel 1 load current warning event stored
1: Channel 1 load current warning event stored
2
1
0
CH2 I-LIMIT WARN
STORED
R
R
R
0b
0b
0b
0: No channel 2 load current warning event stored
1: Channel 2 load current warning event stored
CH3 I-LIMIT WARN
STORED
0: No channel 3 load current warning event stored
1: Channel 3 load current warning event stored
CH4 I-LIMIT WARN
STORED
0: No channel 4 load current warning event stored
1: Channel 4 load current warning event stored
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
69
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.22 OTW TGFB Warn Mem Register (Offset = 0x16) [reset = 0x00]
Register clears to 0x0 upon reading.
Return to the 表7-10.
图7-35. OTW TGFB Warn Mem Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
TGFBW
STORED
OTW STORED
CH1 OTW
STORED
CH2 OTW
STORED
CH3 OTW
STORED
CH4 OTW
STORED
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表7-32. OTW TGFB Warn Mem Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0b
TGFBW STORED
R
0b
0: No thermal gain fold back activation event stored
1: Thermal gain fold back activation event stored
4
3
2
1
0
OTW STORED
R
R
R
R
R
0b
0b
0b
0b
0b
0: No global over temperature warning event stored
1:Global over temperature warning event stored
CH1 OTW STORED
CH2 OTW STORED
CH3 OTW STORED
CH4 OTW STORED
0: No channel 1 over temperature warning event stored
1: Channel 1 over temperature warning event stored
0: No channel 2 over temperature warning event stored
1: Channel 2 over temperature warning event stored
0: No channel 3 over temperature warning event stored
1: Channel 3 over temperature warning event stored
0: No channel 4 over temperature warning event stored
1: Channel 4 over temperature warning event stored
Copyright © 2022 Texas Instruments Incorporated
70
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.23 OTW TGFB Warn Status Register (Offset = 0x17) [reset = 0x00]
Return to the 表7-10.
图7-36. OTW TGFB Warn Status Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
TGFBW
R-0b
OTW
R-0b
CH1 OTW
R-0b
CH2 OTW
R-0b
CH3 OTW
R-0b
CH4 OTW
R-0b
表7-33. OTW TGFB Warn Status Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
TGFBW
R
0b
R
0b
0: Thermal gain fold back is not activated
1: Thermal gain fold back is activated
4
3
2
1
0
OTW
R
R
R
R
R
0b
0b
0b
0b
0b
0: Global die temperature is not above OTW threshold
1: Global die temperature is above OTW threshold
CH1 OTW
CH2 OTW
CH3 OTW
CH4 OTW
0: Channel 1 temperature is not above OTW threshold
1: Channel 1 temperature is above OTW threshold
0: Channel 2 temperature is not above OTW threshold
1: Channel 2 temperature is above OTW threshold
0: Channel 3 temperature is not above OTW threshold
1: Channel 3 temperature is above OTW threshold
0: Channel 4 temperature is not above OTW threshold
1: Channel 4 temperature is above OTW threshold
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
71
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.24 Ch ClipDet Warn Mem Register (Offset = 0x18) [reset = 0x00]
Register clears to 0x0 upon reading.
Return to the 表7-10.
图7-37. Ch ClipDet Warn Mem Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH1 CLIP
STORED
CH2 CLIP
STORED
CH3 CLIP
STORED
CH4 CLIP
STORED
R-0b
R-0b
R-0b
R-0b
表7-34. Ch ClipDet Warn Mem Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
R
0b
CH1 CLIP STORED
R
0b
0: No channel 1 clipping event stored
1: Channel 1 clipping event stored
2
1
0
CH2 CLIP STORED
CH3 CLIP STORED
CH4 CLIP STORED
R
R
R
0b
0b
0b
0: No channel 2 clipping event stored
1: Channel 2 clipping event stored
0: No channel 3 clipping event stored
1: Channel 3 clipping event stored
0: No channel 4 clipping event stored
1: Channel 4 clipping event stored
Copyright © 2022 Texas Instruments Incorporated
72
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.25 Ch ClipDet Warn Status Register (Offset = 0x19) [reset = 0x00]
Return to the 表7-10.
图7-38. Ch ClipDet Warn Status Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH1 CLIP
R-0b
CH2 CLIP
R-0b
CH3 CLIP
R-0b
CH4 CLIP
R-0b
表7-35. Ch ClipDet Warn Status Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
CH1 CLIP
R
0b
R
0b
0: Channel 1 clipping is not present or not above clip detect
threshold
1: Channel 1 clipping is above clip detect threshold
2
1
0
CH2 CLIP
CH3 CLIP
CH4 CLIP
R
R
R
0b
0b
0b
0: Channel 2 clipping is not present or not above clip detect
threshold
1: Channel 2 clipping is above clip detect threshold
0: Channel 3 clipping is not present or not above clip detect
threshold
1: Channel 3 clipping is above clip detect threshold
0: Channel 4 clipping is not present or not above clip detect
threshold
1: Channel 4 clipping is above clip detect threshold
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
73
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.26 TGFB Status Register (Offset = 0x1C) [reset = 0x00]
Return to the 表7-10.
图7-39. TGFB Status Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
TGFB GAIN
R-0b
表7-36. TGFB Status Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4-0
RESERVED
TGFB GAIN
R
0b
R
0b
Gain set by thermal gain foldback control in response to die
temperature is:
00000: 0 dB
00001: -0.5 dB
00010: -1 dB
….
10111: - 11.5 dB
11000: - 12 dB
Copyright © 2022 Texas Instruments Incorporated
74
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.27 Fault Sig Conf 1 Register (Offset = 0x1D) [reset = 0x17]
Return to the 表7-10.
图7-40. Fault Sig Conf 1 Register
7
6
5
4
3
2
1
0
RESERVED
FAULT ON
PROTECTIVE
SHUTDOWN
FAULT ON
INVALID
CLOCK
FAULT ON
OTSD STORED POWER FAULT
STORED
FAULT ON
FAULT ON DC FAULT ON OC
FAULT ON
ILIMIT
STORED
STORED
R/W-1b
STORED
STORED
R/W-0b
R/W-0b
R/W-0b
R/W-1b
R/W-0b
R/W-1b
R/W-1b
表7-37. Fault Sig Conf 1 Register Field Descriptions
Bit
7
Field
RESERVED
Type
Reset
Description
R/W
0b
6
FAULT ON PROTECTIVE R/W
SHUTDOWN
0b
0: Fault signal is not activated by any CH[1..4] STATE REPORT =
'101'
1: If any CH[1..4] STATE REPORT = '101', fault signal is active
5
4
FAULT ON INVALID
CLOCK STORED
R/W
R/W
0b
1b
0: Fault signal is not activated by INVALID CLOCK STORED bit
1: If INVALID CLOCK STORED bit is set, fault signal is active
FAULT ON OTSD
STORED
0: Fault signal is not activated by any CH[1..4] OTSD STORED bit or
OTSD STORED bit
1: If any CH[1..4] OTSD STORED bit or OTSD STORED bit is set,
fault signal is active
3
FAULT ON POWER
FAULT STORED
R/W
R/W
0b
0: Fault Signal is not activated by any stored bit in "Power Fault
Memory Register"
1: If VBAT UV STORED bit, VBAT OV STORED bit, PVDD UV
STORED bit, PVDD OV STORED bit, DVDD POR STORED bit, or
GVDD FAULT STORED bit is set, fault signal is active.
2
1
0
FAULT ON DC STORED
1b
1b
1b
0: Fault signal is not activated by any CH[1..4] DC FAULT STORED
bit
1: If any CH[1..4] DC FAULT STORED bit is set, fault signal is
active
FAULT ON OC STORED R/W
0: Fault signal is not activated by any CH[1..4] OC FAULT STORED
bit
1: If any CH[1..4] OC FAULT STORED bit is set, fault signal is
active
FAULT ON ILIMIT
STORED
R/W
0: Fault signal is not activated by any CH[1..4] I-LIMIT FAULT
STORED bit
1: If any CH[1..4] I-LIMIT FAULT STORED bit is set, fault signal is
active
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
75
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.28 Fault Sig Conf 2 Register (Offset = 0x1E) [reset = 0x00]
Return to the 表7-10.
图7-41. Fault Sig Conf 2 Register
7
6
5
4
3
2
1
0
RESERVED
FAULT ON
WARN
FAULT ON
INVALID
CLOCK
FAULT ON
OTSD
FAULT ON
POWER FAULT
RESERVED
RESERVED
FAULT ON
INCOMPLETE
LDG
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表7-38. Fault Sig Conf 2 Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
Description
0b
6
FAULT ON WARN
0b
0: Fault signal is not activated when warning singal is active.
1: Fault signal is active when warning signal is active
5
4
FAULT ON INVALID
CLOCK
R/W
R/W
0b
0b
0: Fault signal is not activated by INVALID CLOCK bit
1: If INVALID CLOCK bit is set, fault signal is active
FAULT ON OTSD
0: Fault signal is not activated by any CH[1..4] OTSD bit or
OTSD
1: If any CH[1..4] OTSD bit or OTSD bit is set, fault signal is active
3
FAULT ON POWER
FAULT
R/W
0b
0: Fault Signal is not activated by any stored bit in "Power Fault
Status Register"
1: If VBAT UV bit, VBAT OV bit, PVDD UV bit, PVDD OV bit, or
GVDD FAULT bit is set, fault signal is active.
2
1
0
RESERVED
RESERVED
R/W
R/W
0b
0b
0b
FAULT ON INCOMPLETE R/W
LDG
0: Fault signal is not activated by any CH[1..4] LDG STATE
REPORT bit
1: If any CH[1..4] LDG STATE REPORT bit is not set, fault signal Is
active
Copyright © 2022 Texas Instruments Incorporated
76
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.29 Warn Sig Conf 1 Register (Offset = 0x1F) [reset = 0x04]
Return to the 表7-10.
图7-42. Warn Sig Conf 1 Register
7
6
5
4
3
2
1
0
RESERVED
WARN ON
CLIP DET
STORED
WARN ON
INVALID
CLOCK
WARN ON
WARN ON
WARN ON
WARN ON
WARN ON
ILIMIT
STORED
OTSD STORED POWER FAULT OTW STORED TGFB STORED
STORED
STORED
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-1b
R/W-0b
R/W-0b
表7-39. Warn Sig Conf 1 Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
Description
0b
6
WARN ON CLIP DET
STORED
0b
0: Warning signal is not activated by any CH[1..4] CLIP STORED
bit
1: If any CH[1..4] CLIP STORED bit is set, warning signal is active
5
4
WARN ON INVALID
CLOCK STORED
R/W
R/W
0b
0b
0: Warning signal is not activated by INVALID CLOCK STORED
bit
1: If INVALID CLOCK STORED bit is set, warning signal is active
WARN ON OTSD
STORED
0: Warning signal is not activated by any CH[1..4] OTSD
STORED bit or OTSD STORED
1: If any CH[1..4] OTSD STORED bit or OTSD STORED bit is set,
warning signal is active
3
2
WARN ON POWER
FAULT STORED
R/W
0b
1b
0: Warning Signal is not activated by any stored bit in "Power
Fault Memory Register"
1: If VBAT UV STORED bit, VBAT OV STORED bit, PVDD UV
STORED bit, PVDD OV STORED bit, DVDD POR STORED bit, or
GVDD FAULT STORED bit is set, warning signal is active.
WARN ON OTW STORED R/W
0: Warning signal is not activated by any CH[1..4] OTW STORED bit
or OTW STORED bit
1: If any CH[1..4] OTW STORED bit or OTW STORED bit is set,
warning signal is active
1
0
WARN ON TGFB
STORED
R/W
R/W
0b
0b
0: Warning signal is not activated by TGFBW STORED
1: Warning signal is active if TGFBW STORED is active
WARN ON ILIMIT
STORED
0: Warning signal is not activated by any CH[1..4] I-LIMIT WARN
STORED bit
1: If any CH[1..4] I-LIMIT WARN STORED bit is set, warning signal is
active
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
77
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.30 Warn Sig Conf 2 Register (Offset = 0x20) [reset = 0x00]
Return to the 表7-10.
图7-43. Warn Sig Conf 2 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0b
WARN ON
INVALID
CLOCK
WARN ON
OTSD
WARN ON
POWER FAULT
WARN ON
OTW
WARN ON
TGFB
WARN ON
INCOMPLETE
LDG
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表7-40. Warn Sig Conf 2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5
RESERVED
0b
WARN ON INVALID
CLOCK
0b
0: Warning signal is not activated by INVALID CLOCK bit
1: If INVALID CLOCK bit is set, warning signal is active
4
3
2
WARN ON OTSD
R/W
R/W
R/W
R/W
0b
0b
0b
0: Warning signal is not activated by any CH[1..4] OTSD bit or
OTSD
1: If any CH[1..4] OTSD bit or OTSD bit is set, warning signal is
active
WARN ON POWER
FAULT
0: Warning Signal is not activated by any stored bit in "Power
Fault Status Register"
1: If VBAT UV bit, VBAT OV bit, PVDD UV bit, PVDD OV bit, or
GVDD FAULT bit is set, warning signal is active.
WARN ON OTW
0: Warning signal is not activated by any CH[1..4] OTW bit or
OTW bit
1: If any CH[1..4] OTW STORED bit or OTW STORED bit is set,
warning signal is active
1
0
WARN ON TGFB
0b
0b
0: Warning signal is not activated by TGFBW
1: Warning signal is active if TGFBW is active
WARN ON INCOMPLETE R/W
LDG
0: Warning signal is not activated by any CH[1..4] LDG STATE
REPORT bit
1: If any CH[1..4] LDG STATE REPORT bit is not set, warning signal
is active
Copyright © 2022 Texas Instruments Incorporated
78
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.31 Clip Det Sig Conf Register (Offset = 0x21) [reset = 0x00]
Return to the 表7-10.
图7-44. Clip Det Sig Conf Register
7
6
5
4
3
2
1
0
RESERVED
CLIP DET EN
CLIP DET LVL
R/W-0b
CLIP DET
CH34 GRP2
CLIP DET
CH34 GRP1
CLIP DET
CH12 GRP2
CLIP DET
CH12 GRP1
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表7-41. Clip Det Sig Conf Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
Description
0b
6
CLIP DET EN
0b
0: Clip detect is disabled
1: Clip detect is enabled
5-4
3
CLIP DET LVL
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
00: 2% THD
01: 5% THD
10: 10% THD
11: 1% THD
CLIP DET CH34 GRP2
CLIP DET CH34 GRP1
CLIP DET CH12 GRP2
CLIP DET CH12 GRP1
0: Clip Detect Signal Group 2 is not activated by CH3 CLIP or
CH4 CLIP
1: Clip Detect Signal Group 2 is active when CH3 CLIP or CH4 CLIP
is active
2
0: Clip Detect Signal Group 1 is not activated by CH3 CLIP or
CH4 CLIP
1: Clip Detect Signal Group 1 is active when CH3 CLIP or CH4 CLIP
is active
1
0: Clip Detect Signal Group 2 is not activated by CH1 CLIP or
CH2 CLIP
1: Clip Detect Signal Group 2 is active when CH1 CLIP or CH2 CLIP
is active
0
0: Clip Detect Signal Group 1 is not activated by CH1 CLIP or
CH2 CLIP
1: Clip Detect Signal Group 1 is active when CH1 CLIP or CH2 CLIP
is active
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
79
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.32 Fault Pin Conf Register (Offset = 0x22) [reset = 0x00]
Return to the 表7-10.
图7-45. Fault Pin Conf Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0b
FAULT PIN CONF
R/W-0b
表7-42. Fault Pin Conf Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-4
3-0
RESERVED
0b
FAULT PIN CONF
0b
Fault Pin is set to:
0000: FaultZ
Open Drain Output. Active low when fault signal is active.
0001: WarningZ - Open Drain Output. Active low when warning
signal is active.
0010: Clip Detect 1 - Buffer Output. Active high when clip detect
group 1 signal is active.
0011: Clip Detect 2 - Buffer Output. Active high when clip detect
group 2 signal is active.
Copyright © 2022 Texas Instruments Incorporated
80
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.33 GPIO Conf Register (Offset = 0x23) [reset = 0x00]
Return to the 表7-10.
图7-46. GPIO Conf Register
7
6
5
4
3
2
1
0
GPIO2 PIN CONF
R/W-0b
GPIO1 PIN CONF
R/W-0b
表7-43. GPIO Conf Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
GPIO2 PIN CONF
R/W
0b
GPIO 2 pin set to:
0000: Hi-Z
0001: WarningZ Pin - Open Drain Output. Active low when warning
signal is active.
0010: FaultZ Pin - Open Drain Output. Active low when fault signal is
active.
0011: Clip Detect 1 - Buffer Output. Active high when clip detect
group 1 signal is active.
0100: Clip Detect 2 - Buffer Output. Active high when clip detect
group 2 signal is active.
0101: Sync out - Buffer Output. Sends output stage switching
frequency
0110: DVDD (high)
0111: GND (low)
1000: Sync in - Input. Accepts switching frequency of clock master
device
1001: MuteZ - Input. Low level input will mute the device
3-0
GPIO1 PIN CONF
R/W
0b
GPIO 1 pin set to:
0000: Hi-Z
0001: WarningZ - Open Drain Output. Active low when warning
signal is active.
0010: FaultZ - Open Drain Output. Active low when fault signal is
active.
0011: Clip Detect 1 - Buffer Output. Active high when clip detect
group 1 signal is active.
0100: Clip Detect 2 - Buffer Output. Active high when clip detect
group 2 signal is active.
0101: Sync out - Buffer Output. Sends output stage switching
frequency
0110: DVDD (high)
0111: GND (low)
1000: Sync in - Input. Accepts switching frequency of clock master
device
1001: MuteZ - Input. Low level input will mute the device
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
81
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.34 AC LDG Ctrl 1 Register (Offset = 0x24) [reset = 0x00]
Return to the 表7-10.
图7-47. AC LDG Ctrl 1 Register
7
6
5
4
3
2
1
0
RESERVED
AC DIAG GAIN CH1 AC DIAG CH2 AC DIAG CH3 AC DIAG CH4 AC DIAG
START
START
START
START
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表7-44. AC LDG Ctrl 1 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-5
4
RESERVED
0b
AC DIAG GAIN
0b
0: Gain 1 (0-100 Ω)
1: Gain 8 (0-12.5 Ω)
3
2
1
0
CH1 AC DIAG START
CH2 AC DIAG START
CH3 AC DIAG START
CH4 AC DIAG START
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0: Normal operation
1: Start AC diagnostic on channel 1 once channel is in Hi-Z mode
0: Normal operation
1: Start AC diagnostic on channel 2 once channel is in Hi-Z mode
0: Normal operation
1: Start AC diagnostic on channel 3 once channel is in Hi-Z mode
0: Normal operation
1: Start AC diagnostic on channel 4 once channel is in Hi-Z mode
Copyright © 2022 Texas Instruments Incorporated
82
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.35 AC LDG Ctrl 2 Register (Offset = 0x25) [reset = 0x8]
Return to the 表7-10.
图7-48. AC LDG Ctrl 2 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0b
TW DET AVG
R/W-1b
RESERVED
TW DET CALC
TYPE
TW DET
JUDGE
R/W-0b
R/W-0b
R/W-0b
表7-45. AC LDG Ctrl 2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-4
3
RESERVED
0b
TW DET AVG
1b
0: Fast mode
1: Normal mode
2
1
RESERVED
R/W
R/W
0b
0b
TW DET CALC TYPE
0: AC pass/fail judgement type 2
Calculate magnitude of impedance as Re(Z)+0.5*Im(Z)
1: AC pass/fail judgement type 1
Calculate magnitude of impedance as Re(Z)
0
TW DET JUDGE
R/W
0b
0: Enable Tweeter detection judegement
Calculate magnitude of impedance
Check whether calculated result is lower than tweeter detection
threshold value
If yes, set tweeter detection bit
1: Disable Tweeter detection calculation
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
83
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.36 TWEETER DET THRESH Register (Offset = 0x26) [reset = 0x00]
Return to the 表7-10.
图7-49. TWEETER DET THRESH Register
7
6
5
4
3
2
1
0
TW DET THRESHOLD
R/W-0b
表7-46. TWEETER DET THRESH Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
TW DET THRESHOLD
R/W
0b
Set the reference value for AC load diag pass/fail judgement.
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See 节7.6.1.35
Copyright © 2022 Texas Instruments Incorporated
84
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.37 AC LDG Rprt CH1 R Register (Offset = 0x27) [reset = 0x00]
Return to the 表7-10.
图7-50. AC LDG Rprt CH1 R Register
7
6
5
4
3
2
1
0
CH1 AC IMP R
R-0b
表7-47. AC LDG Rprt CH1 R Register Field Descriptions
Bit
7-0
Field
CH1 AC IMP R
Type
Reset
Description
R
0b
Register value corresponds to the real part of complex impedance
seen at CH1 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See 节7.6.1.35
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
85
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.38 AC LDG Rprt CH1 I Register (Offset = 0x28) [reset = 0x00]
Return to the 表7-10.
图7-51. AC LDG Rprt CH1 I Register
7
6
5
4
3
2
1
0
CH1 AC IMP I
R-0b
表7-48. AC LDG Rprt CH1 I Register Field Descriptions
Bit
7-0
Field
CH1 AC IMP I
Type
Reset
Description
R
0b
Register value corresponds to the complement of the imaginary part
of complex impedance seen at CH1 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See 节7.6.1.35
Copyright © 2022 Texas Instruments Incorporated
86
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.39 AC LDG Rprt CH2 R Register (Offset = 0x29) [reset = 0x00]
Return to the 表7-10.
图7-52. AC LDG Rprt CH2 R Register
7
6
5
4
3
2
1
0
CH2 AC IMP R
R-0b
表7-49. AC LDG Rprt CH2 R Register Field Descriptions
Bit
7-0
Field
CH2 AC IMP R
Type
Reset
Description
R
0b
Register value corresponds to the real part of complex impedance
seen at CH2 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See 节7.6.1.35
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
87
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.40 AC LDG Rprt CH2 I Register (Offset = 0x2A) [reset = 0x00]
Return to the 表7-10.
图7-53. AC LDG Rprt CH2 I Register
7
6
5
4
3
2
1
0
CH2 AC IMP I
R-0b
表7-50. AC LDG Rprt CH2 I Register Field Descriptions
Bit
7-0
Field
CH2 AC IMP I
Type
Reset
Description
R
0b
Register value corresponds to the complement of the imaginary part
of complex impedance seen at CH2 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See 节7.6.1.35
Copyright © 2022 Texas Instruments Incorporated
88
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.41 AC LDG Rprt CH3 R Register (Offset = 0x2B) [reset = 0x00]
Return to the 表7-10.
图7-54. AC LDG Rprt CH3 R Register
7
6
5
4
3
2
1
0
CH3 AC IMP R
R-0b
表7-51. AC LDG Rprt CH3 R Register Field Descriptions
Bit
7-0
Field
CH3 AC IMP R
Type
Reset
Description
R
0b
Register value corresponds to the real part of complex impedance
seen at CH3 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See 节7.6.1.35
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
89
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.42 AC LDG Rprt CH3 I Register (Offset = 0x2C) [reset = 0x00]
Return to the 表7-10.
图7-55. AC LDG Rprt CH3 I Register
7
6
5
4
3
2
1
0
CH3 AC IMP I
R-0b
表7-52. AC LDG Rprt CH3 I Register Field Descriptions
Bit
7-0
Field
CH3 AC IMP I
Type
Reset
Description
R
0b
Register value corresponds to the complement of the imaginary part
of complex impedance seen at CH3 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See 节7.6.1.35
Copyright © 2022 Texas Instruments Incorporated
90
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.43 AC LDG Rprt CH4 R Register (Offset = 0x2D) [reset = 0x00]
Return to the 表7-10.
图7-56. AC LDG Rprt CH4 R Register
7
6
5
4
3
2
1
0
CH4 AC IMP R
R-0b
表7-53. AC LDG Rprt CH4 R Register Field Descriptions
Bit
7-0
Field
CH4 AC IMP R
Type
Reset
Description
R
0b
Register value corresponds to the real part of complex impedance
seen at CH4 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See 节7.6.1.35
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
91
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.44 AC LDG Rprt CH4 I Register (Offset = 0x2E) [reset = 0x00]
Return to the 表7-10.
图7-57. AC LDG Rprt CH4 I Register
7
6
5
4
3
2
1
0
CH4 AC IMP I
R-0b
表7-54. AC LDG Rprt CH4 I Register Field Descriptions
Bit
7-0
Field
CH4 AC IMP I
Type
Reset
Description
R
0b
Register value corresponds to the complement of the imaginary part
of complex impedance seen at CH4 output
0.8 Ω/code if AC DIAG GAIN = 0
0.1 Ω/code if AC DIAG GAIN = 1
See 节7.6.1.35
Copyright © 2022 Texas Instruments Incorporated
92
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.45 TWEETER DET Register (Offset = 0x2F) [reset = 0x00]
Return to the 表7-10.
图7-58. TWEETER DET Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH1 TW DET
R-0b
CH2 TW DET
R-0b
CH3 TW DET
R-0b
CH4 TWDET
R-0b
表7-55. TWEETER DET Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3
RESERVED
R
0b
CH1 TW DET
R
0b
0: No tweeter detected on channel 1.
1: Tweeter detected on channel 1.
2
1
0
CH2 TW DET
CH3 TW DET
CH4 TW DET
R
R
R
0b
0b
0b
0: No tweeter detected on channel 2.
1: Tweeter detected on channel 2.
0: No tweeter detected on channel 3.
1: Tweeter detected on channel 3.
0: No tweeter detected on channel 4.
1: Tweeter detected on channel 4.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
93
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.46 Misc Control 3 Register (Offset = 0x30) [reset = 0x00]
Return to the 表7-10.
图7-59. Misc Control 3 Register
7
6
5
4
3
2
1
0
CLEAR FAULT
RESERVED
PRECHG TIME
R/W-0b
OTSD AUTO
RECOVERY
RESERVED
PULL UP
RESERVED
W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表7-56. Misc Control 3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CLEAR FAULT
W
0b
0: Normal operation
1: Clear fault
6
RESERVED
R/W
R/W
0b
0b
5-4
PRECHG TIME
Precharge wait time sets the time for AC coupling input caps to settle
during startup
0: 20 ms
1: 15 ms
2: 40 ms
3: 50 ms
3
OTSD AUTO RECOVERY R/W
0b
0: Device will not auto recover from over temperature shutdown
1: Device will auto recover from over temperature shutdown
2
1
RESERVED
PULL UP
R/W
R/W
0b
0b
Control internal pull-up for GPIO1 and GPIO2 if configured to Open
Drain Output
0: Enable internal pull-up
1: Disable internal pull-up
0
RESERVED
R/W
0b
Copyright © 2022 Texas Instruments Incorporated
94
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.47 REVID Register (Offset = 0x32) [reset = 0x00]
Return to the 表7-10.
图7-60. REVID Register
7
6
5
4
3
2
1
0
REV ID
R-0b
表7-57. REVID Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
REV ID
R
Revision ID
0x21
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
95
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.48 TGFB Ctrl Register (Offset = 0x33) [reset = 0x00]
Return to the 表7-10.
图7-61. TGFB Ctrl Register
7
6
5
4
3
2
1
0
ZC WAIT TIME
R/W-0b
BYPASS
R/W-0b
ZC BYPASS
R/W-0b
ATTACK
R/W-0b
RELEASE
R/W-0b
表7-58. TGFB Ctrl Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
ZC WAIT TIME
R/W
0b
System waits this period for zero crossing, then changes gain
regardless.
00: 20 µs
01: 80 µs
10: 320 µs
11: 1280 µs
5
4
BYPASS
R/W
R/W
0b
0b
0: Enable Thermal Gain Foldback
1: Disable Thermal Gain Foldback
ZC BYPASS
0: Enable zero crossing detection
1: Disable zero crossing detection. Gain changes as soon as thermal
condition is met without waiting for zero detection.
3-2
1-0
ATTACK
R/W
R/W
0b
0b
00: 1 dB / 100ms
01: 1 dB / 200ms
10: 1 dB / 400ms
11: 1 dB / 800ms
RELEASE
00: 1 dB / 200ms
01: 1 dB / 400ms
10: 1 dB / 800ms
11: 1 dB / 1600ms
Copyright © 2022 Texas Instruments Incorporated
96
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.49 AC LDG FREQ Ctrl Register (Offset = 0x34) [reset = 0xC8]
Return to the 表7-10.
图7-62. AC LDG FREQ Ctrl Register
7
6
5
4
3
2
1
0
STIMULUS FREQUENCY (93.75 Hz/bit)
R/W-11001000b
表7-59. AC LDG FREQ Ctrl Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
STIMULUS FREQUENCY R/W
(93.75 Hz/bit)
11001000b 0000 0000: Default. 18.75kHz
0000 0001: 93.75 Hz
0000 0010: 187.5 Hz
….
1100 1000: 18.75 kHz
….
1111 1111: 23.90625 kHz
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
97
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.50 SYNC Ctrl Register (Offset = 0x35) [reset = 0x1]
Return to the 表7-10.
图7-63. SYNC Ctrl Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0b
SYNC ERROR WD
R/W-0b
SYNC ERROR
DET BYPASS
MASTER
SLAVE
R/W-0b
R/W-1b
表7-60. SYNC Ctrl Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-4
3-2
RESERVED
0b
SYNC ERROR WD
0b
SYNC Clock Error watchdog timer.
For PWM frequency of 2.1MHz or 2.3MHz, timer set to
00: 2.5µs
01: 5µs
10: 7.5µs
11: 10µs
For PWM frequency of 384kHz, 460kHz or 576kHz, timer set to
00: 5µs
01: 10µs
10: 15µs
11: 20µs
1
0
SYNC ERROR DET
BYPASS
R/W
R/W
0b
1b
0: SYNC Clock Error detection
1: Clock Error Detection bypassed
MASTER SLAVE
0: Slave Mode - GPIO 1 or 2 need to be configured as SYNC IN and
external clock required
1: Master Mode - Device generates clock internally
Copyright © 2022 Texas Instruments Incorporated
98
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.51 Misc Control 4 Register (Offset = 0x36) [reset = 0x00]
Return to the 表7-10.
图7-64. Misc Control 4 Register
7
6
5
4
3
2
1
0
RESERVED
TLSBY
SSC4
SPREAD
SPECTRUM
SYNC CLOCK
PWM FREQUENCY
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表7-61. Misc Control 4 Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
Description
0b
6
TLSBY
0b
Three level mode for standby pin
0: Two level mode
1: Three level mode with MUTE at mid-voltage level
5-4
3
SSC4
R/W
R/W
0b
0b
Spread Spectrum Control 4
SPREAD SPECTRUM
SYNC CLOCK
Select whether sync clock input will be spread spectrum modulated
before setting PWM frequency. Applies if device is set to clock slave
mode.
0: Spread spectrum mode applied to clock sync input signal
1: Spread spectrum mode not applied to clock sync input signal
2-0
PWM FREQUENCY
R/W
0b
PWM switching frequency setting:
000: 2.1 MHz
001: 2.3 MHz
010: 576 kHz
011: 384 kHz
100: 460 kHz
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
99
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.52 SS Control 1 Register (Offset = 0x37) [reset = 0x22]
Return to the 表7-10.
图7-65. SS Control 1 Register
7
6
5
4
3
2
1
0
SSC1
R/W-100010b
表7-62. SS Control 1 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
SSC1
R/W
100010b
Spread Spectrum Control 1
Copyright © 2022 Texas Instruments Incorporated
100 Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.53 SS Control 2 Register (Offset = 0x38) [reset = 0x80]
Return to the 表7-10.
图7-66. SS Control 2 Register
7
6
5
4
3
2
1
0
SS ENABLE
R/W-1b
RESERVED
R/W-0b
SSC3
SSC2
R/W-0b
R/W-0b
表7-63. SS Control 2 Register Field Descriptions
Bit
Field
SS ENABLE
Type
Reset
Description
7
R/W
1b
0: Disable spread spectrum mode
1: Enable spread spectrum mode
6
RESERVED
SSC3
R/W
R/W
R/W
0b
0b
0b
5-4
3-0
Spread Spectrum Control 3
Spread Spectrum Control 2
SSC2
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback 101
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.54 PWM Phase Ctrl 1 Register (Offset = 0x39) [reset = 0x40]
Return to the 表7-10.
图7-67. PWM Phase Ctrl 1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0b
PHASE CH2
R/W-100b
RESERVED
R/W-0b
PHASE SEL
R/W-0b
表7-64. PWM Phase Ctrl 1 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
RESERVED
PHASE CH2
0b
6-4
100b
Phase offset of Channel 2 vs Channel 1 in manual mode
000: 0 degree
001: 45 degree
010: 90 degree
011: 135 degree
100: 180 degree
101: 225 degree
110: 270 degree
111: 315 degree
3-1
0
RESERVED
PHASE SEL
R/W
R/W
0b
0b
Adjustment mode for PWM phase of channel 2, 3 and 4 relative to
channel 1
0: Manual mode
1: Automatic mode
Copyright © 2022 Texas Instruments Incorporated
102 Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
7.6.1.55 PWM Phase Ctrl 2 Register (Offset = 0x3A) [reset = 0x62]
Return to the 表7-10.
图7-68. PWM Phase Ctrl 2 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0b
PHASE CH4
R/W-110b
RESERVED
R/W-0b
PHASE CH3
R/W-10b
表7-65. PWM Phase Ctrl 2 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
RESERVED
PHASE CH4
0b
6-4
110b
Phase offset of Channel 4 vs Channel 1 in manual mode
000: 0 degree
001: 45 degree
010: 90 degree
011: 135 degree
100: 180 degree
101: 225 degree
110: 270 degree
111: 315 degree
3
RESERVED
PHASE CH3
R/W
R/W
0b
2-0
10b
Phase offset of Channel 3 vs Channel 1 in manual mode
000: 0 degree
001: 45 degree
010: 90 degree
011: 135 degree
100: 180 degree
101: 225 degree
110: 270 degree
111: 315 degree
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback 103
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
8 Application Information Disclaimer
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPA6304-Q1 is a four-channel analog input Class-D audio-amplifier design for use in automotive head units
and external amplifier modules. The TPA6304-Q1 incorporates the necessary functionality to perform in
demanding OEM applications.
8.1.1 AM Radio Avoidance
AM-radio frequency interference is avoided by setting the switching frequency of the device above the AM band.
The switching frequency options available for AM avoidance are 2.1 MHz and 2.3 MHz.
8.1.2 Parallel BTL Operation (PBTL)
The device has the capability of placing two channels into a parallel configuration that allows for twice the current
drive capability for low impedance loads. BTL and PBTL modes can be me mixed. Channels 1 and 2 can be
placed in PBTL, channels 3 and 4 can be placed into PBTL, or both pairs can be placed in PBTL. Follow the
Typical application schematic for proper input and output connections for PBTL configuration useing both pairs.
The speaker output connections must be made on the speaker side of the LC filter. The device can drive more
current with paralleling BTL channels on the load side of the LC output filter. The input connections on channel 2
and channel 4 should be connected to ground.
The Mode Control Register has to be set for PBTL operations. Bit 4 sets channels 1 and 2 to PBTL and Bit 5
sets channels 3 and 4 to PBTL. These bits must only be changed while the STANDBY pin is asserted low.
Load diagnostics is supported for PBTL channels.
8.1.3 Reconstruction Filter Design
The amplifier outputs are driven by high-current LDMOS transistors in an H-bridge configuration. These
transistors are either fully off or fully on. The result is a square-wave output signal with a duty cycle that is
proportional to the amplitude of the audio signal. The amplifier outputs require a reconstruction filter that
comprises a series inductor and a capacitor to ground on each half-bridge output, generally called an LC filter.
The LC filter attenuates the PWM frequency and reduces electromagnetic emissions, allowing the reconstructed
audio signal to pass to the speakers. Design of the reconstruction filter significantly affects the audio
performance of the power amplifier. Therefore, to meet the system THD+N requirements, the selection of the
inductors used in the output filter should be carefully considered. Refer to the Class-D LC Filter Design,
SLAA701A, application report for a detailed description of proper component description and design of the LC
filter based upon the specified load and frequency response.
The recommended low-pass cutoff frequency of the LC filter is dependent on the selected switching frequency.
The low-pass cutoff frequency can be as high as 100 kHz for a PWM frequency of 2.1 MHz.
Certain specifications must be understood for a proper inductor. See the application note TAS6424-Q1 Inductor
Selection Guide, SLOA242, for information on selection the proper inductor. The inductance value is given at
zero current, but the inductors do have current through them as the TPA6304-Q1 drives current into the load.
Use the inductance versus current curve for the inductor to made sure the inductance does not drop below 2 µH
(for fsw = 2.1 MHz) at the maximum current for the system design during normal operation. The DCR of the
inductor directly affects the output power of the system design. The lower the DCR, the more power is provided
to the speakers. The typical inductor DCR for a 4 Ω system is 40 to 50 mΩ and for a 2 Ω system is 15 to 25
mΩ.
Copyright © 2022 Texas Instruments Incorporated
104 Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
8.1.4 Bootstrap Capacitors
The bootstrap capacitors provide the gate-drive voltage of the upper N-channel FET. These capacitors must be
sized appropriately for the system specification. For typical applications use 1 µF.
8.1.5 Line Driver Applications
In many automotive audio applications, the same head unit must drive either a speaker (with several Ω of
impedance) or an external amplifier input (with several kilo Ω of impedance). The design is capable of
supporting both applications and has special line driver gain and diagnostics. Coupled with the high switching
frequency the device is well suited for this type of application. The line driver mode uses the same signal path as
the normal speaker output mode with similar audio performance. Set the desired channel in line driver mode via
the Mode Control Register and the desired gain via the Misc Control 2 Register. The external connected
amplifier needs to have a differential impedance between 600 Ωand 4.7 kΩfor the DC line diagnostic to detect
the connected external amplifier. 图8-1 shows the recommended external amplifier input configuration, balanced
capacitor coupled.
Output Filter
External Amplifier
3.3 µH
1 …F
1 …F
1 nF
600 ꢀ
to
1 …F
4.7 kꢀ
1 nF
3.3 µH
1 …F
100 kꢀ
100 kꢀ
图8-1. Line Driver External Amplifier Input Configuration
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback 105
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
8.2 Typical Applications
8.2.1 BTL Application
图8-2 shows the schematic of a typical 4-channel solution for a head-unit application.
PVDD
INPUT
10 …F 0.1 ꢀF 1 nF
PVDD
150 nH
470 µF
CHASSIS GND
1
1 ꢀF
0.1 ꢀF
44
43
PVDD
PVDD
BST 4P
OUT 4P
1 ꢀF
2
3.3 µH
1 ꢀF
PVDDQ
10 nF
3
4
42
41
VBAT
GND
1 ꢀF
10 nF
3.3 µH
GVDD_RET
OUT_4M
2.2 ꢀF
5
6
40
39
1 ꢀF
1 ꢀF
GVDD
AVDD
BST 4M
BST 3P
1 ꢀF
7
8
3.3 µH
38
37
36
35
34
AVDD_RET
IN_REF
IN_4P
OUT 3P
GND
1 ꢀF
1 ꢀF
10 nF
10 nF
2.2 ꢀF
9
3.3 µH
0.47 ꢀF
0.47 ꢀF
OUT 3M
BST 3M
PVDD
10
11
12
DAC
1 ꢀF
1 ꢀF
IN_3P
0.1 ꢀF 1 ꢀF
0.47 ꢀF
0.47 ꢀF
IN_2P
PVDD
33
32
IN_1P
DVSS
PVDD
1 ꢀF 13
BST 2P
3.3 V
RPU1 RPU2 RPU3
3.3 µH
14
15
31
30
DVDD
SCL
OUT 2P
GND
1 ꢀF
10 nF
10 nF
1 ꢀF
3.3 µH
16
29
SDA
OUT 2M
BST 2M
17
18
28
27
1 ꢀF
1 ꢀF
STANDBY
FAULT
µC
BST 1P
3.3 µH
19
20
21
26
25
24
GPIO1
GPIO2
OUT 1P
GND
1 ꢀF
1 ꢀF
10 nF
10 nF
3.3 µH
OUT 1M
BST 1M
GND
22
23
1 ꢀF
PVDD
PVDD
1 ꢀF
0.1 ꢀF
图8-2. Typical 4-Channel BTL Application Schematic
8.2.1.1 Design Requirements
This head-unit example is focused on the smallest solution size for 4 times 25 W output power into 4 Ω with a
battery supply of 14.4 V.
The switching frequency is set above the AM-band at 2.1 MHz.
Copyright © 2022 Texas Instruments Incorporated
106 Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
The selection of a 2.1 MHz switching frequency enables the use of a small output inductor value of 3.3 µH which
leads to a very small footprint.
8.2.1.2 Detailed Hardware Design Procedure
Use the following procedure for the hardware design:
• Determine the output power that is required into the load. The output power requirement determines the
required power supply voltage and current. The output reconstruction filter components that are required are
also driven by the output power.
• With the requirements, adjust the typical application schematic in 图8-2.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback 107
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
8.2.2 PBTL Application
图 8-3 shows a schematic of a typical 2-channel solution for a head unit or external amplifier application where
high power into 2 Ωis required.
PVDD
INPUT
10 …F 0.1 ꢀF 1 nF
PVDD
150 nH
470 µF
CHASSIS GND
1
2
1 …F
0.1 …F
44
43
PVDD
PVDD
BST 4P
OUT 4P
1 …F
3.3 …H
3.3 …H
PVDDQ
3
4
42
41
VBAT
GND
1 …F
GVDD_RET
OUT 4M
2.2 …F
2.2 …F
2.2 …F
5
6
40
10 nF
10 nF
GVDD
AVDD
BST 4M
BST 3P
39 1 …F
38
1 …F
7
8
3.3 …H
3.3 …H
AVDD_RET
IN_REF
IN_4P
OUT 3P
GND
1 …F
37
9
36
OUT 3M
BST 3M
PVDD
1 …F
10
11
0.47 …F
35
DAC
IN_3P
0.1 …F 1 …F
34
IN_2P
PVDD
12
0.47 …F
33
32
IN_1P
DVSS
PVDD
1 …F 13
BST 2P
3.3 V
RPU1 RPU2 RPU3
1 …F
14
15
3.3 …H
31
DVDD
SCL
OUT 2P
GND
30
29
16
3.3 …H
2.2 …F
1 …F
1 ꢀF
SDA
OUT 2M
BST 2M
17
18
28
27
10 nF
10 nF
STANDBY
FAULT
µC
2.2 …F
3.3 …H
BST 1P
19
20
21
26
25
24
23
GPIO1
GPIO2
OUT 1P
GND
3.3 …H
OUT 1M
BST 1M
GND
22
PVDD
1 …F
PVDD
1 …F
0.1 …F
图8-3. 2-Channel PBTL Application Schematic
8.2.2.1 Detailed Hardware Design Procedure
Use the following procedure for the hardware design:
• Determine the output power that is required into the load. The output power requirement determines the
required power supply voltage and current. The output reconstruction filter components that are required are
also driven by the output power.
• With the requirements, adjust the typical application schematic in 图8-3.
Copyright © 2022 Texas Instruments Incorporated
108 Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
9 Power Supply Recommendations
The TPA6304-Q1 requires a minimum of two power supply rails, PVDD and DVDD, when PVDD and VBAT are
connected to the same supply. In the case VBAT is different from PVDD, then three power supplies will be
required. The PVDD supply is the high-current supply that provides power to the output stage. The VBAT supply
is a lower current rail that provides power to the lower voltage circuitry. The DVDD supply is the 3.3 V logic
supply and must be maintained in the tolerance as shown in the Recommended Operating Conditions table.
PVDD
See Application Diagram for
PVDD and VBAT External
Decoupling Recommendations
Output Stage Power Supply
+
PVDD
PVDDQ
VBAT
œ
Internal Mixed
Signal Circuitry
Gate Drive
Votlage
PVDD and VBAT can be
connected together
GVDD
LDO
2.2 mF
VBAT
+
œ
Internal Analog
Circuitry
GVDD_RET
AVDD
LDO
1 mF
DVDD
Internal Digital
Circuitry
AVDD_RET
+
DVDD
1 mF
œ
DVSS
图9-1. Power Supply Block
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback 109
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
10 Layout
10.1 Layout Guidelines
The pinout of the TPA6304-Q1 was selected to provide flow through layout with all high-power connections on
the right side, and all low-power signals and supply decoupling on left side.
节 10.2 shows the area for the components in the application example (see the 图 8-2 section). This layout
example is taken from the EVM PCB.
The TPA6304-Q1 EVM uses a four-layer PCB. The copper thickness was selected as 70 µm to optimize power
loss.
The small value of the output filter provides a small size and, in this case, the low height of the inductor enables
double sided mounting.
10.1.1 Electrical Connection of Thermal Pad and Heat Sink
For the DDV package, the heat sink connected to the thermal pad of the device should be connected to GND.
The thermal pad must not be connected to any other electrical node.
10.1.2 General Considerations
The EVM layout is optimized for low noise and EMC performance.
The TPA6304-Q1 has an exposed thermal pad that is up, away from the PCB. The layout must consider an
external heat sink.
Refer to Layout Top Example for the following guidelines:
• A ground plane, A, on the same side as the device pins helps reduce EMI by providing a very-low loop
impedance for the high-frequency switching current.
• The decoupling capacitors on PVDD, B, are very close to the device with the ground return close to the
ground pins.
• The ground connections for the capacitors in the LC filter, C, have a direct path back to the device and also
the ground return for each channel is the shared. This direct path allows for improved common mode EMI
rejection.
• The traces from the output pins to the inductors, D, should have the shortest trace possible to allow for the
smallest loop of large switching currents.
• Heat-sink mounting screws, E, should be close to the device to keep the loop short from the package to
ground.
• Many vias, F, stitching together the ground planes can create a shield to isolate the amplifier and power
supply.
Copyright © 2022 Texas Instruments Incorporated
110
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
10.2 Layout Example
A
C
D
F
E
图10-1. Layout Top Example
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
111
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
B
图10-2. Layout Bottom Example
10.3 Thermal Considerations
The thermally enhanced PowerPAD package has an exposed pad up for connection to a heat sink. The output
power of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on
it by the system, such as the ambient operating temperature. The heat sink absorbs heat from the TPA6304-Q1
and transfers it to the air. With proper thermal management this process can reach equilibrium and heat can be
continually transferred from the device. Heat sinks can be smaller than that of classic linear amplifier design
Copyright © 2022 Texas Instruments Incorporated
112
Submit Document Feedback
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
because of the excellent efficiency of class-D amplifiers. This device is intended for use with a heat sink,
therefore, RθJC is used as the thermal resistance from junction to the exposed metal package. This resistance
dominates the thermal management, so other thermal transfers is not considered. The thermal resistance of
RθJA (junction to ambient) is required to determine the full thermal solution. The thermal resistance is comprised
of the following components:
• RθJC of the TPA6304-Q1
• Thermal resistance of the thermal interface material
• Thermal resistance of the heat sink
The thermal resistance of the thermal interface material can be determined from the manufacturer’s value for
the area thermal resistance (expressed in °Cmm2/W) and the area of the exposed metal package. For example,
a typical, white, thermal grease with a 0.0254 mm (0.001 inch) thick layer is approximately 4.52°C mm2/W. The
TPA6304-Q1 in the DDV44 package has an exposed area of 28.7 mm2. By dividing the area thermal resistance
by the exposed metal area determines the thermal resistance for the thermal grease. The thermal resistance of
the thermal grease is 0.157°C/W
表 10-1 lists the modeling parameters for one device on a heat sink. The junction temperature is assumed to be
115°C while delivering an average power of 10 watts per channel into a 4 Ω load. The thermal-grease example
previously described is used for the thermal interface material. Use 方程式1 to design the thermal system.
RθJA = RθJC + thermal interface resistance + heat sink resistance
(1)
表10-1. Thermal Modeling
Description
Value
25°C
Ambient Temperature
Average Power to load
20W (4 x 5W)
Power dissipation
Junction Temperature
6W (See 图6-7)
115°C
3.6°C (0.6°C/W × 6W)
0.942°C (0.157°C/W × 6W)
ΔT inside package
ΔT through thermal interface material
Required heat sink thermal resistance
14.24°C/W ([115°C –25°C –3.6°C –0.942°C] / 6W)
System thermal resistance to ambient RθJA
14.99°C/W
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
113
Product Folder Links: TPA6304-Q1
TPA6304-Q1
www.ti.com.cn
ZHCSMX0B –SEPTEMBER 2019 –REVISED DECEMBER 2020
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
PurePath™ Console 3 Graphical Development Suite
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
Burr-Brown™ and TI E2E™ are trademarks of Texas Instruments.
PurePath™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2022 Texas Instruments Incorporated
114
Submit Document Feedback
Product Folder Links: TPA6304-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPA6304QDDVRQ1
ACTIVE
HTSSOP
DDV
44
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPA6304
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-May-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA6304QDDVRQ1
HTSSOP DDV
44
2000
330.0
24.4
8.9
14.7
1.4
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-May-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DDV 44
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
TPA6304QDDVRQ1
2000
Pack Materials-Page 2
PACKAGE OUTLINE
DDV0044E
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC SMALL OUTLINE
8.3
7.9
C
TYP
A
PIN 1 INDEX
AREA
SEATING
PLANE
0.1 C
42X 0.635
44
1
2X
14.1
13.9
8.00
7.16
13.335
NOTE 3
EXPOSED
THERMAL
PAD
2X (0.28)
NOTE 5
22
23
0.27
0.17
44X
2X (0.9)
NOTE 5
3.80
2.96
0.1
C A B
6.2
6.0
B
SEE DETAIL A
(0.15) TYP
0.25
GAGE PLANE
1.2
1.0
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4224779/A 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. The exposed thermal pad is designed to be attached to an external heatsink.
6. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DDV0044E
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
44X (1.45)
44X (0.4)
SEE DETAILS
SYMM
1
44
(R0.05) TYP
42X (0.635)
SYMM
22
23
(7.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 7X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4224779/A 01/2019
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDV0044E
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
44X (1.45)
44X (0.4)
1
44
(R0.05) TYP
42X (0.635)
SYMM
45
22
23
SYMM
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 7X
4224779/A 01/2019
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TPA6404-Q1
具有负载突降保护功能的汽车类 45W、2MHz、4 通道、4.5V 至 18V 电源模拟输入 D 类音频放大器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA6404QDKQRQ1
具有负载突降保护功能的汽车类 45W、2MHz、4 通道、4.5V 至 18V 电源模拟输入 D 类音频放大器 | DKQ | 56 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPA68
TRISILWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
TPA68
TELECOMMUNICATION PROTECTIONWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
BL Galaxy Ele
TPA68A-12
90V, 30A, SILICON SURGE PROTECTORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
TPA68A-12-RL
90V, 30A, SILICON SURGE PROTECTORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
TPA68A-18
90V, 30A, SILICON SURGE PROTECTORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
TPA68A-18-RL
90V, 30A, SILICON SURGE PROTECTORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
TPA68B-12
82V, 30A, SILICON SURGE PROTECTORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
TPA68B-12-RL
82V, 30A, SILICON SURGE PROTECTORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
TPA68B-18
82V, 30A, SILICON SURGE PROTECTORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
TPA68B-18-RL
82V, 30A, SILICON SURGE PROTECTORWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明