TPD1E01B04DPLR [TI]
适用于 USB-C 和天线且采用 0402 和 0201 封装的 0.13pF、±3.6V、±15kV ESD 保护二极管 | DPL | 2 | -40 to 125;
| 型号： | TPD1E01B04DPLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 USB-C 和天线且采用 0402 和 0201 封装的 0.13pF、±3.6V、±15kV ESD 保护二极管 | DPL | 2 | -40 to 125 局域网 二极管 |
| 文件： | 总23页 (文件大小：810K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
TPD1E01B04
ZHCSF79B –MARCH 2016–REVISED MAY 2016
TPD1E01B04 适用于 USB Type-C 和 Thunderbolt 3 的单通道 ESD 保护
二极管
1 特性
3 说明
1
•
IEC 61000-4-2 4 级静电放电 (ESD) 保护
TPD1E01B04 是一款适用于 USB Type-C 和
Thunderbolt 3 电路保护的双向 TVS ESD 保护二极管
阵列。TPD1E01B04 的额定 ESD 冲击消散值等于
IEC 61000-4-2（4 级）国际标准中规定的最高水平。
–
–
±15kV 接触放电
±17kV 气隙放电
•
•
•
IEC 61000-4-4 瞬态放电 (EFT) 保护
80A (5/50ns)
IEC 61000-4-5 浪涌保护
2.5A (8/20µs)
IO 电容：
–
此器件 特有 一个 0.18pF（典型值）IO 电容，适用于
保护速率高达 20Gbps 的高速接口（例如 USB 3.1
Gen2 和 Thunderbolt 3）。低动态电阻和低钳位电压
可针对瞬变事件提供系统级保护。
–
–
–
0.18pF（典型值）
0.2pF（最大值）
TPD1E01B04 采用符合工业标准的 0201 (DPL) 封
装。
•
•
•
直流击穿电压：6.4V（典型值）
超低泄漏电流：10nA（最大值）
器件信息(1)
低静电放电 (ESD) 钳位电压：16A 传输线路脉冲
(TLP) 时为 15V
器件型号
封装
X2SON (2)
封装尺寸（标称值）
TPD1E01B04
0.60mm x 0.30mm
•
•
•
•
低插入损耗：26.9GHz（–3dB 带宽）
支持速率高达 20Gbps 的高速接口
工业温度范围：-40°C 至 +125°C
超小型 0201 封装
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
典型应用
USB Type-C
Connector
2 应用
SSRX1P
•
终端设备
TPD1E01B04 (x4)
TPD4E05U06
SSRX1N
SSTX1P
SSTX1N
–
–
–
–
–
–
便携式计算机和台式机
手机和平板电脑
机顶盒
VBUS
SBU2
CC1
电视和监视器
USB 软件狗
扩展坞
DPT
DMT
DMB
DPB
TPD4E05U06
•
接口
–
–
–
–
–
–
–
USB Type-C
Thunderbolt 3
SBU1
CC2
USB 3.1 第 2 代
高清多媒体接口 (HDMI) 2.0/1.4
USB 3.0
VBUS
SSRX2N
SSRX2P
SSTX2N
SSTX2P
DisplayPort 1.3
PCI Express 3
TPD1E01B04 (x4)
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDG3
TPD1E01B04
ZHCSF79B –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
目录
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
Power Supply Recommendations...................... 13
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 ESD Ratings—IEC Specification .............................. 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
8
9
10 Layout................................................................... 13
10.1 Layout Guidelines ................................................. 13
10.2 Layout Example .................................................... 13
11 器件和文档支持 ..................................................... 14
11.1 文档支持................................................................ 14
11.2 社区资源................................................................ 14
11.3 商标....................................................................... 14
11.4 静电放电警告......................................................... 14
11.5 Glossary................................................................ 14
12 机械、封装和可订购信息....................................... 14
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (March 2016) to Revision B
Page
•
更改了Electrical Characteristics表。更新了 VHOLD 限值 ......................................................................................................... 1
Changes from Original (March 2016) to Revision A
Page
•
器件状态从产品预览改为量产数据.......................................................................................................................................... 1
2
版权 © 2016, Texas Instruments Incorporated
TPD1E01B04
www.ti.com.cn
ZHCSF79B –MARCH 2016–REVISED MAY 2016
5 Pin Configuration and Functions
DPL Package
2-Pin X2SON
Top View
1
2
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
IO
1
2
I/O
I/O
ESD Protected Channel. If used as ESD IO, connect pin 2 to ground
ESD Protected Channel. If used as ESD IO, connect pin 1 to ground
IO
Copyright © 2016, Texas Instruments Incorporated
3
TPD1E01B04
ZHCSF79B –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
80
UNIT
A
Electrical fast transient
Peak pulse
IEC 61000-4-5 (5/50 ns)
IEC 61000-4-5 power (tp - 8/20 µs)
IEC 61000-4-5 current (tp - 8/20 µs)
Operating free-air temperature
Storage temperature
27
W
2.5
A
TA
–40
–65
125
155
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings—IEC Specification
VALUE
UNIT
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air-gap discharge
±15000
±17000
V(ESD)
Electrostatic discharge
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–3.6
–40
MAX
3.6
UNIT
VIO
TA
Input pin voltage
V
Operating free-air temperature
125
°C
6.5 Thermal Information
TPD1E01B04
THERMAL METRIC(1)
DPL (X2SON)
2 PINS
582
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
264.5
394.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
36.4
ψJB
394.4
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2016, Texas Instruments Incorporated
TPD1E01B04
www.ti.com.cn
ZHCSF79B –MARCH 2016–REVISED MAY 2016
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRWM
VBRF
Reverse stand-off voltage
Breakdown voltage, IO pin to GND
IIO < 10 nA
–3.6
3.6
V
V
V
Measured as the maximum voltage
before device snaps back into VHOLD
voltage
6.4
–6.4
VBRR
Breakdown voltage, GND to IO pin
Holding voltage
VHOLD
IIO = 1 mA, TA = 25°C
5
5.9
7
6.5
V
IPP = 1 A, TLP, from IO to GND
IPP = 5 A, TLP, from IO to GND
IPP = 16 A, TLP, from IO to GND
IPP = 1 A, TLP, from GND to IO
IPP = 5 A, TLP, from GND to IO
IPP = 16 A, TLP, from GND to IO
VIO = ±2.5 V
9.2
15
7
VCLAMP
Clamping voltage
V
9.2
15
ILEAK
RDYN
Leakage current, IO to GND
Dynamic resistance
10
nA
IO to GND
0.57
0.57
Ω
GND to IO
VIO = 0 V, f = 1 MHz, IO to GND
TA = 25°C
CL
Line capacitance
0.18
0.20
pF
Copyright © 2016, Texas Instruments Incorporated
5
TPD1E01B04
ZHCSF79B –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
6.7 Typical Characteristics
30
27
24
21
18
15
12
9
30
27
24
21
18
15
12
9
6
6
3
3
0
0
-3
-3
0
3
6
9
12
15
18
21
24
27
0
3
6
9
12
15
18
21
24
27
Voltage (V)
Voltage (V)
D001
D002
Figure 1. Positive TLP Curve
Figure 2. Negative TLP Curve
110
10
0
100
90
80
70
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-10
-10
0
10 20 30 40 50 60 70 80 90 100
Time (ns)
-10
0
10 20 30 40 50 60 70 80 90 100
Time (ns)
D003
D004
Figure 3. 8-kV IEC Waveform
Figure 4. –8-kV IEC Waveform
30
3.6
3.3
3
0.4
Power
Current
27.5
25
0.35
0.3
22.5
20
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
0.25
0.2
17.5
15
12.5
10
0.15
0.1
7.5
5
-40èC
25èC
85èC
125èC
2.5
0
0.05
0
-2.5
-0.3
-5
0
5
10 15 20 25 30 35 40 45 50 55 60
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
Time (ms)
Voltage Bias (V)
D005
D006
Figure 5. Surge Curve (tp = 8/20µs), IO pin to GND
Figure 6. Capacitance vs. Bias Voltage
6
Copyright © 2016, Texas Instruments Incorporated
TPD1E01B04
www.ti.com.cn
ZHCSF79B –MARCH 2016–REVISED MAY 2016
Typical Characteristics (continued)
1
0.8
0.6
0.4
0.2
0
1000
800
600
400
200
0
-0.2
-0.4
-0.6
-0.8
-1
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
-40 -25 -10
5
20 35 50 65 80 95 110 125
Voltage (V)
Temperature (èC)
D007
D001
Figure 7. Leakage Current vs. Temperature
Figure 8. DC Voltage Sweep I-V Curve
0.3
0.27
0.24
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
2
7
12
17
22
27
30
0.05 0.1
1
10
40
Frequency (GHz)
Frequency (GHz)
D009
D010
Figure 9. Capacitance vs. Frequency
Figure 10. Insertion Loss
Figure 11. USB3.1 Gen 2 10-Gbps Eye Diagram (Bare Board)
Figure 12. USB3.1 Gen 2 10-Gbps Eye Diagram (with
TPD1E01B04)
Copyright © 2016, Texas Instruments Incorporated
7
TPD1E01B04
ZHCSF79B –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPD1E01B04 device is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can
dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-
low capacitance makes this device ideal for protecting any super high-speed signal pins including Thunderbolt 3.
The low capacitance allows for extremely low losses even at RF frequencies such as USB 3.1 Gen 2,
Thunderbolt 3, or antenna applications.
7.2 Functional Block Diagram
IO
GND
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 IEC 61000-4-2 ESD Protection
The I/O pins can withstand ESD events up to ±15-kV contact and ±17-kV air gap. An ESD-surge clamp diverts
the current to ground.
7.3.2 IEC 61000-4-4 EFT Protection
The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω
impedance). An ESD-surge clamp diverts the current to ground.
7.3.3 IEC 61000-4-5 Surge Protection
The I/O pins can withstand surge events up to 2.5 A and 27 W (8/20 µs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.4 IO Capacitance
The capacitance between each I/O pin to ground is 0.18 pF (typical) and 0.20 pF (maximum). This device
supports data rates up to 20 Gbps.
7.3.5 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is ±6.4 V (typical). This ensures that sensitive equipment is protected
from surges above the reverse standoff voltage of ±3.6 V.
7.3.6 Ultra Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of ±2.5 V
7.3.7 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 9.2 V (IPP = 5 A).
7.3.8 Supports High Speed Interfaces
This device is capable of supporting high speed interfaces up to 20 Gbps, because of the extremely low IO
capacitance.
7.3.9 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
8
Copyright © 2016, Texas Instruments Incorporated
TPD1E01B04
www.ti.com.cn
ZHCSF79B –MARCH 2016–REVISED MAY 2016
Feature Description (continued)
7.3.10 Easy Flow-Through Routing Package
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers
flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The TPD1E01B04 device is a passive integrated circuit that triggers when voltages are above VBRF or below
VBRR. During ESD events, voltages as high as ±17 kV (air) can be directed to ground via the internal diode
network. When the voltages on the protected line fall below the trigger levels of TPD1E01B04 (usually within 10s
of nano-seconds) the device reverts to passive.
Copyright © 2016, Texas Instruments Incorporated
9
TPD1E01B04
ZHCSF79B –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD1E01B04 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on
high-speed signal lines between a human interface connector and a system. As the current from ESD passes
through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the
protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
USB Type-C
Connector
SSRX1P
TPD1E01B04 (x4)
TPD4E05U06
SSRX1N
SSTX1P
SSTX1N
VBUS
SBU2
CC1
DPT
DMT
DMB
DPB
TPD4E05U06
SBU1
CC2
VBUS
SSRX2N
SSRX2P
SSTX2N
SSTX2P
TPD1E01B04 (x4)
Copyright © 2016, Texas Instruments Incorporated
Figure 13. USB Type-C for Thunderbolt 3 ESD Schematic
8.2.1 Design Requirements
For this design example eight TPD1E01B04 devices and two TPD4E05U06 devices are being used in a USB
Type-C for Thunderbolt 3 application. This provides a complete ESD protection scheme.
Given the Thunderbolt 3 application, the parameters listed in Table 1 are known.
Table 1. Design Parameters
DESIGN PARAMETER
VALUE
0 V to 3.6 V
up to 10 GHz
0 V to 5 V
Signal range on superspeed Lines
Operating frequency on superspeed Lines
Signal range on CC, SBU, and DP/DM Lines
10
Copyright © 2016, Texas Instruments Incorporated
TPD1E01B04
www.ti.com.cn
ZHCSF79B –MARCH 2016–REVISED MAY 2016
Typical Application (continued)
Table 1. Design Parameters (continued)
DESIGN PARAMETER
VALUE
Operating frequency on CC, SBU, and
DP/DM Lines
up to 480 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The TPD1E01B04 supports signal ranges between –3.6 V and 3.6 V, which supports the SuperSpeed pairs on
the USB Type-C application. The TPD4E05U06 supports signal ranges between 0 V and 5.5 V, which supports
the CC, SBU, and DP-DM lines.
8.2.2.2 Operating Frequency
The TPD1E01B04 has a 0.18 pF (typical) capacitance, which supports the Thunderbolt 3 data rates of 20 Gbps.
The TPD4E05U06 has a 0.5-pF (typical) capacitance, which easily supports the CC, SBU, and DP-DM data
rates.
8.2.3 Application Curves
Figure 14. USB 3.1 Gen 2 10-Gbps Eye Diagram (Bare
Board)
Figure 15. USB 3.1 Gen 2 10-Gbps Eye Diagram (with
TPD1E01B04)
Copyright © 2016, Texas Instruments Incorporated
11
TPD1E01B04
ZHCSF79B –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
0.05 0.1
1
10
40
Frequency (GHz)
D010
Figure 16. Insertion Loss
12
Copyright © 2016, Texas Instruments Incorporated
TPD1E01B04
www.ti.com.cn
ZHCSF79B –MARCH 2016–REVISED MAY 2016
9 Power Supply Recommendations
This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended
I/O specification to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
[egend
Çop [ayer
.oꢀꢀom [ayer
tin ꢀo Db5
ëL! ꢀo ë.Ü{ tlane
ëL! ꢀo oꢀher layer
ëL! ꢀo Db5 tlane
Figure 17. USB Type-C Mid-Mount, Hybrid Connector ESD Layout
版权 © 2016, Texas Instruments Incorporated
13
TPD1E01B04
ZHCSF79B –MARCH 2016–REVISED MAY 2016
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档请参见以下部分：
用户指南《TPD1E01B04 评估模块》，SLVUAN5
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
14
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD1E01B04DPLR
TPD1E01B04DPLT
TPD1E01B04DPYR
TPD1E01B04DPYT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
X2SON
X2SON
X1SON
X1SON
DPL
DPL
DPY
DPY
2
2
2
2
15000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7
7
Samples
Samples
Samples
Samples
NIPDAU
10000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
(5C, A5)
(5C, A5)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPD1E01B04 :
Automotive : TPD1E01B04-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE OUTLINE
DPY0002A
X1SON - 0.45 mm max height
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
B
A
PIN 1 INDEX AREA
0.7
0.5
0.45
0.30
C
SEATING PLANE
0.08 C
0.05
0.00
0.65
1
2
SYMM
0.55
0.45
2X
0.1
C A B
SYMM
0.3
0.2
2X
0.05
C A B
4224561/B 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.3)
SYMM
1
2
SYMM
2X (0.5)
(R0.05) TYP
(0.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224561/B 03/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0)
2X (0.3)
2X (0.5)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2
1
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224561/B 03/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPD1E01B04DPLT
适用于 USB-C 和天线且采用 0402 和 0201 封装的 0.13pF、±3.6V、±15kV ESD 保护二极管 | DPL | 2 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPD1E01B04DPYR
适用于 USB-C 和天线且采用 0402 和 0201 封装的 0.13pF、±3.6V、±15kV ESD 保护二极管 | DPY | 2 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPD1E01B04DPYRQ1
适用于 USB 和 FPD-Link 且采用 0402 封装的汽车类 0.18pF、±3.6V、±15kV ESD 保护二极管 | DPY | 2 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPD1E01B04DPYT
适用于 USB-C 和天线且采用 0402 和 0201 封装的 0.13pF、±3.6V、±15kV ESD 保护二极管 | DPY | 2 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPD1E04U04
适用于 HDMI 2.0 和 USB 3.0 且采用 0402 和 0201 封装的 0.5pF、3.6V、±16kV ESD 保护二极管Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPD1E04U04DPLR
适用于 HDMI 2.0 和 USB 3.0 且采用 0402 和 0201 封装的 0.5pF、3.6V、±16kV ESD 保护二极管 | DPL | 2 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPD1E04U04DPLT
适用于 HDMI 2.0 和 USB 3.0 且采用 0402 和 0201 封装的 0.5pF、3.6V、±16kV ESD 保护二极管 | DPL | 2 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPD1E04U04DPYR
适用于 HDMI 2.0 和 USB 3.0 且采用 0402 和 0201 封装的 0.5pF、3.6V、±16kV ESD 保护二极管 | DPY | 2 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPD1E04U04DPYT
适用于 HDMI 2.0 和 USB 3.0 且采用 0402 和 0201 封装的 0.5pF、3.6V、±16kV ESD 保护二极管 | DPY | 2 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPD1E05U06
1, 4, 6 CHANNEL PROTECTION SOLUTION FOR SUPER-SPEED (UP TO 6 GBPS) INTERFACEWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPD1E05U06-Q1
TPDxE05U06 1, 4, 6 Channel ESD Protection Device for Super-Speed (Up to 6 Gbps) InterfaceWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPD1E05U06DPYR
适用于高速接口且采用 0402 封装的 0.4pF、5.5V、±12kV ESD 保护二极管 | DPY | 2 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明