TPD1E04U04DPYT [TI]
适用于 HDMI 2.0 和 USB 3.0 且采用 0402 和 0201 封装的 0.5pF、3.6V、±16kV ESD 保护二极管 | DPY | 2 | -40 to 125;
| 型号： | TPD1E04U04DPYT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 HDMI 2.0 和 USB 3.0 且采用 0402 和 0201 封装的 0.5pF、3.6V、±16kV ESD 保护二极管 | DPY | 2 | -40 to 125 二极管 |
| 文件： | 总27页 (文件大小：3290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPD1E04U04
ZHCSF81A –MARCH 2016–REVISED APRIL 2016
TPD1E04U04 适用于 HDMI 2.0 和 USB 3.0 的低 RDYN 单通道 ESD 保护二
极管
1 特性
3 说明
1
•
IEC 61000-4-2 4 级静电放电 (ESD) 保护
TPD1E04U04 是一款单向 TVS ESD 保护二极管，用
于为 HDMI 2.0 和 USB 3.0 电路提供保护。
–
–
±16kV 接触放电
±16kV 气隙放电
TPD1E04U04 的额定 ESD 冲击消散值高于 IEC
61000-4-2（4 级）国际标准中规定的最高水平。
•
•
IEC 61000-4-4 瞬态放电 (EFT) 保护
80A (5/50ns)
IEC 61000-4-5 浪涌保护
2.5A (8/20µs)
–
该器件 特有 一个 0.5pF IO 电容，适合于保护速率高
达 6Gbps 的高速接口，例如 HDMI 2.0 和 USB 3.0 接
口。低动态电阻和超低钳位电压可为敏感的 SoC 提供
针对瞬变事件的系统级保护。
–
•
•
IO 电容：0.5pF（典型值）、0.65pF（最大值）
超低 ESD 钳位电压
TPD1E04U04 采用符合行业标准的 0402 (DPY) 封
装。
–
–
16A TLP 时为 8.9V
-16A TLP 时为 -4.6V
器件信息(1)
•
低 RDYN
–
–
IO 与 GND 之间为 0.25Ω
GND 与 IO 之间为 0.18Ω
器件型号
封装
X1SON (2)
封装尺寸（标称值）
TPD1E04U04
0.6mm x 1.00mm
•
•
•
•
•
直流击穿电压：5V（最小值）
超低泄漏电流：10nA（最大值）
支持速率最高达 6Gbps 的高速接口
工业温度范围：-40°C 至 +125°C
符合行业标准的 0402 封装
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
典型的 HDMI 2.0 应用
TMDS_D2+
TMDS_D2-
TMDS_D1+
TMDS_D1-
TMDS_D0+
TMDS_D0-
TMDS_CK+
TMDS_CK-
CEC
2 应用
•
终端设备
–
–
–
–
–
机顶盒
便携式计算机和台式机
电视和监视器
手机和平板电脑
UTILITY
DDC_CLK
DDC_DAT
HOTPLUG_DET
数字视频录像机 (DVR) 和网络视频录像机
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
(NVR)
•
接口
TPD1E04U04 (x8)
GND
TPD1E05U06 (x5)
Copyright © 2016, Texas Instruments Incorporated
–
–
–
–
–
HDMI 2.0
HDMI 1.4b
USB 3.0
DisplayPort 1.2
PCI Express 3.0
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDG4
TPD1E04U04
ZHCSF81A –MARCH 2016–REVISED APRIL 2016
www.ti.com.cn
目录
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
Power Supply Recommendations...................... 13
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 ESD Ratings—IEC Specification ............................. 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
8
9
10 Layout................................................................... 13
10.1 Layout Guidelines ................................................. 13
10.2 Layout Example .................................................... 14
11 器件和文档支持 ..................................................... 15
11.1 文档支持 ............................................................... 15
11.2 社区资源................................................................ 15
11.3 商标....................................................................... 15
11.4 静电放电警告......................................................... 15
11.5 Glossary................................................................ 15
12 机械、封装和可订购信息....................................... 16
7
4 修订历史记录
Changes from Original (March 2016) to Revision A
Page
•
已将器件状态从产品预览更改为量产数据 .............................................................................................................................. 1
2
版权 © 2016, Texas Instruments Incorporated
TPD1E04U04
www.ti.com.cn
ZHCSF81A –MARCH 2016–REVISED APRIL 2016
5 Pin Configuration and Functions
DPY Package
2-Pin X1SON
Top View
1
2
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
IO
1
2
I/O
ESD Protected Channel
GND
Ground
Ground. Connect to ground
Copyright © 2016, Texas Instruments Incorporated
3
TPD1E04U04
ZHCSF81A –MARCH 2016–REVISED APRIL 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
80
UNIT
A
Electrical fast transient
Peak pulse
IEC 61000-4-4 (5/50 ns)
IEC 61000-4-5 power (tp - 8/20 µs)
IEC 61000-4-5 current (tp - 8/20 µs)
Operating free-air temperature
Storage temperature
19
W
2.5
A
TA
–40
–65
125
155
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings—IEC Specification
VALUE
UNIT
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air-gap discharge
±16000
±16000
V(ESD)
Electrostatic discharge
V
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
MAX
3.6
UNIT
VIO
TA
Input pin voltage
V
Operating free-air temperature
–40
125
°C
6.5 Thermal Information
TPD1E04U04
THERMAL METRIC(1)
DPY (X1SON)
2 PINS
683.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
494.2
568.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
217.4
ψJB
568.7
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2016, Texas Instruments Incorporated
TPD1E04U04
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ZHCSF81A –MARCH 2016–REVISED APRIL 2016
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.6
UNIT
VRWM
VBR
VF
Reverse stand-off voltage
Breakdown voltage, IO pin to GND
IIO < 10 nA
TA = 25°C(1)
V
V
V
5
6.2
0.8
7.5
Forward diode voltage, GND to IO
pin
IIO = 1 mA, TA = 25°C
VHOLD
Holding voltage
IIO = 1 mA
5.3
5.3
V
V
VCLAMP
Clamping voltage
IPP = 1 A, TLP, from IO to GND
IPP = 16 A, TLP, from IO to GND
IPP = 1 A, TLP, from GND to IO
IPP = 16 A, TLP, from GND to IO
VIO = 2.5 V
8.9
1.3
4.6
ILEAK
RDYN
Leakage current, any IO to GND
Dynamic resistance
0.1
10
nA
IO to GND
0.25
0.18
0.5
Ω
GND to IO
CL
Line capacitance
VIO = 0 V, f = 1 MHz, IO to GND, TA
= 25°C
0.65
pF
(1) Measured as the maximum voltage before device snaps back into VHOLD voltage.
Copyright © 2016, Texas Instruments Incorporated
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6.7 Typical Characteristics
30
25
20
15
10
5
30
25
20
15
10
5
0
0
-5
-5
0
2
4
6
8
10
12
14
0
1
2
3
4
5
6
7
8
Voltage (V)
Voltage (V)
D012
D014
Figure 1. Positive TLP Curve
Figure 2. Negative TLP Curve
50
45
40
35
30
25
20
15
10
5
5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
0
-5
-10
-10
0
10 20 30 40 50 60 70 80 90 100
Time (ns)
-10
0
10 20 30 40 50 60 70 80 90 100
Time (ns)
D006
D007
Figure 3. 8-kV IEC Waveform
Figure 4. –8-kV IEC Waveform
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
20
18
16
14
12
10
8
3
Power
Current
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
6
4
-40èC
25èC
125èC
2
0
-5
0
5
10 15 20 25 30 35 40 45 50 55
Time (µs)
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
Voltage Bias (V)
D010
D011
Figure 5. Surge Curve (tp = 8/20µs), IO Pin to GND
Figure 6. Capacitance vs. Bias Voltage
6
Copyright © 2016, Texas Instruments Incorporated
TPD1E04U04
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ZHCSF81A –MARCH 2016–REVISED APRIL 2016
Typical Characteristics (continued)
1000
1
0.8
0.6
0.4
0.2
0
800
600
400
200
0
-0.2
-0.4
-0.6
-0.8
-1
-40 -25 -10
5
20 35 50 65 80 95 110 125
-1
0
1
2
3
4
5
6
Temperature (èC)
Voltage (V)
D017
D009
Figure 7. Leakage Current vs. Temperature
Figure 8. DC Voltage Sweep I-V Curve
1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VBIAS = 0 V
VBIAS = 1.8 V
VBIAS = 3.3 V
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
1G
2G
3G
4G
5G
6G
7G
8G
9G 10G
50M 100M
1G
10G
Frequency (Hz)
Frequency (Hz)
D016
D008
Figure 9. Capacitance vs. Frequency
Figure 10. Insertion Loss
Figure 11. HDMI2.0 6-Gbps TP2 Eye Diagram (Bare Board)
Copyright © 2016, Texas Instruments Incorporated
7
TPD1E04U04
ZHCSF81A –MARCH 2016–REVISED APRIL 2016
www.ti.com.cn
Typical Characteristics (continued)
Figure 12. HDMI2.0 6-Gbps TP2 Eye Diagram (with TPD1E04U04)
8
Copyright © 2016, Texas Instruments Incorporated
TPD1E04U04
www.ti.com.cn
ZHCSF81A –MARCH 2016–REVISED APRIL 2016
7 Detailed Description
7.1 Overview
The TPD1E04U04 is a unidirectional ESD Protection Diode with ultra-low capacitance designed for HDMI 2.0
and USB 3.0. This device can dissipate ESD strikes above the maximum level specified by the IEC 61000-4-2
International Standard. The extremely low clamping voltage and low RDYN make this device ideal for supporting
the next-generation small feature size SoCs. The low capacitance also makes this device ideal for protecting any
high-speed signal pins on these sensitive interface pins.
7.2 Functional Block Diagram
I/O
GND
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 IEC 61000-4-2 ESD Protection
The IO pins can withstand ESD events up to ±16-kV contact and ±16-kV air gap. An ESD-surge clamp diverts
the current to ground.
7.3.2 IEC 61000-4-4 EFT Protection
The IO pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50-Ω
impedance). An ESD-surge clamp diverts the current to ground.
7.3.3 IEC 61000-4-5 Surge Protection
The IO pins can withstand surge events up to 2.5 A and 19 W (8/20 µs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.4 IO Capacitance
The capacitance between each IO pin to ground is 0.5-pF (typical) and 0.65-pF (maximum). This device supports
data rates up to 6 Gbps.
7.3.5 Ultra-Low ESD Clamping Voltage
The IO pins feature an ESD clamp that is capable of clamping the voltage to 8.9 V (ITLP = 16 A) and –4.6 V (ITLP
= –16 A).
7.3.6 Low RDYN
The IO pins feature an ESD clamp that has an extremely low RDYN of 0.25 Ω (IO to GND) and 0.18 Ω (GND to
IO) which prevents system damage during ESD events.
Copyright © 2016, Texas Instruments Incorporated
9
TPD1E04U04
ZHCSF81A –MARCH 2016–REVISED APRIL 2016
www.ti.com.cn
Feature Description (continued)
7.3.7 DC Breakdown Voltage
The DC breakdown voltage of each IO pin is a minimum of 5 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of 3.6 V.
7.3.8 Ultra Low Leakage Current
The IO pins feature an ultra-low leakage current of 10 nA (maximum) with a bias of 2.5 V
7.3.9 Supports High Speed Interfaces
This device is capable of supporting high speed interfaces up to 6 Gbps, because of the very low IO capacitance.
7.3.10 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
7.3.11 Easy Flow-Through Routing Package
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers
flow-through routing, requiring minimal modification to an existing layout.
7.4 Device Functional Modes
The TPD1E04U04 is a passive integrated circuit that triggers when voltages are above VBR or below VF. During
ESD events, voltages as high as ±16-kV (air) can be directed to ground via the internal diode network. When the
voltages on the protected line fall below the trigger levels of TPD1E04U04 (usually within 10s of nano-seconds)
the device reverts to passive.
10
Copyright © 2016, Texas Instruments Incorporated
TPD1E04U04
www.ti.com.cn
ZHCSF81A –MARCH 2016–REVISED APRIL 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD1E04U04 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on
high-speed signal lines between a human interface connector and a system. As the current from ESD passes
through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the
protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe level for the protected IC.
8.2 Typical Application
TMDS_D2+
TMDS_D2-
TMDS_D1+
TMDS_D1-
TMDS_D0+
TMDS_D0-
TMDS_CK+
TMDS_CK-
CEC
UTILITY
DDC_CLK
DDC_DAT
HOTPLUG_DET
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
TPD1E04U04 (x8)
GND
TPD1E05U06 (x5)
Copyright © 2016, Texas Instruments Incorporated
Figure 13. HDMI 2.0 ESD Schematic
8.2.1 Design Requirements
For this design example eight TPD1E04U04 devices and five TPD1E05U06 devices are being used in a HDMI
2.0 application. This provides a complete ESD protection scheme.
Given the HDMI 2.0 application, the parameters listed in Table 1 are known.
Table 1. Design Parameters
DESIGN PARAMETER
Signal Range on TMDS Lines
Operating Frequency on TMDS Lines
Signal Range on Control Lines
VALUE
0 V to 3.6 V
up to 3 GHz
0 V to 5.5 V
Copyright © 2016, Texas Instruments Incorporated
11
TPD1E04U04
ZHCSF81A –MARCH 2016–REVISED APRIL 2016
www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The TPD1E04U04 supports signal ranges between 0 V and 3.6 V, which supports the TMDS pairs on the HDMI
2.0 application. The TPD1E05U06 supports signal ranges between 0 V and 5.5 V, which supports the control
lines.
8.2.2.2 Operating Frequency
The TPD1E04U04 has a 0.5-pF (typcal) capacitance, which supports the HDMI 2.0 data rates of 6-Gbps. The
TPD1E05U06 has a 0.5-pF (typical) capacitance as well, which easily supports the control line data rates.
8.2.3 Application Curves
Figure 14. HDMI2.0 6-Gbps TP2 Eye Diagram (Bare Board)
Figure 15. HDMI2.0 6-Gbps TP2 Eye Diagram
(with TPD1E04U04)
12
Copyright © 2016, Texas Instruments Incorporated
TPD1E04U04
www.ti.com.cn
ZHCSF81A –MARCH 2016–REVISED APRIL 2016
9 Power Supply Recommendations
This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended
IO specification (0 V to 3.6 V) to ensure the device functions properly.
10 Layout
10.1 Layout Guidelines
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
版权 © 2016, Texas Instruments Incorporated
13
TPD1E04U04
ZHCSF81A –MARCH 2016–REVISED APRIL 2016
www.ti.com.cn
10.2 Layout Example
[egend
Çop [ꢂyer
Çt51904Ü04 (x8)
Db5
ëL! ꢁo Db5 tlꢂne
Ça5{_52+
Db5
Ça5{_52+
Ça5{_52-
Ça5{_52-
Ça5{_51+
Db5
Db5
Db5
Db5
Db5
Db5
Db5
Ça5{_51+
Ça5{_51-
Ça5{_51-
Ça5{_50+
Db5
Ça5{_50+
Ça5{_50-
Ça5{_50-
Ça5{_/Y+
Db5
Ça5{_/Y+
Ça5{_/Y-
Ça5{_/Y-
/9/
/9/
ÜÇL[LÇò
ÜÇL[LÇò
55/_/[Y
55/_5!Ç
Db5
55/_/[Y
55/_5!Ç
ꢀë_hÜÇ
IhÇt[ÜD_59Ç
ꢀë_{Ütt[ò
IhÇt[ÜD_59Ç
Db5
Çt5190ꢀÜ06 (xꢀ)
Figure 16. HDMI2.0 Type-A Transmitter Port ESD Layout
14
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TPD1E04U04
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ZHCSF81A –MARCH 2016–REVISED APRIL 2016
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档请参见以下部分：
《TPD1E04U04 评估模块用户指南》，SLVUAN8
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏
16
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD1E04U04DPLR
TPD1E04U04DPLT
TPD1E04U04DPYR
TPD1E04U04DPYT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
X2SON
X2SON
X1SON
X1SON
DPL
DPL
DPY
DPY
2
2
2
2
15000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
K
Samples
Samples
Samples
Samples
NIPDAU
K
10000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU Level-1-260C-UNLIM
3K
3K
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jul-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD1E04U04DPLR
TPD1E04U04DPLR
TPD1E04U04DPLT
TPD1E04U04DPLT
TPD1E04U04DPYR
TPD1E04U04DPYT
TPD1E04U04DPYT
X2SON
X2SON
X2SON
X2SON
X1SON
X1SON
X1SON
DPL
DPL
DPL
DPL
DPY
DPY
DPY
2
2
2
2
2
2
2
15000
15000
250
178.0
178.0
178.0
178.0
180.0
180.0
180.0
8.4
9.5
9.5
8.4
9.5
9.5
8.4
0.36
0.39
0.39
0.36
0.66
0.66
0.07
0.66
0.68
0.68
0.66
1.15
1.15
1.1
0.33
0.38
0.38
0.33
0.66
0.66
0.47
2.0
2.0
2.0
2.0
2.0
2.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
250
10000
250
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPD1E04U04DPLR
TPD1E04U04DPLR
TPD1E04U04DPLT
TPD1E04U04DPLT
TPD1E04U04DPYR
TPD1E04U04DPYT
TPD1E04U04DPYT
X2SON
X2SON
X2SON
X2SON
X1SON
X1SON
X1SON
DPL
DPL
DPL
DPL
DPY
DPY
DPY
2
2
2
2
2
2
2
15000
15000
250
205.0
184.0
184.0
205.0
184.0
184.0
203.2
200.0
184.0
184.0
200.0
184.0
184.0
196.8
33.0
19.0
19.0
33.0
19.0
19.0
33.3
250
10000
250
250
Pack Materials-Page 2
PACKAGE OUTLINE
DPY0002A
X1SON - 0.45 mm max height
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.1
0.9
B
A
PIN 1 INDEX AREA
0.7
0.5
0.45
0.30
C
SEATING PLANE
0.08 C
0.05
0.00
0.65
1
2
SYMM
0.55
0.45
2X
0.1
C A B
SYMM
0.3
0.2
2X
0.05
C A B
4224561/B 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.3)
SYMM
1
2
SYMM
2X (0.5)
(R0.05) TYP
(0.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224561/B 03/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DPY0002A
X1SON - 0.45 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0)
2X (0.3)
2X (0.5)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2
1
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224561/B 03/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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