TPD2E2U06QDCKRQ1 [TI]
适用于 USB 和高速接口的汽车类双路 1.5pF、5.5V、±25kV ESD 保护二极管 | DCK | 3 | -40 to 125;
| 型号： | TPD2E2U06QDCKRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 USB 和高速接口的汽车类双路 1.5pF、5.5V、±25kV ESD 保护二极管 | DCK | 3 | -40 to 125 二极管 |
| 文件： | 总24页 (文件大小：1957K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPD2E2U06-Q1
ZHCSD47E –DECEMBER 2014 –REVISED OCTOBER 2022
TPD2E2U06-Q1 汽车类双通道高速ESD 保护器件
1 特性
3 说明
• 符合AEC-Q101 标准
• IEC 61000-4-2 级4 ESD 保护
TPD2E2U06-Q1 是瞬态电压抑制器 (TVS) 静电放电保
护二极管阵列，具有低电容。该双通道 ESD 保护二极
管的额定 ESD 冲击消散值高于 IEC 61000-4-2 国际标
准中规定的最高水平。TPD2E2U06-Q1 具有 1.5pF 线
路电容，非常适合用于保护 USB 2.0、以太网、
LVDS、天线和I2C 等接口。
– ±25kV（接触放电）
– ±30kV（气隙放电）
• ISO 10605（330pF，330Ω）ESD 保护
– ±20kV（接触放电）
– ±25kV（气隙放电）
封装信息(1)
• IO 电容1.5pF（典型值）
• 直流击穿电压为6.5V（最小值）
• 超低漏电流10nA（最大值）
• 低ESD 钳位电压
封装尺寸（标称值）
器件型号
封装
DBZ（SOT23，3） 2.92mm × 1.30mm
TPD2E2U06-Q1
DCK（SC70，3）
2.00mm × 1.25mm
(1) 有关所有的可用封装，请参阅数据表末尾的可订购产品附录。
• 工业温度范围：–40°C 至+125°C
• 易于布线的小型DBZ 和DCK 封装
2 应用
• 终端设备：
– 音响主机
– 后座娱乐系统
– 远程信息处理系统
– 导航模块
– 媒体接口
• 接口：
– USB 2.0
– 以太网™
– 天线
– LVDS
– I2C
Power
Supply
Vbus
D+
D-
TPD2E2U06-Q1
1
2
3
GND
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简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEJ9
TPD2E2U06-Q1
ZHCSD47E –DECEMBER 2014 –REVISED OCTOBER 2022
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Table of Contents
7.4 Device Functional Modes............................................9
8 Application and Implementation..................................10
8.1 Application Information............................................. 10
8.2 Typical Application.................................................... 10
9 Power Supply Recommendations................................11
10 Layout...........................................................................12
10.1 Layout Guidelines................................................... 12
10.2 Layout Example...................................................... 12
11 Device and Documentation Support..........................13
11.1 Documentation Support.......................................... 13
11.2 接收文档更新通知................................................... 13
11.3 支持资源..................................................................13
11.4 Trademarks............................................................. 13
11.5 Electrostatic Discharge Caution..............................13
11.6 术语表..................................................................... 13
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings—AEC Specification...............................4
6.3 ESD Ratings—IEC Specification................................ 4
6.4 ESD Ratings—ISO Specification................................ 4
6.5 Recommended Operating Conditions.........................4
6.6 Thermal Information....................................................5
6.7 Electrical Characteristics.............................................5
6.8 Typical Characteristics................................................6
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................8
Information.................................................................... 13
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (May 2016) to Revision E (October 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Updated the Surge Curve (tp = 8/20 μs) IO to GND figure................................................................................6
Changes from Revision C (March 2016) to Revision D (May 2016)
Page
• 更新了特性、应用和说明.................................................................................................................................. 1
• 更新了ESD 等级- AEC 规格表.........................................................................................................................1
Changes from Revision B (December 2014) to Revision C (March 2016)
Page
• 添加了DCK 封装................................................................................................................................................ 1
• 在热性能信息表中添加了DCK 热性能数据........................................................................................................1
Changes from Revision A (December 2014) to Revision B (December 2014)
Page
• Added temperature specification to VBR TEST CONDITIONS. ......................................................................... 5
Changes from Revision * (December 2014) to Revision A (December 2014)
Page
• 完整文档的初始发行版........................................................................................................................................1
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5 Pin Configuration and Functions
IO1
1
3
GND
IO2
2
图5-1. DBZ Package, 3-Pin SOT23 (Top View)
IO1
1
3
GND
IO2
2
图5-2. DCK Package, 3-Pin SC70 (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
IO1
NO.
1
I/O
I/O
G
The IO1 and IO2 pins are an ESD protected channel. Connect these pins to the data
line as close to the connector as possible.
IO2
2
GND
3
The GND (ground) pin is connected to ground.
(1) I = input, O = output, G = ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
5.5(2)
75(2)
125
UNIT
A
IPP
Peak pulse current (tp = 8/20 μs)
PPP
W
Peak pulse power (tp = 8/20 μs)
TJ
Junction temperature
Storage temperature
°C
–40
–65
Tstg
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Measured at 25°C.
6.2 ESD Ratings—AEC Specification
VALUE
±10000
±1000
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AAEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
UNIT
Contact discharge
Air-gap discharge
±25000
±30000
V(ESD)
Electrostatic discharge
IEC 61000-4-2
V
6.4 ESD Ratings—ISO Specification
VALUE
±20000
±25000
UNIT
Contact discharge
Air-gap discharge
V(ESD)
Electrostatic discharge
V
ISO 10605 (330 pF, 330 Ω)
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
MAX
5.5
UNIT
V
VIO
TA
Input pin voltage
Operating free air temperature
125
–40
℃
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6.6 Thermal Information
TPD2E2U06-Q1
THERMAL METRIC(1)
DBZ (SOT23)
3 PINS
439.5
DCK (SC70)
3 PINS
308.3
170.7
89.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
194.9
173.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
53.7
34.2
ψJT
172
88.6
ψJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VRWM
Reverse stand-off voltage
IIO < 10 µA
5.5
V
IPP = 1 A, TLP(1) (3)
IPP = 5 A, TLP(1) (3)
IPP = 1 A, TLP(1) (3)
IPP = 5 A, TLP(1) (3)
IO to GND(2) (3)
9.7
12.4
1.9
4
VCLAMP
IO to GND
GND to IO
V
V
VCLAMP
0.6
0.4
1.5
0.02
RDYN
Dynamic resistance
Line capacitance
Ω
GND to IO(2) (3)
CL
f = 1 MHz, VBIAS = 2.5 V(3)
1.9
pF
pF
Channel-to-channel input
capacitance
Pin 3 = 0 V, f = 1 MHz, VBIAS = 2.5 V, between
channel pins(3)
0.03
CCROSS
Variation of channel input
capacitance
Pin 3 = 0 V, f = 1 MHz, VBIAS = 2.5 V,
Pin 1 to GND –Pin 2 to GND(3)
0.03
0.1
pF
∆
CL
VBR
Break-down voltage
Leakage current
IIO = 1 mA(3)
6.5
8.5
10
V
ILEAK
VIO = 2.5 V
1
nA
(1) Transmission Line Pulse with 10-ns rise time, 100-ns width.
(2) Extraction of RDYN Using least squares fit of TLP characteristics between I = 20 A and I = 30 A.
(3) Measured at 25°C.
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6.8 Typical Characteristics
Measured at TA = 25°C unless otherwise specified
30
25
20
15
10
5
30
25
20
15
10
5
0
0
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
Voltage (V)
Voltage (V)
C001
C002
图6-1. TLP, Data to GND
图6-2. TLP, GND to Data
120
105
90
15
0
œ15
75
œ30
60
œ45
45
œ60
30
œ75
15
œ90
0
œ105
œ120
œ15
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
Time (ns)
Time (ns)
C003
C004
图6-3. IEC 61000-4-2 Clamping Voltage, 8-kV Contact
图6-4. IEC 61000-4-2 Clamping Voltage, –8-kV Contact
0.001
500
400
300
200
100
0
0.0005
0
-0.0005
-0.001
10
35
60
85
110
135
0
1
2
3
4
5
6
7
8
9
10
œ40
œ15
œ2 œ1
Temperature (°C)
Voltage (V)
C006
C005
图6-6. ILEAK vs Temperature, VIN = 2.5 V
图6-5. IV Curve, TA = 25°C
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6.8 Typical Characteristics (continued)
Measured at TA = 25°C unless otherwise specified
7
6
5
4
3
2
1
0
105
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
Current
Power
90
75
60
45
30
15
0
0
10
20
30
Time (s)
40
50
60
70
0
1
2
3
4
5
Voltage (V)
C007
图6-8. Surge Curve (tp = 8/20 μs) IO to GND
图6-7. Capacitance Across VBIAS f = 1 MHz
0
œ3
œ6
œ9
œ12
œ15
œ18
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
Frequency (Hz)
C009
图6-9. Insertion Loss
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7 Detailed Description
7.1 Overview
The TPD2E2U06-Q1 device is a TVS ESD protection diode array with low capacitance. It is rated to dissipate
ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard. The 1.5-pF line
capacitance makes it ideal for protecting interfaces such as USB 2.0, LVDS, antenna, and I2C.
7.2 Functional Block Diagram
IO1
IO2
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
The TPD2E2U06-Q1 device is a TVS ESD protection diode array with low capacitance. It is rated to dissipate
ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard. The 1.5-pF line
capacitance makes it ideal for protecting interfaces such as USB 2.0, LVDS, antenna, and I2C.
7.3.1 AEC-Q101 Qualified
This device is qualified to AEC-Q101 standards. It passes HBM H3B (±8 kV) and CDM C5 (±1 kV) ESD ratings
and is qualified to operate from –40°C to +125°C.
7.3.2 IEC 61000-4-2 Level 4
The I/O pins can withstand ESD events up to ±25-kV contact and ±30-kV air. An ESD-surge clamp diverts the
current to ground.
7.3.3 IO Capacitance
The capacitance between each I/O pin to ground is 1.5 pF. These capacitances support data rates in excess of
1.5 Gbps.
7.3.4 DC Breakdown Voltage
The DC breakdown voltage of each I/O pin is a minimum of 6.5 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of 5.5 V.
7.3.5 Ultra-Low Leakage Current
The I/O pins feature an ultra-low leakage current of 10 nA (Maximum) with a bias of 2.5 V.
7.3.6 Low ESD Clamping Voltage
The I/O pins feature an ESD clamp that is capable of clamping the voltage to 9.7 V (IPP = 1 A).
7.3.7 Industrial Temperature Range
This device is designed to operate from –40°C to +125°C.
7.3.8 Small Easy-to-Route Packages
The layout of this device makes it simple and easy to add protection to an existing layout. The packages offer
flow-through routing, requiring minimal modification to an existing layout.
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7.4 Device Functional Modes
The TPD2E2U06-Q1 device is a passive integrated circuit that triggers when voltages are above VBR or below
the lower diodes Vf (–0.6 V). During ESD events, voltages as high as ±30 kV (air) can be directed to ground
through the internal diode network. When the voltages on the protected line fall below the trigger levels of the
TPD2E2U06-Q1 (usually within 10s of nano-seconds) the device reverts to passive.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPD2E2U06-Q1 device is a diode type TVS which is typically used to provide a path to ground for
dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the
current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the
voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a safe
level for the protected IC.
8.2 Typical Application
Power
Supply
Vbus
D+
D-
TPD2E2U06-Q1
1
2
3
GND
Copyright © 2016, Texas Instruments Incorporated
图8-1. Typical USB Application Diagram
8.2.1 Design Requirements
For this design example, one TPD2E2U06-Q1 device will be used in a USB 2.0 application. This will provide
complete port protection.
Given the USB 2.0 application, the parameters listed in 表8-1 are known.
表8-1. Design Parameters
DESIGN PARAMETER
Signal range on pins 1 or 2
Operating frequency
VALUE
0 V to 3.3 V
240 MHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Signal Range
The TPD2E2U06-Q1 device has 2 identical protection channels for signal lines. The symmetry of the device
provides flexibility when selecting which of the 2 I/O channels will protect which signal lines. Any I/O will support
a signal range of 0 to 5.5 V.
8.2.2.2 Operating Frequency
The TPD2E2U06-Q1 device has a capacitance of 1.5 pF (typical), supporting USB 2.0 data rates.
8.2.3 Application Curve
1
0
œ1
œ2
œ3
œ4
œ5
œ6
œ7
œ8
œ9
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
Frequency (Hz)
C010
图8-2. Insertion Loss Graph
9 Power Supply Recommendations
This device is a passive ESD protection device and there is no need to power it. Make sure that the maximum
voltage specifications for each line are not violated.
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10 Layout
10.1 Layout Guidelines
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
This application is typical of a differential data pair application, such as USB 2.0.
IO1
GND
IO2
= VIA to GND
图10-1. Routing with DBZ Package
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Reading and Understanding an ESD Protection Data Sheet application report
• Texas Instruments, ESD Protection Layout Guide application report
• Texas Instruments, TPD4E02B04EVM user's guide
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
以太网™ is a trademark of Fuji Xerox Co., Ltd.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD2E2U06QDBZRQ1
TPD2E2U06QDCKRQ1
ACTIVE
ACTIVE
SOT-23
SC70
DBZ
DCK
3
3
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
22U6Q
11X
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
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Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
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lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2021
OTHER QUALIFIED VERSIONS OF TPD2E2U06-Q1 :
Catalog : TPD2E2U06
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD2E2U06QDBZRQ1 SOT-23
TPD2E2U06QDCKRQ1 SC70
DBZ
DCK
3
3
3000
3000
180.0
178.0
8.4
9.0
3.15
2.4
2.77
2.5
1.22
1.2
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPD2E2U06QDBZRQ1
TPD2E2U06QDCKRQ1
SOT-23
SC70
DBZ
DCK
3
3
3000
3000
213.0
180.0
191.0
180.0
35.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0003A
SOT-SC70 - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR SC70
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
0.65
1.3
2.15
1.85
3
0.30
3X
0.15
C A B
0.1
0.0
0.1
(0.9)
TYP
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
TYP
TYP
0
SEATING PLANE
4220745/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0003A
SOT-SC70 - 1.1 max height
SMALL OUTLINE TRANSISTOR SC70
PKG
3X (0.95)
3X (0.4)
1
SYMM
3
(1.3)
(0.65)
2
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220745/C 06/2021
NOTES: (continued)
3. Publication IPC-7351 may have alternate designs.
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0003A
SOT-SC70 - 1.1 max height
SMALL OUTLINE TRANSISTOR SC70
PKG
3X (0.95)
3X (0.4)
1
SYMM
3
(1.3)
(0.65)
2
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4220745/C 06/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
6. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.12 MAX
1.4
1.2
B
A
0.1 C
PIN 1
INDEX AREA
1
0.95
(0.125)
3.04
2.80
1.9
3
(0.15)
NOTE 4
2
0.5
0.3
3X
0.10
0.01
(0.95)
TYP
0.2
C A B
0.25
GAGE PLANE
0.20
0.08
TYP
0.6
0.2
TYP
SEATING PLANE
0 -8 TYP
4214838/D 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214838/D 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/D 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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