TPD2S701QDGSRQ1 [TI]
Automotive USB D+/D- short-to-VBUS and IEC ESD protection | DGS | 10 | -40 to 125;型号: | TPD2S701QDGSRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | Automotive USB D+/D- short-to-VBUS and IEC ESD protection | DGS | 10 | -40 to 125 光电二极管 接口集成电路 |
文件: | 总33页 (文件大小:2617K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPD2S701-Q1
ZHCSGF6A –APRIL 2017–REVISED JULY 2017
TPD2S701-Q1 汽车类 USB 双通道数据线路 VBUS 短路保护和 IEC ESD 保
护
1 特性
在这些引脚上,此器件可实现直流电高达 7V 的过压保
护。这为 USB VBUS 轨的数据线路短路提供了充分保
护。该过压保护电路提供业界最可靠的 VBUS 短路隔
离,能在 200ns 内关闭数据开关,并保护上游电路免
受有害电压和电流尖峰影响。
1
•
符合 AEC-Q100 标准
–40°C 至 125°C 的工作温度范围
–
•
•
VD+ 和 VD– 上的 VBUS 短路保护
ESD 性能 VD+,VD–
–
±8kV 接触放电(IEC 61000-4-2 和 ISO 10605
330pF,330Ω)
此外,TPD2S701-Q1 只需要 5V 的单一电源,这优化
了电源树的大小和成本。该器件允许通过电阻分压器网
络调整 OVP 阈值和钳位电路,为优化系统保护提供了
一种简单且经济高效的方法(适用于任何收发器)。
TPD2S701-Q1 还包括一个 FLT 引脚,该引脚会在器
件出现过压状况时发出指示,并在过压状况消除后自动
复位。
–
±15kV 气隙放电(IEC 61000-4-2 和 ISO
10605 330pF,330Ω)
•
•
•
•
•
•
•
高速数据开关(1GHz 带宽)
只需要 5V 电源
可调节 OVP 阈值
快速过压响应时间(典型值 200ns)
热关断特性
TPD2S701-Q1 还在 VD+ 和 VD– 引脚上集成了系统级
别的 IEC 61000-4-2 和 ISO 10605 ESD 钳位,因此在
应用中无需再配置高压、低电容的外部 TVS 钳位电
路。
集成输入使能和故障输出信号
保证数据完整性的直通路由
–
–
10 引脚 VSSOP 封装 (3mm × 3mm)
10 引脚 QFN 封装 (2.5mm × 2.5mm)
器件信息(1)
器件型号
封装
VSSOP (10)
QFN (10)
封装尺寸(标称值)
3.00mm × 3.00mm
2.50mm x 2.50mm
2 应用
TPD2S701-Q1
•
终端设备
–
–
–
–
–
–
音响主机
(1) 要了解所有可用封装,请参见产品说明书末尾的可订购产品附
录。
后座娱乐系统
远程信息处理
USB 集线器
导航模块
功能框图
VPWR
媒体接口
VREF
•
接口
MODE
Control Logic
FLT
–
–
USB 2.0
USB 3.0
EN
Overvoltage
Protection
3 说明
VD+
VD-
D+
D-
TPD2S701-Q1 是一款用于汽车高速接口(如 USB
2.0)的双通道线路 VBUS 短路和 IEC61000-4-2 ESD
保护器件。TPD2S701-Q1 包含两个数据线路 nFET 开
关。这些开关通过提供业界一流的带宽,实现最小的信
号衰减,同时可保护内部系统电路(在 VD+ 和 VD–
引脚上),使其免受过压情况的损坏,从而确保安全的
数据通信。
ESD
Clamps
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEY0
TPD2S701-Q1
ZHCSGF6A –APRIL 2017–REVISED JULY 2017
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史................................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings—AEC Specification ............................. 4
6.3 ESD Ratings—IEC Specification .............................. 4
6.4 ESD Ratings—ISO Specification .............................. 4
6.5 Recommended Operating Conditions....................... 5
6.6 Thermal Information.................................................. 5
6.7 Electrical Characteristics........................................... 6
9
10 Power Supply Recommendations ..................... 21
10.1 VPWR Path............................................................. 21
10.2 VREF Pin ................................................................ 21
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 22
12 器件和文档支持 ..................................................... 23
12.1 文档支持................................................................ 23
12.2 接收文档更新通知 ................................................. 23
12.3 社区资源................................................................ 23
12.4 商标....................................................................... 23
12.5 静电放电警告......................................................... 23
12.6 Glossary................................................................ 23
13 机械、封装和可订购信息....................................... 24
6.8 Power Supply and Supply Current Consumption
Chracteristics ............................................................. 7
6.9 Timing Requirements................................................ 8
6.10 Typical Characteristics.......................................... 10
Parameter Measurement Information ................ 14
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
7
8
4 修订历史
Changes from Original (April 2017) to Revision A
Page
•
Updated 图 19 ..................................................................................................................................................................... 14
2
Copyright © 2017, Texas Instruments Incorporated
TPD2S701-Q1
www.ti.com.cn
ZHCSGF6A –APRIL 2017–REVISED JULY 2017
5 Pin Configuration and Functions
DGS Package
10-Pin SSOP
Top View
DSK Package
10-Pin QFN
Top View
VD-
VD+
GND
FLT
1
2
3
4
5
10
9
D-
VD-
VD+
GND
FLT
1
2
3
4
5
10
9
D-
D+
D+
8
VREF
VPWR
MODE
Thermal
Pad
8
VREF
VPWR
MODE
7
7
EN
6
EN
6
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
High voltage D– USB data line, connect to USB connector D+, D– IEC61000-4-2 ESD
protection
1
VD–
I/O
I/O
High voltage D+ USB data line, connect to USB connector D+, D– IEC61000-4-2 ESD
protection
2
VD+
3
4
GND
FLT
Ground
O
Ground pin for internal circuits and IEC ESD clamps
Open-drain fault pin. See 表 1
Enable active-low input. Drive EN low to enable the switches. Drive EN high to disable the
switches. See 表 1 for mode selection
5
EN
I
Selects between device modes. See the Detailed Description section. Acts as LDO reference
voltage for mode 1
6
7
8
MODE
VPWR
VREF
I
I
5-V DC supply input for internal circuits. Connect to internal power rail on PCB
Pin to set OVP threshold. See the Detailed Description section for instructions on how to set
OVP threshold
I/O
9
D+
D–
I/O
I/O
I/O protected low voltage D+ USB data line, connects to transceiver
Protected low voltage D– USB data line, connects to transceiver
10
Copyright © 2017, Texas Instruments Incorporated
3
TPD2S701-Q1
ZHCSGF6A –APRIL 2017–REVISED JULY 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
–0.3
–0.3
MAX
7.7
6
UNIT
V
VPWR
VREF
5-V DC supply voltage for internal circuitry
Pin to set OVP threshold
V
VD+,
VD–
Voltage range from connector-side USB data lines
–0.3
7.7
V
D+, D– Voltage range for internal USB data lines
–0.3
–0.3
–0.3
–0.3
–40
VREF + 0.3
7.7
V
V
VMODE
VFLT
VEN
Voltage on MODE pin
Voltage on FLT pin
7.7
V
Voltage on enable pin
Operating free air temperature(3)
Storage temperature
7.7
V
TA
125
°C
°C
TSTG
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) Thermal limits and power dissipation limits must be observed.
6.2 ESD Ratings—AEC Specification
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1) All pins
All pins besides
±2000
V(ESD)
Electrostatic discharge
±500
±750
V
corners
Charged-device model (CDM), per AEC Q100-011
Corner pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
UNIT
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air-gap discharge
VD+, VD– pins(1)
VD+, VD– pins(1)
±8000
V(ESD)
Electrostatic discharge
V
±15000
(1) See 图 19 for details on system level ESD testing setup.
6.4 ESD Ratings—ISO Specification
VALUE
UNIT
ISO 10605 (330 pF, 330 Ω) contact discharge
(10 strikes)
VD+, VD– pins
VD+, VD– pins
VD+, VD– pins
VD+, VD– pins
VD+, VD– pins
VD+, VD– pins
VD+, VD– pins
±8000
ISO 10605 (330 pF, 330 Ω) air-gap discharge
(10 strikes)
±15000
±8000
ISO 10605 (150 pF, 330 Ω) contact discharge
(10 strikes)
ISO 10605 (150 pF, 330 Ω) air-gap discharge
(10 strikes)
(1)
VESD
Electrostatic discharge
±15000
±8000
V
ISO 10605 (330 pF, 2 kΩ) contact discharge (10
stikes)(2)
ISO 10605 (330 pF, 2 kΩ) air-gap discharge (10
strikes)
±15000
±25000
ISO 10605 (150 pF, 2 kΩ) air-gap discharge (10
discharges)
(1) See 图 19 for details on system level ESD testing setup.
(2) VREF > 3 V.
4
Copyright © 2017, Texas Instruments Incorporated
TPD2S701-Q1
www.ti.com.cn
ZHCSGF6A –APRIL 2017–REVISED JULY 2017
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN TYP
MAX UNIT
VPWR
5-V DC supply voltage for internal circuitry
Mode 0. Voltage range for VREF pin (for setting OVP threshold)
Mode 1. Voltage range for VREF pin (for setting OVP threshold)
Voltage range from connector-side USB data lines
Voltage range for internal USB data lines
Voltage range for enable
4.5
7
3.6
3.8
3.6
3.6
7
V
V
VREF
3
VREF
0.63
V
VD+, VD–
D+, D–
VEN
0
0
0
0
0
V
V
V
VFLT
Voltage range for FLT
7
V
IFLT
Current into open drain FLT pin FET
3
mA
µF
µF
pF
kΩ
kΩ
CVPWR
CVREF
CMODE
RMODE_0
RMODE_1
VPWR capacitance(1)
External Capacitor on VPWR pin
External Capacitor on VREF pin
1
10
1
VREF capacitance
0.3
3
20
Allowed parasitic capacitance on mode pin from PCB and mode 1 external resistors
Resistance to GND to set to mode 0
2
2.6
Resistance to GND to set to mode 1 (calculate parallel combination of RTOP and RBOT
)
14
20
(1) For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin.
Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature
variation. The effective value presented should be within the minimum and maximums listed in the table.
6.6 Thermal Information
TPD2S701-Q1
THERMAL METRIC(1)
DGS (VSSOP)
10 PINS
167.3
56.9
DSK (WSON)
UNIT
10 PINS
61.5
51.3
34
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
87.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.7
1.3
ψJB
86.2
34.3
7.7
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017, Texas Instruments Incorporated
5
TPD2S701-Q1
ZHCSGF6A –APRIL 2017–REVISED JULY 2017
www.ti.com.cn
6.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.5
50
MAX
UNIT
V
MODE 1 ADJUSTABLE VREF
Mode 1 VREF feedback
regulator voltage
Standard mode 1 set-up. EN = 0 V. Once
VREF = 3.3 V, measure voltage on mode pin
VMODE_CMP
VMODE
0.47
0.53
200
Standard mode 1. Remove RTOP and RBOT.
Power up device and wait until start-up time has
passed. Then force 0.53 V on the MODE pin
and measure current into pin
Mode pin mode 1 leakage
current
IMODE_LEAK
IMODE
nA
Informative, test parameters below; accuracy
with RTOP and RBOT as ±1% resistors
VREF_ACCURACY
VREF accuracy
VREF
–8%
3.04
8%
Standard mode 1 set-up. RTOP = 140 kΩ ± 1%,
RBOT = 24.9 kΩ ± 1%. EN = 0. Measure value
of VREF once it settles
VREF_3.3V
Mode 1 VREF set to 3.3 V
VREF
3.31
0.66
3.81
3.58
V
V
V
Standard mode 1 set-up. RTOP = 47.5 kΩ ± 1%,
RBOT = 150 kΩ ± 1%.EN = 0. Measure value of
VREF once it settles
VREF_0.66V
Mode 1 VREF set to 0.66 V
Mode 1 VREF set to 3.8 V
VREF
0.6
3.5
0.72
4.12
Standard mode 1 set-up. RTOP = 165 kΩ ± 1%,
RBOT = 24.9 kΩ ± 1%. EN = 0. Measure value
of VREF once it settles
VREF_3.8V
VREF
EN, FLT PINS
Mode 0. Connect VPWR = 5 V; VREF = 3.3 V;
VD+ = 3.3 V; Set VIH(EN) = 0 V; Sweep VIH
from 0 V to 1.4 V; Measure when D+ drops low
(less than or equal to 5% of 3.3 V) from 3.3 V
High-level input voltage
Low-level input voltage
1.2
VIH
EN
V
Mode 0. Connect VPWR = 5 V; VREF = 3.3 V;
VD+ = 3.3 V. Set VIH(EN) = 3.3 V; Sweep VIH
from 3.3 V to 0.5 V; Measure when D+ rise to
95% of 3.3 V from 0 V
0.8
Mode 0. VPWR = 5 V; VREF = 3.3 V; VI (EN) =
3.3 V ; Measure current into EN pin
IIL
Input leakage current
EN
1
µA
V
Mode 0. Drive the TPS2S701-Q1 in OVP to
assert FLT pin. Source IOL = 1 mA into FLT pin
and measure voltage on FLT pin when asserted
VOL
Low-level output voltage
FLT
0.4
The rising over temperature
protection shutdown threshold
VPWR = 5 V, ENZ = 0 V, TA stepped up until
FLTZ is asserted
TSD_RISING
140
125
150
138
165
150
℃
℃
The falling over temperature
protection shutdown threshold
VPWR = 5 V, ENZ = 0 V, TA stepped down
from TSD_RISING until FLTZ is cleared
TSD_FALLING
The over temperature
protection shutdown threshold
hysteresis
TSD_HYST
TSD_RISING – TSD_FALLING
10
12
15
℃
OVP CIRCUIT—VD±
Mode 1. Set VPWR = 5 V; EN = 0 V; RTOP = 165
kΩ, RBOT = 24.9 kΩ. Connect D± to 40-Ω load.
Increase VD+ or VD– from 4.1 V to 4.9 V.
Measure the value at which FLTZ is asserted
Input overvoltage protection
threshold, VREF > 3.6 V
VOVP_RISING
VD±
4.3
4.5
4.7
V
Mode 1. Set VPWR = 5 V; EN = 0 V; RTOP = 140
kΩ, RBOT = 24.9 kΩ. Increase VD+ or VD– from
3.6 V to 4.6 V. Measure the value at which
FLTZ is asserted. Repeat for RTOP = 39 kΩ,
RBOT = 150 kΩ. Increase VD+ or VD– from 0.6
V to 0.9 V. Measure the value at which FLTZ is
asserted. See the resultant values meet the
equation, and make sure to observe data
switches turnoff.
1.19
×
VREF
1.25
×
VREF
Input overvoltage protection
threshold
1.31 ×
VREF
VOVP_RISING
VD±
VD±
V
Also check for mode 0 when VREF = 3.3 V
Difference between rising and falling OVP
thresholds on VD±
VHYS_OVP
Hysteresis on OVP
25
mV
VOV
P_RI
SING
–
VHYS
_OVP
After collecting each rising OVP threshold,
lower the VD± voltage until you see FLT
deassert. This gives the falling OVP threshold.
Use this value to calculate VHYS_OVP
Input overvoltage protection
threshold
VOVP_FALLING
VD±
VD±
V
Leakage current on VD±
during normal operation
Standard mode 0 or mode 1. Set VD± = 0 V. D±
= floating. Measure current flowing into VD±
µA
IVD_LEAK_0 V
–0.1
0.1
6
Copyright © 2017, Texas Instruments Incorporated
TPD2S701-Q1
www.ti.com.cn
ZHCSGF6A –APRIL 2017–REVISED JULY 2017
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Leakage current on VD±
during normal operation
VD±
VD±
Standard mode 0 or mode 1. Set VD± = 3.6 V.
D± = floating. Measure current flowing into VD±
µA
IVD_LEAK_3.6V
2.5
4
Standard mode 1. RTOP = 140 kΩ ± 1%, RBOT
24.9 kΩ ± 1%. Connect D± to 40-Ω load.
Measure the value at which FLTZ is asserted
=
V
V
Input overvoltage threshold
for VREF = 3.3 V
VOVP_3.3V
3.61
0.72
4.14
0.83
4.67
0.94
VD±
Standard mode 1. RTOP = 47.5 kΩ ± 1%, RBOT
150 kΩ ± 1%. Connect D± to 40-Ω load.
Measure the value at which FLTZ is asserted
=
Input overvoltage threshold
for VREF = 0.66 V
VOVP_0.66V
DATA LINE SWITCHES – VD+ to D+ or VD– to D–
Mode 0 or 1. Set VPWR = 5 V; VREF = 3.3 V; EN
= 0 V; Measure resistance between D+ and
VD+ or D– and VD–, voltage between 0 and 0.4
V
RON
On resistance
4
6.5
1
Ω
Ω
Mode 0 or 1. Set VPWR = 5 V; VREF = 3.3 V; EN
= 0 V; Measure resistance between D+ and
VD+ or D– and VD–, sweep voltage between 0
and 0.4 V. Take difference of resistance at 0.4-
V and 0-V VD± bias
RON(Flat)
On resistance flatness
On bandwidth (–3-dB)
Mode 0 or 1. Set VPWR = 5 V; VREF = 3.3 V; EN
= 0 V; Measure S21 bandwidth from D+ to VD+
or D– to VD– with voltage swing = 400 mVpp,
Vcm = 0.2 V
BWON
960
MHz
6.8 Power Supply and Supply Current Consumption Chracteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Use standard mode 0 set-up. Set EN = 0 V, load D+ to 45
VPWR rising UVLO threshold Ω, VD+ = 3.3 V. Set VPWR = 3.5 V, and step up VPWR until
VUVLO_RISING_
VPWR
3.7
250
2.6
75
3.95
300
2.7
4.2
400
2.9
V
mV
V
90% of VD+ appears on D+
Use standard mode 0 set up. Set EN = 0 V, load D+ to 45
Ω, VD+ = 3.3 V. Set VPWR = 4.3 V, and step down
VUVLO_HYST_V
PWR
VPWR UVLO hysteresis
VPWR until D+ falls to 10% of VD+. This gives
VUVLO_FALLING_VPWR. VUVLO_RISING_VPWR
–
VUVLO_FALLING_VPWR = VUVLO_HYST_VPWR for this unit
Use standard mode 0 set up. Set EN = 0V, load D+ to 45
Ω, VD+ = 3.3 V. Set VREF = 2.5 V, and step up
VREF until 90% of VD+ appears on D+
VUVLO_RISING_ VREF rising UVLO threshold
VREF
in mode 0
Use standard mode 0 set up. Set EN = 0 V, load D+ to 45
Ω, VD+ = 3.3 V. Set VREF = 3 V, and step down
VREF until D+ falls to 10% of VD+. This gives
VUVLO_FALLING_VREF. VUVLO_RISING_VREF
VUVLO_HYST_V
REF
VREF UVLO hysteresis
125
200
mV
–VUVLO_FALLING_VREF = VUVLO_HYST_VREF for this unit
IVPWR_DISABLE VPWR disabled current
Use standard mode 0. EN = 5 V . Measure current into
VPWR
110
110
10
µA
µA
µA
µA
µA
µA
consumption
D_MODE0
IVPWR_DISABLE VPWR disabled current
Use standard mode 1. EN = 5 V. Measure current into
VPWR
consumption
D_MODE1
IVREF_DISABLE VREF disabled current
Use standard mode 0. EN = 5 V. Measure current into
VREF
consumption mode 0
D
VPWR pperating current
IVPWR_MODE0
Use standard mode 0. EN = 0 V. Measure current into
VPWR
250
350
20
consumption
VPWR operating current
IVPWR_MODE1
Use standard mode 1. EN = 0 V. Measure current into
VPWR
consumption
VREF operating current
IVREF
Use standard mode 0. EN = 0 V. Measure current into
VREF
12
22
consumption mode 0
Standard mode 1. 0.1 µF < CVREF < 3 µF. Set-up for
charging to 3.3 V. Use a high voltage capacitor that does
not derate capacitance up the 3.3 V. Measure slope to
calculate the current when CVREF cap is being
ICHG_VREF
VREF fast charge current
mA
charged. Test to check this OPEN LOOP method
Copyright © 2017, Texas Instruments Incorporated
7
TPD2S701-Q1
ZHCSGF6A –APRIL 2017–REVISED JULY 2017
www.ti.com.cn
MAX UNIT
Power Supply and Supply Current Consumption Chracteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
ID_OFF_LEAK_S
TB
Mode 0. Measured flowing into D+ or D– supply, VPWR = 0
V, VD+ or VD– = 18 V, EN = 0 V, VREF = 0 V, D± = 0 V
–1
1
1
µA
ID_ON_LEAK_ST
B
Mode 0. Measured flowing into D+ or D– supply, VPWR = 5
V, VD+ or VD– = 18 V, EN = 0 V, VREF = 3.3 V, D± = 0 V
–1
µA
Mode 0. Measured flowing out of VD+ or VD– supply,
VPWR = 0 V, VD+ or VD– = 18 V, EN = 0 V, VREF = 0 V,
D± = 0 V
IVD_OFF_LEAK_
STB
120
120
Mode 0. Measured flowing out of VD+ or VD– supply,
VPWR = 5 V, VD+ or VD– = 18 V, EN = 0 V, VREF = 3.3 V,
D± = 0 V
IVD_ON_LEAK_S
TB
µA
IVPWR_TO_VRE Leakage from VPWR to
Use standard mode 0. Set VREF = 0 V. Measured
current flowing out of VREF pin
1
1
µA
µA
VREF
F_LEAK
IVREF_TO_VPW Leakage from VREF to
Use standard mode 0. Set VPWR = 0 V. Measured as
current flowing out of VPWR pin
VPWR
R_LEAK
6.9 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
MIN
NOM MAX UNIT
ENABLE PIN AND VREF FAST CHARGE
Time between when 5 V is applied to VPWR, and VREF
TVREF_CHG
VREF fast charge time
reaches VVREF_FAST_CHG. Needs to happen before or at
same time tON_STARTUP completes
0.5
0.5
1
1
ms
ms
Mode 0. EN = 0 V, measured from VPWR and VREF
=
UVLO+ to data FET ON, VPWR comes to UVLO+ second.
Place 3.3 V on VD±. Ramp VREF to 3.3 V, then VPWR
to 5 V and measure the time it takes for D± to reach 90%
of VD±
TON_STARTU Device turnon time from UVLO
P_MODE0
mode 0
Informative. mode 1. EN = 0 V, measured from VPWR
UVLO+ to data FET ON
=
0.5 +
TCHG_C
TON_STARTU Device turnon time from UVLO
ms
ms
µs
mode 1
P_MODE1
VREF
Mode 1. EN = 0 V, measured from VPWR = UVLO+ to
data FET ON, CVREF = 1 µF, VREF_FINAL = 3.3 V.
Measure the time it takes for D± to reach 90% of VD±
TON_STARTU Device turnon time from UVLO
0.6
1
mode 1
P_MODE1_3.3V
Mode 0. VPWR = 5 V, VREF = 3.3 V, time from EN is
asserted until data FET is ON. Place 3.3 V on VD±,
measure the time it takes for D± to reach 90% of VD±
TON_EN_MOD
E0
Device turnon time mode 0
150
Mode 1. VPWR = 5 V, VREF_INITIAL = 0 V, time from EN is
asserted until data FET is ON. Place 3.3 V on VD±,
measure the time it takes for D± to reach 90% of VD±
150 +
TCHG_V
TON_EN_MOD
E1
Device turnon time mode 1
µs
REF
Mode 1. VPWR = 5 V, VREF_INITIAL = 0 V, time from EN is
TON_EN_MOD Device turnon time mode 1 for asserted until data FET is ON. Place 3.3 V on VD±,
300
µs
µs
VREF = 3.3 V
measure the time it takes for D± to reach 90% of
VD±. CVREF = 1 µF, VREF_FINAL = 3.3 V
E1_3.3V
Mode 0 or 1. VPWR = 5 V, VREF = 3.3 V, time from EN is
deasserted until data FET is off. Place 3.3 V on VD±,
measure the time it takes for D± to fall to 10% of
VD±, RD± = 45 Ω
TOFF_EN
Device turnoff time
5
Informative. Mode 1. Time from VREF = 0 V to 80% ×
VREF_FINAL after EN transitions from high to low
(CVREF
× 0.8
(VREF_FI
NAL)/(IC
TCHG_CVREF Time to charge CVREF
s
HG_VREF
)
TCHG_CVREF
_3.3V
Mode 1. Time from VREF = 0 V to 90% × 3.3 V after EN
transitions from high to low, CVREF = 1 µF
Time to charge CVREF to 3.3 V
132
µs
8
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ZHCSGF6A –APRIL 2017–REVISED JULY 2017
Timing Requirements (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM MAX UNIT
Mode 1. Time from VREF = 0 V to 90% × 0.63 V after EN
transitions from high to low, CVREF = 1 µF. RTOP = 47.5
kΩ ± 1%, RBOT = 150 kΩ ± 1%
TCHG_CVREF Time to charge CVREF to 0.66
26
µs
V
_0.66V
OVERVOLTAGE PROTECTION
Mode 0 or 1. Measured from OVP condition to FET turn
off . Short VD± to 5 V and measure the time it takes D±
voltage to reach 0.1 × VD±_CLAMP_MAX from the time the 5-
V hot-plug is applied. RLOAD_D± = 45 Ω.(1) (2)
tOVP_response
_VBUS
OVP response time to VBUS
2
µs
Mode 0 or 1. Measured from OVP condition to FET turn
off . Short VD± to 18 V and measure the time it takes D±
voltage to reach 0.1 × VD±_CLAMP_MAX from the time the
18-V hot-plug is applied. RLOAD_D± = 45 Ω(1) (2)
tOVP_response OVP response time
0.1
1
µs
tOVP_Recov
_FLT
Recovery time FLT pin
Measured from OVP clear to FLT deassertion(1)
32
32
ms
Measured from OVP clear until FET turns back on. Drop
VD+ from 16 V to 3.3 V with VREF = 3.3 V, measure time
it takes for D+ to reach 90% of 3.3 V
tOVP_Recov
_FET
Recovery time for data FET to
turn back on
ms
ms
tOVP_ASSERT FLT assertion time
Measured from OVP on VD+ or VD– to FLT assertion
12.6
18 23.4
(1) Shown in 图 1.
(2) Specified by design, not production tested.
VOVP
VD+/-
/EN
tOVP_OFF
tOVP_Recov
D+/-
/FLT
tOVP_/FLT_ON
tOVP_/FLT_OFF
(1) OVP Operation – VD+, VD–
图 1. TPD2S701-Q1 Timing Diagram
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6.10 Typical Characteristics
100
80
60
40
20
0
60
40
20
0
VD-
D-
VD-
D-
-20
-40
-60
-20
-40
-10
0
10 20 30 40 50 60 70 80 90 100
Time (ns)
-10
0
10 20 30 40 50 60 70 80 90 100
Time (ns)
Fig1
Fig2
图 2. 8-kV IEC 61400-4-2 Contact Waveform
图 3. –8-kV IEC 61400-4-2 Contact Waveform
80
40
20
VD-
D-
VD-
D-
60
40
20
0
0
-20
-40
-60
-80
-20
-40
-60
-10
0
10 20 30 40 50 60 70 80 90 100
Time (ns)
-10
0
10 20 30 40 50 60 70 80 90 100
Time (ns)
Fig3
Fig4
图 4. 8-kV ISO 10605 (330-pF, 330-Ω) Contact Waveform
图 5. –8-kV ISO 10605 (330-pF, 330-Ω) Contact Waveform
6
1
0.8
5
4
3
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
2
/EN
VDê
1
Dê
/FLT
0
-5
0
5
10
15
20
25
-600
-400
-200
0
200
400
600
Voltage (V)
Time (ms)
Fig5
Fig6
图 6. Data Line I-V Curve
图 7. Data Switch Turnon Time
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Typical Characteristics (接下页)
200
200
180
160
140
120
100
80
Diabled
Enabled
180
160
140
120
100
80
60
60
40
40
Disabled
Enabled
20
20
0
0
3
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
80
100 120 140
Bias Voltage (V)
Temperature (èC)
Fig7
Fig8
图 8. VPWR Operating Current vs Bias Voltage
图 9. VPWR Operating Current vs Temperature
(VPWR = 5 V)
6
5.5
5
4.5
4
3.5
3
4.5
4
2.5
2
3.5
3
1.5
1
2.5
2
-40èC
25èC
85èC
125èC
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
Bias Voltage (V)
Bias Voltage (V)
D010
Fig1
图 10. VD± Leakage Current at 7 V Across Temperature
图 11. Data Switch RON vs Bias Voltage
(Enabled)
10.5
9.5
8.5
7.5
6.5
5.5
4.5
3.5
2.5
1.5
0.5
-0.5
13.5
7
6
5
4
3
2
1
0
VD+ V
VD+ I
D+ V
/FLT
VDê
/FLT
12
10.5
9
7.5
6
4.5
3
1.5
0
-1.5
-3
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
5
10
15
20
25
30
35
40
Time (us)
Time (ms)
D011
Fig1
图 12. Data Switch Short-to-5 V Response Waveform
图 13. FLT Assertion Time During OVP
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Typical Characteristics (接下页)
7
0
-1
-2
-3
-4
-5
-6
VDê
/FLT
6
5
4
3
2
1
0
-7
0
10
20
30
40
50
60
70
80
90 100
1E+5
1E+6
1E+7
1E+8
1E+9
5E+9
Time (ms)
Frequency (Hz)
Fig1
D01051
图 15. Data Switch Differential Bandwidth
图 14. FLT Recover Time After OVP Clear
0
-1
-2
-3
-4
-5
-6
-7
1E+5
1E+6
1E+7
1E+8
1E+9
5E+9
Frequency (Hz)
D016
图 16. Data Switch Single-Ended Bandwidth
图 17. USB2.0 Eye Diagram (No TPD2S701-Q1)
12
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Typical Characteristics (接下页)
图 18. USB2.0 Eye Diagram (With TPD2S701-Q1)
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7 Parameter Measurement Information
USB 2.0
CMC
10 nH
10 nH
D-
D+
VD-
45 Ω
VD+
GND
45 Ω
CCLAMP
5V
TPD2S701-Q1
VREF
RTOP
5 V
VPWR
FLT
EN
CPWR
MODE
RBOT
Copyright © 2017, Texas Instruments Incorporated
图 19. ESD Setup
14
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ZHCSGF6A –APRIL 2017–REVISED JULY 2017
8 Detailed Description
8.1 Overview
The TPD2S701-Q1 is a 2-Channel Data Line Short-to-VBUS and IEC61000-4-2 ESD protection device for
automotive high-speed interfaces like USB2.0. The TPD2S701-Q1 contains two data line nFET switches which
ensure safe data communication while protecting the internal system circuits from any overvoltage conditions at
the VD+ and VD– pins. On these pins, this device can handle overvoltage protection up to 7-V DC. This provides
sufficient protection for shorting the data lines to the USB VBUS rail.
Additionally, the TPD2S701-Q1 has a FLT pin which provides an indication when the device sees an overvoltage
condition and automatically resets when the overvoltage condition is removed. The TPD2S701-Q1 also
integrates IEC ESD clamps on the VD+ and VD– pins, thus eliminating the need for external TVS clamp circuits
in the application.
The TPD2S701-Q1 has an internal oscillator and charge pump that controls the turnon of the internal nFET
switches. The internal oscillator controls the timers that enable the charge pump and resets the open-drain FLT
output. If VD+ and VD– are less than VOVP, the internal charge pump is enabled. After an internal delay, the
charge-pump starts-up, turning on the internal nFET switches. At any time, if VD+ or VD– rises above VOVP
,
TPD2S701-Q1 asserts FLT pin LOW and the nFET switches are turned off.
8.2 Functional Block Diagram
VPWR
VREF
MODE
Control Logic
FLT
EN
Overvoltage
Protection
VD+
VD-
D+
D-
ESD
Clamps
GND
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8.3 Feature Description
8.3.1 OVP Operation
When the VD+, or VD– voltages rise above VOVP, the internal nFET switches are turned off, protecting the
transceiver from overvoltage conditions. The response is very rapid, with the FET switches turning off in less
than 1 µs. Before the OVP condition, the FLT pin is High-Z, and is pulled HIGH via an external resistor to
indicate there is no fault. Once the OVP condition occurs, the FLT pin is asserted LOW. When the VD+, or VD–
voltages returns below VOVP – VHYS-OVP, the nFET switches are turned on again. When the OVP condition is
cleared and the nFETs are completely turned on, the FLT is reset to high-Z.
8.3.2 OVP Threshold
5.0 V
4.5 V
4.5
1.875 V
0.9 V
4.0 V
0.375 V
VOVP = 0.75 V
3.6 V
1 / Ratio = 1.25
VREF = 0.6 V
0.15 V
1.5 V
图 20. OVP Threshold
The OVP Threshold VOVP is set by VREF according to 公式 1, 公式 2 and 公式 3.
VOVP = 1.25 ì VREF
(1)
(2)
(3)
VREF Ç 3.6 V
VOVP = 4.5 V for VREF > 3.6 V
公式 1, 公式 2 and 公式 3 yield the typical VOVP values. See the parametric tables for the minimum and maximum
values that include variation over temperature and process. 图 20 gives a graphical representation of the
relationship between VOVP and VREF
.
VREF can be set either by an external regulator (Mode 0) or an internal adjustable regulator (Mode 1). See the
VREF Operation section for more details on how to operate VREF in Mode 0 and Mode 1.
8.3.3 D± Clamping Voltage
The TPD2S701-Q1 provides a differentiated device architecture which allows the system designer to control the
clamping voltage the protected transceiver sees from the D+ and D– pins. This architecture allows the system
designer to minimize the amount of stress the transceiver sees during ESD events. The clamping voltage that
appears on the D+ and D– lines during an ESD event obeys 公式 4.
VCLAMP _ DP / M = VREF + VBR + IRDYN
(4)
16
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Feature Description (接下页)
Where VBR approximately = 0.7 V, IRDYN approximately = 1 V. By adjusting VREF, the clamping voltage of the D+
and D– lines can be adjusted. As VREF also controls the OVP threshold, take care to insure that the VREF setting
both satisfies the OVP threshold requirements while simultaneously optimizing system protection on the D+ and
D– lines.
The size of the capacitor used on the VREF pin also influences the clamping voltage as transient currents during
ESD events flow into the VREF capacitor. This causes the VREF voltage to increase, and likewise the clamping
voltage on D± according to 公式 4. The larger capacitor that is used, the better the clamping performance of the
device is going to be. See the parametric tables for the clamping performance of the TPD2S701-Q1 with a 1-µF
capacitor.
8.4 Device Functional Modes
The TPD2S701-Q1 has two modes of operation which vary the way the VREF pin functions. In Mode 0, the
VREF pin is connected to an external regulator which sets the voltage on the VREF pin. In Mode 1, the
TPD2S701-Q1 uses an adjustable internal regulator to set the VREF voltage. Mode 1 enables the system
designer to operate the TPD2S701-Q1 with a single power supply, and have the flexibility to easily set the VREF
voltage to any voltage between 0.6 V and 3.8 V with two external resistors.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPD2S701-Q1 offers 2-channels of short-to-VBUS protection and IEC ESD protection for automotive high
speed interfaces such as USB 2.0. For the overvoltage protection (OVP), this device integrates N-channel FET’s
which quickly isolate (200 ns) the protected circuitry in the event of an overvoltage condition on the VD+ and
VD– lines. With respect to the ESD protection, the TPD2S701-Q1 has an internal clamping diode on each data
line (VD+ and VD–) which provides 8-kV contact ESD protection and 15-kV air-gap ESD protection. More details
on the internal components of the TPD2S701-Q1 can be found in the Overview section.
The TPD2S701-Q1 also has the ability to vary the OVP threshold based on the configuration of the Mode pin and
the voltage present on the VREF pin (0.6 V-4.5 V). This functionality is discussed in greater depth in the OVP
Threshold section. Once the VREF threshold is crossed, a fault is detectable to the user through the FLT pin,
where 5 V on the pin indicates no fault is detected, and 0 V-0.4 V represents a fault condition. 图 21 shows the
TPD2S701-Q1 in a typical application, interfacing between the protected internal circuitry and the connector side,
where ESD vulnerability is at its highest.
9.2 Typical Application
VBAT
DC/DC
SW
RSENSE
VOUT
VIN
FB
Sens+
Sens-
VBUS
Dœ
TPD2S701-Q1
D-
D+
VD-
VD+
GND
/FLT
Transciever
D+
CCLAMP
VREF
GND
RTOP
VPWR
5 V
CPWR
MODE
/EN
RBOT
DSK Package
(2.5mm x 2.5mm x 0.75mm)
/opyright © 2017, Çexas Lnstruments Lncorporated
图 21. USB 2.0 Port With Short-to-VBUS and IEC ESD Protection
18
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ZHCSGF6A –APRIL 2017–REVISED JULY 2017
Typical Application (接下页)
9.2.1 Design Requirements
9.2.1.1 Device Operation
表 1 gives the complete device functionality in response to the EN pin, to overvoltage conditions at the connector
(VD± pins), to thermal shutdown, and to the conditions of the VPWR, VREF, and MODE pins.
表 1. Device Operation Table
Functional Mode EN
NORMAL OPERATION
MODE
VREF
VPWR
VD±
TJ
FLT
Comments
Mode 0
X
Device unpowered, data
switches open
R
bot ≤ 2.6 kΩ
bot ≤ 2.6 kΩ
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
unpowered 1
Mode 0
X
Device unpowered, data
switches open
R
X
X
unpowered 2
Mode 1
X
Device unpowered, data
switches open
Rtop | | Rbot > 14 kΩ
bot ≤ 2.6 kΩ
Rtop | | Rbot > 14 kΩ
X
X
unpowered
Device disabled, data switches
open
Mode 0 disabled
Mode 1 disabled
H
H
R
>UVLO
>UVLO
>UVLO
<TSD
<TSD
Set by Rtop
and Rbot
Device disabled, data switches
open, VREF is disabled
Device enabled, data switches
closed, VREF is the value set
by the power supply on VREF
Mode 0 enabled
Mode 1 enabled
L
L
R
bot ≤ 2.6 kΩ
>UVLO
>UVLO
>UVLO
<OVP
<OVP
<TSD
<TSD
H
H
Device enabled, data switches
closed, VREF is the value set
by the Rtop and Rbot resistor
divider
Set by Rtop
and Rbot
Rtop | | Rbot > 14 kΩ
FAULT CONDITIONS
Thermal shutdown, data
switches opened, FLT pin
asserted
Mode 0 thermal
X
R
bot ≤ 2.6 kΩ
X
>UVLO
>UVLO
X
X
>TSD
>TSD
L
L
shutdown
Thermal shutdown, data
switches opened, VREF is
disabled, FLT pin asserted
Mode 1 thermal
shutdown
Set by Rtop
and Rbot
X
L
Rtop | | Rbot > 14 kΩ
Data line overvoltage
protection mode. OVP is set
relative to the voltage on VREF
Data switches opened, FLT
pin asserted
Mode 0 OVP fault
Mode 1 OVP fault
Rbot ≤ 2.6 kΩ
>UVLO
>UVLO
>UVLO
>OVP
>OVP
<TSD
<TSD
L
L
.
Data line overvoltage
protection mode. OVP is set
relative to the voltage on VREF
Data switches opened, fault
pin asserted
Set by Rtop
and Rbot
L
Rtop | | Rbot > 14 kΩ
.
9.2.2 Detailed Design Procedure
9.2.2.1 VREF Operation
The TPD2S701-Q1 has two modes of operation which vary the way the VREF pin functions. In Mode 0, the VREF
pin is connected to an external regulator which sets the voltage on the VREF pin. In Mode 1, the TPD2S701-Q1
uses an adjustable internal regulator to set the VREF voltage. Mode 1 enables the system designer to operate the
TPD2S701-Q1 with a single power supply, and have the flexibility to easily set the VREF voltage to any voltage
between 0.6 V and 3.8 V with two external resistors.
9.2.2.1.1 Mode 0
To set the device into Mode 0, ensure that Rbot, resistance between the MODE pin and ground, is less than 2.6
kΩ. The easiest way to implement Mode 0 is to directly connect the mode pin to GND on your PCB. With this
resistance condition met, connect VREF to an external regulator to set the VREF voltage.
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9.2.2.1.2 Mode 1
To operate in Mode 1, ensure that Rtop || Rbot, resistance between the MODE pin and ground, is greater than 14
kΩ. This is accomplished by insuring Rtop || Rbot > 14 kΩ because when the device is initially powered up, VREF is
at ground until the internal circuitry recognizes if the device is in Mode 1 or Mode 2.
In Mode 1, VREF is set by using an internal regulator to set the voltage. Using a resistor divider off of a feedback
comparator is how to set VREF, similar to a standard LDO or DC/DC. VREF is set in Mode 1 according to 公式 5.
VMODE RTOP + RBOT
(
)
VREF =
RBOT
(5)
公式 5 yields the typical value for VREF. When using ±1% resistors RTOP and RBOT, VREF accuracy is going to be
±5%. Therefore, the minimum and maximum values for VREF can be calculated off of the typical VREF. The
parametric tables above give example RTOP and RBOT resistors to use for standard output VREF voltages for Mode
1.
9.2.2.2 Mode 1 Enable Timing
In Mode 1, when the TPD2S701-Q1 is disabled, the output regulator is disabled, leading VREF to discharge to 0 V
through RTOP and RBOT. It is desired for VREF to be at 0 V when the device is disabled to minimize the clamping
voltage during a power disabled ESD event. If VREF is at 0 V, this holds D± near ground during these fault
events.
When enabling the TPD2S701-Q1, VREF is quickly charged up to insure a quick turnon time of the Data FETs.
Data FET turnon is gated by VREF reaching 80% of its final voltage plus 150 µs to insure a proper OVP threshold
is set before passing data. This prevents false OVPs due to normal operation. Because Data FET turnon is gated
by charging the VREF clamping capacitor, the size of the capacitor influences the turnon time of the Data
switches. The TPD2S701-Q1’s internal regulator uses a constant current source to quickly charge the VREF
clamping capacitor, so the charging time of CVREF can easily be calculated with 公式 6.
CVREF ì0.8 VREFFINAL
(
)
tCHG _ CVREF =
ICHG _ VREF
(6)
Where CVREF is the clamping capacitance on VREF, VREFFINAL is the final value VREF is set to, and ICHG_VREF = 22
mA (typical). If VREF = 1 V, 0.8 is used in the above equation because 80% of VREF is the amount of time that
gates the turnon of the Data FETs. Once tCHG_CVREF is calculated, the typical turnon time of the Data FETs can
be calculated from 公式 7.
tON_EN_MODE1 = tCHG_CVREF + 150 ms
(7)
20
版权 © 2017, Texas Instruments Incorporated
TPD2S701-Q1
www.ti.com.cn
ZHCSGF6A –APRIL 2017–REVISED JULY 2017
9.2.3 Application Curves
图 23. USB2.0 Eye Diagram (System from Typical
图 22. USB2.0 Eye Diagram (Board Only, Through Path)
Application Schematic)
10 Power Supply Recommendations
10.1 VPWR Path
The VPWR pin provides power to the TPD2S701-Q1. A 10-μF capacitor is recommended on VPWR as close to the
pin as possible for localized decoupling of transients. A supply voltage above the UVLO threshold for VPWR must
be supplied for the device to power on.
10.2 VREF Pin
The VREF pin provides a voltage reference for the data switch OVP level as well as a bypass for ESD clamping. A
1-μF capacitor must be placed as close to the pin as possible and the supply must be set to be above the UVLO
threshold for VREF
.
版权 © 2017, Texas Instruments Incorporated
21
TPD2S701-Q1
ZHCSGF6A –APRIL 2017–REVISED JULY 2017
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
Proper routing and placement maintains signal integrity for high-speed signals. The following guidelines apply to
the TPD2S701-Q1:
•
Place the bypass capacitors as close as possible to the VPWR and VREF pins. Capacitors must be attached
to a solid ground. This minimizes voltage disturbances during transient events such as ESD or overcurrent
conditions.
•
High speed traces (data switch path) must be routed as straight as possible and any sharp bends must be
minimized.
Standard ESD recommendations apply to the VD+, VD- pins as well:
•
The optimum placement is as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
TPS2S701-Q1
图 24. TPD2S701-Q1 Layout
22
版权 © 2017, Texas Instruments Incorporated
TPD2S701-Q1
www.ti.com.cn
ZHCSGF6A –APRIL 2017–REVISED JULY 2017
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档:
《TPD2S701-Q1 评估模块用户指南》
12.2 接收文档更新通知
要接收文档更新通知,请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我 进行注册,即可收到任意产
品信息更改每周摘要。有关更改的详细信息,请查看任意已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2017, Texas Instruments Incorporated
23
TPD2S701-Q1
ZHCSGF6A –APRIL 2017–REVISED JULY 2017
www.ti.com.cn
13 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时,我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本,请参见左侧的导航栏。
24
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD2S701QDGSRQ1
TPD2S701QDSKRQ1
ACTIVE
ACTIVE
VSSOP
SON
DGS
DSK
10
10
2500 RoHS & Green
3000 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
15R
14H
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD2S701QDGSRQ1
TPD2S701QDSKRQ1
VSSOP
SON
DGS
DSK
10
10
2500
3000
330.0
180.0
12.4
8.4
5.3
2.8
3.4
2.8
1.4
1.0
8.0
4.0
12.0
8.0
Q1
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPD2S701QDGSRQ1
TPD2S701QDSKRQ1
VSSOP
SON
DGS
DSK
10
10
2500
3000
366.0
210.0
364.0
185.0
50.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSK 10
2.5 x 2.5 mm, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225304/A
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Copyright © 2023,德州仪器 (TI) 公司
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