TPD3S714-Q1 [TI]
汽车类 USB 0.55A 固定电流限制和 VBUS/D+/D- VBATT 短路保护;
| 型号： | TPD3S714-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 USB 0.55A 固定电流限制和 VBUS/D+/D- VBATT 短路保护 |
| 文件： | 总33页 (文件大小：3536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPD3S714-Q1
ZHCSEZ9C – JANUARY 2016 – REVISED AUGUST 2020
具有电池短路和其他短路保护功能的 TPD3S714-Q1 汽车 USB 2.0 接口保护器件
1 项目符号
3 说明
•
符合 AEC-Q100 标准（1 级）
– 工作温度范围：–40°C 至 +125°C
提供功能安全
TPD3S714-Q1 是一款单芯片解决方案，可为汽车
USB 集线器、音响主机、后座娱乐系统、远程信息处
理和媒体接口应用中 USB 连接器的 VBUS 和数据线路
提供电池短路保护、短路保护以及 ESD 保护。集成的
数据开关提供了出色的带宽，能够在 USB 发生电池短
路时更大限度地减少信号衰减。高达 1GHz 的带宽可
利用汽车 USB 环境中常见的长系留线缆来实现干净的
USB 2.0 高速 (480Mbps) 眼图。
•
– 可帮助进行功能安全系统设计的文档
• VBUS_CON 引脚上具有电池短路保护（高达 18V）
和接地短路保护
• VD+ 和 VD– 引脚上具有电池短路保护（高达
18V）和 VBUS 短路保护
•
在 VBUS_CON、VD+ 和 VD– 上提供
IEC 61000-4-2 ESD 保护
– ±8kV 接触放电
电 池 短 路 保 护 可 隔 离 内 部 系 统 电 路 ， 防 止 其 受 到
V
BUS_CON、VD+ 和 VD– 引脚上任何过压情况的影
响。在这些引脚上，TPD3S714-Q1 能够针对热插拔和
直流事件处理高达 18V 的过压情况。过压保护电路可
提供业界最可靠的电池短路隔离，能够关闭开关并保护
上 游 收 发 器 免 受 有 害 电 压 和 电 流 尖 峰 的 影 响 。
VBUS_CON 引脚还提供了一个最高限值为 0.5A 的精确
限流负载开关。过流保护会自动限制电流，以便在发生
接地短路时防止上游电源轨发生压降。此外，该器件还
在 VBUS_CON、VD+ 和 VD– 引脚上集成了系统级 IEC
61000-4-2 和 ISO 10605 ESD 保护功能，无需使用高
电压、低容值的外部 ESD 二极管
– ±15kV 气隙放电
• VBUS_CON、VD+ 和 VD– 引脚上具有 ISO 10605
330pF、330Ω ESD 保护
– ±8kV 接触放电
– ±15kV 气隙放电
•
•
•
低 RON nFET VBUS 开关（典型值为 63mΩ）
高速数据开关（–3dB 时的带宽为 1GHz）
断续电流限制
– 550mA 过流限制（最小值）
快速过压响应时间
器件信息 (1)
•
封装尺寸（标称值）
器件型号
封装
SSOP (16)
– 2µs 典型值（VBUS 开关）
– 200ns 典型值（数据开关）
集成输入使能，适用于 VBUS、VD+ 和 VD–
故障输出信号
TPD3S714-Q1
4.90mm × 3.90mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
•
5 V
热关断特性
VBUS_SYS
VBUS_CON
VBUS
100 µF
7 V
1 µF
100 V
X7R
10 kΩ
• 16 引脚 SSOP 封装 (4.9mm × 3.9mm)
FLT
USB
Transceiver
Dœ
Dœ
VDt
VD+
GND
2 应用
10 nH
10 nH
D+
D+
EN
USB2.0
CMC
•
终端设备
From Processor
3.3 V
GND
– 音响主机
– 后座娱乐系统
– 远程信息处理
– USB 集线器
– 导航模块
– 媒体接口
接口
VIN
TPD3S714-Q1
1 µF
7 V
Copyright © 2016, Texas Instruments Incorporated
典型应用原理图
•
– USB 2.0
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSCG4
TPD3S714-Q1
ZHCSEZ9C – JANUARY 2016 – REVISED AUGUST 2020
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................16
9 Application and Implementation..................................17
9.1 Application Information............................................. 17
9.2 Typical Application.................................................... 17
10 Power Supply Recommendations..............................20
10.1 VBUS Path................................................................20
10.2 VIN Pin.....................................................................20
11 Layout...........................................................................21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Documentation Support.......................................... 22
12.2 Receiving Notification of Documentation Updates..22
12.3 Support Resources................................................. 22
12.4 Trademarks.............................................................22
12.5 Electrostatic Discharge Caution..............................22
12.6 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
1 项目符号............................................................................ 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings—AEC Specification...............................4
6.3 ESD Ratings—IEC Specification................................ 4
6.4 ESD Ratings—ISO Specification................................ 4
6.5 Recommended Operating Conditions.........................4
6.6 Thermal Information....................................................5
6.7 Electrical Characteristics.............................................5
6.8 Timing Requirements..................................................8
6.9 Typical Characteristics................................................9
7 Parameter Measurement Information..........................12
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................14
8.3 Feature Description...................................................14
Information.................................................................... 22
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (August 2017) to Revision C (August 2020)
Page
更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
向特性 部分添加了功能安全链接........................................................................................................................ 1
•
•
Changes from Revision A (April 2016) to Revision B (August 2017)
Page
• Updated ESD Protection on VBUS_CON, VD+, VD– section.............................................................................15
Changes from Revision * (January 2016) to Revision A (April 2016)
Page
•
•
•
•
更新了典型应用原理图、图 7-1 和 图 7-2 .......................................................................................................... 1
更新了{4}{5}电气特性{6}{7} 表............................................................................................................................ 1
向电池短路容差 添加了内容................................................................................................................................1
更新了典型特性 中具有更准确数据的 IEC 波形图.............................................................................................. 1
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5 Pin Configuration and Functions
NC
1
2
3
4
5
6
7
8
16
NC
V
V
V
15
14
13
12
11
10
9
BUS_CON
BUS_SYS
V
BUS_CON
GND
BUS_SYS
GND
GND
EN
VD–
VD+
D-
FLT
D+
V
IN
图 5-1. DBQ Package 16-Pin SSOP Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
2
NC
NC
O
No connect, leave floating or connect to ground. Do not connect to VBUS_CON
Connect to USB connector VBUS_CON; provides IEC 61000-4-2 ESD protection
VBUS_CON
3
4
GND
VD–
VD+
D–
Ground
I/O
I/O
I/O
I/O
I
Connect to PCB ground plane
5
Connect to USB connector D–; provides IEC 61000-4-2 ESD protection
Connect to USB connector D+; provides IEC 61000-4-2 ESD protection
Connect to internal D– transceiver
6
7
8
VD+
VIN
Connect to internal D+ transceiver
9
Connect to 3.3-V I/O. Controls the OVP threshold for VD+/VD–
Open-Drain fault pin. Refer device description for operation
10
FLT
O
Enable Active-Low Input. Drive EN low to enable the device. Drive EN high to disable the
device
11
EN
I
12
13
14
15
16
GND
Ground
Connect to PCB ground plane
VBUS_SYS
NC
I
Connect to internal VBUS plane
NC
No connect, leave floating or connect to ground. Do not connect to VBUS_CON
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
V
VBUS_CON
VBUS_SYS
VD+, VD–
D+, D–
VIN
Supply voltage from USB connector
Internal supply DC voltage rail on the PCB
Voltage range from connector-side USB data lines
Voltage range for internal USB data lines
Voltage range for VIN supply input
Voltage on enable pin
18
6
V
18
V
VIN + 0.3
V
4
7
V
EN
V
TA
Operating free air temperature
125
150
°C
°C
–40
–65
TSTG
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
6.2 ESD Ratings—AEC Specification
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification
VALUE
UNIT
Contact discharge(1)
Air-gap discharge(1)
±8000
IEC 61000-4-2, VBUS_CON, VD
+, VD– pins
V(ESD)
Electrostatic discharge
V
±15000
(1) See the ESD System Test Setup diagram for details on system level ESD testing setup.
6.4 ESD Ratings—ISO Specification
VALUE
±8000
UNIT
Contact discharge(1)
ISO 10605 (330 pF, 330 Ω),
VBUS_CON, VD+, VD– pins
V(ESD)
Electrostatic discharge
V
Air-gap discharge(1)
±15000
(1) See the ESD System Test Setup diagram for details on system level ESD testing setup.
6.5 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
V
VBUS_CON
VBUS_SYS
VD+, VD–
D+, D–
VIN
Supply voltage from USB connector
Internal supply DC voltage rail on the PCB
Voltage range from connector-side USB data lines
Voltage range for internal USB data lines
Voltage range for VIN supply
5.25
5.25
4.75
V
0
0
3
VIN + 0.3
VIN + 0.3
3.6
V
V
V
IBUS
Current through VBUS switch
500
mA
V
EN
Voltage range for enable
0
5.9
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6.5 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
µF
CSYS
CLOAD
CVIN
Input capacitance(1)
Output load capacitance(1)
VIN capacitance(1)
VBUS_SYS pin
VBUS_CON pin
VIN pin
100
1
1
µF
µF
(1) See 图 9-1 for configuration details
6.6 Thermal Information
TPD3S714-Q1
THERMAL METRIC(1)
DBQ (SSOP)
16 PINS
98.8
UNIT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJA
48
θJCtop
θJB
Junction-to-board thermal resistance
41.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.5
ψJT
41.2
ψJB
N/A
θJCbot
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.7 Electrical Characteristics
over operating free-air temperature range, EN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON = float (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT CONSUMPTION
IVBUS_SLEEP
IVBUS
VBUS sleep current consumption
VBUS operating current consumption
Leakage current for VIN
Measured at VBUS_SYS pin, EN = 5 V
Measured at VBUS_SYS pin
45
285
12
150
380
25
µA
µA
µA
IVIN
Measured at VIN pin, VIN = 3.6 V
Leakage through VBUS while shorted to battery
and powered on
Measured flowing in to VBUS_SYS pin, VBUS_SYS
= 5 V, VBUS_CON = 18 V
ION(LEAK)
IOFF(LEAK)
120
50
µA
µA
Leakage through VBUS while shorted to battery
and unpowered
Measured flowing out of VBUS_SYS pin,
VBUS_SYS = 0 V, VBUS_CON = 18 V
Measured flowing in to VD+ or VD– pins,
VBUS_SYS = 0 V, VD+ or VD– = 18 V, VIN = 0 V,
D+/D– = 0 V
Leakage into data path while shorted to battery
and unpowered
IVD(OFF_LEAK)
80
80
µA
µA
Measured flowing in to VD+ or VD– pins,
VBUS_SYS = 5 V, VD+ or VD– = 18 V, D+/D– =
0 V
Leakage into data path while shorted to battery
and powered on
IVD(ON_LEAK)
VIN PIN
Undervoltage lockout rising for
VIN
Ramp VIN down until FLT is deasserted, EN = 5
V
VUVLO(RISING)
2.6
2.5
2.7
2.6
2.9
2.8
VIN
V
Undervoltage lockout falling
for VIN
VUVLO(FALLING)
EN, FLT PINS
VIH
Ramp VIN until FLT is asserted, EN = 5 V
Set EN = 0 V; Sweep EN to 1.4 V; Measure
when FLT is asserted
High-level input voltage
Low-level input voltage
EN
EN
1.2
V
V
Set EN = 3.3 V; Sweep EN from 3.3 V to 0.5 V;
Measure when FLT is deasserted
VIL
0.8
IIL
Input leakage current
EN
V(EN) = 3.3 V ; Measure Current into EN pin
IOL = 3 mA
1
µA
V
VOL
Low-level output voltage
FLT
0.4
OCP CIRCUIT—VBUS
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6.7 Electrical Characteristics (continued)
over operating free-air temperature range, EN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON = float (unless
otherwise noted)
PARAMETER
Overcurrent limit
OVERTEMPERATURE PROTECTION
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Progressively load VBUS_CON until device
asserts FLT
ILIM
VBUS
550
700
850
mA
The rising overtemperature protection shutdown VBUS_SYS = 5 V, EN = 0 V, No Load on
TSD(RISING)
150
125
10
165
130
35
180
140
55
℃
℃
℃
threshold
VBUS_CON, TA stepped up until FLT is asserted
VBUS_SYS = 5 V, EN = 0 V, No Load on
VBUS_CON, TA stepped down from TSD(RISING)
until FLT is deasserted
The falling overtemperature protection shutdown
threshold
TSD(FALLING)
The overtemperature protection shutdown
threshold hysteresis
TSD(HYST)
TSD(RISING) – TSD(FALLING)
OVP CIRCUIT—VBUS
Input overvoltage protection
VBUS_CON
Increase VBUS_CON from 5 V to 7 V. Measure
when FLT is asserted
VOVP(RISING)
5.4
5.6
50
5.8
V
mV
V
threshold
Difference between rising and falling OVP
thresholds on VBUS_CON
VHYS(OVP)
Hysteresis on OVP
VBUS_CON
VBUS_CON
VBUS_SYS
VBUS_SYS
VBUS_SYS
Input overvoltage protection
threshold
Decrease VBUS_CON from 7 V to 5 V. Measure
when FLT is deasserted
TOVP(FALLING)
5.36
3.1
50
5.74
3.6
Undervoltage lockout rising for
VBUS_SYS
VUVLO(SYS_RISING)
VHYS(UVLO_SYS)
VUVLO(SYS_FALLING)
VBUS_SYS voltage rising from 0 V to 5 V
3.3
75
V
Difference between rising and falling UVLO
thresholds on VBUS_SYS
VBUS_SYS UVLO hysteresis
100
3.5
mV
V
Undervoltage lockout falling
for VBUS_SYS
VBUS_SYS voltage falling from 7 V to 3 V
3
3.2
Increase VBUS_CON voltage from 0 V until the
device transitions from the short-circuit to over-
current mode of operation
Short-to-ground comparator
rising threshold
VSHRT(RISING)
VBUS_CON
2.5
2.4
2.6
2.7
2.6
V
V
Set VBUS_SYS = 5 V; VIN = 3.3 V; EN = 0 V;
Decrease VBUS_CON voltage from 5 V until the
device transitions from the overcurrent to short-
circuit mode of operation
Short-to-ground comparator
falling threshold
VSHRT(FALLING)
VBUS_CON
2.5
Short-to-ground comparator
hysteresis
Difference between VSHRT(RISING) and
VSHRT(FALLING)
VSHRT(HYST)
ISHRT
VBUS_CON
VBUS_CON
100
150
125
150
350
mV
mA
Short-to-ground current
source
Current sourced from VBUS_SYS when device is
in short-circuit mode
OVP CIRCUIT—VD+/VD–
Increase VD+ or VD– (with D+ and D–) from
3.3 V to 4.5 V. Measure the value at which FLT
is asserted
Input overvoltage protection
threshold
VIN
0.6
+
VIN +
0.8
VOVP(RISING)
VIN + 1
V
mV
V
VD+/VD–
VD+/VD–
VD+/VD–
Difference between rising and falling OVP
thresholds on VD+/VD–
VHYS(OVP)
Hysteresis on OVP
50
Decrease VD+ or VD– (with D+ or D–) from
4.5 V to 2 V. Measure the value at FLT is
deasserted
Input overvoltage protection
threshold
VIN
0.525
+
VIN
+
VIN +
0.975
VOVP(FALLING)
0.75
SHORT-TO-BATTERY
VBUS hotplug short-to-battery
Charge battery-equivalent capacitor to test
voltage then discharge to pin under test
through a 1-meter, 18-gauge wire. (See 图 7-1
for more details)
V(VBUS_STB)
VBUS_CON
18
18
V
V
tolerance
Data line hotplug short-to-
battery tolerance
V(DATA_STB)
VD+/VD–
DATA LINE SWITCHES—VD+ to D+ or VD–to D–
Capacitance of D+/D– switches when enabled
- measure on connector side across bias
voltage 0 V to 0.4 V
CON
Equivalent on capacitance
On resistance
6.2
4
pF
Ω
Ω
Measure resistance between D+ and VD+ or
D– and VD–, voltage between 0 and 0.4 V
RON
6.5
1
Measure resistance between D+ and VD+ or
D– and VD–, sweep voltage between 0 V and
0.4 V
RON(Flat)
On resistance flatness
0.2
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6.7 Electrical Characteristics (continued)
over operating free-air temperature range, EN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON = float (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Measure S21 bandwidth from D+ to VD+ or D–
BWON
860
MHz
On bandwidth (–3 dB)
to VD– with voltage swing = 400 mVpp, VCM
=
0.2 V
Measure SDD21 bandwidth from D+ to VD+ and
D– to VD– with voltage swing = 800 mVpp
differential, VCM = 0.2 V
BWON_DIFF
1050
MHz
dB
On bandwidth (–3 dB)
Measure S21 bandwidth from D+ to VD– or
D– to VD+ with voltage swing = 400 mVpp. Be
sure to terminate open sides to 50 ohms. f =
480 MHz
Xtalk
Crosstalk
–34
nFET SWITCH—VBus
R(DISCHARGE) Output discharge resistance
RON Switch ON resistance
EN = 5 V, Set VBUS_CON = 5 V and measure
current flow to ground
12500
150
Ω
VBUS_CON = 5 V, IOUT = 0.5 A
63
mΩ
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6.8 Timing Requirements
over operating free-air temperature range, EN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON = float (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
ENABLE PIN
tON
Enable on time
Time between enable device until FLT deasserts
13
ms
OVERCURRENT PROTECTION
Time from overcurrent condition until FLT assertion and
VBUS FET turnoff
tBLANK
tRETRY
tRECV
Overcurrent blanking time
2
ms
ms
ms
Time from overcurrent FET shut off until FET turns back
on
Overcurrent retry time
100
8
Time from end of tRETRY until FLT deassertion if
overcurrent condition is removed
Overcurrent recovery time
OVERVOLTAGE PROTECTION
tOVP_response
tOVP_response
Measured from OVP Condition to FET turnoff
Measured from OVP Condition to FET turnoff
2
4
4
µs
ns
OVP response time – VBUS
OVP response time – data
switches
200
SHORT-TO-GROUND PROTECTION
tSHRT Short to ground response time
CLOAD = 0 uF, Time from short condition until current falls
below 120% of ISHRT
2
µs
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6.9 Typical Characteristics
120
100
80
60
40
20
0
40
20
VD-
D-
VD-
D-
0
-20
-40
-60
-80
-100
-20
-15
-15
0
15 30 45 60 75 90 105 120 135 150
Time (ns)
0
15
30
Time (ns)
45
60
75
90
D002
D001
图 6-2. –8-kV IEC Contact Waveform
图 6-1. 8-kV IEC Contact Waveform
1.00
8
Vbus_con
0.75
0.50
7
6
5
4
3
2
1
0
EN
FLT
0.25
0.00
-0.25
-0.50
-0.75
-1.00
VD-
VD+
25
0
5
10
15
20
0
5
10
15
20
œ5
Time (ms)
Voltage (V)
C004
C003
图 6-4. VBUS tON Time
图 6-3. Data Line I-V Curve
6
5
4
3
2
1
0
125
100
75
50
25
0
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C005
C006
图 6-5. VD± Short-to-5 V (while Enabled) Across
图 6-6. VD± Short-to-5 V (while Unpowered) Across
Temperature
Temperature
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100
80
6
5
4
3
2
1
0
60
40
-40C
25C
85C
20
Powered, Enabled
Unpowered
80 100
125C
0
0
20
40
60
120
0
0.1
0.2
0.3
0.4
œ40
œ20
Temperature (°C)
Bias Voltage (V)
C007
C008
图 6-7. VD± Short-to-18 V Across Temperature
图 6-8. Data Switch RON vs Bias Voltage
8
7
6
5
4
3
2
1
0
1600
1400
1200
1000
800
600
400
200
0
8
1600
1400
1200
1000
800
600
400
200
0
Vbus_con
FLT
Vbus_con
FLT
I_Vbus_sys
7
6
5
4
3
2
1
0
I_Vbus_sys
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
0
0.2
0.4
0.6
0.8 1
Time (ms)
1.2
1.4
1.6
1.8
C010
D009
图 6-10. Overcurrent tBLANK_RETRY Response
图 6-9. Overcurrent tBLANK Response Waveform
Waveform
50
40
10
8
8
Vbus_con
I_Vbus_con
Vbus_sys
FLT
Vbus_con
I_Vbus_con
Vbus_sys
FLT
7
6
30
6
5
20
4
4
3
10
2
2
0
0
1
œ10
œ20
-2
-4
0
œ1
œ2
0
5
10
15
20
25
30
Time (µs)
C012
0
5
10
15
20
25
30
35
40
Time (µs)
图 6-12. VBUS Short-to-18 V Response Waveform
C011
图 6-11. VBUS Short-to-Ground Response Waveform
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12
10
8
12
10
8
25
20
15
10
5
12.5
VD-
I_VD-
FLT
D-
VD-
I_VD-
FLT
D-
10
7.5
5
6
6
4
4
2.5
0
2
2
0
0
0
-2.5
œ2
-2
œ5
0
0.5
1
1.5
2
0
0.5
1
1.5
2
Time (µs)
Time (µs)
C014
C013
图 6-14. Data Switch Short-to-18 V Response
图 6-13. Data Switch Short-to-5 V Response
Waveform
Waveform
图 6-15. USB2.0 Eye Diagram (No TPD3S714-Q1)
图 6-16. USB2.0 Eye Diagram (With TPD3S714-Q1)
0
0
œ1
œ2
œ3
œ4
œ5
œ6
œ3
œ6
œ9
œ12
1.E+07
1.E+08
1.E+09
1.E+07
1.E+08
1.E+09
Frequency (Hz)
Frequency (Hz)
C015
C016
图 6-17. Data Switch Differential Bandwidth
图 6-18. Data Switch Single-Ended Bandwidth
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0
œ10
œ20
œ30
œ40
œ50
D- to VD+
D+ to VD-
œ60
0.E+00
1.E+09
2.E+09
3.E+09
Frequency (Hz)
C017
图 6-19. Data Switch Crosstalk
7 Parameter Measurement Information
5 V
VBUS_SYS
VBUS_CON
100 µF
7 V
1 µF
100 V
X7R
10 kΩ
FLT
VDt
Dœ
10 nH
10 nH
45 Ω
VD+
D+
EN
USB2.0
CMC
45 Ω
1 m cable
GND
STB
Strike
Output
From GPIO
DC Power
Supply
VIN
3.3 V
TPD3S714-Q1
22 mF
35 V
1 µF
7 V
STB Test Aparatus
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图 7-1. Short-to-Battery System Test Setup
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5 V
VBUS_SYS
VBUS_CON
100 µF
7 V
1 µF
100 V
X7R
10 kΩ
FLT
VDt
VD+
GND
Dœ
10 nH
10 nH
45 Ω
D+
USB2.0
CMC
45 Ω
EN
VIN
From GPIO
3.3 V
TPD3S714-Q1
1 µF
7 V
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Incorporated
图 7-2. ESD System Test Setup
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8 Detailed Description
8.1 Overview
The TPD3S714-Q1 provides a single-chip ESD protection and overvoltage protection solution for automotive
USB interfaces. It offers short to battery protection up to 18 V and short to ground protection on VBUS_CON. The
TPD3S714-Q1 also provides a FLT pin that indicates to the system if a fault condition has occurred. The
TPD3S714-Q1 offers ESD clamps on the VBUS_CON, VD+, and VD– pins, thus eliminating the need for external
TVS clamp circuits in the application.
The TPD3S714-Q1 has internal circuitry that controls the turnon of the internal nFET switches. An internal
oscillator controls the timers that enable the switches and resets the open-drain FLT output. If VBUS_CON is less
than VOVP, the switches are enabled. After an internal delay, the charge-pump starts-up, turns on the internal
nFET switch through a soft start. Once the nFET is completely turned ON, TPD3S714-Q1 releases FLT pin to
HIGH. At any time, if any of the external pins rise above VOVP, FLT pin is pulled LOW. The nFET switches are
turned OFF.
8.2 Functional Block Diagram
BUS_CON
BUS_SYS
ESD
Clamp
Short-
to-
UVLO
+
Ground
Detection
Overcurrent
Detection
Control
Logic
FLT
EN
Overvoltage
Protection
VIN
VD+
D+
ESD Clamps
VDœ
Dœ
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8.3 Feature Description
8.3.1 AEC-Q100 Qualified
The TPD3S714-Q1 is an automotive qualified device according to the AEC-Q100 standards. This device is
qualified to operate from –40 to +125°C ambient temperature.
8.3.2 Short-to-Battery and Short-to-Ground Protection on VBUS_CON
The VBUS_CON pin is protected against shorts to battery and shorts to ground.
Once a voltage on VBUS_CON is detected as too low (below the VSHRT threshold) after the device is enabled, the
device enters short-circuit protection mode and assert FLT. It sources the ISHRT current until it detects the
voltage rising above the VSHRT threshold, where it resumes standard operating mode and deassert FLT.
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Once a voltage above the VOVP threshold is detected by the device, it shuts off all FETs and asserts a fault on
the FLT pin. Once the excessive voltage is removed, the device automatically re-enables and FLT deasserts
(see the Timing Requirements table for more details).
8.3.3 Short-to-Battery and Short-to-VBUS Protection on VD+, VD–
The VD+ and VD– pins are protected against shorts to battery and shorts to bus. The OVP threshold on the VD
+ and VD– pins is low enough that it protects against shorts to VBUS
.
Once a voltage above the VOVP threshold is detected by the device, it shuts off all FETs and asserts a fault on
the FLT pin. Once the excessive voltage is removed, the device automatically re-enables and FLT deasserts.
8.3.4 ESD Protection on VBUS_CON, VD+, VD–
The protected pins (VBUS_CON, VD+, VD–) are tested to pass the IEC 61000-4-2 ESD standard up to Level 4
ESD protection. Additionally, these pins are tested against ISO 10605 with the 330-pF, 330-Ω equivalent
network. This guarantees passing of at least ±8-kV contact discharge and ±15-kV air gap discharge according to
both standards using test setup shown in 图 7-2.
8.3.5 Low RON nFET VBUS Switch
The VBUS switch has a low RON that provides minimal voltage droop from system to connector. Typical
resistance is 63 mΩ and is specified for 150 mΩ at 125°C ambient temperature.
8.3.6 High Speed Data Switches
The D+ and D– switches have a very low capacitance and a high bandwidth (1-GHz typical), allowing for a
clean USB 2.0 eye diagram.
8.3.7 Hiccup Current Limit
The VBUS path of this device has an integrated overcurrent protection circuit. Above the overcurrent threshold
(550-mA minimum), the device goes into a fault state where it limits current to the threshold. After a short
blanking time, the device cycles on and off to try to check if the connected device is still in overcurrent.
8.3.8 Fast Overvoltage Response Time
The overvoltage FETs are designed to have a fast turnoff time to protect the upstream SoC as quickly as
possible. Typical response time for complete turnoff is 2 µs for the VBUS path and 200 ns for the data path.
8.3.9 Integrated Input Enable
The TPD3S714-Q1 has an enable input to turn on and off the device. The EN pin disables and enables the VBUS
and data paths.
8.3.10 Fault Output Signal
The TPD3S714-Q1 has a fault pin, FLT that indicates when there is any sort of fault condition because of OVP,
OCP, or short-circuit.
8.3.11 Thermal Shutdown Feature
In the event that the device exceeds the maximum allowable junction temperature, it shuts down the device to
prevent damage to itself and indicate via the fault pin.
8.3.12 16-pin SSOP Package
This device is packaged in a standard 16-pin SSOP leaded package.
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8.4 Device Functional Modes
8.4.1 Normal Operation
The TPD3S714-Q1 operates normally (all FETs on) when enabled, both VBUS_SYS and VIN are above their UVLO
thresholds, and the device is not in any fault conditions.
8.4.2 Overvoltage Condition
When the VD+, VD–, or VBUS_CON pins exceed their OVP threshold, the device enters the overvoltage state. All
FETs are disabled and the FLT pin is asserted. Once the protected pins drop below their OVP threshold, the
device automatically turns back on.
8.4.3 Overcurrent Condition
When the current through the VBUS path exceeds the ILIM current threshold, the device enters into the
overcurrent state. The TPD3S714-Q1 limits current to the ILIM threshold by dropping voltage across the VBUS
FET to maintain constant current. Once it continues to sense an overcurrent condition for the blanking time
tBLANK, the device disables itself for the retry time, tRETRY and then retry automatically for the retry time,
tBLANK_RETRY. In the event that the current is below the overcurrent threshold, the device deasserts fault and
resumes normal operation.
8.4.4 Short-Circuit Condition
When the voltage on the VBUS_CON side drops below the VSHRT threshold while enabled, the TPD3S714-Q1
enters the short-circuit mode. It sources a constant current of ISHRT until it rises above the VSHRT threshold. Once
that occurs, the device automatically re-enters normal operation and deasserts fault.
8.4.5 Device Logic Tables
表 8-1 shows the TPD3S714-Q1 VBUS Logic Table.
表 8-1. TPD3S714-Q1 VBUS Logic Table
VOLTAGE CONDITION
CURRENT CONDITION
COMMENT
VBUS_CON
VBUS_SYS
EN
CURRENT FLOW
FLT PIN
X
<UVLO
X
No Flow
Switch off because of UVLO
High-Z
<OVP and
>VSHRT
Current flows through the switch, normal host
mode
>UVLO
>UVLO
>UVLO
Low
High
Low
VBUS_SYS to VBUS_CON
No Flow
High-Z
Low
X
Switch off
Current flow through switch, device detects short
circuit, current limited to ISHRT
<VSHRT
VBUS_SYS to VBUS_CON
Low
Device switches off because of overcurrent limit,
auto-retrys until <OCP or thermal shutdown
conditions occur
X
X
Low
>OCP
Low
>OVP
X
>UVLO
X
Low
X
No Flow
No Flow
Switch off because of OVP
Thermal Shutdown Condition
Low
Low
表 8-2 shows the TPD3S714-Q1 Data Line Logic Table
表 8-2. TPD3S714-Q1 Data Line Logic Table
VOLTAGE CONDITION
CURRENT CONDITION
EN
Low
High
Low
X
SWITCHES ON?
COMMENT
FLT PIN
High-Z
Low
VD+/VD–
<OVP
X
Yes
No
No
No
Device operates normally, data transfer can occur
Switches off
>OVP
X
Switches off because of OVP limit
Thermal Shutdown Condition
Low
Low
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TPD3S714-Q1 offers fully featured automotive USB2.0 protection including short-to-battery, overcurrent,
and ESD protection. Care must be taken during the implementation to make sure the device provides adequate
protection to the system.
9.2 Typical Application
图 9-1 shows a fully featured USB2.0 high speed port, with an 18-V short-to-battery requirement on the
connector side.
5 V
VBUS_SYS
VBUS_CON
VBUS
100 µF
7 V
1 µF
100 V
X7R
10 kΩ
FLT
USB
Transceiver
Dœ
Dœ
VDt
VD+
GND
10 nH
10 nH
D+
D+
EN
USB2.0
CMC
From Processor
3.3 V
GND
VIN
TPD3S714-Q1
1 µF
7 V
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图 9-1. Typical Application Configuration for TPD3S714-Q1
9.2.1 Design Requirements
For this design example, the input parameters shown in 表 9-1 are used:
表 9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
18 V
Short-to-battery tolerance on VD+, VD–, VBUS_CON
Maximum current in normal operation on VBUS
USB data rate
500 mA
480 Mbps
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9.2.2 Detailed Design Procedure
To begin the design process, the designer must know the following parameters:
• Short-to-Battery tolerance on connector pins
• Maximum current in normal operation on VBUS
• USB Data Rate
9.2.2.1 Short-to-Battery Tolerance
The TPD3S714-Q1 is capable of handling up to 18-V DC on the VD+, VD–, and VBUS_CON pins. In the event of
a short-to-battery on VBUS_CON, significant ringing is expected because of the hot plug-like nature of the short-to-
battery event. In typical ceramic capacitor configurations, a standard RLC response is expected which results in
a ringing of nearly two times the applied DC voltage. The TPD3S714-Q1 is capable of withstanding the transient
ringing from hot plug-like events, assuming some precautions are taken.
Careful capacitor selection on the VBUS_CON pin must be observed. A capacitor with a low derating percentage
under the applied voltages must be used to prevent excess ringing. In the example, a 1-µF 100-V tolerant
ceramic X7R capacitor is used. It is best practice to carefully select the capacitors used in this circuit to prevent
derating-based voltage spikes under hot plug events. See the application example graphs, 图 9-4 and 图 9-5 to
compare ringing of a 100-V capacitor to a 50-V capacitor. 图 9-6 shows the 100-V capacitor with the TPD3S714-
Q1 installed.
Another alternative to a high rated ceramic capacitor is to implement either a standard R-C snubber circuit, or a
small external TVS diode. Depending on the short-to-battery tolerance needed, no special precautions may be
needed.
For more information on this topic, see the white paper Designing USB for short-to-battery tolerance in
automotive environments.
9.2.2.2 Maximum Current on VBUS
The TPD3S714-Q1 is capable of operating up to 5500 mA of current (minimum) until going into current limit
mode. In this example, the maximum current for USB2.0 of 500 mA has been chosen.
9.2.2.3 USB Data Rate
The TPD3S714-Q1 is capable of operating at the maximum USB2.0 High Speed data rate of 480 Mbps because
of the high data switch bandwidth of 1 GHz (typical). In this design example the maximum data rate of 480 Mbps
has been chosen.
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9.2.3 Application Curves
图 9-2. USB2.0 Eye Diagram (Board Only, Through 图 9-3. USB2.0 Eye Diagram (System from Typical
Path) Application Schematic)
60
40
Voltage
Current
Voltage
Current
50
30
40
20
30
20
10
10
0
0
œ10
œ20
œ10
œ20
0
10
20
30
Time (µs)
40
50
60
70
0
10
20
30
40
50
60
70
œ10
œ10
Time (µs)
C018
C019
图 9-4. 50-V, 1-µF X7R Ceramic Shorted to 18-V
图 9-5. 100-V, 1-µF X7R Ceramic Shorted to 18 V
(Not Recommended)
40
30
Voltage
Current
20
10
0
œ10
œ20
0
10
20
30
40
50
60
70
œ10
Time (µs)
C020
图 9-6. TPD3S714-Q1 and 100-V, 1-µF X7R Shorted to 18 V (Powered Off)
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10 Power Supply Recommendations
10.1 VBUS Path
The VBUS_SYS pins provide power to the chip and supply current through the load switch to VBUS_CON. A 100-µF
bulk capacitor is recommended on VBUS_SYS to supply the USB port and maintain compliance. A 1-µF capacitor
is recommended on the VBUS_CON pin with adequate voltage rating to tolerate short-to-battery conditions. A
supply voltage above the UVLO threshold for VBUS_SYS must be supplied for the device to power on.
10.2 VIN Pin
The VIN pin provides a voltage reference for the data switch OVP level as well as a bypass for ESD clamping. A
1-µF capacitor must be placed as close to the pin as possible and the supply must be set to be above the UVLO
threshold for VIN.
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11 Layout
11.1 Layout Guidelines
Proper routing and placement maintains signal integrity for high-speed signals. The following guidelines apply to
the TPD3S714-Q1:
• Place the bypass capacitors as close as possible to the VIN, VBUS_SYS, and VBUS_CON pins. Capacitors must
be attached to a solid ground. This minimizes voltage disturbances during transient events such as short-to-
battery, ESD, or overcurrent conditions.
• High speed traces (data switch path) must be routed as straight as possible and any sharp bends must be
minimized.
Our standard ESD recommendations apply to the VD+, VD–, and VBUS_CON pins as well:
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
图 11-1 shows a full layout for a standard USB2.0 port. A common mode choke and inductors are used on the
high speed data lines, and the requisite bypassing caps are placed on VBUS_CON, VBUS_SYS, and VIN.
VBUS
N.C.
N.C.
VBUS_CON
VBUS_SYS
VBUS_CON
GND
VD-
VBUS_SYS
D-
GND
GND
EN
TPD3S714-Q1
VD+
D-
To Processor
FLT
VIN
To Transceiver
D+
D+
Legend
Pin to GND
GND
VIA to 3.3V Plane
To Transceiver
To Transceiver
USB2.0 Connector
VIA to 5V Plane
VIA to GND Plane
图 11-1. Typical Layout Example for TPD3S714-Q1
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• TPD3S714-Q1EVM User’s Guide
• Reading and Understanding an ESD Protection Datasheet
• ESD Layout Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TPD3S714-Q1
TPD3S714-Q1
ZHCSEZ9C – JANUARY 2016 – REVISED AUGUST 2020
www.ti.com.cn
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TPD3S714-Q1
TPD3S714-Q1
ZHCSEZ9C – JANUARY 2016 – REVISED AUGUST 2020
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TPD3S714-Q1
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将独自承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于开发本资源所述的使用 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三
方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 () 或 TI.com.cn 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方
式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020，德州仪器 (TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD3S714QDBQRQ1
ACTIVE
SSOP
DBQ
16
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RJ714Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD3S714QDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DBQ 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPD3S714QDBQRQ1
2500
Pack Materials-Page 2
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.175
[4.45]
8
9
16X .008-.012
[0.21-0.30]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.007 [0.17]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 - 8
.016-.035
[0.41-0.88]
DETAIL A
TYPICAL
(.041 )
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
8
9
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2021 德州仪器半导体技术（上海）有限公司
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