TPD4E6B06DPWR [TI]
采用 0.5mm 间距、0.64mm2 SON 封装的四路 4.8pF、±5.5V、±15kV ESD 保护二极管 | DPW | 4 | -40 to 125;
| 型号： | TPD4E6B06DPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 0.5mm 间距、0.64mm2 SON 封装的四路 4.8pF、±5.5V、±15kV ESD 保护二极管 | DPW | 4 | -40 to 125 局域网 二极管 |
| 文件： | 总26页 (文件大小：1474K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPD4E6B06
ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
具有 15kV 接触放电和超低钳位电压的 TPD4E6B06 四通道双向低电容
ESD 保护器件
1 特性
3 说明
1
•
IEC 61000-4-2 4 级
TPD4E6B06 是一款采用超小型 DPW 封装的四通道静
电放电 (ESD) 保护器件。此器件是业内领先的小型 4
通道瞬态电压抑制器 (TVS) 二极管，间距为
–
–
±15kV 接触放电
±15kV 气隙放电
0.48mm。这种较大的间距有助于节省印刷电路板
(PCB) 的制造成本。此器件提供符合 IEC61000-4-2 标
准的高达 15kV 的接触放电要求。此器件具有 ESD 钳
位电路，该电路的背对背二极管支持双极双向信号。
4.8pF（典型值）的线路电容使得此器件适用于 支持
高达 700MHz 数据速率的广泛应用。
•
•
•
•
•
•
•
•
IEC 61000-4-5（浪涌）：3A (8/20µs)
IO 电容值：4.8pF（典型值）
RDYN：0.75Ω（典型值）
直流击穿电压：±6V（最小值）
超低泄漏电流：100nA（最大值）
钳位电压：10V（IPP = 1A 时的最大值）
工业温度范围：-40°C 至 +125°C
节省空间的 DPW 封装 (0.8mm × 0.8mm)
器件信息(1)
器件型号
TPD4E6B06
封装
X2SON (4)
封装尺寸（标称值）
0.80mm × 0.80mm
2 应用
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
•
音频线路
–
–
–
麦克风
耳机
免提电话
•
•
•
•
•
•
•
•
•
SD 接口
SIM 接口
移动键盘或其它按钮
手机
电子书
便携式媒体播放器
数码摄像机
平板个人电脑
可佩带产品
引脚分配
简化电路原理图
1
2
1
4
2
GND
GND
3
3
4
0.8 mm x 0.8mm X2SON Package
(Bottom View)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCK3
TPD4E6B06
ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 9
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
Power Supply Recommendations...................... 12
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
8
9
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
10.2 Layout Examples................................................... 12
11 器件和文档支持 ..................................................... 14
11.1 文档支持................................................................ 14
11.2 接收文档更新通知 ................................................. 14
11.3 社区资源................................................................ 14
11.4 商标....................................................................... 14
11.5 静电放电警告......................................................... 14
11.6 Glossary................................................................ 14
12 机械、封装和可订购信息....................................... 15
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (February 2017) to Revision C
Page
•
Added "Power Supply Recommendations" section.............................................................................................................. 12
Changes from Revision A (December 2015) to Revision B
Page
•
Changed the value of RDYN from 0.75 and 0.65 to 0.45 and 0.42 respectively, in the Electrical Characteristics table ......... 5
Changes from Original (May 2014) to Revision A
Page
•
•
•
•
Updated the Handling Ratings table into an ESD Ratings table and moved Tstg to the Absolute Maximum Ratings table... 4
Added new note to Absolute Maximum Ratings table ........................................................................................................... 4
Added frequency test condition to IO capacitance in the Electrical Characteristics table...................................................... 5
已添加 社区资源 .................................................................................................................................................................. 14
2
Copyright © 2014–2017, Texas Instruments Incorporated
TPD4E6B06
www.ti.com.cn
ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
5 Pin Configuration and Functions
DPW Package
5-Pin X2SON
Bottom View
IO1
IO2
1
2
GND
3
4
IO3
IO4
Pin Functions
PIN
I/O
DESCRIPTION
NO
1
NAME
IO1
IO
IO
IO
IO
—
ESD protected line
2
IO2
ESD protected line
ESD protected line
ESD protected line
Ground
3
IO3
4
IO4
5
GND
Copyright © 2014–2017, Texas Instruments Incorporated
3
TPD4E6B06
ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN
MAX
3
UNIT
A
IEC 61000-4-5 Current (tp – 8/20 µs)(4)
Peak pulse
IEC 61000-4-5 Power (tp – 8/20 µs)(4)
40
W
Operating temperature
–40
–65
125
155
°C
Storage temperature
Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Absolute maximum ratings apply over recommended junction temperature range.
(3) Voltages are with respect to GND unless otherwise noted.
(4) Measured at 25°C.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 2 kV
may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V
may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–5.5
–40
MAX
5.5
UNIT
V
VIO
TA
Input pin voltage
Operating free-air temperature
125
°C
6.4 Thermal Information
TPD4E6B06
THERMAL METRIC(1)
DPW (X2SON)
5 PINS
291.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
224.2
245.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
31.4
ψJB
245.6
RθJC(bot)
195.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2014–2017, Texas Instruments Incorporated
TPD4E6B06
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ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
6.5 Electrical Characteristics
TA = –40°C to +125°C (unless otherwise specified)
PARAMETER
TEST CONDITION
IIO = 10 µA
MIN
–5.5
6
TYP
MAX UNIT
VRWM
VBRF
VBRR
ILEAK
Reverse stand-off voltage
Break-down voltage
Break-down voltage
Leakage current
5.5
V
V
IIO to GND = 1 mA
IGND to IO = 1 mA
6
V
VIO = 5 V
100
nA
V
I = 1 A, IO to GND, 8/20 μs(1)
I = 5 A, IO to GND, 8/20 μs(1)
I = 1 A, IO to GND, 8/20 μss(1)
I = 5 A, IO to GND, 8/20 μs(1)
Any IO to GND pin(2)
GND to any IO pin(2)
VIO = 2.5 V; ƒ = 10 MHz
10
13
V
VCLAMP
Clamp voltage with ESD strike
9
V
13
V
0.45
0.42
4.8
Ω
Ω
pF
RDYN
CL
Dynamic resistance
IO capacitance
7
(1) Non-repetitive current pulse 8/20 µs exponentially decaying waveform according to IEC61000-4-5.
(2) Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A.
Copyright © 2014–2017, Texas Instruments Incorporated
5
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ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
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6.6 Typical Characteristics
60
50
40
30
20
10
0
10
0
−10
−20
−30
−40
−50
−60
−10
−15
0
15 30 45 60 75 90 105 120 135 150
Time (ns)
−15
0
15 30 45 60 75 90 105 120 135 150
Time (ns)
G001
G002
Figure 1. IEC 61000-4-2 Clamping Voltage, 8-kV Contact
Figure 2. IEC 61000-4-2 Clamping Voltage, –8-kV Contact
10
10
RDYN = 0.45 Ω
tPW = 100 ns*
RDYN = 0.42 Ω
tPW = 100 ns*
9
9
tRISE = 10 ns*
tRISE = 10 ns*
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
0
3
6
9
12
15
18
21
24
27
30
0
3
6
9
12
15
18
21
24
27
30
Voltage (V)
Voltage (V)
G003
G004
Figure 3. TLP, tPW = 100 ns, tRISE = 10 ns, IO to GND
Figure 4. TLP, tPW = 100 ns, tRISE = 10 ns, GND to IO
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
50
0.0010
Current
Power
45
0.0008
0.0006
40
35
30
25
20
15
10
5
0.0004
0.0002
0.0000
−0.0002
−0.0004
−0.0006
−0.0008
−0.0010
0
0
5
10
15
20
Time (µs)
25
30
35
40
45
50
−10 −8 −6 −4 −2
0
2
4
6
8
10 12
G006
Voltage (V)
G005
Figure 6. Surge Curves, IO to GND
Figure 5. IV Curve
6
Copyright © 2014–2017, Texas Instruments Incorporated
TPD4E6B06
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ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
Typical Characteristics (continued)
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
50
45
40
35
30
25
20
15
10
5
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
Current
Power
0
0
5
10
15
20
25
30
35
40
45
50
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time (µs)
G007
Bias Voltage (V)
G008
Figure 7. Surge Curves, GND to IO
Figure 8. Capacitance
3
0
−3
−6
−9
−12
−15
−18
−21
−24
−27
−30
−33
100k
1M
10M
100M
1G 3G
Frequency (Hz)
G009
Figure 9. Insertion Loss
Copyright © 2014–2017, Texas Instruments Incorporated
7
TPD4E6B06
ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPD4E6B06 is a four channel ESD Protection device in an ultra small DPW package. It is the industry’s
smallest 4-CH ESD protection device with 0.48-mm pitch. This larger pitch helps save on PCB manufacturing
costs. The device provides IEC61000-4-2 compliance up to 15-kV contact discharge. It has an ESD clamp circuit
with back-to-back diodes for bipolar/bidirectional signal support. The 4.8-pF (Typical) line capacitance is suitable
for a wide range of applications supporting frequencies up to 700 MHz.
7.2 Functional Block Diagram
IO1 IO2 IO3 IO4
GND
7.3 Feature Description
7.3.1 IEC 61000-4-2 Level 2 ESD Protection
The IO pins can withstand ESD events up to ±15-kV contact and ±15-kV air. An ESD-surge clamp diverts the
current to ground.
7.3.2 IEC 61000-4-5 Surge Protection
The IO pins can withstand surge events up to 3 A and 40 W (8/20 µs waveform). An ESD-surge clamp diverts
this current to ground.
7.3.3 IO Capacitance
The capacitance between any IO pin to ground is 4.8 pF (typical). This capacitance supports frequencies up to
700 MHz.
7.3.4 RDYN
The low RDYN of 0.75 Ω (typical) allows for lower clamping voltages.
7.3.5 DC Breakdown Voltage
The DC breakdown voltage of any IO pin is a minimum of ±6 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of ±5.5 V (minimum).
7.3.6 Ultra-Low Leakage Current
The IO pins feature an ultra-low leakage current of 100 nA (maximum) with a bias of 2.5 V.
8
Copyright © 2014–2017, Texas Instruments Incorporated
TPD4E6B06
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ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
Feature Description (continued)
7.3.7 Clamping Voltage
The IO pins feature an ESD clamp capable of clamping the voltage to 10 V (IO to GND) or 9 V (GND to IO) of
IEC61000-4-5 surge when IPP = 1 A.
7.3.8 Industrial Temperature Range
This device features an industrial operating range of –40°C to +125°C.
7.3.9 Space Saving DPW Package
The small 0.8 mm × 0.8 mm package size saves board space and makes it easy to add ESD protection.
7.4 Device Functional Modes
The TPD4E6B06 is a passive integrated circuit that triggers when voltages are above VBRF or VBRR. During ESD
events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network. Once the
voltages on the protected line fall below the trigger levels of the TPD4E6B06 (usually within 10s of nano-
seconds) the device reverts to passive.
Copyright © 2014–2017, Texas Instruments Incorporated
9
TPD4E6B06
ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPD4E6B06 is a diode array type TVS. These low capacitance types of TVSs are typically used to provide a
path to ground for dissipating ESD events on hi speed signal lines between a human interface connector and a
system. During high voltage ESD strikes, the device clamps to a safe voltage level to protect the system.
The typical application of the TPD4E6B06 is to be placed in between the connector and the system. The low
capacitance of the TPD4E6B06 gives flexibility in the end application, as it can be used on many different high
speed interfaces.
8.2 Typical Application
1
4
2
GND
3
Figure 10. Protecting Data Lines
8.2.1 Design Requirements
Table 1 shows the design parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
–5.5 V to 5.5 V
Up to 700 MHz
Signal range on data lines
Operating frequency
8.2.2 Detailed Design Procedure
The designer needs to know the following:
•
•
Signal range on all the protected lines
Operating frequency
8.2.2.1 Signal Range
The TPD4E6B06 has 4 protection channels for signal lines. Any I/O supports a signal range of –5.5 V to
5.5 V.
8.2.2.2 Operating Frequency
The TPD4E6B06 has 4.8 pF of capacitance (Typical), supporting up to 700 MHz frequencies.
10
Copyright © 2014–2017, Texas Instruments Incorporated
TPD4E6B06
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ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
8.2.3 Application Curve
3
0
−3
−6
−9
−12
−15
−18
−21
−24
−27
−30
−33
100k
1M
10M
100M
1G 3G
Frequency (Hz)
G009
Figure 11. Insertion Loss (Any IO to GND)
Copyright © 2014–2017, Texas Instruments Incorporated
11
TPD4E6B06
ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
9 Power Supply Recommendations
The TPD4E6B06 is a passive TVS diode-based ESD protection device, so there is no need to power it. Ensure
that the maximum voltage specifications for each pin are not violated.
10 Layout
10.1 Layout Guidelines
•
Place the device as close to the connector as possible.
–
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
–
The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
•
•
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
–
Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Examples
= VIA to GND Plane
1
4
2
3
Figure 12. Single Layer Routing
12
版权 © 2014–2017, Texas Instruments Incorporated
TPD4E6B06
www.ti.com.cn
ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
Layout Examples (接下页)
=
VIA
1
2
4
GND
3
Figure 13. Double Layer Routing
版权 © 2014–2017, Texas Instruments Incorporated
13
TPD4E6B06
ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
相关文档如下：
•
•
阅读和理解 ESD 保护数据表
《ESD 布局指南》
11.2 接收文档更新通知
如需接收文档更新通知，请访问 ti.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14
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ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
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PACKAGE OUTLINE
DPW0004A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 4
(0.1)
0.25 0.1
0.05
0.00
THERMAL PAD
2
3
4
NOTE 4
5
2X
(45 ) TYP
0.48
1
0.27
4X
PIN 1 ID
(OPTIONAL)
NOTE 5
0.17
0.32
3X
0.1 C A
0.05 C
B
0.27
0.17
0.23
4218860/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. The size and shape of this feature may vary.
5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
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ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
EXAMPLE BOARD LAYOUT
DPW0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
( 0.1)
VIA
SYMM
4X (0.42)
0.05 MIN
ALL AROUND
TYP
1
4
4X (0.22)
5
SYMM
4X (0.26)
(0.48)
2
3
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4218860/A 12/2015
NOTES: (continued)
6. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
版权 © 2014–2017, Texas Instruments Incorporated
17
TPD4E6B06
ZHCSCO4C –MAY 2014–REVISED FEBRUARY 2017
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DPW0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
4
1
4X (0.22)
(
0.24)
4X (0.26)
5
SYMM
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
2
3
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 5:
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4218860/A 12/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
18
版权 © 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPD4E6B06DPWR
ACTIVE
X2SON
DPW
4
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
(B1, B5)
B2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD4E6B06DPWR
X2SON
DPW
4
3000
180.0
9.5
0.94
0.94
0.5
2.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
X2SON DPW
SPQ
Length (mm) Width (mm) Height (mm)
184.0 184.0 19.0
TPD4E6B06DPWR
4
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DPW0004A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 4
(0.1)
0.25 0.1
0.05
0.00
THERMAL PAD
2
3
4
NOTE 4
5
2X
(45 ) TYP
0.48
1
0.27
4X
PIN 1 ID
(OPTIONAL)
NOTE 5
0.17
0.32
3X
0.1 C A
0.05 C
B
0.27
0.17
0.23
4218860/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. The size and shape of this feature may vary.
5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
(
0.1)
SYMM
4X (0.42)
VIA
0.05 MIN
ALL AROUND
TYP
1
4
4X (0.22)
5
SYMM
4X (0.26)
(0.48)
2
3
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4218860/A 12/2015
NOTES: (continued)
6. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
4
1
4X (0.22)
SYMM
(
0.24)
4X (0.26)
5
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
2
3
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 5:
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4218860/A 12/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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