TPD4S214 [TI]
USB OTG Companion Device with VBUS Over Voltage, Over Current Protection, and Four Channel ESD Clamps; USB OTG配套设备与VBUS过电压，过电流保护，以及四通道ESD钳位
| 型号： | TPD4S214 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | USB OTG Companion Device with VBUS Over Voltage, Over Current Protection, and Four Channel ESD Clamps |
| 文件： | 总21页 (文件大小：1300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPD4S214
www.ti.com
SLVSBR1A –JANUARY 2013–REVISED FEBRUARY 2013
USB OTG Companion Device with V Over Voltage, Over Current Protection, and Four
BUS
Channel ESD Clamps
Check for Samples: TPD4S214
1
FEATURES
•
•
ESD Performance D+, D-, ID, VBUS PINS
–
–
±15-kV Contact Discharge (IEC 61000-4-2)
±15-kV Air Gap Discharge (IEC 61000-4-2)
•
Input Voltage Protection at VBUS from –7 V to
30 V
•
Low RDS(ON) N-CH FET Switch for High
Efficiency
Space Saving WCSP (12-YFF) Package
APPLICATIONS
•
•
Compliant with USB2.0 and USB3.0 OTG spec
User Adjustable Current Limit From 250 mA to
Beyond 1.2 A
•
•
•
•
•
Cell Phones
Tablet, eBook
•
•
•
•
•
Built-in Soft-start
Set-Top Box
Reverse Current Blocking
Over Voltage Lock Out for VBUS
Under Voltage Lock Out for VOTG_IN
Portable Media Players
Digital Camera
Thermal Shutdown and Short Circuit
Protection
YFF PACKAGE
(TOP SIDE/SEE-THROUGH VIEW)
1.4-mm
•
Auto Retry on any Fault; no Latching off
States
12-YFF Pin Proposal
1
2
3
•
•
Integrated VBUS Detection Circuit
A
B
C
D
VOTG_IN
DET
VBUS
Low Capacitance TVS ESD Clamp for USB2.0
High Speed Data Rate
VOTG_IN
EN
FLT\
GND
D-
VBUS
ID
•
Internal 16ms Startup Delay
ADJ
D+
DESCRIPTION
The TPD4S214 is a single-chip protection solution for USB On-the-Go and other current limited USB
applications. This device includes an integrated low (RDS(ON) N-channel current limited switch for OTG current
supply to peripheral devices. TPD4S214 offers low capacitance TVS ESD clamps for the D+, D-, ID pins for both
USB2.0 and USB3.0 applications. The VBUS pin can handle continuous voltage ranging from –7 V to 30 V. The
over voltage lock-out (OVLO) at the VBUS pin ensures that if there is a fault condition at the VBUS line, the
TPD4S214 is able to isolate it and protects the internal circuitry from damage. Similarly, the under voltage lock
out (UVLO) at the VOTG_IN pin ensures that there is no power drain from the internal OTG supply to external VBUS
if VOTG_IN droops below safe operating level.
When EN is high, the OTG switch is activated and the FLT pin indicates whether there is a fault condition. The
soft start feature waits 16 ms to turn on the OTG switch after all operating conditions are met. The FLT pin
asserts low during any one of the following fault conditions: OVLO (VBUS > VOVLO), UVLO condition (VOTG_IN
<
VUVLO) over temperature, over current, short circuit condition, or reverse-current-condition (VBUS > VOTG_IN). The
OTG switch is turned off during any fault condition. Once the switch is turned off, the IC periodically rechecks the
faults internally. If the IC returns to normal operating conditions, the switch turns back on and FLT is reset to
high.
There is also a VBUS detection feature for facilitating USB communication between USB host and peripheral
device. See Table 2 for detection scheme. If this is not used, DET pin can be either floating or connected to
ground.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
Copyright © 2013, Texas Instruments Incorporated
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
TPD4S214
SLVSBR1A –JANUARY 2013–REVISED FEBRUARY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART
NUMBER
TOP-SIDE MARKING
–40°C to 85°C
WCSP – YFF (0.4-mm pitch)
Tape and reel
TPD4S214YFFR
B3214
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
CIRCUIT SCHEMATIC DIAGRAM
DET
OTG Switch
V
OTG_IN
Current Limiting
Internal
Band Gap
Referance
V
BUS
UVLO
VBUS Detection
+
OVLO
ADJ
FLT
Control Logic
+
Charge Pump
EN
GND
D+
D–
ID
Figure 1. Circuit Schematic
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SLVSBR1A –JANUARY 2013–REVISED FEBRUARY 2013
Table 1. Device Operation
EN
X
VOTG_IN
VBUS
OCP
F
OTP
F
OTG SW
OFF
OFF
OFF
OFF
OFF
OFF
ON
FLT FAULT CONDITION
0
0
L
L
L
L
L
L
H
SW Disabled
X
X
X
X
T
Over Temperature
Over Current
H
H
H
H
H
X
X
T
X
VOTG_IN > VUVLO
X
VBUS > VOTG_IN
VBUS > VOVLO
X
F
F
Reverse-current
VBUS over-voltage
VOTG_IN under-voltage
Normal (SW Enabled)
F
F
VOTG_IN < VUVLO
F
F
VOTG_IN > VBUS and
VOTG_IN > VUVLO
VSHORT < VBUS < VOTG_IN and
VSHORT < VBUS < VOVLO
F
F
Table 2. VBUS Detection Scheme(1)
EN
X
VOTG_IN (VBUS Detect Power)
VBUS
DET
H
Condition
X
X
VBUS_VALID- < VBUS < VBUS_VALID
+
VBUS within VBUS_VALID
VBUS outside of VBUS_VALID
X
VBUS_VALID+ > VBUS or VBUS > VBUS_VALID
+
L
(1) X = Don’t Care, H = Signal High, and L = Signal Low
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
D–
YFF
D2
D3
C3
B2
DRC
TBD
TBD
TBD
TBD
TYPE
I/O
USB data–
USB data+
USB ID signal
D+
I/O
ID
I/O
FLT
O
Open-Drain Output. Connect a pullup resistor from FLT\ to the supply voltage of the
host system.
ADJ
EN
D1
C1
TBD
TBD
TBD
TBD
TBD
I
I
Attach external resistor to adjust the current limit
Enable Input. Drive EN high to enable the OTG switch.
USB Power Output
VBUS
VOTG_IN
DET
A3, B3
A1, B1
A2
O
I
USB OTG Supply Input
O
Open-Drain Output. Connect a pullup resistor from DET to the supply voltage of the
host system.
GND
C2
Thermal
Pad
Ground
Connect to PCB ground plane
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(1)(2)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–7
MAX UNIT
VOTG_IN, ADJ, EN
VBUS
Input voltage
7
30
V
Output voltage to USB connector
Output voltage
FLT, DET
–0.5
7
Input clamp current VI < 0
-50
10
mA
mA
mA
°C
IOUT Continuous current through FLT and DET output
IGND Continuous current through GND
TJ(max) maximum junction temperature
IEC 61000-4-2 Contact Discharge at 25°C
100
150
±15
–65
D+, D-, ID, VBUS
pins
kV
D+, D-, ID, VBUS
pins
IEC 61000-4-2 Air-gap Discharge at 25°C
±15
kV
All pins
Human-Body Model at 25°C
±2
7.8
84
kV
A
D+, D-, ID pins
D+, D-, ID pins
Peak Pulse Current (tp = 8/20 μs) at 25°C
Peak Pulse Power (tp = 8/20 μs) at 25°C
W
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
-40
1.2
TYP MAX
UNIT
°C
V
TA
Operating free-air temperature
High-level input voltage EN
Low-level input voltage EN
EN ramp rate for proper turn on
85
VIH
VIL
tEN
0.4
V
Valid ramp rate is between 10us and 100ms,
rising and falling
0.01
0.01
0.01
100
ms
tUVLO_SLEW
tOVLO_SLEW
TA_VBUS_ATT
VOTG_IN ramp rate for proper UVLO
operation
Valid ramp rate is between 10us and 100ms,
rising and falling
100
100
200
ms
ms
ms
VBUS ramp rate for proper OVLO
operation
Valid ramp rate is between 10us and 100ms,
rising and falling
Time to detect VBUS device attachment and turn on DET
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
THERMAL METRICS(1)
YFF
UNITS
°C/W
θJA
Package thermal impedance
Package thermal impedance
89.1
(1) The published θJA was modeled assuming a 76mm x 114mm PCB with 4 copper layers and the exposed land pad of the PCB has
thermal vias connecting the exposed center pad of the package to an internal GND plane for maximum heat dissipation. For more
information about traditional and new thermal metrics, see the IC Package Metrics application report, SPRA953A.
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SLVSBR1A –JANUARY 2013–REVISED FEBRUARY 2013
ELECTRICAL CHARACTERISTICS FOR EN, FLT, DET, D+, D–, VBUS, ID Pins
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IIL_EN
EN pin input leakage current
FLT\, DET pin output leakage current
Low-level output voltage FLT\
Low-level output voltage DET
EN = 3.3 V
1
1
µA
µA
IOL
FLT, DET = 3.6 V
VOL_FLT
VOL_DET
VBUS or VOTG_IN = 5 V or 0 V IOL = 100 µA
VBUS and VOTG_IN = 5 V or 0 V IOL = 100 µA
100
100
mV
mV
VBIAS = 1.8 V, f = 1 MHz, 30 mVpp ripple,
VOTG_IN = 5 V
CEN
Enable capacitance
4.5
pF
Diode forward voltage D+, D–, ID pins;
lower clamp diode
VD
IO = 8 mA
0.95
100
V
IL_D
ΔCIO
Leakage current on D+, D–, ID Pins
D+, D–, ID = 3.3 V
nA
pF
Differential capacitance between the D+, VBIAS = 1.8 V, f = 1 MHz, 30 mVpp ripple,
D– lines
0.04
VOTG_IN = 5 V
Capacitance to GND for the D+, D– lines
Capacitance to GND for the ID lines
Breakdown voltage D+, D–, ID pins
Breakdown voltage on Vbus
1.9
1.9
VBIAS = 1.8 V, f = 1 MHz, 30 mVpp ripple,
VOTG_IN = 5 V
CIO
pF
Ibr = 1 mA
Ibr = 1 mA
6
V
V
VBR
33
Dynamic on resistance D+, D–, ID
clamps
RDYN
1
Ω
ELECTRICAL CHARACTERISTICS FOR UVLO / OVLO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
INPUT UNDER-VOLTAGE LOCKOUT
Under-voltage lock-out, input power
detected threshold rising
VOTG_IN increasing from 0 V to 5 V, No load on
VBUS pin
VUVLO+
3.4
3.0
3.6
3.8
3.5
V
Under-voltage lock-out, input power
detected threshold falling
VOTG_IN decreasing from 5 V to 0 V, No load on
VBUS pin
VUVLO–
3.2
V
VHYS-UVLO
Hysteresis on UVLO
Δ of VUVLO+ and VUVLO–
260
mV
VOTG_IN increasing from 0V to 5V, No load on
VBUS pin;
time from VOTG_IN = VUVLO+ to FLT toggles high
TRUVLO
Recovery time from UVLO
18
ms
µs
VOTG_IN decreasing from 5V to 0V, No load on
VBUS pin;
TRESP_UVLO
Response time for UVLO
0.18
time from VOTG_IN = VUVLO– to FLT\ toggles low
OUTPUT OVERVOLTAGE LOCKOUT
Both VOTG_IN and VBUS increasing from 5 V to 7
V
VOVP+
OVLO rising threshold
5.55 6.15 6.45
V
Both VOTG_IN and VBUS decreasing from 7 V to 5
V
VOVP–
OVLO falling threshold
Hysteresis on OVLO
5.4
6
6.3
V
VHYS-OVP
Δ of VUVLO+ and VUVLO–
100
mV
Both VOTG_IN and VBUS decreasing from 7 V to
5 V, VOTG_IN = 5 V;
time from VBUS = VOVP– to FLT toggles high
TROVLO
Recovery time from OVLO
Response time for OVLO
9
ms
µs
Both VOTG_IN and VBUS increasing from 5 V to 7
V, VOTG_IN = 5 V;
TRESP_OVLO
17
time from VBUS = VOVP+ to FLT toggles low
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ELECTRICAL CHARACTERISTICS FOR DET CIRCUITS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
VBUS_VALID–
VBUS_VALID+
Valid VBUS voltage detect
Valid VBUS voltage detect
VBUS = 7 V to 0 V
VBUS = 0 V to 7 V
2.7
5.3
2.9
5.4
3
V
V
5.6
VBUS detect propagation
delay–
VBUS 0 V to 4 V, 200 ns ramp; VBUS = VBUS_VALID– MIN to
DET toggles high
TDET_DELAY–
TDET_DELAY+
4.9
1.8
µs
µs
VBUS detect propagation
delay+
VBUS 6 V to 4 V, 200 ns ramp; VBUS = VBUS_VALID+ MAX to
DET toggles low
ELECTRICAL CHARACTERISTICS FOR OTG SWITCH
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
RDS_ON
VDROP
OTG switch resistance
OTG switch voltage drop
VBUS = 5 V, IOUT = 100 mA, RADJ = 75 kΩ(1)
263
12.6
6
290
29
mΩ
mV
µA
nA
µA
µA
nA
nA
µA
ms
µs
VBUS = 5 V, IOUT = 100 mA, RADJ = 75 kΩ
VBUS = 30 V, EN = 5 V, VOTG_IN = 5 V
IOTG_OFF_30V Leakage current at 30V
IOTG_OFF_2V Leakage current at–2V
VBUS = 30 V, EN = 5 V, VOTG_IN = 0 V
VBUS = -2 V, EN = 5 V, VOTG_IN = 5 V
VBUS = 0 V, EN = 0 V, VOTG_IN = 5 V
VBUS = 5 V, EN = 0 V, VOTG_IN = 0 V
VBUS = 5 V, EN = 5 V, VOTG_IN = 0V
VBUS = 5.5 V, EN = 5 V, VOTG_IN = 5 V
11
30
32
10
1
Measured at
VOTG_IN
IOTG_OFF
Standby Leakage current
Reverse Leakage current
IBUS_REV
6
TON
Turn-ON time
Turn-OFF time
Turn-OFF time
Output rise time
Output fall time
RL = 100 Ω, CL = 1 uF, RADJ = 75 kΩ
16
80
0.5
137
1.6
TOFF_EN
TOFF_OTG
TRISE
RL = 100 Ω, CL = 1 uF, RADJ = 75 kΩ, toggle EN
RL = 100 Ω, CL = 1 uF, RADJ = 75 kΩ, toggle VOTG_IN
RL = 100 Ω, CL = 1 uF, RADJ = 75 kΩ
µs
µs
TFALL
RL = 100 Ω, CL = 1 uF, RADJ = 75 kΩ
µs
(1) RDS_ON is measured at 25°C
ELECTRICAL CHARACTERISTICS FOR CURRENT LIMIT and SHORT CIRCUIT PROTECTION
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RADJ = 226 kΩ(1)
MIN
235
TYP
255
MAX UNIT
281
RADJ = 75 kΩ(1)
RADJ = 62 kΩ(1)
RADJ = 45 kΩ(1)
735
792
830
mA
Current−limit threshold
(maximum DC output current
IOUT delivered to load)
IOCP
VOTG_IN = 5 V
885
959
1005
1128
1200
1363
RL = 1 Ω, CL = 1 uF,
RADJ = 75 kΩ
TBLANK
Blanking time after enable
VOTG_IN = 5 V
4
ms
TDEGL
Deglitch time while enabled
Response time to short circuit
9.4
10
ms
µs
TDET_SC
VOTG_IN = 5 V, RL = 100 Ω,
CL = 1 uF, RADJ = 75 kΩ,
apply short to ground
Hiccup pulse width; auto-
retry time
TREG
Short circuit regulation time
13
ms
Short circuit over current
protection time
TOCP
Hiccup pulse period
153
4
ms
V
VSHORT
IINRUSH
Short circuit threshold
See Figure 5 under test
configuration
RL = 100 Ω, CL = 22 µF,
RADJ = 75 kΩ
Inrush current during a startup
726
mA
(1) External resistor tolerance is ±1%
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ELECTRICAL CHARACTERISTICS FOR REVERSE VOLTAGE PROTECTION
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VBUS > VOTG_IN
MIN
TYP
50
MAX UNIT
VREV
Reverse-voltage comparator trip point (at VBUS port)
mV
ms
TRRVP
Time from reverse-voltage condition to MOSFET switch off
and FLG = low
17.5
TRREV
Re-arming time
25
µs
SUPPLY CURRENT CONSUMPTION
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOTG_IN = 5 V, No load on VBUS
EN = 5 V
TYP
162
150
MAX UNIT
,
High-level VOTG_IN operating current
IVOTG_INON
RADJ = 75 kΩ
RADJ = 226 kΩ
200
200
µA
µA
consumption
THERMAL SHUTDOWN
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
141
125
16
MAX UNIT
TSHDN+
TSHDN–
THYST
PMAX
Shutdown temp rising
ºC
ºC
ºC
Shutdown temp falling
Thermal-shutdown Hysteresis
Maximum power dissipation
Junction Temp at max power dissipation
0.16
150
W
VOTG_IN = 5 V, Rload = 5 Ω, EN = 5 V, RADJ = 75 KΩ
TJMAX
ºC
APPLICATION DIAGRAM
OTG 5 V
Source
System Side Supply
(1.8 V to 3.6 V)
C
*
OTG
V
OTG_IN
ADJ
USB Connector
V
V
BUS
BUS
TPD4S214
D+
D–
D+
D–
USB Controller
+
Detection
DET
ID
ID
FLT\
EN
GND
C
*
BUS
Figure 2. USB2.0 Application Diagram Without Using On-chip VBUS Detect
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OTG 5 V
Source
C
*
OTG
System Side Supply
(1.8 V to 3.6 V)
V
OTG_IN
ADJ
USB Connector
V
V
BUS
BUS
TPD4S214
D+
D–
D+
D–
DET
USB Controller
ID
ID
FLT\
EN
GND
C
*
BUS
Figure 3. USB 2.0 Application Diagram Using On-chip VBUS Detect
OTG 5 V
Source
System Side Supply
(1.8 V to 3.6 V)
C
*
OTG
V
OTG_IN
ADJ
USB Connector
TX+
V
V
BUS
BUS
TX–
TPD4S214
D–
D+
D–
GND
D+
USB Controller
+
Detection
DET
RX+
GND
ID
FLT\
EN
RX–
C
*
BUS
*CBUS and COTG have minimum recommended values of 1 µF each
Figure 4. USB 3.0 Application Diagram Without Using On-chip VBUS Detect
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TEST CONFIGURATION
TPD4S214
V
V
OTG_IN
BUS
R
LOAD
C
LOAD
C
IN
EN
ADJ
75 kΩ
Figure 5. Inrush Current Test Configuration.
Enable is toggled from low to high. See the Application Information section for CIN and CLOAD value
recommendations.
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TYPICAL CHARACTERISTICS
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
400
350
300
250
200
150
100
50
œ40°C
25°C
85°C
250mA
500mA
0
0
50
100
150
200
250
300
350
400
œ40
œ20
0
20
40
60
80
C001
C002
RADJ (kꢀ)
Temperature (°C)
Figure 6. IOCP vs. RADJ
Figure 7. 3RDSON vs. Temperature
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
6.0
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
œ0.5
Votgin
Vbus
Iotgin
Votgin
Vbus
Iotgin
œ0.2
œ15
0
15
30
45
60
75
90
105 120
œ2
0
2
4
6
8
10
12
14
16
C003
C004
Time (ꢀs)
Time (ꢀs)
Figure 8. Inrush, RADJ = 75 kΩ
Figure 9. 10 Ω Load to Short, 2 µs
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
œ0.5
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
œ0.5
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Votgin
Vbus
Iotgin
Votgin
Vbus
Iotgin
œ0.2
œ0.2
œ20
0
20
40
60
80
100
œ5
0
5
10
Time (ms)
15
20
C005
C006
Time (ꢀs)
Figure 10. 10 Ω Load to Short, 20 µs
Figure 11. 10 Ω Load to Short, 5 ms
10
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TYPICAL CHARACTERISTICS (continued)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
œ0.2
3
0
œ3
œ6
Votgin
Vbus
Iotgin
œ9
œ12
œ15
œ18
œ21
œ24
œ27
œ0.5
œ100
0
100
200
300
400
500
1M
œ15
œ5
10M
100M
1G
10G
C007
Time (ms)
C008
Frequency (Hz)
Figure 12. 10 Ω Load to Short, 100 ms
Figure 13. Data Line Insertion Loss
70
60
50
40
30
20
10
0
20
10
ID
D+
Dœ
ID
D+
Dœ
0
œ10
œ20
œ30
œ40
œ50
œ60
œ70
œ10
œ20
œ15
0
15 30 45 60 75 90 105 120 135 150 165 180
0
15 30 45 60 75 90 105 120 135 150 165 180
C009
C010
Time (ns)
Time (ns)
Figure 14. +8 kV Contact, 1 GHz
Figure 15. -8 kV Contact, 1 GHz
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
7
6
5
4
3
2
1
0
VBUS
EN
FLT
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
5
10
15
20
25
C011
C012
VBIAS (V)
Time (ms)
Figure 16. CIO vs. VBIAS, f = 1 MHz
Figure 17. TPD4S214 Turn On Characteristics
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TYPICAL CHARACTERISTICS (continued)
6
5
4
3
2
1
0
6
5
4
3
2
1
0
VBUS
EN
FLT
VBUS
VOTG
FLT
œ25
0
25
50
75 100 125 150 175 200 225
0
10
20
30
40
50
60
70
80
C013
C014
Time (ꢀs)
Time (ms)
Figure 18. TPD4S214 Turn Off Characteristics
Figure 19. UVLO
10
9
8
7
6
5
4
3
2
1
0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
VBUS
VOTG
FLT
VBUS
DET
0
25
50
75
100
125
150
175
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
C015
C016
Time (ms)
Time (ms)
Figure 20. OVLO
Figure 21. VBUS Valid Detect Upper
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VBUS
DET
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
C017
Time (ms)
Figure 22. VBUS Valid Detect Lower
Figure 23. Eye Diagram with no EVM and no IC, Full USB2.0
Speed at 480 Mbps
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SLVSBR1A –JANUARY 2013–REVISED FEBRUARY 2013
TYPICAL CHARACTERISTICS (continued)
Figure 24. Eye Diagram with TPD4S214EVM but no IC, Full
USB2.0 Speed at 480 Mbps
Figure 25. Eye Diagram with TPD4S214EVM and IC, Full
USB2.0 Speed at 480 Mbps
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SLVSBR1A –JANUARY 2013–REVISED FEBRUARY 2013
www.ti.com
APPLICATION INFORMATION
A USB OTG device’s one and only connector is the AB receptacle, which accepts either an A or B plug. When
an A-plug is inserted, the OTG device is called the A-device and when a B-plug is inserted it is called the B-
device. A-device is often times referred to as “Targeted Host” and B-device as “USB peripheral”. TPD4S214
supports an OTG device when TPD4S214’s system is acting as an A-device and powering the USB interface.
The TPD4S214 may also be used in non-OTG applications where it resides on the current source side.
Inrush Current Protection
As soon as TPD4S214 is enabled, its logic block detects the presence of any fault conditions highlighted in
Table 1. In the absence of any fault condition, a counter waits for 16 ms, after which a trickle charge of 1 µA
slowly turns on the main switch. During the inrush period, the peak inrush current will be limited to no more than
the current limit set by the external resistor RADJ
.
INPUT CAPACITOR (OPTIONAL)
To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a
discharged load capacitor or short-circuit, a capacitor needs to be placed between VOTG_IN and GND. A 10-μF
ceramic capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further
reduce the voltage drop during high-current application. When switching heavy loads, it is recommended to have
an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop.
OUTPUT CAPACITOR (OPTIONAL)
Due to the integrated body diode in the NMOS switch, a CIN greater than CLOAD is highly recommended. A CLOAD
greater than CIN can cause VBUS to exceed VOTG_IN when the system supply is removed. A CIN to CLOAD ratio of
10 to 1 is recommended for minimizing VOTG_IN dip caused by inrush currents during startup.
Current Limit
The TPD4S214 provides current limiting function, which is set by an external resistor connected from the ADJ pin
to ground shown in Figure 26. The current limiting threshold IOCP is set by the external resistor RADJ. Figure 6
shows the minimum, typical, and maximum current limit for a corresponding RADJ value with ±1% tolerance.
ADJ
R
ADJ
TPD4S214
Figure 26.
55.358
=
RADJ
Where:
IOCP
(1)
RADJ = external resistor used to set the current limit (kΩ)
IOCP = current limit set by the external RADJ resistor (A)
RADJ is placed between the ADJ pin and ground, shown in the figure above, providing a minimum current limit
between 250 mA and 1.2 A.
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SLVSBR1A –JANUARY 2013–REVISED FEBRUARY 2013
VBUS Detection
There are several important protocols defined in [OTG and EH Supplement] that governs communication
between Targeted Hosts (A-device) and USB peripherals (B-device). Communication between host and
peripheral is usually done on the ID pin only. In case when two OTG devices that could both act as either host or
peripheral are connected, measuring voltage level on VBUS will aid in the handshaking process. If an embedded
host instead of a USB device is connected to the OTG device, OTG charging would not be required and the
system’s OTG source should remain off to conserve power. The TPD4S214 VBUS detection block aids power
conservation and is powered from VBUS. See figure 3. The DET pin is an open drain PMOS output with default
state low.
In the event when an A-plug is attached, the system detects ID pin as FALSE, in which case ID pin resistance to
ground is less than 10 Ω. For a B-plug, the system detects ID pin as TRUE and ID pin resistance to ground is
greater than 100 kΩ. For the system to power a USB device through OTG switch once it is connected, voltage on
VBUS should remain below VBUS_VALID MIN within TA_VBUS_ATT of the ID pin becoming FALSE. After this event, the
system confirms that the USB device requires power and enables both TPD4S214 and OTG source. However, if
VBUS_VALID is detected on VBUS within TA_VBUS_ATT of the ID pin becoming FALSE, there is either a system error or
the device connected does not require charging. OTG source remains switched off and the entire sequence
would restart when the system detects another FALSE on the ID pin.
Table 3. VBUS Detection scheme
EN
X
VOTG_IN (VBUS Detect Power)
VBUS
DET
H
Condition
X
X
VBUS_VALID- < VBUS < VBUS_VALID
+
VBUS within VBUS_VALID
VBUS outside of VBUS_VALID
X
VBUS_VALID- > VBUS or VBUS > VBUS_VALID
+
L
Figure 27 and Figure 28 shows suggested system level timing diagram for detecting VBUS according to [OTG and
EH Supplement]. Figure 3 shows the application diagram. In Figure 27, DET pin remains low after ID pin
becomes FALSE, indicating there is not an active voltage source on VBUS. The USB controller proceeds to turn
on OTG 5V source and the TPD4S214 respectively; this sequence is recommended because TPD4S214 is
powered through the OTG source. After a period of tON, current starts to flow through the OTG switch and VBUS is
ramped to the voltage level of VOTG_IN
.
TA_VBUS_ATT
TON
ID Pin
HIGH
LOW
HIGH
VBUS Pin
DET Pin
LOW
HIGH
LOW
HIGH
OTG 5V Source
LOW
HIGH
LOW
TPD4S214 EN
Figure 27. Timing Diagram for Valid USB Device
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In Figure 28, DET pin toggles high after an active voltage is detected on VBUS within TA_VBUS_ATT. This indicates
that the USB device attached is not suitable for OTG charging and both OTV 5V source and TPD4S214 remain
off.
TA_VBUS_ATT
ID Pin
HIGH
LOW
HIGH
VBUS_VALID MIN
VBUS Pin
DET Pin
LOW
TDET_DELAY
HIGH
LOW
HIGH
OTG 5V Source
LOW
HIGH
TPD4S214 EN LOW
Figure 28. System Level Timing Diagram for invalid USB Device
Related Documents
OTG and EH Supplement] On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification,
July 14th, 2011. www.usb.org
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
TPD4S214AYFFR
TPD4S214YFFR
PREVIEW
ACTIVE
DSBGA
DSBGA
YFF
12
12
3000
3000
TBD
Call TI
Call TI
-40 to 85
-40 to 85
YFF
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD4S214YFFR
DSBGA
YFF
12
3000
180.0
8.4
1.48
1.78
0.69
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YFF 12
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TPD4S214YFFR
3000
Pack Materials-Page 2
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