首页 > 电信电路 > 网络接口 > TPIC1021AQDRQ1

TPIC1021AQDRQ1

更新时间：2025-06-28 12:31:53
品牌：TI
描述：LIN PHYSICAL INTERFACE

PDF下载

中文翻译

CAD模型

免费 PCB/SMT

TPIC1021AQDRQ1 概述

LIN PHYSICAL INTERFACE LIN物理接口 接口芯片 网络接口

TPIC1021AQDRQ1 规格参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：SOIC
包装说明：SOP, SOP8,.24针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：7.95Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：4084
Samacsys Pin Count：8Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Small Outline PackagesSamacsys Footprint Name：D (R-PDSO-G8)
Samacsys Released Date：2015-04-16 09:48:08Is Samacsys：N
数据速率：20 MbpsJESD-30 代码：R-PDSO-G8
JESD-609代码：e4长度：4.905 mm
湿度敏感等级：1功能数量：1
端子数量：8收发器数量：1
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.24封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.75 mm
最大压摆率：7.5 mA标称供电电压：14 V
表面贴装：YES电信集成电路类型：INTERFACE CIRCUIT
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.895 mmBase Number Matches：1

TPIC1021AQDRQ1 数据手册

通过下载TPIC1021AQDRQ1数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

PDF下载
TPIC1021A-Q1  
www.ti.com.......................................................................................................................................................... SLIS117A–AUGUST 2007–REVISED JUNE 2009  
LIN PHYSICAL INTERFACE  
1
FEATURES  
•
LIN Physical Layer Specification Revision 2.0  
Compliant and Conforms to SAEJ2602  
Recommended Practice for LIN  
•
•
•
•
Dominant State Timeout Protection  
Wake-Up Request on RXD Pin  
Control of External Voltage Regulator (INH Pin)  
•
•
LIN Bus Speed up to 20-kbps LIN Specified  
Maximum  
Integrated Pullup Resistor and Series Diode  
for LIN Slave Applications  
Sleep Mode: Ultralow Current Consumption,  
Allows Wake-Up Events From LIN Bus,  
Wake-Up Input (External Switch), or Host MCU  
•
•
Low Electromagnetic Emission (EME), High  
Electromagnetic Immunity (EMI)  
Bus Terminal Short Circuit Protected for  
Short to Battery or Short to Ground  
•
•
High-Speed Receive Capable  
ESD Protection to ±12 kV (Human-Body Model)  
on LIN Pin  
•
•
Thermally Protected  
Ground Disconnection Fail Safe at System  
Level  
•
•
LIN Pin Handles Voltage From –40 V to 40 V  
Survives Transient Damage in Automotive  
Environment (ISO 7637)  
•
•
Ground Shift Operation at System Level  
Unpowered Node Does Not Disturb the  
Network  
•
•
Extended Operation With Supply From 7 V to  
27 V DC (LIN Specification 7 V to 18 V)  
•
Supports ISO9141 (K-Line)-Like Functions  
Interfaces to MCU With 5-V or 3.3-V I/O Pins  
FUNCTIONAL BLOCK DIAGRAM  
TPIC1021A  
INH  
VSUP  
RXD  
EN  
V
SUP  
/2  
Receiver  
Filter  
V
SUP  
Wake Up, State,  
and INH Control  
NWake  
Filter  
Fault  
Detection  
and Protection  
LIN  
Driver  
With Slope  
Control  
GND  
Dominant  
State  
Timeout  
TXD  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2009, Texas Instruments Incorporated  
TPIC1021A-Q1  
SLIS117A–AUGUST 2007–REVISED JUNE 2009.......................................................................................................................................................... www.ti.com  
DESCRIPTION  
The TPIC1021A is the Local Interconnect Network (LIN) physical interface, which integrates the serial transceiver  
with wake-up and protection features. The LIN bus is a single-wire bidirectional bus typically used for low-speed  
in-vehicle networks using data rates between 2.4 kbps and 20 kbps. The LIN protocol output data stream on TXD  
is converted by the TPIC1021A into the LIN bus signal through a current-limited wave-shaping driver as outlined  
by the LIN Physical Layer Specification Revision 2.0. The receiver converts the data stream from the LIN bus  
and outputs the data stream via RXD. The LIN bus has two states: dominant state (voltage near ground) and the  
recessive state (voltage near battery). In the recessive state, the LIN bus is pulled high by the TPIC1021A’s  
internal pullup resistor (30 kΩ) and series diode, so no external pullup components are required for slave  
applications. Master applications require an external pullup resistor (1 kΩ) plus a series diode per the LIN  
specification.  
In sleep mode, the TPIC1021A requires low quiescent current even though the wake-up circuits remain active,  
allowing for remote wake up via the LIN bus or local wake up via the NWake or EN pins.  
The TPIC1021A has been designed for operation in the harsh automotive environment. The device can handle  
LIN bus voltage swings from 40 V down to ground and survive –40 V. The device also prevents back-feed  
current through LIN to the supply input, in case of a ground shift or supply voltage disconnection. It also features  
undervoltage, overtemperature, and loss-of-ground protection. In the event of a fault condition, the output is  
immediately switched off and remains off until the fault condition is removed.  
TERMINAL FUNCTIONS  
D PACKAGE  
(TOP VIEW)  
RXD  
EN  
NWake  
TXD  
INH  
1
2
3
4
8
7
6
5
VSUP  
LIN  
GND  
TERMINAL ASSIGNMENTS  
PIN  
TYPE  
DESCRIPTION  
NAME  
RXD  
NO.  
1
O
RXD output (open drain) interface reporting state of LIN bus voltage  
Enable input  
EN  
2
I
NWake  
TXD  
GND  
LIN  
3
I
I
High voltage input for device wake up  
4
TXD input interface to control state of LIN output  
Ground  
5
GND  
I/O  
6
LIN bus single-wire transmitter and receiver  
Device supply voltage (connected to battery in series with external reverse blocking diode)  
Inhibit controls external voltage regulator with inhibit input  
VSUP  
INH  
7
Supply  
O
8
ORDERING INFORMATION(1)  
PART NUMBER  
PACKAGE(2)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
TPIC1021A-Q1  
SOIC-8 – D  
TPIC1021AQDRQ1 (reel)  
T1021A  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
2
Submit Documentation Feedback  
Copyright © 2007–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPIC1021A-Q1  
TPIC1021A-Q1  
www.ti.com.......................................................................................................................................................... SLIS117A–AUGUST 2007–REVISED JUNE 2009  
Local Interconnect Network (LIN) Bus  
This I/O pin is the single-wire LIN bus transmitter and receiver.  
Transmitter Characteristics  
The driver is a low-side transistor with internal current limitation and thermal shutdown. There is an internal  
30-kΩ pullup resistor with a serial diode structure to VSUP, so no external pullup components are required for LIN  
slave mode applications. An external pullup resistor of 1 kΩ, plus a series diode to VSUP must be added when the  
device is used for master node applications.  
Voltage on LIN can go from –40-V to 40-V dc without any currents other than through the pullup resistance.  
There are no reverse currents from the LIN bus to supply (VSUP), even in the event of a ground shift or loss of  
supply (VSUP).  
The LIN thresholds and ac parameters are LIN Protocol Specification Revision 2.0 compliant.  
During a thermal shut down condition the driver is disabled.  
Receiver Characteristics  
The receiver’s characteristic thresholds are ratio-metric with the device supply pin. Typical thresholds are 50%,  
with a hysteresis between 5% and 17.5% of supply.  
The receiver is capable of receiving higher data rates (>100 kbps) than supported by LIN or SAEJ2602  
specifications. This allows the TPIC1021A to be used for high-speed downloads at end-of-line production or  
other applications. The actual data rates achievable depend on system time constants (bus capacitance and  
pullup resistance) and driver characteristics used in the system.  
Transmit Input (TXD)  
TXD is the interface to the MCU’s LIN protocol controller or SCI/UART used to control the state of the LIN output.  
When TXD is low, the LIN output is dominant (near ground). When TXD is high, the LIN output is recessive (near  
battery). The TXD input structure is compatible with microcontrollers with 3.3-V and 5-V I/O. TXD has an internal  
pulldown resistor.  
TXD Dominant State Timeout  
If TXD is inadvertently driven permanently low by a hardware or software application failure, the LIN bus is  
protected by TPIC1021A’s dominant state timeout timer. This timer is triggered by a falling edge on TXD. If the  
low signal remains on TXD for longer than tDST, the transmitter is disabled, thus allowing the LIN bus to return to  
the recessive state and communication to resume on the bus. The timer is reset by a rising edge on TXD.  
Receive Output (RXD)  
RXD is the interface to the MCU’s LIN protocol controller or SCI/UART, which reports the state of the LIN bus  
voltage. LIN recessive (near battery) is represented by a high level on RXD and LIN dominant (near ground) is  
represented by a low level on RXD. The RXD output structure is an open-drain output stage. This allows the  
TPIC1021A to be used with 3.3-V and 5-V I/O microcontrollers. If the microcontroller’s RXD pin does not have an  
integrated pullup, an external pullup resistor to the microcontroller I/O supply voltage is required.  
RXD Wake-up Request  
When the TPIC1021A has been in low-power mode and encounters a wake-up event from the LIN bus or NWake  
pin, RXD goes low, while the device enters and remains in standby mode (until EN is reasserted high and the  
device enters normal mode).  
Supply Voltage (VSUP  
)
VSUP is the TPIC1021A device power supply pin. VSUP is connected to the battery through an external reverse  
battery blocking diode. The characterized operating voltage range for the TPIC1021A is from 7 V to 27 V. VSUP is  
protected for harsh automotive conditions up to 40 V.  
The device contains a reset circuit to avoid false bus messages during undervoltage conditions when VSUP is less  
than VSUP_UNDER  
.
Copyright © 2007–2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): TPIC1021A-Q1  
TPIC1021A-Q1  
SLIS117A–AUGUST 2007–REVISED JUNE 2009.......................................................................................................................................................... www.ti.com  
Ground (GND)  
GND is the TPIC1021A device ground connection. The TPIC1021A can operate with a ground shift as long as  
the ground shift does not reduce VSUP below the minimum operating voltage. If there is a loss of ground at the  
ECU level, the TPIC1021A does not have a significant current consumption on LIN bus.  
Enable Input (EN)  
EN controls the operation mode of the TPIC1021A (normal or sleep mode). When EN is high, the TPIC1021A is  
in normal mode allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low the device  
is put into sleep mode and there are no transmission paths available. The device can enter normal mode only  
after being woken up. EN has an internal pulldown resistor to ensure the device remains in low-power mode  
even if EN floats.  
NWake Input (NWake)  
NWake is a high-voltage input used to wake up the TPIC1021A from low-power mode. NWake is usually  
connected to an external switch in the application. A low on NWake that is asserted longer than the filter time  
(tNWAKE) results in a local wake-up. NWake provides an internal pullup source to VSUP  
.
Inhibit Output (INH)  
INH is used to control an external voltage regulator that has an inhibit input. When the TPIC1021A is in normal  
operating mode, the inhibit high-side switch is enabled and the external voltage regulator is activated. When  
TPIC1021A is in low-power mode, the inhibit switch is turned off, which disables the voltage regulator. A wake-up  
event on for the TPIC1021A returns INH to VSUP level. INH can also drive an external transistor connected to an  
MCU interrupt input.  
4
Submit Documentation Feedback  
Copyright © 2007–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPIC1021A-Q1  
TPIC1021A-Q1  
www.ti.com.......................................................................................................................................................... SLIS117A–AUGUST 2007–REVISED JUNE 2009  
OPERATING STATES  
Unpowered System  
V
sup £ Vsup_under  
Vsup £ Vsup_under  
Vsup > Vsup_under  
EN = high  
V
sup £ Vsup_under  
Vsup £ Vsup_under  
Vsup > Vsup_under  
EN = low  
Standby Mode  
Driver : Off  
RXD: Low  
INH: High (On)  
Termination: 30 kW  
Sleep Mode  
Normal Mode  
LIN Bus Wake-Up  
or  
Nwake Pin Wake-Up  
EN = high  
Driver : Off  
RXD: Floating  
INH: High impedance (Off)  
Termination:Weak pullup  
Driver : On  
RXD: LIN bus data  
INH: High (On)  
Termination: 30 kW  
EN = low  
EN = high  
Figure 1. Operating States Diagram  
Table 1. Operating Modes  
LIN BUS  
INH  
MODE  
Sleep  
EN  
Low  
Low  
High  
RXD  
Floating  
Low  
TRANSMITTER  
Off  
COMMENTS  
TERMINATION  
Weak current pullup High impedance  
Wake-up event detected, waiting  
on MCU to set EN  
Standby  
Normal  
30 kΩ (typ)  
30 kΩ (typ)  
High  
High  
Off  
On  
LIN bus data  
LIN transmission up to 20 kbps  
Normal Mode  
This is the normal operational mode, in which the receiver and driver are active, and LIN transmission up to the  
LIN specified maximum of 20 kbps is supported. The receiver detects the data stream on the LIN bus and  
outputs it on RXD for the LIN controller, where recessive on the LIN bus is a digital high, and dominate on the  
LIN bus is digital low. The driver transmits input data on TXD to the LIN bus. Normal mode is entered as EN  
transitions high while the TPIC1021A is in sleep or standby mode.  
Sleep Mode  
Sleep mode is the power saving mode for the TPIC1021A and the default state after power up (assuming EN is  
low during power up). Even with the extremely low current consumption in this mode, the TPIC1021A can still  
wake up from LIN bus via a wake-up signal, a low on NWake, or if EN is set high. The LIN bus and NWake are  
filtered to prevent false wake-up events. The wake-up events must be active for their respective time periods  
(tLINBUS, tNWake).  
The sleep mode is entered by setting EN low.  
Copyright © 2007–2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): TPIC1021A-Q1  
TPIC1021A-Q1  
SLIS117A–AUGUST 2007–REVISED JUNE 2009.......................................................................................................................................................... www.ti.com  
While the device is in sleep mode, the following conditions exist:  
•
The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if  
LIN is short circuited to ground). However, the weak current pullup is active to prevent false wake-up events  
in case an external connection to the LIN bus is lost.  
•
•
•
The normal receiver is disabled.  
INH is high impedance.  
EN input, NWake input, and the LIN wake-up receiver are active.  
Wake-Up Events  
There are three ways to wake up the TPIC1021A from sleep mode:  
•
Remote wake-up via recessive (high) to dominant (low) state transition on LIN bus. The dominant state must  
be held for tLINBUS filter time and then the bus must return to the recessive state (to eliminate false wake-ups  
from disturbances on the LIN bus or if the bus is shorted to ground).  
•
•
Local wake-up via a low on NWake, which is asserted low longer than the filter time tNWake (to eliminate false  
wake-ups from disturbances on NWake)  
Local wake-up via EN being set high  
Standby Mode  
This mode is entered whenever a wake-up event occurs via LIN bus or NWake while the TPIC1021A is in sleep  
mode. The LIN bus slave termination circuit and INH are turned on when standby mode is entered. The  
application system powers up once INH is turned on, assuming the system is using a voltage regulator  
connected via INH. Standby mode is signaled via a low level on RXD.  
When EN is set high while the TPIC1021A is in standby mode the device returns to normal mode and the normal  
transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.  
EN  
V
sup  
INH  
High Impedance  
TXD  
t > t  
go_to_operate  
V
sup  
LIN  
Floating  
Sleep  
RXD  
Normal  
MODE  
Figure 2. Wake-Up Via EN  
6
Submit Documentation Feedback  
Copyright © 2007–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPIC1021A-Q1  
 
TPIC1021A-Q1  
www.ti.com.......................................................................................................................................................... SLIS117A–AUGUST 2007–REVISED JUNE 2009  
LIN  
0.6 × V  
0.6 × V  
SUP  
SUP  
V
sup  
0.4 × V  
0.4 × V  
SUP  
SUP  
t < t  
t
LINBUS  
LINBUS  
V
sup  
High Impedance  
INH  
TXD  
EN  
t > t  
go_to_operate  
Floating  
Sleep  
RXD  
Standby  
MODE  
Normal  
Figure 3. Wake-Up Via LIN  
Copyright © 2007–2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
Product Folder Link(s): TPIC1021A-Q1  
 
TPIC1021A-Q1  
SLIS117A–AUGUST 2007–REVISED JUNE 2009.......................................................................................................................................................... www.ti.com  
NWake V  
NWake V  
IH  
IL  
NWake V  
IL  
NWake  
V
sup  
t < t  
t
NWake  
NWake  
V
sup  
High Impedance  
INH  
TXD  
t > t  
go_to_operate  
EN  
Floating  
RXD  
V
sup  
LIN  
Normal  
MODE  
Sleep  
Standby  
Figure 4. Wake-Up Via NWake  
8
Submit Documentation Feedback  
Copyright © 2007–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPIC1021A-Q1  
 
TPIC1021A-Q1  
www.ti.com.......................................................................................................................................................... SLIS117A–AUGUST 2007–REVISED JUNE 2009  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
RATING  
0 to 40  
UNIT  
(2)  
VSUP  
Supply line supply voltage(3)  
V
VNWake  
INWake  
VINH  
NWake dc and transient input voltage (through 33-kΩ serial resistor)  
–0.3 to 40  
NWake current if due to ground shifts VNWake ≤ VGND - 0.3V, thus the current into NWake must  
-3.6 mA be limited via a serial resistance.  
-3.6  
mA  
V
INH voltage  
–0.3 to VSUP + 0.3  
–0.3 to 5.5  
–40 to 40  
–12 to 12  
–11 to 11  
–4 to 4  
Logic pin input voltage  
LIN dc-input voltage  
RXD, TXD, EN  
VLIN  
LIN(4)  
Human-Body Model  
Charge-Device Model  
NWake(4)  
All other pins(4)  
All pins(5)  
kV  
V
Electrostatic discharge  
–1500 to 1500  
–40 to 125  
–40 to 150  
–40 to 165  
145  
TA  
Operational free-air temperature range  
Junction temperature range  
Storage temperature range  
TJ  
°C  
Tstg  
RθJA  
Thermal resistance, junction to ambient  
Thermal shutdown  
°C/W  
°C  
200  
Thermal shutdown hysteresis  
25  
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings  
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating  
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to GND.  
(3) The device is specified for operation in the range of VSUP from 7 V to 27 V. Operating the device above 27 V may significantly raise the  
junction temperature of the device and system level thermal design needs to be considered.  
(4) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.  
(5) Tested in accordance to JEDEC Standard 22, Test Method C101 (JESD22-C101).  
Copyright © 2007–2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
9
Product Folder Link(s): TPIC1021A-Q1  
TPIC1021A-Q1  
SLIS117A–AUGUST 2007–REVISED JUNE 2009.......................................................................................................................................................... www.ti.com  
ELECTRICAL CHARACTERISTICS  
VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP(1)  
MAX UNIT  
SUPPLY  
Device is operational beyond the LIN 2.0  
Operational supply voltage(2) defined nominal supply line voltage range  
of 7 V < VSUP < 18 V  
7
14  
27  
V
Normal and standby modes  
Nominal supply line voltage  
7
7
14  
12  
18  
Sleep mode  
18  
VSUP undervoltage threshold  
4.5  
6.2  
Normal mode, EN = High, Bus dominant  
(total bus load where RLIN ≥ 500 Ω and  
C
NWake = VSUP  
1.2  
1
7.5  
2.1  
mA  
mA  
LIN ≤ 10 nF (see Figure 7)(3), INH = VSUP  
,
,
Standby mode, EN = Low, Bus dominant  
(total bus load, where RLIN ≥ 500 Ω and  
C
LIN ≤ 10 nF (see Figure 7)(3), INH = VSUP  
NWake = VSUP  
Normal mode, EN = High, Bus recessive,  
LIN = VSUP, INH = VSUP, NWake = VSUP  
450  
450  
775  
775  
ICC  
Supply current  
µA  
Standby mode, EN = Low, Bus recessive,  
LIN = VSUP, INH = VSUP, NWake = VSUP  
Sleep mode, EN = 0,  
7 V < VSUP ≤ 12 V, LIN = VSUP  
NWake = VSUP  
,
15  
30  
50  
µA  
µA  
Sleep mode, EN = 0,  
12 V < VSUP < 27 V, LIN = VSUP  
NWake = VSUP  
,
RXD OUTPUT PIN  
VO  
IOL  
IIKG  
Output voltage  
–0.3  
3.5  
–5  
5.5  
5
V
Low-level output current,  
open drain  
LIN = 0 V, RXD = 0.4 V  
LIN = VSUP, RXD = 5 V  
mA  
µA  
Leakage current, high-level  
0
TXD INPUT PIN  
VIL  
VIH  
Low-level input voltage  
–0.3  
2
0.8  
5.5  
V
High-level input voltage  
Input threshold hysteresis  
voltage  
VIT  
30  
500  
mV  
Pulldown resistor  
125  
–5  
350  
0
800  
5
kΩ  
µA  
IIL  
Low-level input current  
TXD = Low  
(1) Typical values are given for VSUP = 14 V at 25°C, except for low power mode where typical values are given for VSUP = 12 V at 25°C.  
(2) All voltages are defined with respect to ground; positive currents flow into the TPIC1021A device.  
(3) In the dominant state, the supply current increases as the supply voltage increases due to the integrated LIN slave termination  
resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN  
slave termination is 20 kΩ, so the maximum supply current attributed to the termination is:  
ISUP (dom) max termination ≈ (VSUP – (VLIN_Dominant + 0.7 V) / 20 kΩ  
10  
Submit Documentation Feedback  
Copyright © 2007–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPIC1021A-Q1  
TPIC1021A-Q1  
www.ti.com.......................................................................................................................................................... SLIS117A–AUGUST 2007–REVISED JUNE 2009  
ELECTRICAL CHARACTERISTICS (continued)  
VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP(1)  
MAX UNIT  
LIN PIN (Referenced to VSUP  
)
LIN recessive, TXD = High,  
IO = 0 mA, VSUP = 14 V  
VOH  
High-level output voltage  
VSUP – 1  
0
V
LIN dominant, TXD = Low,  
IO = 40 mA, VSUP = 14 V  
VOL  
Low-level output voltage  
Pullup resistor to VSUP  
0.2 × VSUP  
V
Rslave  
Normal and standby modes  
20  
–2  
45  
–5  
30  
60  
kΩ  
µA  
Pullup current source to VSUP Sleep mode, VSUP = 14 V, LIN = GND  
–20  
IL  
Limiting current  
Leakage current  
TXD = 0 V  
160  
0
250  
mA  
ILKG  
LIN = VSUP  
5
7 V < LIN ≤ 12 V, VSUP = GND  
12 V < LIN < 18 V, VSUP = GND  
LIN dominant  
5
10  
µA  
Leakage current, loss of  
supply  
ILKG  
VIL  
Low-level input voltage  
High-level input voltage  
Input threshold voltage  
Hysteresis voltage  
0.4 × VSUP  
VIH  
VIT  
LIN recessive  
0.6 × VSUP  
0.4 × VSUP  
0.05 × VSUP  
0.5 × VSUP  
0.6 × VSUP  
V
Vhys  
0.175 × VSUP  
Low-level input voltage for  
wake-up  
VIL  
0.4 × VSUP  
EN PIN  
VIL  
Low-level input voltage  
High-level input voltage  
Hysteresis voltage  
–0.3  
2
0.8  
5.5  
500  
800  
5
V
VIH  
Vhys  
30  
mV  
kΩ  
µA  
Pulldown resistor  
125  
–5  
350  
0
IIL  
Low-level input current  
EN = Low  
INH PIN  
Vo  
DC output voltage  
On state resistance  
Leakage current  
–0.3  
–5  
VSUP + 0.3  
V
Ω
Between VSUP and INH, INH = 2-mA drive,  
Normal or standby mode  
Ron  
35  
0
85  
5
IIKG  
Low-power mode, 0 < INH < VSUP  
µA  
NWake PIN  
VIL  
VIH  
Low-level input voltage  
–0.3  
VSUP – 1  
–45  
VSUP – 3.3  
V
High-level input voltage  
Pullup current  
VSUP + 0.3  
NWake = 0 V  
–10  
0
–2  
5
µA  
IIKG  
Leakage current  
VSUP = NWake  
–5  
THERMAL SHUTDOWN  
Shutdown junction thermal  
temperature  
190  
°C  
Copyright © 2007–2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
11  
Product Folder Link(s): TPIC1021A-Q1  
TPIC1021A-Q1  
SLIS117A–AUGUST 2007–REVISED JUNE 2009.......................................................................................................................................................... www.ti.com  
ELECTRICAL CHARACTERISTICS (continued)  
VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP(1)  
MAX UNIT  
AC CHARACTERISTICS  
THREC(max) = 0.744 × VSUP  
,
THDOM(max) = 0.581 × VSUP  
,
VSUP = 7 V to 18 V,  
tBIT = 50 µs (20 kbps),  
D1 = tBus_rec(min)/ (2 × tBIT).  
See Figure 5  
D1  
D2  
D3  
D4  
Duty cycle 1(4)  
Duty cycle 2(4)  
Duty cycle 3(4)  
Duty cycle 4(4)  
0.396  
THREC(min) = 0.422 × VSUP  
,
THDOM(min) = 0.284 × VSUP  
VSUP = 7.6 V to 18 V,  
tBIT = 50 µs (20 kbps),  
,
0.581  
D2 = tBus_rec(max)/ (2 × tBIT).  
See Figure 5  
THREC(max) = 0.778 × VSUP  
,
THDOM(max) = 0.616 × VSUP  
VSUP = 7 V to 18 V,  
tBIT = 96 µs (10.4 kbps),  
D3 = tBus_rec(min)/ (2 × tBIT).  
See Figure 5  
,
0.417  
THREC(min) = 0.389 × VSUP  
,
THDOM(min) = 0.251 × VSUP  
VSUP = 7.6 V to 18 V,  
,
0.59  
tBIT = 96 µs (10.4 kbps),  
D4 = tBus_rec(max)/ (2 × tBIT).  
See Figure 5  
RRXD = 2.4 kΩ, CRXD = 20 pF  
See Figure 6  
See Figure 7  
Receiver rising propagation  
delay time  
trx_pdr  
6
6
RRXD = 2.4 kΩ, CRXD = 20 pF  
See Figure 6  
See Figure 7  
Receiver falling propagation  
delay time  
trx_pdf  
rising edge with respect to falling edge  
(trx_sym = trx_pdf - trx_pdr  
RRXD = 2.4 kΩ, CRXD = 20 pF  
See Figure 6  
)
Symmetry of receiver  
propagation delay time  
µs  
trx_sym  
–2  
25  
2
See Figure 7  
NWake filter time for local  
wake-up  
tNWake  
See Figure 4  
50  
50  
150  
150  
LIN wake-up filter time  
tLINBUS (dominant time for wake-up  
via LIN bus)  
See Figure 3  
25  
tDST  
tgo_to_operate  
Dominant state timeout(5)  
5.5  
20  
1
ms  
See Figure 2 to Figure 3  
0.5  
µs  
(4) Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are  
defined for 10.4-kbps operation. The TPIC1021A also meets these lower data rate requirements, while it is capable of the higher speed  
20-kbps operation as specified by Duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle  
definitions, for details see the SAEJ2602 specification.  
(5) Dominant state timeout limits the minimum data rate to 2.4 kbps.  
12  
Submit Documentation Feedback  
Copyright © 2007–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPIC1021A-Q1  
TPIC1021A-Q1  
www.ti.com.......................................................................................................................................................... SLIS117A–AUGUST 2007–REVISED JUNE 2009  
TIMING DIAGRAMS  
t
Bit  
t
Bit  
RECESSIVE  
DOMINANT  
D = 0.5  
TXD (Input)  
TH  
Rec(max)  
Threshold:s  
Worst case 1  
LIN Bus  
Signal  
TH  
Dom(max)  
V
sup  
TH  
Rec(min)  
Threshold:s  
Worst case 2  
TH  
Dom(min)  
t
t
Bus_dom(max)  
Bus_rec(max)  
D = t /(2 x t )  
Bus_rec(min) Bit  
RXD  
D1 (20 kbps) and  
D3 (10 kbps) case  
t
t
Bus_dom(min)  
Bus_rec(min)  
D = t /(2 x t )  
Bus_rec(max) Bit  
RXD  
D2 (20 kbps) and  
D4 (10 kbps) case  
Figure 5. Definition of Bus Timing Parameters  
Copyright © 2007–2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
13  
Product Folder Link(s): TPIC1021A-Q1  
TPIC1021A-Q1  
SLIS117A–AUGUST 2007–REVISED JUNE 2009.......................................................................................................................................................... www.ti.com  
TIMING DIAGRAMS (continued)  
LIN Bus  
0.6 V  
0.4 V  
SUP  
V
SUP  
SUP  
t
t
rx_pdf  
rx_pdr  
RXD  
50%  
50%  
Figure 6. Propagation Delay  
V
CC  
TPIC1021A  
R
RXD  
RXD  
INH  
C
RXD  
V
SUP  
100 nF  
EN  
R
LIN  
NWake  
LIN  
C
LIN  
TXD  
GND  
Figure 7. Test Circuit for AC Characteristics  
14  
Submit Documentation Feedback  
Copyright © 2007–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPIC1021A-Q1  
TPIC1021A-Q1  
www.ti.com.......................................................................................................................................................... SLIS117A–AUGUST 2007–REVISED JUNE 2009  
APPLICATION INFORMATION  
VBAT  
VSUP  
TPSxxxx  
VSUP  
MASTER  
NODE  
VDD  
NWake  
VSUP  
INH  
VDD  
Master  
Node  
Pullup(3)  
VDD  
EN  
8
2
3
7
I/O  
MCU w/o  
pullup(2)  
VDD I/O  
1 kW  
MCU  
TMS470  
TPIC1021A  
LIN  
Controller  
or  
SCI/UART(1)  
LIN  
1
4
RXD  
TXD  
6
5
220 pF  
GND  
VSUP  
SLAVE  
NODE  
TPSxxxx  
VSUP  
VDD  
NWake  
INH  
VSUP  
VDD  
EN  
8
2
3
7
I/O  
MCU w/o  
pullup(2)  
VDD I/O  
MCU  
TMS470  
TPIC1021A  
LIN  
LIN  
1
4
RXD  
TXD  
6
Controller  
or  
(1)  
SCI/UART  
5
220 pF  
GND  
(1) RXD on MCU or LIN slave has internal pullup, no external pullup resistor is needed.  
(2) RXD on MCU or LIN slave without internal pullup, requires external pullup resistor.  
(3) Master node applications require an external 1-kΩ pullup resistor and serial diode.  
Figure 8.  
Copyright © 2007–2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
15  
Product Folder Link(s): TPIC1021A-Q1  
TPIC1021A-Q1  
SLIS117A–AUGUST 2007–REVISED JUNE 2009.......................................................................................................................................................... www.ti.com  
Device Comparison: TPIC1021 vs TPIC1021A  
The TPIC1021A is pin-to-pin compatible to the TPIC1021 device. The TPIC1021A is an enhanced LIN  
transceiver, including enhanced immunity to RF disturbances. Table 2 is a summary of the differences between  
the two devices.  
Table 2. TPIC1021A vs TPIC1021 Differences  
SPECIFICATION  
LIN termination  
TPIC1021A  
TPIC1021  
High Ω in low-power mode  
Weak current pullup in sleep mode  
Enhanced high-speed receive capable  
LIN receiver  
High-speed receive capable  
LIN leakage current  
(unpowered device):  
<5 µA at 12 V (max)  
<10 µA at 12 V (typ)  
7 V < LIN < 12 V, VSUP = GND  
Remote wake-up via recessive-to-dominant  
transition on LIN bus where dominant bus state  
is held for at least tLINBUS time followed by a  
transition back to the recessive state  
Remote wake-up via recessive-to-dominant  
transition on LIN bus where dominant bus state  
is held for at least tLINBUS time  
LIN bus wake-up  
Low-power current  
INH pin  
<30 µA at 12 V (max)  
<50 µA at 14 V (max)  
Enhanced driving of bus master termination via  
lower Ron  
Driving of bus master termination  
16  
Submit Documentation Feedback  
Copyright © 2007–2009, Texas Instruments Incorporated  
Product Folder Link(s): TPIC1021A-Q1  
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
30-Aug-2010  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
TPIC1021AQDRQ1  
ACTIVE  
SOIC  
D
8
2500  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
Request Free Samples  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale  
supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information  
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or  
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the  
third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration  
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered  
documentation. Information of third parties may be subject to additional restrictions.  
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service  
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.  
TI is not responsible or liable for any such statements.  
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements  
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support  
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which  
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause  
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use  
of any TI components in safety-critical applications.  
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to  
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and  
requirements. Nonetheless, such components are subject to these terms.  
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties  
have executed a special agreement specifically governing such use.  
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in  
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components  
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and  
regulatory requirements in connection with such use.  
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which  
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such  
components to meet such requirements.  
Products  
Applications  
Audio  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Automotive and Transportation www.ti.com/automotive  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
www.ti.com/computers  
www.ti.com/consumer-apps  
www.ti.com/energy  
dsp.ti.com  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
Medical  
Logic  
Security  
www.ti.com/security  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Space, Avionics and Defense  
Video and Imaging  
www.ti.com/space-avionics-defense  
www.ti.com/video  
microcontroller.ti.com  
www.ti-rfid.com  
www.ti.com/omap  
OMAP Applications Processors  
Wireless Connectivity  
TI E2E Community  
e2e.ti.com  
www.ti.com/wirelessconnectivity  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2012, Texas Instruments Incorporated  

TPIC1021AQDRQ1 CAD模型

原理图符号

PCB 封装图

TPIC1021AQDRQ1 替代型号

型号 制造商 描述 替代类型 文档
TPIC1021D TI LIN Physical Interface 完全替代
TPIC1021DR TI LIN Physical Interface 完全替代
TPIC1021DRG4 TI LIN Physical Interface 完全替代

TPIC1021AQDRQ1 相关器件

型号 制造商 描述 价格 文档
TPIC1021D TI LIN Physical Interface 获取价格
TPIC1021DG4 TI LIN Physical Interface 获取价格
TPIC1021DR TI LIN Physical Interface 获取价格
TPIC1021DRG4 TI LIN Physical Interface 获取价格
TPIC1301 TI 3-HALF H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY 获取价格
TPIC1301DW TI 3-HALF H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY 获取价格
TPIC1301DWR TI 2.25A, 60V, 0.275ohm, 6 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-013AD, PLASTIC, SOIC-24 获取价格
TPIC1310 TI 3-HALF H-BRIDGE GATE PROTECTED POWER DMOS ARRAY 获取价格
TPIC1310KTR TI 3-HALF H-BRIDGE GATE PROTECTED POWER DMOS ARRAY 获取价格
TPIC1310KTS TI 3-HALF H-BRIDGE GATE PROTECTED POWER DMOS ARRAY 获取价格

TPIC1021AQDRQ1 相关文章

  • 意法半导体中国市场突围：双供应链战略铸就 “芯” 蓝图
    2025-06-30
    28
  • 小米首款 AI 眼镜正式亮相，芯片市场迎来哪些新机遇？
    2025-06-30
    24
  • 剖析汽车安全气囊控制单元：从拆解看核心技术
    2025-06-30
    18
  • AI 时代算力困局待解，晶圆级芯片潜力无限
    2025-06-30
    41

    • 热门型号

  • 1N5930
  • 1N5942B
  • 1N4001
  • MBR3050CT
  • RTA02-8D
  • 4116T
  • 5KP43A/4
  • 1N5260A
  • MC79L05
  • BZX85C30
  • 9510-G
  • W2PE-54WZ-P
  • 1N6063
  • 2SA673
  • 20IMX35
    • Hi,有什么可以帮您？ 在线客服 或 微信扫码咨询
  • 概述
  • 规格参数
  • 数据手册
  • CAD模型
  • 替代型号
    • 2025 ICPDF网 联系我们和版权申明:QQ 272164286