TPIC1021中文资料_数据手册_规格书

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113–OCTOBER 2004

FEATURES

•

Dominant State Timeout Protection on TXD

•

LIN Physical Layer Specification Revision 2.0

compliant. Conforms to SAEJ2602

Recommended Practice for LIN

•

Wake-Up Request on RXD Pin

Control of External Voltage Regulator (INH

Pin)

•

LIN Bus Speed up to 20 kbps

ESD Protection to 12 kV (Human Body Model)

on LIN Pin

•

Integrated Pull-Up Resistor and Series Diode

for LIN Slave Applications

•

LIN Pin Handles Voltage from -40 V to +40 V

Low EME (Electromagnetic Emissions), High

EMI (Electromagnetic Immunity)

Survives Transient Damage in Automotive

Environment (ISO 7637)

Bus Terminal Short-Circuit Protected for

Short to Battery or Short to Ground

•

Operation with Supply from 7 V to 27 V DC

•

Thermally Protected

Two Operation Modes: Normal and Low

Power (Sleep) Mode

Ground Disconnection Fail Safe at System

Level

•

Low Current Consumption in Low Power

Mode

•

Ground Shift Operation at System Level

Wake-Up Available from LIN Bus, Wake-Up

Input (External Switch) or Host MCU

Unpowered Node Does Not Disturb the

Network

Interfaces to MCU with 5 V or 3.3 V I/O Pins

D PACKAGE

(TOP VIEW)

RXD

EN

NWake

TXD

INH

1

2

3

4

8

7

6

5

V

SUP

LIN

GND

DESCRIPTION

The TPIC1021 is the LIN (Local Interconnect Network) physical interface, which integrates the serial transceiver

with wake up and protection features. The LIN bus is a single wire, bi-directional bus typically used for low-speed

in-vehicle networks using baud rates between 2.4 kbps and 20 kbps.

The LIN bus has two logical values: the dominant state (voltage near ground) represents a logic ‘0’ and the

recessive state (voltage near battery) and represents logic ‘1’.

In the recessive state the LIN bus is pulled high by the TPIC1021’s internal pull-up resistor (30kΩ) and series

diode, so no external pull-up components are required for slave applications. Master applications require an

external pull-up resistor (1kΩ) plus a series diode.

The LIN Protocol output data stream on the TXD pin is converted by the TPIC1021 into the LIN bus signal

through a current limited, wave-shaping low-side driver with control as outlined by the LIN Physical Layer

Specification Revision 2.0. The receiver converts the data stream from the LIN bus and outputs the data stream

via the RXD pin.

In Low Power mode, the TPIC1021 requires very low quiescent current even though the wake-up circuits remain

active allowing for remote wake up via the LIN bus or local wake ups via NWake or EN pins.

The TPIC1021 has been designed for operation in the harsh automotive environment. The device can handle LIN

bus voltage swing from +40 V down to ground and survive -40 V. The device also prevents back feed current

through the LIN pin to the supply input in case of a ground shift or supply voltage disconnection. It also features

under-voltage, over temperature, and loss of ground protection. In the event of a fault condition the output is

immediately switched off and remains off until the fault condition is removed.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the forma-

tive or design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the

right to change or discontinue these products without notice.

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113–OCTOBER 2004

TERMINAL FUNCTIONS

Terminal Assignments

PIN NAME

RXD

PIN NO.

PIN TYPE

DESCRIPTION

1

2

3

4

5

6

7

8

O

RXD output (open drain) pin interface reporting state of LIN bus voltage

Enable input pin

EN

I

NWake

TXD

GND

LIN

I

High voltage input pin for device wake up

TXD input pin interface to control state of LIN output

Ground connection

I

I/O

LIN bus pin single wire transmitter and receiver

V_SUP

INH

Supply

O

Device supply pin (connected to battery in series with external reverse blocking diode)

Inhibit pin controls external voltage regulator with inhibit input

LIN Bus Pin

This I/O pin is the single-wire LIN bus transmitter and receiver.

Transmitter Characteristics

The driver is a low side transistor with internal current limitation and thermal shutdown. There is an internal

30-kΩ pull-up resistor with a serial diode structure to V_supso no external pull-up components are required for LIN

slave mode applications. An external pull-up resistor of 1 kΩ plus a series diode to V_supmust be added when the

device is used for master node applications.

Voltage on the LIN pin can go from -40 V to +40 V DC without any currents other than through the pull-up

resistance. There are no reverse currents from the LIN bus to supply (V_sup), even in the event of a ground shift or

loss of supply (V_sup).

The LIN thresholds and ac parameters are compatible LIN Protocol Specification Revision 2.0.

During a thermal shut down condition the driver is disabled.

Receiver Characteristics

The receiver’s characteristic thresholds are ratio-metric with the device supply pin. Typical thresholds are 50%,

with a hysteresis between 5% and 17.5% of supply.

Transmit Input Pin (TXD)

This pin is the interface to the MCU’s LIN Protocol Controller or SCI/UART used to control the state of the LIN

output. When TXD is low, LIN output is dominant (near ground). When TXD is high, LIN output is recessive (near

battery). TXD input structure is compatible with microcontrollers with 3.3 V and 5.0 V I/O. This pin has an internal

pull-down resistor.

TXD Dominant State Timeout

If the TXD pin is inadvertently driven permanently low by a hardware or software application failure, the LIN bus

is protected by TPIC1021’s Dominant State Timeout Timer. This timer is triggered by a falling edge on the TXD

pin. If the low signal remains on the TXD pin for longer than t_DST, the transmitter is disabled thus allowing the LIN

bus to return to the recessive state and communication to resume on the bus. The timer is reset by a rising edge

on TXD pin.

Receive Output Pin (RXD)

This pin is the interface to the MCU’s LIN Protocol Controller or SCI/UART, which reports the state of the LIN

bus voltage. LIN recessive (near battery) is represented by a high level on RXD and LIN dominant (near ground)

is represented by a low level on RXD. The RXD output structure is an open-drain output stage. This allows the

TPIC1021 to be used with 3.3 V and 5 V I/O microcontrollers. If the microcontroller’s RXD pin does not have an

integrated pull-up, an external pull-up resistor to the microcontroller I/O supply voltage is required.

2

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113–OCTOBER 2004

RXD Wake-up Request

When the TPIC1021 has been in low power mode and encounters a wake-up event from the LIN bus or NWake

pin the RXD pin will go LOW while the device enters and remains in Standby Mode (until EN is re-asserted high

and the device enters Normal Mode).

Supply Voltage (V_SUP

)

The TPIC1021 device power supply pin. This pin is connected to the battery through an external reverse battery

blocking diode. The continuous DC operating voltage range for the TPIC1021 is from 7 V to +27 V. The V_SUPis

protected to for harsh automotive conditions of up to + 40 V.

The device contains a reset circuit to avoid false bus messages during under-voltage conditions when V_SUPis

less than V_{SUP_UNDER}

.

Ground (GND)

TPIC1021 device ground connection. The TPIC1021 can operate with a ground shift as long as the ground shift

does not reduce V_SUPbelow the minimum operating voltage. If there is a loss of ground at the ECU level, the

TPIC1021 will not have a significant current consumption on the LIN pin while in the recessive state (<100 µA

sourced via the LIN pin) and for the dominant state the pull-up resistor should be active.

Enable Input Pin (EN)

The enable input pin controls the operation mode of the TPIC1021 (Normal or Low Power Mode). When enable

is high, the TPIC1021 is in normal mode allowing a transmission path from TXD to LIN and from LIN to RXD.

When the enable input is low, the device is put into low power (sleep) mode and there are no transmission paths.

The device can enter normal operating mode only after being woken up. The enable pin has an internal

pull-down resistor to ensure the device remains in low power mode even if the enable pin floats.

NWake Input Pin (NWake)

The NWake input pin is a high-voltage input used to wake up the TPIC1021 from low power mode. NWake is

usually connected to an external switch in the application. A falling edge on NWake with a low that is asserted

longer than the filter time (t_NWAKE) results in a local wake-up. The NWake pin provides an internal pull-up current

source to V_SUP

.

Inhibit Output Pin (INH)

The inhibit output pin is used to control an external voltage regulator that has an inhibit input. When the

TPIC1021 is in normal operating mode, the inhibit high-side switch is enabled and the external voltage regulator

is activated. When TPIC1021 is in low power mode, the inhibit switch is turned off, which disables the voltage

regulator. A wake-up event on for the TPIC1021 will return the INH pin to V_SUPlevel. The INH pin output current

is limited to 2 mA. The INH pin can also drive an external transistor connected to an MCU interrupt input.

3

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113–OCTOBER 2004

Functional Block Diagram

8

7

INH

V_SUP

1

RXD

V_SUP/2

Receiver

2

EN

Wake−Up

and

Filter

Vreg Control

3

Filter

NWake

Fault

Detection and

Protection

6

5

Dominant

State

Timeout

LIN

GND

4

Driver

TXD

with

Slope Control

OPERATING STATES

Unpowered

System

A: V

B: V

C:V

< V

> V

SUP

SUP_under

, EN = 0

SUP_unde

V

< V

SUP_under

SUP

> V

, EN = 1

SUP_unde

A

Standby

Mode

TXD: off

C

B

RXD: LOW

IHN: HIGH (high

side switched on)

Term: 30 kW

EN = 1

LIN Bus Wake−UP

or

NWake Pin Wake−Up

Low Power

Normal Mode

TXD: on

Mode

TXD: off

RXD: LIN bus data

IHN: HIGH (high

side switched on)

Term: 30 kW

RXD: floating

IHN: high

impedance (high

side switched off)

Term: highW

EN = 0

EN = 1

Figure 1. Operating States Diagram

4

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113–OCTOBER 2004

OPERATING STATES (continued)

Operating Modes

MODE

EN

RXD

Floating

LIN BUS

INH

TRANSMITTER

Off

COMMENTS

TERMINATION

High impedance

30 kΩ (typical)

Low Power

Standby

0

High impedance

High

Low

Off

Wake-up event detected,

waiting on MCU to set EN

Normal

1

LIN bus data

30 kΩ (typical)

High

On

Normal Mode

This is the normal operational mode where the receiver and driver are active. The receiver detects the data

stream on the LIN bus and outputs it on the RXD pin for the LIN controller where recessive on the LIN bus is a

digital high and dominate on the LIN bus is digital low. The driver will transmit input data on the TXD pin to the

LIN bus.

Low Power Mode

The power saving mode for the TPIC1021 and the default state after power-up (assuming EN=0). Even with the

extremely low current consumption in this mode, the TPIC1021 can still wake-up from LIN bus activity, a falling

edge on the NWake pin or if EN is set high. The LIN bus and NWake pins are filtered to prevent false wake-up

events. The wake-up events must be active for their respective time periods: t_LINBUS, t_NWake

.

The low power mode is entered by setting the EN pin low.

While the device is in low power mode the following conditions exist:

•

The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if

LIN is short-circuited to ground).

•

The normal receiver is disabled.

The INH pin is high impedance.

EN input, NWake input and the LIN wake-up receiver are active.

Wake-Up Events

There are three ways to wake-up the TPIC1021 from Low Power Mode.

•

Remote wake-up via recessive (high) to dominant (low) state transition on LIN Bus where dominant bus state

of 50% threshold is detected. The dominant state must be held for t_LINBUSfilter time (to eliminate false wake

ups from disturbances on the LIN Bus).

•

Local wake-up via falling edge on NWake pin which is held low for filter time t_NWake(to eliminate false wake

ups from disturbances on NWake).

Local wake-up via EN being set high

Standby Mode

This mode is entered whenever a wake-up event occurs via the LIN bus or NWake pin while the TPIC1021 is in

low power mode. The LIN bus slave termination circuit and the INH pin are turned on when standby mode is

entered. The application system will power up once the INH pin is turn assuming it is using a voltage regulator

connected via INH pin. Standby Mode is signaled via a low level on RXD pin.

When EN pin is set high while the TPIC1021 is in Standby Mode the device returns to Normal Mode and the

normal transmission paths from TXD to LIN bus and LIN bus to RXD are turned on.

5

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113–OCTOBER 2004

LIN

t

LINBUS

V

SUP

INH

EN

High Impedance

System Wake−Up Time (Vreg + MCU)

Floating

RXD

Low Power

Standby

Normal

MODE

Figure 2. Wake-Up Via LIN Bus Timing Diagram

Falling Edge on NWake

NWake

t

NWake

V

SUP

INH

EN

High Impedance

System Wake−Up Time (Vreg + MCU)

Floating

RXD

Low Power

Standby

Normal

MODE

Figure 3. Wake-Up Via NWake Timing Diagram

6

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113–OCTOBER 2004

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER

RATING

UNIT

V

(2)

V_SUP

Supply line supply voltage (continuous)

Supply line supply voltage (transient)

NWake DC and transient input voltage (through 33-kΩ serial resistor)

Logic pin input voltage (RXD, TXD, EN)

LIN DC input voltage

Electrostatic discharge: Human Body Model: LIN pin⁽³⁾

Electrostatic discharge: Human Body Model: All other pins⁽³⁾

Electrostatic discharge: Machine Model: LIN pin⁽⁴⁾

Electrostatic discharge: Machine Model: All other pins⁽⁴⁾

Operational free-air temperature

0 to 27

0 to 40

V

-1 to 40

V

-0.3 to 5.5

-40 to 40

-12 to 12

-4 to 4

V

kV

V

-400 to 400

-200 to 200

-40 to 125

-40 to 150

-40 to 165

V

T_A

°C

°C/W

°C

T_J

Junction temperature

T_stg

R_θJA

Storage temperature

Thermal resistance, junction-to-ambient

Thermal shutdown

200

25

Thermal shutdown hysteresis

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND.

(3) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

(4) The machine model is a 200-pF capacitor through a 10-Ω resistor and a 0.75-µH coil.

7

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113–OCTOBER 2004

ELECTRICAL CHARACTERISTICS

V_SUP= 7 V to 27 V, T_A= -40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

SUPPLY

Operational supply voltage⁽²⁾

Nominal supply line voltage⁽²⁾

V_SUPundervoltage threshold⁽²⁾

Supply Current

7

14

27

18

V

4.5

1.2

V

I_CC

Normal Mode, EN = 1, Bus domi-

2.5

2.1

500

50

mA

nant (total bus load > 500 Ω)⁽³⁾

Standby Mode, EN = 0, Bus domi-

1

300

20

mA

µA

nant (total bus load > 500 Ω)⁽³⁾

Normal Mode, EN = 1, Bus recess-

ive

Standby Mode, EN = 0, Bus recess-

ive

Low Power Mode, EN = 0, V_SUP

14 V, NWake = V_SUP

<

Low Power Mode, EN = 0, 14 V <

V_SUP< 27 V, NWake = V_SUP

50

100

RXD OUTPUT PIN

V_O

I_OL

I_IKG

Output voltage

Low-level output current, open drain LIN = 0 V, RXD = 0.4 V

Leakage current, high-level LIN = V_SUP, RXD = 5 V

-0.3

3.5

-5

5.5

5

V

mA

µA

0

TXD INPUT PIN

V_IL

V_IH

V_IT

Low-level input voltage⁽²⁾

-0.3

2

0.8

5.5

500

800

5

V

High-level input voltage⁽²⁾

Input threshold hysteresis voltage⁽²⁾

Pull-down resistor

30

125

-5

mV

kΩ

µA

350

0

I_IL

Low-level input current

TXD = 0

LIN PIN (Referenced to V_SUP

)

V_OH

High-level output voltage⁽²⁾

LIN recessive, TXD = High, I_O= 0

mA

V_SUP-1V

0

V

V_OL

Low-level output voltage⁽²⁾

LIN dominant, TXD = Low, I_O= 40

mA

0.2×V_SUP

Pull-up resistor to V_SUP

Limiting current

20

50

30

150

0

60

250

kΩ

mA

µA

V

I_L

TXD = Low

LIN = V_SUP

I_IKG

V_IL

V_IH

V_IT

V_hys

Leakage current

-5

5

Low-level input voltage⁽²⁾

High-level input voltage⁽²⁾

Input threshold voltage⁽²⁾

Hysteresis voltage⁽²⁾

LIN dominant

LIN recessive

V_SUP

0.4×V_SUP

V_SUP

0.6×V_SUP

0.4×V_SUP

0.05×V_SUP

V

0.5×V_SUP

0.6×V_SUP

V

0.175×V_SU

P

V

V_IL

Low-level input voltage for

wake-up⁽²⁾

0

0.4×V_SUP

V

EN PIN

V_IL

Low-level input voltage⁽²⁾

High-level input voltage⁽²⁾

Hysteresis voltage⁽²⁾

-0.3

2

0.8

5.5

V

V_IH

V_hys

30

500

mV

(1) Typical values are give for V_SUP= 14 V at 25°C.

(2) All voltages are defined with respect to ground; positive currents flow into the TPIC1021 device.

(3) In the dominant state the supply current increases as the supply voltage increases due to the integrated LIN slave termination

resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN

slave termination is 20 kΩ so the maximum supply current attributed to the termination is: I_{SUP (dom) max termination}≈ (V_SUP

(V_{LIN_Dominant}+0.7V) / 20 kΩ.

–

8

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113–OCTOBER 2004

ELECTRICAL CHARACTERISTICS (continued)

V_SUP= 7 V to 27 V, T_A= -40°C to 125°C (unless otherwise noted)

PARAMETER

Pull-down resistor

TEST CONDITIONS

MIN

125

-5

TYP⁽¹⁾

350

0

MAX

800

5

UNIT

kΩ

I_IL

Low-level input current

EN = 0 V

µA

INH PIN

V_o

DC output voltage

Ouptut current

Transient voltage

-0.3

-50

25

V_SUP+0.3

V

mA

Ω

I_O

2

R_on

On state resistance

Between V_SUPand INH, INH = 2 mA

drive, Normal or Standby Mode

40

0

100

I_IKG

Leakage current

Low Power mode, 0 < INH < V_SUP

-5

5

µA

NWake PIN

(4)

V_IL

V_IH

Low-level input voltage

-0.3

V_SUP-1

-40

V_SUP-3.3

V

High-level input voltage⁽⁴⁾

V_SUP+0.3

Pull-up current

NWake = 0 V

-10

0

-4

5

µA

I_IKG

Leakage current

V_SUP= NWake

-5

THERMAL SHUTDOWN

Shutdown junction thermal tempera-

185

°C

ture

AC CHARACTERISTICS

D1

D2

D3

D4

Duty cycle 1⁽⁵⁾⁽⁶⁾

TH_REC(max)= 0.744×V_SUP

TH_DOM(max)= 0.581×V_SUP, V_SUP

7.0 V to 18 V, t_BIT= 50 µs (20 kbps),

See Figure 4

,

0.396

0.417

=

Duty cycle 2⁽⁵⁾⁽⁶⁾

Duty cycle 3⁽⁵⁾⁽⁶⁾

Duty cycle 4⁽⁵⁾⁽⁶⁾

TH_REC(max)= 0.284×V_SUP

TH_DOM(max)= 0.422×V_SUP, V_SUP

7.6 V to 18 V, t_BIT= 50 µs (20 kbps),

See Figure 4

,

0.581

0.590

=

TH_REC(max)= 0.778×V_SUP

,

TH_DOM(max)= 0.616×V_SUP, V_SUP

7.0 V to 18 V, t_BIT= 96 µs (10.4

kbps), See Figure 4

=

TH_REC(max)= 0.251×V_SUP

,

TH_DOM(max)= 0.389×V_SUP, V_SUP

7.6 V to 18 V, t_BIT= 96 µs (10.4

kbps), See Figure 4

=

t_{rx_pdr}

t_{rx_pdf}

t_{rx_sym}

Receiver rising propagation delay

time

R_L= 2.4 kΩ, C_L= 20 pF, See

Figure 4

6

2

µs

Receiver falling propagation delay

time

R_L= 2.4 kΩ, C_L= 20 pF, See

Figure 4

Symmetry of receiver propagation

delay time (rising edge)

wrt falling edge, See Figure 4

-2

t_NWake

t_LINBUS

NWake filter time for local wake-up

See Figure 4

25

50

100

µs

LIN wake-up filter time (dominant

time for wake-up via LIN bus)

t_DST

Dominant state timeout

See Figure 4

4

9

14

ms

(4) All voltages are defined with respect to ground; positive currents flow into the TPIC1021 device.

(5) Duty cycle = t_{BUS_rec(min)}/ (2×t_BIT

)

(6) Duty Cycles: LIN Driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 6.8 nF, 660 Ω; Load3 = 10 nF, 500 Ω.

Duty Cycles 3 and 4 are defined for 10.4 kbps operation. The TPIC1021 also meets these lower speed requirements, while it is capable

of of the higher speed 20.0 kbps operation as specified by Duty Cycles 1 and 2. SAEJ2602 derives propagation delay equations from

the LIN 2.0 duty cycle definitions, for details please refer to the SAEJ2602 specification.

9

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113–OCTOBER 2004

TIMING DIAGRAMS

t_Bit

RECESSIVE

TXD (Input)

DOMINANT

t_{Bus_dom(max)}

t_{Bus_rec(min)}

TH_Rec(max)

TH_Dom(max)

Thresholds of

receiving node 1

V_SUP

(Transceiver supply

of transmitting node)

LIN Bus Signal

Thresholds of

receiving node 2

TH_Rec(min)

TH_Dom(min)

t_{Bus_dom(min)}

t_{Bus_rec(max)}

RXD

(Output of receiving node 1)

t_{rx_pdf(1)}

t_{rx_pdr(1)}

RXD

(Output of receiving node 2)

t_{rx_pdf(2)}

t_{rx_pdr(2)}

Figure 4. Definition of Bus Timing Parameters

10

TPIC1021

LIN Physical Interface

www.ti.com

SLIS113–OCTOBER 2004

APPLICATION INFORMATION

V

BAT

V

SUP

TPIC7xxxx

MASTER

NODE

V

SUP

V

DD

NWake

INH

V

DD

Master Node

Pull−Up

V

SUP

3

V

DD

EN

8

3

7

2

MCU w/o

pull−up

2

1 kΩ

V

DD

I/O

MCU

V

TPIC1021

TMS430

TMS470

LIN

Controller

or

LIN

1

4

RXD

TXD

6

220 pF

5

1

SCI/UART

bat

GND

SLAVE

NODE

V

SUP

TPIC7xxxx

V

SUP

V

DD

NWake

INH

V

SUP

V

DD

EN

8

2

3

7

MCU w/o

2

pull−up

V

DD

I/O

MCU

TPIC1021

TMS430

TMS470

LIN

Controller

or

LIN

1

4

RXD

TXD

6

220 pF

5

1

SCI/UART

GND

(1) RXD on MCU or LIN Slave has internal pull-up, no external pull-up resistor is needed.

(2) RXD on MCU or LIN Slave without internal pull-up, requires external pull-up resistor.

(3) Master Node applications require an external 1-kΩ pull-up resistor and serial diode.

Figure 5.

11

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型号	制造商	描述	价格	文档
TPIC1021A-Q1	TI	LIN PHYSICAL INTERFACE	获取价格
TPIC1021AQDRQ1	TI	LIN PHYSICAL INTERFACE	获取价格
TPIC1021D	TI	LIN Physical Interface	获取价格
TPIC1021DG4	TI	LIN Physical Interface	获取价格
TPIC1021DR	TI	LIN Physical Interface	获取价格
TPIC1021DRG4	TI	LIN Physical Interface	获取价格
TPIC1301	TI	3-HALF H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY	获取价格
TPIC1301DW	TI	3-HALF H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY	获取价格
TPIC1301DWR	TI	2.25A, 60V, 0.275ohm, 6 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-013AD, PLASTIC, SOIC-24	获取价格
TPIC1310	TI	3-HALF H-BRIDGE GATE PROTECTED POWER DMOS ARRAY	获取价格

TPIC1021

TPIC1021 概述

TPIC1021 数据手册

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