TPIC2050RDFDRG4 [TI]
TPIC2050 具有 3 波束激光二极管驱动器、由串行接口控制的 9 通道电机驱动器 | DFD | 56 | -20 to 75;
| 型号： | TPIC2050RDFDRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPIC2050 具有 3 波束激光二极管驱动器、由串行接口控制的 9 通道电机驱动器 | DFD | 56 | -20 to 75 电动机控制 电机 驱动 光电二极管 激光二极管 驱动器 |
| 文件： | 总66页 (文件大小：1280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPIC2050
ZHCSEQ5 –AUGUST 2015
TPIC2050 具有 3 波束激光二极管驱动器、由串行接口控制的 9 通道电机驱
动器
1 特性
通道中具有短路保护
–
–
硬件器件禁用引脚，XRSTIN
1
•
串行端口数字接口
具有欠压锁定 (UVLO) 和过压保护 (OVP) 的电
源监视器
–
–
–
–
串行外设接口 (SPI)
4 线接口：SSZ、SCLK、SIMO、SOMI
最大读写频率 35MHz
–
–
托盘锁定检测
PREOVP-12V：在 SPM 制动时防止通过电机
BEMF 进行 12V OVP 检测
3.3V 数字输入输出 (I/O)
•
执行器和电机驱动器
–
–
具有 H 桥输出的脉冲宽度调制 (PWM) 控制
2 应用
具有 12 位数模转换器 (DAC) 控制的聚焦/跟踪/
倾斜执行器驱动器
光盘驱动器（蓝光碟、DVD、CD）
–
–
–
具有电流模式、10 位 DAC 控制的滑动电机驱
动器
3 说明
TPIC2050 是一款适用于 12V ODD 的超低噪声电机驱
动器集成电路 (IC)。该驱动器 IC 有 9 条通道且由串行
接口控制，非常适用于驱动主轴电机、滑动电机（适用
的步进电机）、负载电机以及针对准直透镜的聚焦/跟
踪/倾斜执行器和步进电机。
具有 12 位 DAC 控制的负载驱动器可选 5V 或
12V
具有 8 位 PWM 控制的步进电机驱动器
•
主轴电机驱动器
–
–
–
0.3Ω 低导通电阻、典型金属氧化物半导体场效
应晶体管 (MOSFET) 输出
器件信息(1)
无传感器：通过电机反电动势 (BEMF) 感测转
子位置
器件型号
TPIC2050
封装
封装尺寸（标称值）
HTSSOP (56)
6.10mm x 14.00mm
适用于 10500rpm 转速（假设使用 12 极点电
机）
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
–
–
–
通过串行端口编程设定的 12 位主轴 DAC
独立的感应位置感测和启动
ICOM
TPIC2050
ISENSE
自动制动功能，在每种转速下均可选择最佳制动
模式
12 V
MCOM
5 V
Motor Drive
Spindle
U
V
–
最大持续电流为 1.5A，不存在散热问题
3.3 V
9.5 V
•
•
实用功能
W
–
状态锁存器：执行器定时器、SIF 错误、电源监
视器、热保护和过流保护 (OCP) 故障
SLED1+
Motor Drive
DAC PWM
SLED1œ
SLED2+
SLED2œ
–
片上温度计（15°C 至 165°C）
SPI
3 波束激光二极管驱动器
Controller
TLT+
Motor Drive
DAC PWM
–
120mA 电流输出，通过 11 位 DAC 寄存器或模
拟输入 (VLDDIN)
TLTœ
FCS+
FCSœ
TRK+
TRKœ
Motor Drive
DAC PWM
–
–
通过斜率控制电流快速变化
通过串行位选择光盘 (CD)、数字化视频光盘
(DVD)、蓝光光盘 (BD) 的输出端口
VDDDIN
Motor Drive
DAC PWM
Analog
Input for LDD
ILDO_BD
12 V
5 V
P5V12L
TRK+
•
保护
LDD
Driver
–
同步永磁电机 (SPM) 和执行器驱动器上均配有
独立热保护电路
Motor Drive
DAC PWM
TRKœ
ILDO_DVD
ILDO_CD
LDD
Driver
STP1+
–
–
两个警报级别：热保护中的预检测和检测
Motor Drive
DAC PWM
STP1œ
LDD
Driver
ACTTEMP：监视由过去累积的 DAC 值计算得
出的执行器温度
STP2+
STP2œ
–
SPM、滑动电机、负载、执行器和步进驱动器
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLIS167
TPIC2050
ZHCSEQ5 –AUGUST 2015
www.ti.com.cn
目录
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 23
8.5 Programming........................................................... 24
8.6 Register Maps......................................................... 26
Application and Implementation ........................ 47
9.1 Application Information............................................ 47
9.2 Typical Application ................................................. 56
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Serial I/F Write Timing Requirements..................... 11
7.7 Serial I/F Read Timing Requirements..................... 12
7.8 Typical Characteristics............................................ 13
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
9
10 Power Supply Recommendations ..................... 58
11 Layout................................................................... 59
11.1 Layout Guidelines ................................................. 59
11.2 Layout Example .................................................... 59
12 器件和文档支持 ..................................................... 60
12.1 社区资源................................................................ 60
12.2 商标....................................................................... 60
12.3 静电放电警告......................................................... 60
12.4 Glossary................................................................ 60
13 机械、封装和可订购信息....................................... 60
8
4 修订历史记录
日期
修订版本
注释
2015 年 8 月
*
最初发布。
2
版权 © 2015, Texas Instruments Incorporated
TPIC2050
www.ti.com.cn
ZHCSEQ5 –AUGUST 2015
5 说明 （续）
主轴电机驱动器部分内置无传感器逻辑，可确保以低噪声启动和运行。启动电路可实现自启动或通过 BEMF 执行位
置检测，无需使用电机或传感器，例如霍尔器件。由于所有通道的输出级均在高效的 PWM 驱动下工作，因此可通
过 PWM 控制实现低功率运行。可以对聚焦/跟踪/倾斜执行器驱动器进行无中性点区域控制。此外，该器件还内置
有主轴部件输出电流限制电路、热关断电路、滑动结束位置检测电路、准直透镜结束检测电路、执行器保护和三波
束激光驱动器。新增的内置温度计可测量 IC 温度。
6 Pin Configuration and Functions
DFD Package
56-Pin HTSSOP
Top View
1
2
3
4
5
6
7
8
9
SLED1_ P
SLED1_ N
P12V_ 3
SLED2_ P
SLED2_ N
PGND_ 2
C10V
P5V_ 2 56
STP2_ N 55
STP2_ P 54
STP1_ N
53
STP1_ P
52
AGND
51
ISENSE 50
MCOM 49
CP1
ICOM2
CP2
48
47
46
45
44
43
W
P12V_ 2
V
10 CP3
11 GPOUT
12 XFG
ICOM1
U
13 RDY
14 SSZ
15 SCLK
P12V_ 1 42
PGND_ 1 41
FCS_ N 40
FCS_ P 39
TRK_ N 38
TRK_ P 37
TLT_ P 36
TLT_ N 35
P5V_ 1 34
16 SIMO
17 SOMI
18 SIOV
19 XRSTIN
20 TEST1
21 VLDDIN
22 CV3P3
23 AGND/DGND
24 A9P5V
25 ILDD_ BD
26 ILDD_ DVD
27 ILDD_ CD
28 CA5V
33
32
TEST3
TEST2
P5V12L 31
LOAD_ N 30
LOAD_ P 29
Copyright © 2015, Texas Instruments Incorporated
3
TPIC2050
ZHCSEQ5 –AUGUST 2015
www.ti.com.cn
Pin Functions
PIN
I/O
DESCRIPTION
NAME
SLED1_P
SLED1_N
P12V_3
SLED2_P
SLED2_N
PGND_2
C10V
NO.
1
2
OUT
OUT
PS
Sled1 positive output terminal
Sled1 negative output terminal
3
Power supply terminal for 12-V drivers output
Sled2 positive output terminal
4
OUT
OUT
PS
5
Sled2 negative output terminal
6
GND terminal for 12-V drivers
7
MISC
MISC
MISC
MISC
OUT
OUT
OUT
IN
Capacitance connection terminal for internal regulator
Capacitance connection for charge pump
Capacitance connection for charge pump
Capacitance connection for charge pump
General-purpose output (test monitor)
Motor speed signal output
CP1
8
CP2
9
CP3
10
11
12
13
14
15
16
17
18
19
20
GPOUT
XFG
RDY
Device ready signal. Internally pulled up to SIOV
SIO slave select low active input terminal
SIO serial clock input terminal
SSZ
SCLK
IN
SIMO
IN
SIO slave input master output terminal
SIO slave output master input terminal
Power-supply terminal for serial port. 3.3-V typical
RESET input terminal to disable the driver IC
Test pin. Should be open
SOMI
OUT
PS
SIOV
XRSTIN
TEST1
IN
MISC
Laser diode control analog signal input 0 to 3-V terminal. Required to set register when using
VLDDIN input. Open in case of non-use analog input.
VLDDIN
21
IN
CV3P3
22
23
24
25
26
27
MISC
PS
Capacitance terminal for internal 3.3-V core (typical 0.1 µF)
Ground terminal for internal digital and analog
Power-supply terminal 9.5-V laser diode for BD
Laser diode for BD output terminal
AGND/DGND
A9P5V
PS
ILDD_BD
ILDD_DVD
ILDD_CD
OUT
OUT
OUT
Laser diode for DVD output terminal
Laser diode for CD output terminal
Capacitance connection terminal for control system power supply. Connect a ≥0.1-µF
decoupling capacitor.
CP5V
28
MISC
LOAD_P
LOAD_N
P5V12L
TEST2
TEST3
P5V_1
TLT_N
TLT_P
TRK_P
TRK_N
FCS_P
FCS_N
PGND_1
P12V_1
U
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
OUT
OUT
PS
Load positive output terminal
Load negative output terminal
Power-supply terminal (5 or 12 V) for load driver output stages.
Test pin. Should be open
MISC
MISC
PS
Test pin. Should be connected to P5V.
Power-supply terminal for tilt/focus/tracking drivers
Tilt negative output terminal
OUT
OUT
OUT
OUT
OUT
OUT
PS
Tilt positive output terminal
Tracking positive output terminal
Tracking negative output terminal
Focus positive output terminal
Focus negative output terminal
GND terminal for tilt/focus/tracking channel drivers
Power-supply terminal for 12-V driver output stage
U-phase output terminal for spindle motor
Current sense resistor terminal for spindle driver
V-phase output terminal for spindle motor
PS
OUT
MISC
OUT
ICOM1
V
4
Copyright © 2015, Texas Instruments Incorporated
TPIC2050
www.ti.com.cn
ZHCSEQ5 –AUGUST 2015
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
P12V_2
W
NO.
46
47
48
49
50
51
52
53
54
55
56
PS
OUT
MISC
IN
Power-supply terminal for 12-V driver output stage
W-phase output terminal for spindle motor
Current sense resistor terminal for spindle driver
Motor center tap connection
ICOM2
MCOM
ISENSE
AGND
IN
Current sense input terminal for spindle drivers
Ground terminal for internal analog
PS
STP1_P
STP1_N
STP2_P
STP2_N
P5V_2
OUT
OUT
OUT
OUT
PS
STP1 positive output terminal for collimator
STP1 negative output terminal for collimator
STP2 positive output terminal for collimator
STP2 negative output terminal for collimator
Power supply terminal for 5-V driver output
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
6
UNIT
5-V supply voltage P5V
12-V supply voltage P12V
15
9.5-V supply voltage A9P5V
Load supply P5V12 voltage
15
V
15
Spindle output peak voltage
Spindle output current
15
2.5
Spindle output peak current, (PW ≤ 2 ms, Duty ≤ 30%)
Sled output peak current
3.5
1.0
A
Focus/tracking/tilt driver output peak current
Load driver output peak current
Laser diode driver output peak current
Input/output voltage
1.0
1.0
247(2)
VCC + 0.3
1344
75
mA
V
–0.3
–20
–60
Power dissipation(3)
mW
Operating temperature
Lead temperature 1.6 mm from case for 10 s
260
150
°C
Tstg
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The LDD output time of the maximum current should maintain 25% or less of the xsleep total ON time.
(3) A lower RθJC is attainable if the exposed pad is connected to a large copper ground plane. RθJC and RθJA are values for 56-pin TSSOP
without a exposed heat slug (HSL) on bottom. Actual thermal resistance would be better than the above values.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2015, Texas Instruments Incorporated
5
TPIC2050
ZHCSEQ5 –AUGUST 2015
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
5.0
MAX
5.5
UNIT
P5V
Operating supply voltage (apply for P5V)
P12V
A9P5V
Driver 12-V supply voltage (apply for P12V(1)
)
10.8
7.65
4.5
12.0
9.5
13.2
10.45
5.5
Power supply laser diode for BD (apply for A9P5V)
V
5.0
P5V12L
Load operating supply voltage (apply for P5V12L)
10.8
3.0
12.0
3.3
13.2
36
VSIOV
Tope
SIOV voltage
Operating temperature range
–20
30
25
75
°C
Fck
SCLK frequency
33.8688
35
MHz
VSIFH
VSIFL
VIHB
SIMO, SSZ, SCLK pin 'H' level input voltage range
SIMO, SSZ, SCLK pin 'L' level input voltage range
XRSTIN pin 'H' level input voltage
XRSTIN pin 'L' level input voltage range
Spindle output average current U,V,W Total)
Spindle output current
2.2
SIOV + 0.2
0.8
–0.2
2.2
V
P5V + 0.1
0.8
VILB
–0.1
ISPMOA
ISPMO
ISLDOA
IACTOA
ISTPOA
0.5
1.7
1.7
A
Sled output average current
0.25
0.5
0.8
Focus/ tracking/ tilt/ loading output average current
STP output average current
0.8
300
mA
(1) (P5V = 4.5 to 5.5 V, P12V = 10.8 to 13.2 V, CATA ≈ –20℃ to 75℃, unless otherwise noted)
7.4 Thermal Information
TPIC2050
THERMAL METRIC(1)
DFD (HTSSOP)
UNIT
56 PINS
16.7
0.8
RθJA
RθJC
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-board thermal resistance
5.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJB
5.1
RθJC(bot)
0.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6
Copyright © 2015, Texas Instruments Incorporated
TPIC2050
www.ti.com.cn
ZHCSEQ5 –AUGUST 2015
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
COMMON PART
ISTBY
VCV3
RXM
Standby supply current
CV3P3 output voltage
XRSTIN pulldown resistor
RDY pullup resistor
Standby mode
Iload = 25 mA
0.6
3.3
200
33
1.2
3.4
mA
V
3.1
100
1.5
300
49.5
0.3
kΩ
RRDY
VRDY
RXFG
RDY low level output voltage
XFG output resistor
SIOV = 3.3 V, IOL = –100 µA
V
100
200
300
Ω
SIOV = 3.3 V, XSLEEP = 1, IOH = 100
µA
VXFGH
XFG high-level output voltage
SIOV – 0.3
V
SIOV = 3.3 V, XSLEEP = 1, IOL = 100
µA
VXFGL
RGPO
VGPOH
XFG low-level output voltage
GPOUT output resistor
0.3
100
200
300
Ω
SIOV = 3.3 V, XSLEEP = 1,
GPOUT high-level output voltage GPOUT_ENA = 1, GPOUT_HL = 1,
IOH = 100 µA
SIOV – 0.3
V
SIOV = 3.3 V, XSLEEP = 1,
VGPOL
GPOUT low-level output voltage
GPOUT_ENA = 1, GPOUT_HL = 0,
IOH = 100 µA
0.3
Thermal protection on
temperature
TTSD
Design value
135
5
150
15
165
25
°C
Thermal protection hysteresis
temperature
TSDhys
Vonvcc
Voffvcc
Vonvcc
Voffcc
P5V reset on voltage
P5V reset off voltage
P12V reset on voltage
P12V reset off voltage
CV3P3 reset on voltage
CV3P3 reset off voltage
3.6
3.8
7.9
8.3
2.6
2.7
3.7
3.9
8.4
8.8
2.7
2.8
3.8
4.0
8.9
9.3
2.8
2.9
V
V
V
V
V
V
VonCV3
VoffCV3
OVP predetection voltage
(spindle)
VovpPspmOn
13.4
14.1
14.8(1)
V
VovpPspmOff
VovpspmOn
VovpspmOff
OVP prerelease voltage (spindle)
OVP detection voltage (spindle)
OVP release voltage (spindle)
13.1
14.2
13.9
13.8
14.9
14.6
14.5(1)
15.6(1)
15.3(1)
V
V
V
OVP detection voltage (except
spindle)
VovpOn
VovpOff
6.0
5.8
6.2
6.0
6.4(1)
6.2(1)
V
V
OVP release voltage (except
spindle)
CHARGE PUMP PART
FCHGP Frequency
VCHGP Output voltage
SPINDLE MOTOR DRIVER PART
XSLEEP = 1
132.6
15.6
156
179.4
21.4
kHz
V
Ccp1 = Ccp3 = 0.1 µF Io = –1 mA
18.5
Total output resistance high side
+ low side
RttlSPM
IOUT = 500 mA
0.3
0.6
Ω
VIsns
160
179
170
194
12
180
209
Spindle current limit reference
voltage
mV
bit
VIsnsP
ResSPM
VoutSPM
For flash peak current detection
Magnification to 1.0 inputs
Resolution
Spindle gain
12.4
14.0
15.6 times
(1) These value are protection functions only, and stress beyond those listed under Recommended Operating Conditions may cause
permanent damage to the device.
Copyright © 2015, Texas Instruments Incorporated
7
TPIC2050
ZHCSEQ5 –AUGUST 2015
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
12h
TYP
52h
MAX UNIT
92h
Forward
Reverse
WidDZSPM
Spindle dead band
–92h
–52h
–12h
SLED MOTOR DRIVER PART
Total output resistance high side
+ low side
RttlSLD
P12V = 10.8 to 13.2 V, IO = 500 mA
1.6
2.5
Ω
ResSLD
Resolution
10
+33h
–33h
bit
Forward
Reverse
+4h
+62h
–4h
WidDZSLD
Input dead band
Sled current gain
–62h
P5V = 5 V, P12V = 12 V VSLED =
7FFh
GnSLD
760
62
880
124
1000
186
mA
mV
END_DET BEMF threshold
voltage
ENDDET_SLCT = 0,
SLEDENDTH<1:0> = ,SLED Enable
VthEdetSLD
FOCUS/TILT/TRACKING DRIVER PART
Each channel total output
RttlAct
P5V = 4.5 V to 5.5 V, IO = 500 mA
0.7
12
0
1.1
30
Ω
bit
resistance high side + low side
ResACT
VOfstACT
GnAct
Resolution
Each channel output offset
voltage
DAC_code = 000h
–30
4.7
mV
Each channel voltage gain
Magnification to 1.0 inputs
6.0
7.6 times
LOAD DRIVER PART
P5V12L = 4.5 to 5.5 V, IO = 500 mA
Total output resistance high side
RttlLOD
1.2
1.9
Ω
P5V12L = 10.8 to 13.2 V, IO = 500
mA
+ low side
Resolution
Voltage gain
ResLOD
GnLOD
12
6.0
bit
V
P5V12L = 4.5 to 5.5 V
P5V12L = 10.8 to 13.2 V
Forward
4.7
7.6
11.1
14.0
20h
17.6
WidDZLOD
Dead band
Reverse
–21h
8
Copyright © 2015, Texas Instruments Incorporated
TPIC2050
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ZHCSEQ5 –AUGUST 2015
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
P5V12L = 5 V, TRAY_LOCKDET[2:0]
= 1
80
100
100
150
150
200
200
250
250
300
300
300
300
400
400
120
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 1
80
120
120
160
160
212
212
255
255
297
297
340
340
120
180
180
240
240
P5V12L = 5 V, TRAY_LOCKDET[2:0]
= 2
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 2
P5V12L = 5 V, TRAY_LOCKDET[2:0]
= 3
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 3
P5V12L = 5 V, TRAY_LOCKDET[2:0]
= 4
287
mA
287
LockDth
Tray lock detect threshold current
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 4
P5V12L = 5 V, TRAY_LOCKDET[2:0]
= 5
345
345
345
345
460
460
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 5
P5V12L = 5 V, TRAY_LOCKDET[2:0]
= 6
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 6
P5V12L = 5 V, TRAY_LOCKDET[2:0]
= 7
P5V12L = 12 V,
TRAY_LOCKDET[2:0] = 7
STEPPING MOTOR DRIVER PART
Total output resistance high side
+ low side
RttlSTP
IO = 100 mA
1.0
1.5
Ω
ResSTP
IocpSTP
Resolution
8
850
1.0
25
bit
mA
µs
Overcurrent protection level
OCP monitor delay time
OCP hold time
595
0.7
17
1148(1)
1.3(1)
32(1)
tDlyocpSTP
thlocpSTP
ms
ENDDET_SLCT = 1,
STPDENDTH<1:0> = 00, STP Enable
VthEdetSTP
END_DET threshold level
19
39
59
mV
LDD DRIVER PART
LDD_MSEL:01(CD), 10(DVD) A9P5V
= 7.65 to 10.45 V
102
102
98
120
120
120
120
120
120
138
138
141
138
138
141
LDD current gain in digital mode
VLDD = 0x7FF
IUP = 00
LDD_MSEL:11(BD) A9P5V = 8.55 to
10.45 V
AV(2)
mA
LDD_MSEL:11(BD) A9P5V = 7.65 to
8.55 V
LDD_MSEL:01(CD), 10(DVD) A9P5V
= 7.65 to 10.45 V
102
102
98
LDD current gain in analog mode
VLDDIN input voltage = 3 V
IUP = 00
LDD_MSEL:11(BD) A9P5V = 8.55 to
10.45 V
AV(2)
mA
LDD_MSEL:11(BD) A9P5V = 7.65 to
8.55 V
(2) ILDD_BD = 4.5 V, ILDD_CD = 2.1 V ILDD_DVD = 2.1 V
Copyright © 2015, Texas Instruments Incorporated
9
TPIC2050
ZHCSEQ5 –AUGUST 2015
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
102
–10
119
141
164
102
–10
119
141
164
98
TYP
120
0
MAX UNIT
VLDD = 0x7FF, LDD_IUP = 00
VLDD = 0, LDD_IUP = 00
138
10
LDD current gain by IUP setting
(digital mode only)
LDD_MSEL: 01(CD), 10(DVD)
AV(2)(3)
AV(2)(3)
AV(2)(3)
VLDD = 0x7FF, LDD_IUP = 01
VLDD = 0x7FF, LDD_IUP = 10
VLDD = 0x7FF, LDD_IUP = 11
VLDD = 0x7FF, LDD_IUP = 00
VLDD = 0, LDD_IUP = 00
149
177
206
120
0
178
212
247
138
10
mA
mA
mA
LDD current gain by IUP setting
(digital mode only)
LDD_MSEL:11(BD) at A9P5V =
8.55 to 10.45 V
VLDD = 0x7FF, LDD_IUP = 01
VLDD = 0x7FF, LDD_IUP = 10
VLDD = 0x7FF, LDD_IUP = 011
VLDD = 0x7FF, LDD_IUP = 00
VLDD = 0, LDD_IUP = 00
149
177
206
120
0
178
212
247
141
10
LDD current gain by IUP setting
(digital mode only)
LDD_MSEL:11(BD) at A9P5V =
7.65 to 8.55 V
–10
114
136
158
VLDD = 0x7FF, LDD_IUP = 01
VLDD = 0x7FF, LDD_IUP = 10
VLDD = 0x7FF, LDD_IUP = 11
P5V = 4.5 V to 5.5 V, A9P5V = 9.5 V
149
177
206
11
183
217
253
ResLDD
tr
LDD current gain
Rise time of ILDD
bit
µs
P5V = 5 V VLDDIN = 0 → 0x7FF
162
162
203
203
243
243
120 mA
P5V = 5 V VLDDIN = ꢀ0x7FF → 0
tf
Fall time of ILDD
50 mA
IZ
VLDDIN input impedance
100
140
200
200
300
260
kΩ
mV
bit
LDDdbA
LDDdbA
Low voltage dead band
0x3F
THERMOMETER PART
ResTEMP
Resolution
6
15
bit
°C
CHIPTEMP[5:0] = 00
CHIPTEMP[5:0] = 3Fh
8
22
Trng
Temperature range
Update cycle
155
165
10
175
FTEMP
kHz
ACTUATOR PROTECTION
tintACTTEMP Update cycle
SERIAL PORT VOLTAGE LEVELS
26
ms
SOMI
SOMI
SIMO
SIMO
tSIMO
High-level output voltage, VOH
IOH = 1 mA
IOL = 1 mA
80% SIOV
70% SIOV
V
V
Low-level output voltage, VOL
High-level input voltage, VIH
Low-level input voltage, VIL
Input rise/fall time
20% SIOV
V
20% SIOV
3.5
V
20% ⇔ 80% SIOV
ns
ns
kΩ
kΩ
tSOMI
Output rise/fall time(4)
Cload = 30 pF, 20% ⇔ 80% SIOV
10
RSCLK
RSSZ
Internal pulldown resistance
Internal pullup resistance
100
100
200
200
300
300
(3) LDD_IUP settings are only for digital mode.
(4) Specified by design
10
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TPIC2050
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ZHCSEQ5 –AUGUST 2015
7.6 Serial I/F Write Timing Requirements
MIN
NOM
MAX
UNIT
MHz
ns
ƒck
tckl
SCLK clock frequency
SCLK low time
SIOV = 3.3 V
35
11
11
7
tckh
tsens
tsenh
tsl
SCLK high time
ns
SSZ setup time
ns
SSZ hold time
7
ns
SSZ disable high time
SIMO setup time (Write)
SIMO hold time (Write)
11
7
ns
tds
ns
tdh
7
ns
Tsl
SSZ
Fck
Tsens
Tsenh
SCLK
Tckl
Tckh
SIMO
SOMI
Tds
Tdh
Hi-Z
Figure 1. Serial Port Write Timing
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7.7 Serial I/F Read Timing Requirements
MIN
NOM
MAX
UNIT
MHz
ns
ƒck
tckl
SCLK clock frequency
SCLK low time
SIOV = 3.3 V
35
11
11
7
tckh
tsens
tsenh
tsl
SCLK high time
ns
SSZ setup time
ns
SSZ hold time
7
ns
SSZ disable high time
SIMO setup time (Write)
SIMO hold time (Write)
SOMI delay time (Read)
SOMI hold time (Read)
11
7
ns
tds
ns
tdh
7
ns
trdly
tsendl
CLOAD = 10 pF, SIOV = 3.3 V
CLOAD = 10 pF, SIOV = 3.3 V
2
9
9
ns
2
ns
CLOAD = 10 pF, SIOV = 3.3 V from SSZ rise to
SOMI HIZ
trls
SOMI release time (Read)
0
9
ns
Tsl
SSZ
Tsenh
Fck
Tsens
SCLK
Trls
Tdh
Tds
Tckh Tckl
SIMO
R
SOMI
Hi-Z
Trdly
Tsendl
Figure 2. Serial Port Read Timings
Tsl
SSZ
Tsenh
Fck
Tsens
SCLK
Tdh
Tds
Tckh Tck l
SIMO
R
Trls
SOMI
Hi-Z
Trdly
Tsendl
Figure 3. Serial Port Read Timings (Advanced Read Mode)
12
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ZHCSEQ5 –AUGUST 2015
7.8 Typical Characteristics
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
STP1+
STP2+
STP1œ
STP2œ
-2047
-1535
-1023
-511
1
513
1025
1537
2049
D001
-2047
-1535
-1023
-511
1
513
1025
1537
2049
D002
DAC Code
DAC Code
Figure 4. STP1 Driver: DAC Code vs Output On Duty
Figure 5. STP2 Driver: DAC Code vs Output On Duty
Copyright © 2015, Texas Instruments Incorporated
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8 Detailed Description
8.1 Overview
TPIC2050 is very-low noise type motor driver IC suitable for 12V ODD. The 9-channels driver IC controlled by
serial I/F is optimum for driving a spindle motor, a sled motor (stepping motor applicable), a load motor, and
Focus / Tracking / Tilt actuators and stepping motor for collimator lens. This IC’s integrated current sense
resistance which measures SPM current then it is able to reduce drive system cost in drastically. The spindle
motor driver part builds in the sensor less logic which attained low noise-operation at the time of starting and run.
In order to carry out self-starting by the starting circuit and to perform position detection by BEMF of a motor,
sensors, such as a Hall device, are not needed. As the output stage of all channels works in efficient PWM
driving, it is possible to attain low power operation by PWM control. Dead zone less control is possible for a
Focus / Tracking / Tilt actuator driver. In addition, the spindle part output current limiting circuit, the thermal shut
down circuit, the sled end detection circuit, collimator lens end detection circuit, actuator protection.
14
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TPIC2050
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ZHCSEQ5 –AUGUST 2015
8.2 Functional Block Diagram
P12V
0.1u
P5V
P12V
0.1u
ICOM1
ICOM2
Charge
pum p
19V
XSLEEP
SIOV
0.1
SPM
Current lim it
ISENSE
MCOM
XFG
XFG
XSLEEP
SPM Logic
DAC PW M
BEMF
detector
On chip
therm om eter
SPM_ ENA
U
1k
SIOV
TEMPMON_ENA
pre- power
driver FET
V
SSZ
SCLK
SIMO
SSZ
W
SCLK
SIMO
SLED1+
SLED1-
SIOV
DAC
PW M
pre- power
driver FET
SOMI
SIOV
SOM I
SOMI_HIZ
SLD_ ENA
SLD_ ENA
F/B
3.3V
SLED END
detection
Digital core
ENDDET
SIOV
GPOUT
XRSTIN
GPOUT
SLED2+
SLED2-
GPOUT_ENA
DAC
PW M
pre- power
driver FET
RESETIN
F/B
TLT+
TLT-
DAC
PW M
pre- power
driver FET
A5V
TLT_ ENA
F/B
CV3P3V
int3.3V
Regulator
DIFF_ TLT
0.1u
FCS+
FCS-
SIOV
DAC
PW M
pre- power
driver FET
F/B
RDY
power
m onitor
RDY
P12V
P5V
TRK+
pre- power
driver FET
TRK-
F/B
P5V12L
P12V
P5V
DAC
PW M
TRK_ ENA
LOAD+
LOAD-
pre- power
driver FET
LOAD_ ENA
P12V
F/B
int10V
Regulator
TRAY Lock
detection
C10V
CA5V
ENDDET
0.1u
0.1u
P5V
STP1+
DAC
PW M
Analog
5V
pre- power
driver FET
STP_ ENA
STP1-
STP2+
VLDDIN
DAC
VLDDIN
DAC
PW M
pre- power
driver FET
LDD_AMODE
ILDD_ DVD
V/I
V/I
STP2-
STEP END
detection
ILDD_ CD
ILDD_ BD
ENDDET
LD
select
ENDDET_ ENA
V/I
ENDDET
LDD_MSEL
ENDDET_ SEL[1:0]
A9P5V
10u
TPIC2050
9.5V
AGND/DGND
PGND_ 1-2
AGND
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8.3 Feature Description
8.3.1 Protect Functions
The TPIC2050 has five protection features to protect target equipment: overvoltage protection (OVP), short-
circuit protection (SCP), overcurrent protection (OCP), thermal protection (TSD), and actuator temperature
protection (ACTTIMER).
8.3.1.1 OVP
OVP function protects the unit from the supplying high voltage. When the supply voltage exceeds 6.2 V (for
P5V), all driver output goes to Hi-Z. The SPM, sled, and load channels go to Hi-Z when P12V is over 14.9 V.
When power supply exceeds 14.1 V, the SPM channel enters short brake mode. This operation occurs after a
rise in voltage in the motor BEMF. Regardless of the input voltage of the P5V12L, the load channel becomes Hi-
Z when OVP_P5V or OVP_P12V. When the supply voltage falls below 6 V, all outputs start to operate again
(14.6 V for 12-V driver channel). The OVP and POR (RDY) functions do not interlock. This function is intended to
protect the device in the evaluation stage as a temporary and back-up solution.
8.3.1.2 OCP and SCP
The OCP and SCP protect the device from a breakdown caused by a large current. The OCP is provided only for
the step channel, and SCP is provided for all driver channels other than the LDD driver. Table 1 indicates each
behavior.
Table 1. Protection Threshold Table
BLOCK
FUNCTION
DETECTION CURRENT
DETECT TIME
HI-Z HOLD TIME
STEP driver
OCP
850 mA
1 µs
25 ms
STEP driver (low-side FET only)
SPM driver
Monitor driver output voltage
High-side FET output V = GND
Low-side FET output V = Supply V
Sled driver
SCP
0.8 to 1.6 µs
1.6 ms
Load driver
Actuator driver
When a large current is detected on each block, the device puts the output FET to Hi-Z.
When OCP or SCP occurs, it returns automatically after the set Hi-Z hold time expires. The OCPSCPERR
(REG7F) and OCP, SCP flags (REG7B) are set at detection.
8.3.1.2.1 OCP for Step Driver
The STP1 and STP2 channels have current trip function. The output of the STEP channel is changed to Hi-Z if
the current exceeds the current limit threshold (850 mA typical). When the trip period (25 ms) expires, the trip
state is automatically released.
16
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TPIC2050
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ZHCSEQ5 –AUGUST 2015
detect1us
STEP load-I
850mA
0mA
Hi-Z
Hi-Z
STEP+ voltage
STEP- voltage
RDY
25ms
Figure 6. Overcurrent Protection Step
8.3.1.2.2 SCP
The SCP function monitors the output voltage of the high-side and low-side FET of the output driver, and when
the setting voltage is not outputted, it recognizes it as 'SCP' and changes the output to Hi-Z. It automatically
returns to the original state after 1.6 ms.
VDAC set
Driver current
Hi-Z
Hi-Z
detect1.6us
Drivervoltage
1.6m s
RDY
Figure 7. Example of SCP (Driver Short to GND)
8.3.1.3 Thermal Protection (TSD)
The TSD is a protection function which intercepts an output and suspends an operation when the IC temperature
exceeds a maximum permissible safe temperature. TSD creates an output Hi-Z when the temperature rises up
and a threshold value is exceeded. The two levels for the threshold are alert and trip. An alarm is given by status
register TSD_FAULT_ on Alert level at 135°C. If the temperature continues to rise, the register TSD_ is set at
150°C and the driver output changes to Hi-Z. If the temperature falls and reaches 135°C, it outputs again. The
TPIC2050 has 11 temperature sensors in each circuit block. The particular sensor assigned to the appropriate
status flag is listed in Table 2.
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TPIC2050
ZHCSEQ5 –AUGUST 2015
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Table 2. Thermal Sensor Assignment
CIRCUIT
U
ALERT (°C)
135
TRIP (°C)
150
RELEASE (°C)
ALERT FLAG
TRIP FLAG
TSD_SPM
TSD_SPM
TSD_SPM
TSD_ACT
TSD_ACT
TSD_ACT
TSD_ACT
TSD_ACT
TSD_ACT
TSD_ACT
TSD_LDD
135
135
135
135
135
135
135
135
135
135
135
TSD_FAULT_SPM
TSD_FAULT_SPM
TSD_FAULT_SPM
TSD_FAULT_ACT
TSD_FAULT_ACT
TSD_FAULT_ACT
TSD_FAULT_ACT
TSD_FAULT_ACT
TSD_FAULT_ACT
TSD_FAULT_ACT
TSD_FAULT_LDD
V
135
150
W
135
150
TLT
135
150
FCS
TRK
SLED1
SLED2
STP
LOAD
LDD
135
150
135
150
135
150
135
150
135
150
135
150
135
150
8.3.1.4 Actuator Temperature Protection (ACTTIMER)
The TPIC2050 has an actuator protect function, ACTTIMER. This function sets the actuator channel output to Hi-
Z when the actuator coil current exceeds a specific value. This new protection calculates heat accumulation and
judges appropriately. When this function operates, the LDD and load driver channel outputs are Hi-Z, and the
spindle channel is forced to auto short brake, stopping the disc motor.
The user can know if protection occurred by checking the Fault register ACTTIMER_FAULT (REG7F) and
ACT_TIMER_PROT (REG78). ACTTIMER_FAULT sets a character of advance notice, before detecting
ACT_TIMER_PROT. After an ACT_TIMER_PROT is set, even if the temperature falls, it does not automatically
release protection. The user must clear the flag by setting the RST_ERR_FLAG (REG77) or setting 0 to
ACTTEMPTH (REG72). The ACTTIMER function is disabled by setting H to ACTPROT_OFF (REG72) or setting
0 to ACTTEMPTH (REG72). To acquire the optimal value for ACTTEMPTH, set the device into the condition of
the detection level and read the value of ACTTEMP, as the present value can be read from ACTTEMP (REG78).
The ACTTEMP data is updated on the register in ACTPROT_OFF = 0 and ACTTEMPTH > 0.
18
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ZHCSEQ5 –AUGUST 2015
RST_ ERR_ FLAG
ACTTIMER_ FAULT
ACT_ TIMER_ PROT
ACTTEMPTH
ACTTEMPTH-1
ACTTEMPcount
Hi-Z
Hi-Z
FCS+ , TRK+ , TLT+
FCS-, TRK-, TLT-
Sled1+ , Sled2+
Sled1-, Sled2-
Step1+ ,Step2+
Step1-,Step2-
Load+
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Load-
Motor rpm
0
auto short brake
XFG
disable 300m s
Figure 8. Actuator Temperature Protections
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8.3.1.5 Prevent OVP 12 V (PREOVP-12V)
When using the power supply unit without current-sinking capability for 12-V supply, the P12V voltage goes up
with the motor BEMF at slowdown. As a result, 12-V OVP is detected if this voltage exceeds the threshold value.
To prevent this detection, the TPIC2050 provides a PREOVP-12V function. The SPM driver output is forced into
three-phase short brake mode if P12V is over the threshold voltage. The PREOVP-12V function is disabled by
OVPPRE12V_OFF = 1 (REG6B[0]).
OVP_12V Hi
OVP_12V Lo
OVPPRE_12V Hi
OVPPRE_12V Lo
P12V voltage
Motorrpm
3phase short brake
OVPPRE_ 12V
OVP_ 12V
Figure 9. OVPPRE_12V
8.3.2 DAC Type
The TPIC2050 has nine channel drivers and one LDD driver. Each channel is assigned to the most suitable DAC
engine with a different type. ACT (focus/tracking/tilt) has a 12-bit DAC. Upper 8 (MSB sign bit) are converted one
at a time in 5 MHz, and LSB 4 bits are output in sequence with a 1.25 MHz PWM. SPIN and Load DAC have the
same types and sampling rate of 312 kHz. The SPM channel has x14 gain, and other channels (except for SLED
and STP) have x6 gain. The DAC for STP is 8-bits resolution output with 40-kHz PWM, and no feedback. The
gain for STP is x5 relative to P5V voltage. Table 3 shows the configuration of each driver.
Table 3. DAC Type
FCS/TRK/TLT
SLED
SPIN
LOAD
STP
LDD
Resolution
Type
12 bit
10 bit
12 bit
12 bit
8 bit
11 bit
10-bit voltage
DAC
8-bit over
sampling
8-bit over
sampling
1-bit direct duty
PWM
11-bit voltage
DAC
8-bit oversampling
1.25M / 10 bit
312K / 12 bit
Sampling
312K
312K
40 kHz
About 156 kHz
(variable)
PWM frequency
Out range
312 kHz
±6 V
156 kHz
±14 V
312 kHz
±6 V
40 kHz
±880 mA
±(P5V*1)
0 to 120 mA
No F/B
Power supply
compensation
Voltage F/B
shared with TRK
Direct PWM no
F/B
Feedback
Voltage F/B
Current F/B
20
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ZHCSEQ5 –AUGUST 2015
8.3.3 Example of 12-Bit DAC Sampling Rate for FCS/TRK/TLT
The input data is separated in the upper 8 bits and the lower 4 bits. Upper 8 bits (MSB sign 1 bit) are put into an
8-bit current DAC in every 5 MHz. The lower 4 bits are put into one bit current DAC in sequence, from the upper
to lower bit. This is a one bit DAC output with PWM in 1.25 MHz. At any PWM duty, 100%, 75%, 50%, 25% or
0% is summed in 8-bit current DAC every 1.25 MHz. Therefore, it takes 3.2 µs for all lower 4 bits to sum to the
PWM output. As a result, 12-bit data is sampled in every PWM cycle. An example of the sampling rate for
FCS/TRK/TLT is in Figure 10.
WriteDAC
5 MHz
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1.25 MHz
625 KHz
312 KHz
PWM duty
10bit
10bit
10bit
10bit
11bit
11bit
12bit
LSB 4bit width
12bit DAC(8bit DAC+ 4bit PWM DAC) output
one PWM cycle (312 KHz = 3.2us)
Figure 10. Example of 12-Bit DAC Conversion Time (FCS/TRK/TLT)
8.3.4 Digital Input Coding
The output voltage (current) is commanded via programming to the DAC. All of the DAC input format is 12 bit in
complement of 2's, though some DAC has a low resolution. When 12 bits data is inputted as 8-bits DAC, the
TPIC2050 recognizes four subordinate position bits (LSB) as 0. To arrange for 12-bit DAC format, the DSP
should shift 8-bit or 10-bit data to an appropriate bit position. The full scale is ±1.0 V, and the driver gain is set to
6 or 14. The output voltage (Vout) is given by the following equation:
Copyright © 2015, Texas Instruments Incorporated
21
TPIC2050
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6.0
Vout = DACcode ì
2048
14.0
VSPMout = DACcode ì
2048
Calculation by fixed point number :
Vdac = 1.0 ì bit[10] ì 0.51 + bit[9] ì 0.52 + bit[8] ì 0.53 + ... + bit[0] ì 0.511
(
)
Vdac = (œ1.0) ì bit[10] ì 0.51 + bit[9] ì 0.52 + bit[8] ì 0.53 + ... + bit[0] ì 0.511 + 0.512
(
)
Vout = Vdac ì 6.0 (V)
VSPMout = Vdac ì 14.0 (V)
STPVout = Vdac ì (P5V) (V)
SLEDIout = Vdac ì 0.88 (A)
where
•
bit[11:0] is the digital input value, range 000000000000b to 111111111111b
(1)
Table 4. DAC Format
ANALOG OUTPUT ANALOG OUTPUT
LSB
MSB DIGITAL INPUT (BIN)
HEX
DEC
VDAC
(5 V)
–5.997
–5.997
–0.003
0.000
0.003
5.994
5.997
(12 V)
–13.993
–13.993
–0.007
0.000
1000_0000_0000
1000_0000_0001
1111_1111_1111
0000_0000_0000
0000_0000_0001
0111_1111_1110
0111_1111_1111
0x800
0x801
0xFFF
0x000
0x001
0x7FE
0x7FF
–2048
–2047
–1
–0.9995
–0.9995
–0.0005
0
0
1
0.0005
0.9990
0.9995
0.007
2046
2047
13.986
13.993
Analog output(V)
+ 6.0 / + 14.0
VDAC
+ 1.000
+ 5.0 / + 12.0
*
800h
7FFh
DACcode
000
-5.0 / -12.0
-6.0 / -14.0
*
-1.000
*follow ing P5V, P12Vinputvoltage
Figure 11. Output Voltage vs DAC Code
22
Copyright © 2015, Texas Instruments Incorporated
TPIC2050
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ZHCSEQ5 –AUGUST 2015
8.4 Device Functional Modes
8.4.1 Differential Tilt Mode
The TPIC2050 supports differential tilt mode, which outputs the value calculated from focus and tilt. Focus and tilt
can be set in differential mode by DIFF_TLT (REG74) = 1. Because focus and tilt are updated at the same time,
the update interval of tilt can be thinned out. Output data changes after writing the VFCS data; therefore, write
VFCS data when setting VTLT. In differential mode, the output value is calculated as follows:
FCS_OUT = (VFCS + VTLT) × 6
TLT_OUT = (VFCS – VTLT) × 6
(2)
(3)
8.4.2 Power-On Reset (POR)
8.4.2.1 RDY (Power Ready)
The TPIC2050 prepares the RDY pin to show a power status to the host controller. A device sets RDY output to
high (= POR) if the supply voltage and internal regulator voltage reach a rated value. All registers initialize at the
time of the POR operation. Figure 12 shows the behavior of RDY.
RDY : High
(Write data)
Registerreset
Registervalid data
XRSTIN= L(*1)
or RST_ REGS= 1
P5V > 3.9V
CV3P3 > 2.8V
P5V < 3.7V
&
orCV3P3< 2.7 V
or SIOV < 2.0V
or P12V < 8.4V
& SIOV> 2.1V
& P12V> 8.8V
RDY : Low
(*1)TheperiodofXRSTINcannotbecommunicatedwithdevice.
Figure 12. RDY Pin Behavior
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8.5 Programming
8.5.1 Serial Port Functional Description
The serial communication of the TPIC2050 is based on an SPI communications protocol. The TPIC2050 is put
on the slave side. All 16-bit transmission data is effective in SSZ = L period.
The bit stream sent through SIMO from a master (DSP) is latched to an internal shift register by the rising edge
of SCLK. All the data is transmitted in a 16-bit command and data format. A format has two types of data, 8 bits
and 12 bits in length. To access specific registers, an address and R/W flag are specified as a command part. In
addition, 12-bit data does not have an R/W flag in the packet, because the DAC registersꢀ(= 12-bit data form)
are Write only. A transfer packet (command and data) is transmitted sequentially from MSB to LSB. A packet is
distinguished in MSB by 2 bits of command. In the case of 11, it handles a packet for control register access, and
the other is processed as a packet for a DAC data setting.
The four kinds of serial-data communication packets are:
•
•
•
•
Write 12 bits DAC data (MSB two bit ≠ 11)
Write 8 bits control register (MSB two bit = 11)
Read 8 bits control register (MSB two bit = 11)
Write 12 bits focus DAC data + Read 8 bits status register at the same time (MSB two bit ≠ 11)
8.5.2 Write Operation
For write operations, the DSP transmits 16-bit (command + address + data) data in order from MSB. Only the 16-
bit data, which means 16 SCLK sent from the master during SSZ = L, becomes effective. If more than 17 or less
than 15 SCLK pulses are received during the time that SSZ is low, the whole packet is ignored. For all valid write
operations, the data of the shift register is latched into its designated internal register at the rising edge of the
16th SCLK. All internal register bits, except indicated otherwise, are reset to their default states upon power-on
reset.
SSZ
SCLK
SIMO
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SOMI
Hi-Z
Figure 13. Write 12-Bits DAC Data
SSZ
SCLK
SIMO
SOMI
A6
A5
A4
A3
A2
A1
A0
W
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
Figure 14. Write 8-Bits Control Register
24
Copyright © 2015, Texas Instruments Incorporated
TPIC2050
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ZHCSEQ5 –AUGUST 2015
Programming (continued)
8.5.3 Read Operation
The DSP sends an 8-bit header through SIMO to perform a Read operation. The TPIC2050 starts to drive the
SOMI line upon the eighth falling edge of SCLK and shifts out eight data bits. The master DSP inputs 8-bit data
from SOMI after the ninth rising edge of SCLK. ꢀ
SSZ
SCLK
SIMO
SOMI
A6
A5
A4
A3
A2
A1
A0
R
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
Figure 15. Read 8-Bits Control Register
8.5.4 Write and Read Operation
Optionally, the master DSP can read the Status register while writing the 12 bits DAC (Focus DAC) packet. This
is enabled by setting the bit RDSTAT_ON_VFCS (REG74) = H.
SSZ
SCLK
SIMO
C3
C2
C1
C0
D11
D10
D9
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SOMI
Hi-Z
Figure 16. Write 12-Bits Focus DAC Data + Read 8-Bits Status Data
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8.6 Register Maps
All registers are in WRITE-protect mode after XRSTIN release. WRITE_ENA bit (REG76) = 1 is required before
writing data in the register.
8.6.1 Register State Transition
version data
Device Pow er On
(REG7E)
POR
Registerinitialized
P5V < 3.7V
or CV3P3 < 2.7V
orSIOV< 2.0V
P5V < 2.0V
or C V3P3 < 2.0V
orRST_ ERR_ FLAG= 1
or P12V < 8.4V
or P5V > 6.3V
or P12V > 14.5V
or SIF_ TIMEOUT_ ERR= 1
orRST_ REGS= 1
orXRSTIN= L
W RITE_ ENABLE= 0
orXSLEEP= 0
XRSTIN= H
P5V < 3.7V
or CV3P3 < 2.7V
orSIOV< 2.0V
or P12V < 8.4V
or P5V > 6.3V
or P12V > 14.5V
orXRSTIN= L
VDAC Reg data
(REG01-0A)
Control Reg data
REG70-77,7C
REG78[4:0]
REG7F[7,6,0]
REG6C-6F
or SIF_ TIMEOUT_ ERR= 1
orRST_ REGS= 1
Initial(000)
Vxxx W rite
RST_ INDAC= 1
or XXX_ ENA= 0
Error latched Reg data
(REG78[5],79,7A,7B,7F[5:1])
SPM option Reg
set Value
REG61-62
(REG6X_ W rite= 1)
(error occur)
Register valid data
Theregister contents are not affected.
Figure 17. Register Behavior
26
Copyright © 2015, Texas Instruments Incorporated
TPIC2050
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ZHCSEQ5 –AUGUST 2015
Register Maps (continued)
8.6.2 DAC Register (12-Bit Write Only)
Two different forms apply to the 12-bit DAC registers. The forms can be selected by setting VDAC_MAPSW
(REG74h).
Table 5. DAC Register (VDAC_MAPSW = 0)
Reg
Name
11
10
9
8
7
6
5
4
3
2
1
0
00h
N/A
N/A
VTLT
[11]
VTLT
[10]
VTLT
[9]
VTLT
[8]
VTLT
[7]
01h
02h
03h
VTLT
VFCS
VTRK
VTLT[6] VTLT[5] VTLT[4]
VFCS[6] VFCS[5] VFCS[4]
VTRK[6] VTRK[5] VTRK[4]
VTLT[3]
VFCS[3]
VTRK[3]
VSLD1[3]
VSLD2[3]
VTLT[2]
VFCS[2]
VTRK[2]
VSLD1[2]
VSLD2[2]
VTLT[1]
VFCS[1]
VTLT[0]
VFCS[0]
VFCS
[11]
VFCS
[10]
VFCS
[9]
VFCS
[8]
VFCS
[7]
VTRK
[11]
VTRK
[10]
VTRK
[9]
VTRK
[8]
VTRK
[7]
VTRK[1]
VTRK[0]
VSLD1 VSLD1 VSLD1 VSLD1 VSLD1 VSLD1
[11] [10] [9] [8] [7] [6]
VSLD1
[5]
VSLD1
[4]
04h VSLD1
05h VSLD2
06h VSTP1
07h VSTP2
VSLD1[1](1)
VSLD2[1](1)
VSTP1[1](1)
VSTP2[1](1)
VSPM[1]
VSLD1[0](1)
VSLD2[0](1)
VSTP1[0](1)
VSTP2[0](1)
VSPM[0]
VSLD2 VSLD2 VSLD2 VSLD2 VSLD2 VSLD2
[11] [10] [9] [8] [7] [6]
VSLD2
[5]
VSLD2
[4]
VSTP1 VSTP1 VSTP1 VSTP1 VSTP1 VSTP1
[11] [10] [9] [8] [7] [6]
VSTP1
[5]
VSTP1
[4]
VSTP1[3](1) VSTP1[2](1)
VSTP2[3](1) VSTP2[2](1)
VSTP2 VSTP2 VSTP2 VSTP2 VSTP2 VSTP2
[11] [10] [9] [8] [7] [6]
VSTP2
[5]
VSTP2
[4]
VSPM VSPM VSPM VSPM VSPM
[11] [10] [9] [8] [7]
08h
VSPM
VSPM[6] VSPM[5] VSPM[4]
VSPM[3]
VLOAD[3]
VLDD[3]
VSPM[2]
VLOAD[2]
VLDD[2]
VLOAD VLOAD VLOAD VLOAD VLOAD VLOAD
[11]
VLOAD
[5]
VLOAD
[4]
09h VLOAD
VLOAD[1]
VLDD[1]
VLOAD[0]
VLDD[0]
[10]
[9]
[8]
[7]
[6]
VLDD
[11]
VLDD
[10]
VLDD
[9]
VLDD
[8]
VLDD
[7]
0Ah
0Bh
VLDD
N/A
VLDD[6] VLDD[5] VLDD[4]
N/A
(1) TPIC2050 processes as 0 even if set to 1
Table 6. DAC Register (VDAC_MAPSW = 1)
Reg
Name
11
10
9
8
7
6
5
4
3
2
1
0
00h
N/A
N/A
VTRK
[11]
VTRK
[10]
01h
02h
03h
04h
05h
06h
VTRK
VFCS
VTLT
VTRK[9] VTRK[8] VTRK[7] VTRK[6] VTRK[5] VTRK[4] VTRK[3] VTRK[2] VTRK[1]
VFCS[9] VFCS[8] VFCS[7] VFCS[6] VFCS[5] VFCS[4] VFCS[3] VFCS[2] VFCS[1]
VTRK[0]
VFCS[0]
VTLT[0]
VFCS
[11]
VFCS
[10]
VTLT
[11]
VTLT
[10]
VTLT[9]
VTLT[8]
VTLT[7]
VTLT[6]
VTLT[5]
VTLT[4]
VTLT[3]
VTLT[2]
VTLT[1]
VSLD1
[11]
VSLD1
[10]
VSLD1
[9]
VSLD1
[8]
VSLD1
[7]
VSLD1
[6]
VSLD1
[5]
VSLD1
[4]
VSLD1
[3]
VSLD1
[2]
VSLD1
[1](1)
VSLD1
[0](1)
VSLD1
VSLD2
VSPM
VSLD2
[11]
VSLD2
[10]
VSLD2
[9]
VSLD2
[8]
VSLD2
[7]
VSLD2
[6]
VSLD2
[5]
VSLD2
[4]
VSLD2
[3]
VSLD2
[2]
VSLD2
[1](1)
VSLD2
[0](1)
VSPM
[11]
VSPM
[10]
VSPM[9] VSPM[8] VSPM[7] VSPM[6] VSPM[5] VSPM[4] VSPM[3] VSPM[2] VSPM[1]
VSPM[0]
VLDD[0]
VLDD
[11]
VLDD
[10]
07h
08h
09h
VLDD
N/A
VLDD[9] VLDD[8] VLDD[7] VLDD[6] VLDD[5] VLDD[4] VLDD[3] VLDD[2] VLDD[1]
N/A
VLOAD
[11]
VLOAD
[10]
VLOAD
[9]
VLOAD
[8]
VLOAD
[7]
VLOAD
[6]
VLOAD
[5]
VLOAD
[4]
VLOAD
N/A
N/A
N/A
VSTP1
[11]
VSTP1
[10]
VSTP1
[9]
VSTP1
[8]
VSTP1
[7]
VSTP1
[6]
VSTP1
[5]
VSTP1
[4]
0Ah
0Bh
VSTP1
VSTP2
VSTP2
[11]
VSTP2
[10]
VSTP2
[9]
VSTP2
[8]
VSTP2
[7]
VSTP2
[6]
VSTP2
[5]
VSTP2
[4]
(1) TPIC2050 processes as 0 even if set to 1
Copyright © 2015, Texas Instruments Incorporated
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ZHCSEQ5 –AUGUST 2015
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8.6.3 Control Register (8-Bit Read/Write)
Table 7. Control Register (8-Bit Read/Write)
Reg
Name
F
7
6
5
4
3
2
1
0
70h
DriverEna
R/W
TLT_ENA
FCS_ENA
TRK_ENA
SPM_ENA
SLD_ENA
STP_ENA
LOAD_ENA
XSLEEP
ENDDET
_ENA
TEMPMON
_ENA
71h
72h
73h
74h
75h
76h
77h
78h
79h
FuncEna
ACTCfg
Parm0
R/W
R/W
R/W
R/W
R/W
R/W
W
TI Rsvd
ENDDET_SEL
LDD_ENA
LDD_MSEL
P12VMUTE
_NORST
ACTPROT
_OFF
RSTIN_OFF
ACTTEMPTH
SLEDEND
_HZTIME
STPEND
_HZTIME
SIF_TIMEOUT_TH
SLDENDTH
STPENDTH
LDD_AMOD
E
STATUS
_ON_VFCS
VSLD2
_POL
VSTP2
_POL
ADVANCE
_RD
VDAC
_MAPSW
SIFCfg
DIFF_TLT
SOMI_HIZ
SPM_FAST SPM_SLNT
SPM
_HIZMODE
Parm1
TRAY_LOCKDET
TI Reserved
TI Reserved
_BRK
_BRK
WRITE
_ENABLE
REG6X
_Write
WriteEna
ClrReg
RST_ERR
_FLAG
RST_INDAC RST_REGS
TI Reserved
TI Reserved
ACTTEMP
ACT_TIMER
_PROT
ActTemp
UVLOMon
R
UVLO
_INT3P3
UVLO
_P12V
R
TI Reserved
TSD
UVLO_P5V
UVLO_SIOV OVP_P5V
OVP_P12V
TSD
_FAULT
_ACT
TSD
_FAULT
_LDD
TSD
_LDD
7Ah
TSDMon
R
TI Rsvd
_FAULT
_SPM
TI Rsvd
TSD_SPM
TSD_ACT
SCP_ACT
7Bh
7Ch
OCPMon
TempMon
R
R
TI Reserved
OCP_STP
SCP_SPM
SCP_SLED SCP_LOAD
CHIPTEMP
SCP_STP
CHIPTEMP
_STATUS
7Dh
7Eh
Protect
Version
R
R
TI Reserved
Version
SIF
_TIMEOUT
ERR
ACTTIMER
_FAULT
OCPSCPER
R
7Fh
60h
61h
Status
Protect
SPM1
R
ENDDET
TI Rsvd
PWRERR
TSDERR
TSDFAULT
FG
R/W
R/W
TI Reserved
TI Reserved
OVP
_SBRAKE
_OFF
PWMmaxDu
ty_R_SEL1
SBRAKE
_ON
TI Reserved
PWMmaxDu
ty_R_SEL0
62h
SPM2
R/W
TI Reserved
63h
64h
65h
66h
67h
68h
Protect
Protect
Protect
Protect
Protect
Protect
R/W
R/W
R/W
R/W
R/W
R/W
TI Reserved
TI Reserved
TI Reserved
TI Reserved
TI Reserved
TI Reserved
SCP_SPM
_OFF
SCP_SLED SCP_LOAD
SCP_ACT
_OFF
SCP_STP
_OFF
OCP_STP
_OFF
OVPPRE12
V_OFF
6Bh
DisProt
R/W
TI Rsvd
_OFF
_OFF
STP_WIND
_HIZ
STP
_WIND_H
6Ch
6Dh
6Eh
STPCfg
Protect
UtilCfg
R/W
R/W
R/W
TI Reserved
LDD_IUP
TI Reserved
TI Rsvd
GPOUT
_ENA
GPOUT_HL
TI Reserved
SIF_TIMEO
UTERR_MO
N
ACTTIMER
_FLT_MON
ENDDET
_MON
PWRERR
_MON
TSDERR
_MON
OCPERR
_MON
TSDFAULT
_MON
6Fh
MonitorSet
R/W
TI Rsvd
VTRK and VLOAD are exclusive, using same DAC circuit block.
28
Copyright © 2015, Texas Instruments Incorporated
TPIC2050
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ZHCSEQ5 –AUGUST 2015
8.6.4 Detailed Description of Registers
8.6.4.1 REG01 12-Bit DAC for Tilt (offset = 01h) [reset = ]
(VDAC_MAPSW = 0)
Figure 18. REG01 12-Bit DAC for Tilt
11
10
9
8
VTLT
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VTLT
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. REG01 12-Bit DAC for Tilt Field Descriptions
Bit
Field
Type
Reset
Description
11-0
VTLT
W
0h
Digital input code for tilt
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Output is changed by differential tilt mode (REG74[7])
TLT_OUT = VTLT × (6.0 / 2048) (DIFF_TLT = 0)
TLT_OUT = (VFCS – VTLT) × (6.0 / 2048) (DIFF_TLT = 1)
TLT_OUT should be changed after writing VFCS.
In DIFF_TLT mode (DIFF_TLT
changed after writing VFCS.
= 1), TLT_OUT should be
8.6.4.2 REG02 12-Bit DAC for Focus (offset = 02h) [reset = ]
(VDAC_MAPSW=0)
Figure 19. REG02 12-Bit DAC for Focus
11
10
9
8
VFCS
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VFCS
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. REG02 12-Bit DAC for Focus Field Descriptions
Bit
Field
Type
Reset
Description
11-0
VFCS
W
0h
Digital input code for focus
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Output is changed by differential tilt mode (REG74[7])
FCS_OUT = VFCS × (6.0 / 2048) (DIFF_TLT = 0)
FCS_OUT = (VFCS + VTLT) × (6.0 / 2048) (DIFF_TLT = 1)
Copyright © 2015, Texas Instruments Incorporated
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8.6.4.3 REG03 12-Bit DAC for Tracking (offset = 03h) [reset = ]
(VDAC_MAPSW=0)
Figure 20. REG03 12-Bit DAC for Tracking
11
10
9
8
VTRK
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VTRK
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. REG03 12-Bit DAC for Tracking Field Descriptions
Bit
Field
Type
Reset
Description
11-0
VTRK
W
0h
Digital input code for tracking
2’s complement format 0x800(-2048) to 0x7ff(+2047)
TRK_OUT = VTRK × (6.0 / 2048)
8.6.4.4 REG04 12-Bit DAC for Sled1 (offset = 04h) [reset = ]
(VDAC_MAPSW=0)
Figure 21. REG04 12-Bit DAC for Sled1
11
10
9
8
VSLD1
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VSLD1
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. REG04 12-Bit DAC for Sled1 Field Descriptions
Bit
Field
Type
Reset
Description
11-0
VSLD1
W
0h
Digital input code for Sled1.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Two bits on LSB, VSLD1[1:0], handled with zero.
SLD1_OUT = VSLD1 × (880 mA / 2048)
30
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8.6.4.5 REG05 12-Bit DAC for Sled2 (offset = 05h) [reset = ]
(VDAC_MAPSW=0)
Figure 22. REG05 12-Bit DAC for Sled2
11
10
9
8
VSLD2
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VSLD2
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. REG05 12-Bit DAC for Sled2 Field Descriptions
Bit
Field
Type
Reset
Description
11-0
VSLD2
W
0h
Digital input code for Sled2.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Two bits on LSB, VSLD2[1:0], are handled with zero.
SLD2_OUT = VSLD2 × (880 mA/2048)
8.6.4.6 REG06 12-Bit DAC for Stepping1 (offset = 06h) [reset = ]
(VDAC_MAPSW = 0)
Figure 23. REG06 12-Bit DAC for Stepping1
11
10
9
8
VSTP1
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VSTP1
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. REG06 12-Bit DAC for Stepping1 Field Descriptions
Bit
Field
Type
Reset
Description
11-0
VSTP1
W
0h
Digital input code for Stepping1
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Although VSTP1 is 12-bit width, MSB 8 bits is effective.
Four bits on LSB, VSTP1[3:0], are handled with zero.
VSTP1_OUT = VSTP1 × (P5V / 2048)
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8.6.4.7 REG07 12-Bit DAC for Stepping2 (offset = 07h) [reset = ]
(VDAC_MAPSW=0)
Figure 24. REG07 12-Bit DAC for Stepping2
11
10
9
8
VSTP2
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VSTP2
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. REG07 12-Bit DAC for Stepping2 Field Descriptions
Bit
Field
Type
Reset
Description
11-0
VSTP2
W
0h
Digital input code for Stepping2
2’s complement format 0x800(-2048) to 0x7ff(+2047)
Although VSTP2 is 12-bit width, MSB 8 bits is effective.
Four bits on LSB, VSTP2[3:0], are handled with zero.
VSTP2_OUT = VSTP2 × (P5V / 2048)
8.6.4.8 REG08 12-Bit DAC for Spindle (offset = 08h) [reset = ]
(VDAC_MAPSW = 0)
Figure 25. REG08 12-Bit DAC for Spindle
11
10
9
8
VSPM
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VSPM
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. REG08 12-Bit DAC for Spindle Field Descriptions
Bit
Field
Type
Reset
Description
11-0
VSPM
W
0h
Digital input code for Spindle
2’s complement format 0x800(-2048) to 0x7ff(+2047)
SPM_OUT = VSPM × (14.0 / 2048)
32
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8.6.4.9 REG09 12-Bit DAC for Load (offset = 09h) [reset = ]
(VDAC_MAPSW = 0)
Figure 26. REG09 12-Bit DAC for Load
11
10
9
8
VLOAD
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VLOAD
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. REG09 12-Bit DAC for Load Field Descriptions
Bit
Field
Type
Reset
Description
11-0
VLOAD
W
0h
Digital input code for Load.
2’s complement format 0x800(-2048) to 0x7ff(+2047)
LOAD_OUT = VLOAD × (6.0 / 2048) at P5V12L = 5.0 V
LOAD_OUT = VLOAD × (14.0/2048) at P5V12L = 12.0 V
8.6.4.10 REG0A 12-Bit DAC for Laser Diode Driver (offset = 0Ah) [reset = ]
(VDAC_MAPSW = 0)
Figure 27. REG0A 12-Bit DAC for Laser Diode Driver
11
10
9
8
VLDD
w-0
3
w-0
2
w-0
1
w-0
0
7
6
5
4
VLDD
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. REG0A 12-Bit DAC for Laser Diode Driver Field Descriptions
Bit
Field
Type
Reset
Description
11-0
VLDD
W
0h
Digital input code for VLDD.
Since VLDD is 11 bit length, VLDD[11] should be set 0.
Binary format 0x000 to 0x7ff(+2047)
LDD_OUT = VLDD × (120 mA / 2048)
MSB (bit 11) is secured in order to unite with other 12-bit form.
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8.6.4.11 REG70 8-Bit Control Register for DriverEna (offset = 70h) [reset = ]
Figure 28. REG70 8-Bit Control Register for DriverEna
7
6
5
4
3
2
1
0
TLT_ENA
rw-0
FCS_ENA
rw-0
TRK_ENA
rw-0
SPM_ENA
rw-0
SLD_ENA
rw-0
STP_ENA
rw-0
LOAD_ENA
rw-0
XSLEEP
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. REG70 8-Bit Control Register for DriverEna Field Descriptions
Bit
7
Field
Type
RW
RW
RW
RW
RW
RW
RW
Reset
0h
Description
TLT_ENA
FCS_ENA
TRK_ENA
SPM_ENA
SLD_ENA
STP_ENA
LOAD_ENA
1h = Tilt enable (with XSLEEP = 1)
1h = Focus enable (with XSLEEP = 1)
1h = Track enable (with XSLEEP = 1)
1h = Spindle enable (with XSLEEP = 1)
1h = Sled enable (with XSLEEP = 1)
1h = Step enable (with XSLEEP = 1)
6
0h
5
0h
4
0h
3
0h
2
0h
1
0h
1h = LOAD enable (with XSLEEP = 1)
Track (bit5:TRK_ENA) will be disabled at LOAD_ENA = 1
because of sharing the DAC PWM module. Load priority is
higher than TRK_ENA.
0
XSLEEP
RW
0h
1h = Operation mode (need 1 ms)
0h = Power save mode
Charge pump enable bit
All driver enable bit (Bit[7:1]) change disabled and output
change to Hi-Z (regardless of setting xxx_ENA bit is 1) when
setting XSLEEP to 0. Therefore, set 1 to XSLEEP before setting
each enable bits.
8.6.4.12 REG71 8-Bit Control Register for FuncEna (offset = 71h) [reset = ]
Figure 29. REG71 8-Bit Control Register for FuncEna
7
6
5
4
3
2
1
0
TI reserved
ENDDET_ENA
ENDDET_SEL
LDD_ENA
LDD_MSEL
rw-0
TEMPMON
_ENA
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. REG71 8-Bit Control Register for FuncEna Field Descriptions
Bit
7
Field
Type
RW
Reset
0h
Description
Reserved
ENDDET_ENA
6
RW
0h
1h = Use sled/step_End, load tray lock detection enable (with
STP_ENA = 1, or SLD_ENA = 1, or LOAD_ENA = 1)
5-4
ENDDET_SEL
RW
0h
00 : Sled end detection monitor
01 : Step end detection monitor
10 : Load tray lock detection monitor
1h = LDD enable (with XSLEEP = 1)
3
LDD_ENA
RW
RW
0h
0h
2-1
LDD_MSEL
Laser diode driver output selection
00: No select
01: CD
10: DVD
11: BD
0
TEMPMON_ENA
RW
0h
1h = Enable chip temperature monitoring (with XSLEEP = 1)
34
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8.6.4.13 REG72 8-Bit Control Register for ACTCfg (offset = 72h) [reset = ]
Figure 30. REG72 8-Bit Control Register for ACTCfg
7
6
5
4
3
2
1
0
P12VMUTE
_NORST
RSTIN_OFF
ACTPROT
_OFF
ACTTEMPTH
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. REG72 8-Bit Control Register for ACTCfg Field Descriptions
Bit
Field
Type
Reset
Description
7
P12VMUTE_NORST
RW
0h
0h = System reset at P12V low voltage
1h = Output High-Z only at P12V low voltage detection
6
5
RSTIN_OFF
RW
RW
RW
0h
0h
0h
0h = XRSTIN input enable
1h = Ignored XRSTIN pin input (do not reset device when
XRSTIN = L)
ACTPROT_OFF
ACTTEMPTH
0h = Actuator protection ON
1h = Actuator fault monitor disable (no protection for ACT
channel)
4-0
Actuator thermal protection (= ACT Timer) threshold level
ACT Timer Protection enable except ACTTEMPTH[4:0] = 0x00
ACTTEMPTH = 0x00 equal to ACTPROT_OFF = 1
By writing value 0x00, ACTTIMER_PROT flag is cleared.
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8.6.4.14 REG73 8-Bit Control Register for Parm0 (offset = 73h) [reset = ]
Figure 31. REG73 8-Bit Control Register for Parm0
7
6
5
4
3
2
1
0
SIF_TIMEOUT_TH
SLEDEND
_HZTIME
SLDENDTH
rw-0
STPEND
_HZTIME
STPENDTH
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. REG73 8-Bit Control Register for Parm0 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
SIF_TIMEOUT_TH
RW
0h
Watch dog timer for serial communication
0h = disable
1h = 1 ms
2h = 100 µs
3h = 10 µs
Set SIF_TIMEOUTERR (REG7D) if communication is
suspended for this time period. Reset register processing is
performed if a SIF_TIMEOUTERR occurs.
5
SLEDEND_HZTIME
SLDENDTH
RW
RW
0h
0h
Time window for sled end detection.
0h = 400 µs
1h = 200 µs
Note: Need to recycle SLD_ENDDET_ENA = 0 → 1 after writing
this bit.
4-3
Sled end detection sensibility setting. Detection threshold for
motor BEMF
00: 124 mV
01: 168 mV
11: 73 mVꢀ
10: 0 mV
2
STPEND_HZTIME
STPENDTH
RW
RW
0h
0h
Step High-Z detection period in end detection
0h = 400 µs
1h = 200 µs
Note: Need to recycle STP_ENDDET_ENA = 0 → 1 after writing
this bit.
1-0
Step end detection sensibility setting
00: 39 mV
01: 60 mV
11: 19 mV
10: 0 mV
36
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8.6.4.15 REG74 8-Bit Control Register for SIFCfg (offset = 74h) [reset = ]
Figure 32. REG74 8-Bit Control Register for SIFCfg
7
6
5
4
3
2
1
0
DIFF_TLT
LDD_AMODE
RDSTAT
VSLD2_POL
VSTP2_POL
ADVANCE_RD
SOMI_HIZ
VDAC_MAPSW
_ON_VFCS
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. REG74 8-Bit Control Register for SIFCfg Field Descriptions
Bit
Field
Type
Reset
Description
7
DIFF_TLT
RW
0h
1h = Differential tilt mode enable (with TLT_ENA = FCS_ENA =
1)
Differential tilt mode (DIFF_TLT = 1), DAC value setting as
follows
FCS_OUT = (VFCS + VTLT) × 6 / 2048
TLT_OUT = (VFCS – VTLT) × 6 / 2048
In DIFF_TLT mode (DIFF_TLT
changed after writing VFCS.
= 1), TLT_OUT should be
6
5
LDD_AMODE
RW
RW
0h
0h
Setting LDD analog mode
0h = VLDD set by VDAC register (REG0A)
1h = VLDD set by voltage input via VLDDIN pin
RDSTAT_ON_VFCS
Set Read status data (REG7F) at VFCS write command
(REG02)
1h = Enable Write and Read mode
(Write 12 bits Focus DAC data + Read 8 bits status data)
Change direction of SLED rotation
4
3
2
VSLD2_POL
VSTP2_POL
ADVANCE_RD
RW
RW
RW
0h
0h
0h
Change direction of STEP rotation
0h = Normal read timing
1h = Read timing is advanced half clock cycle
1
0
SOMI_HIZ
RW
RW
0h
0h
0h = SOMI line High-Z at bus idling time.
1h = SOMI line pull down at bus idling time.
VDAC_MAPSW
1h = Change channel assignments of DAC register (REG01~0A)
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8.6.4.16 REG75 8-Bit Control Register for Parm1 (offset = 75h) [reset = ]
Figure 33. REG75 8-Bit Control Register for Parm1
7
6
5
4
3
2
1
0
TRAY_LOCKDET
TI reserved
rw-0
SPM_FAST
_BRK
SPM_SLNT
_BRK
SPM
_HIZMODE
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. REG75 8-Bit Control Register for Parm1 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
TRAY_LOCKDET
RW
0H
Load tray locking detection control
0h = Disable detection
1-7: Detection threshold
1h = 100 mA
2h = 150 mA
3h = 200 mA
4h = 250 mA
5h = 300 mA
6h = 350 mA
7h = 400 mA
4-3
2
Reserved
RW
RW
0h
0h
SPM_FAST_BRK
Fast brake mode selection
0h = Normal brake mode perform auto short brake sequence in
specific speed
1h = No short brake under 5500 rpm
1
0
SPM_SLNT_BRK
SPM_HIZMODE
RW
RW
0h
0h
Silent brake mode selection
0h = Normal brake mode
1h = No active brake under 5500 rpm
Active brake mode is not performed inputting any value into
VSPIN.
Spindle output Hi-Z mode
0h = Normal operation
1h = Spindle output (UVW) put Hi-Z (use for test purpose)
8.6.4.17 REG76 8-Bit Control Register for WriteEna (offset = 76h) [reset = ]
Figure 34. REG76 8-Bit Control Register for WriteEna
7
6
5
4
3
2
1
0
WRITE
_ENABLE
TI reserved
rw-0
REG6X_Write
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. REG76 8-Bit Control Register for WriteEna Field Descriptions
Bit
Field
Type
Reset
Description
7
WRITE_ENABLE
RW
0h
0h = Register Write disable except REG76
1h = Write enable for registers REG01~09, REG70~7F
6-1
0
Reserved
RW
RW
0h
0h
REG6X_Write
0h = Disable Write access REG6X bank
1h = Enable Write access REG6X bank
38
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8.6.4.18 REG77 8-Bit Control Register for ClrReg (offset = 77h) [reset = ]
Figure 35. REG77 8-Bit Control Register for ClrReg
7
6
5
4
3
2
1
0
RST_INDAC
RST_REGS
RST_ERR
_FLAG
TI reserved
w-0
w-0
w-0
w-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. REG77 8-Bit Control Register for ClrReg Field Descriptions
Bit
Field
Type
Reset
Description
7
RST_INDAC
W
0h
1h = Reset all 12-bit input DAC register (REG01~09)
*Self clear bit
6
5
RST_REGS
RST_ERR_FLAG
Reserved
W
W
W
0h
0h
0h
1h = Reset all 8-bit R/W Registers (REG70h~77h, 60h-6Fh)
*Self clear bit
1h = Reset Fault Flag Latch (REG7F, REG79~REG7D)
*Self clear bit
4-0
8.6.4.19 REG78 8-Bit Control Register for ActTemp (offset = 78h) [reset = ]
Figure 36. REG78 8-Bit Control Register for ActTemp
7
6
5
4
3
2
1
0
TI reserved
r-0
ACT_TIMER
_PROT
ACTTEMP
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. REG78 8-Bit Control Register for ActTemp Field Descriptions
Bit
7-6
5
Field
Type
R
Reset
0h
Description
Reserved
ACT_TIMER_PROT
R
0h
ACT timer protection flag
1h = ACT timer protection has detected and latched.
(ACTTEMP > ACTTEMPTH)
This bit holds data after temperature change to low since this is
latch bit. Also driver output keep Hi-Z until setting
a
RST_ERR_FLAG or ACTTEMPTH = 0.
4-0
ACTTEMP
R
0h
An integrated value of ACT_TIMER counters at present
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8.6.4.20 REG79 8-Bit Control Register for UVLOMon (offset = 79h) [reset = ]
Figure 37. REG79 8-Bit Control Register for UVLOMon
7
6
5
UVLO_P5V
r-0
4
UVLO_INT3P3
r-0
3
UVLO_P12V
r-0
2
UVLO_SIOV
r-0
1
OVP_P5V
r-0
0
OVP_P12V
r-0
TI Reserved
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. REG79 8-Bit Control Register for UVLOMon Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
(1)
5
UVLO_P5V
UVLO_INT3P3
UVLO_P12V
UVLO_SIOV
OVP_P5V
OVP_P12V
R
0h
UVLO flag for detection Low P5V supply
4
R
0h
UVLO flag for detection Low internal 3.3 V regulator(1)
(1)
3
R
0h
UVLO flag for detection Low P12V supply
(1)
2
R
0h
UVLO flag for detection Low SIOV supply
(1)
1
R
0h
Overvoltage protection flag for P5V supply
(1)
0
R
0h
Overvoltage protection flag for P12V supply
(1) Latched first reset event only. Cleared by RST_ERR_FLG (REG77)
8.6.4.21 REG7A 8-Bit Control Register for TSDMon (offset = 7Ah) [reset = ]
Figure 38. REG7A 8-Bit Control Register for TSDMon
7
6
5
4
3
2
1
0
TI reserved
TSD_FAULT
_SPM
TSD_FAULT
_ACT
TSD_FAULT
_LDD
TI reserved
TSD_SPM
TSD_ACT
TSD_ LDD
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. REG7A 8-Bit Control Register for TSDMon Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
6
TSD_FAULT_SPM
TSD_FAULT_ACT
R
0h
Pre alert of thermal protection of Spindle block(1)
5
R
0h
Pre alert of thermal protection of focus, track, tilt, sled1, sled2,
step1, step2, load(1)
4
3
2
TSD_FAULT_LDD
Reserved
R
R
R
0h
0h
0h
Prealert of thermal protection of LDD(1)
Thermal protection flag for Spindle(1)
SPM output Hi-Z until temperature falls on release level
1h = Detect (latch)
TSD_SPM
1
0
TSD_ACT
TSD_ LDD
R
R
0h
0h
Thermal protection flag for focus, track, tilt, sled1, sled2, step1,
step2, load(1)
Actuator output Hi-Z until temperature falls on release level
1h = Detect (latch)
Thermal protection flag for LDD(1)
LDD output Hi-Z until temperature falls on release level
1h = Detect (latch)
(1) Cleared by RST_ERR_FLAG bit (REG77)
40
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8.6.4.22 REG7B 8-Bit Control Register for OCPMon (offset = 7Bh) [reset = ]
Figure 39. REG7B 8-Bit Control Register for OCPMon
7
6
5
4
SCP_SPM
r-0
3
SCP_SLED
r-0
2
SCP_LOAD
r-0
1
0
TI reserved
OCP_STP
SCP_ACT
r-0
SCP_STP
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 29. REG7B 8-Bit Control Register for OCPMon Field Descriptions
Bit
7-6
5
Field
Type
R
Reset
0h
Description
Reserved
OCP_STP
SCP_SPM
SCP_SLED
SCP_LOAD
SCP_ACT
SCP_STP
R
0h
Overcurrent protection flag bit for step block(1)
Short protection flag bit for spindle block(1)
Short protection flag bit for sled block(1)
Short protection flag bit for load block(1)
Short protection flag bit for actuator block(1)
Short protection flag bit for step block(1)
4
R
0h
3
R
0h
2
R
0h
1
R
0h
0
R
0h
(1) Cleared by RST_ERR_FLAG bit (REG77)
8.6.4.23 REG7C 8-Bit Control Register for TempMon (offset = 7Ch) [reset = ]
Figure 40. REG7C 8-Bit Control Register for TempMon
7
6
5
4
3
2
1
0
TI Reserved
CHIPTEMP
_STATUS
CHIPTEMP
r-0
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30. REG7C 8-Bit Control Register for TempMon Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
6
CHIPTEMP_STATUS
R
0h
1h = New data CHIPTEMP[5:0] is updated It will be cleared after
reading.
5-0
CHIPTEMP
R
0h
Chip temperature monitor (2.38°/LSB)
15(0) to 165(63) degrees.
For monitoring, TEMPMON_ENA = 1 and XSLEEP = 1 is
required
8.6.4.24 REG7E 8-Bit Control Register for Version (offset = 7Eh) [reset = ]
Figure 41. REG7E 8-Bit Control Register for Version
7
6
5
4
3
2
1
0
Version
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31. REG7E 8-Bit Control Register for Version Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Version
R
0h
Version[7:4] = Revision number of TPIC2050
Version[3:0] = Option
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8.6.4.25 REG7F 8-Bit Control Register for Status (offset = 7Fh) [reset = ]
Figure 42. REG7F 8-Bit Control Register for Status
7
6
5
4
3
2
1
0
ACTTIMER
_FAULT
ENDDET
SIF_TIMEOUT
ERR
PWRERR
TSDERR
OCPERR
TSDFAULT
FG
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32. REG7F 8-Bit Control Register for Status Field Descriptions
Bit
Field
Type
Reset
Description
7
ACTTIMER_FAULT
R
0h
Status flag of ACTTIMER protection
1h
= Prealert of ACTTIMER protection. It is close to the
threshold level. The user can get the current ACTTIMER value
in REG78.
Both this bit and ACT_TIMER_PROT (REG78) are set when
over the threshold.
6
5
ENDDET
R
R
0h
0h
Status flag of END detection
1h
= End position detected (not latch bit) for step/sled.
(ENDDET_SEL = 10)
Load motor current exceeds threshold at using load tray lock
detection. (ENDDET_SEL = 10)
SIF_TIMEOUTERR
Error flag of serial interface watch dog timer
1h = SIF communication was interrupted, expired watch dog
timer
4
3
2
1
0
PWRERR
TSDERR
OCPERR
TSDFAULT
FG
R
R
R
R
R
0h
0h
0h
0h
0h
Error flag of power
1h = Voltage problem occurred, details in REG79
Error flag of any overthermal protections
1h = Dispatched thermal protection, details in REG7A
Error flag of any short-circuit protection
1h = Dispatched SCP, details in REG7Bh
Warning of TSD of any thermal protection
1h = Detect pre thermal protection, details in REG7A
FG signal. Spindle rotation pulse for speed monitor
42
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8.6.4.26 REG61 8-Bit Control Register for SPM1 (offset = 61h) [reset = ]
Figure 43. REG61 8-Bit Control Register for SPM1
7
6
5
4
3
2
1
0
PWMmaxDuty
_R_SEL1
TI reserved
OVP_SBRAKE
_OFF
TI reserved
rw-0
SBRAKE_ON
TI reserved
rw-0
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33. REG61 8-Bit Control Register for SPM1 Field Descriptions
Bit
Field
Type
Reset
Description
7
PWMmaxDuty_R_SEL1
RW
0h
PWM duty maximum setting in active brake mode (upper bit of
PWMmaxDuty_R_SEL[1:0])
00: Maximum PWM duty 12.5%
ꢀ 01: Maximum PWM duty 25%
10: Maximum PWM duty 37.5%
11: Maximum PWM duty 37.5%
(TI recommends to set to 0X in case of use in no-disk, because
it may not stop in a specific motor setting 37.5%.)
6
5
Reserved
RW
RW
0h
0h
OVP_SBRAKE_OFF
Select short brake mode of P12V pre-OVP
0h = 3-phase short brake mode
1h = 2-phase short brake mode
4-3
2
Reserved
RW
RW
0h
0h
SBRAKE_ON
Force short brake
0h = No brake
1h = Perform 3-phase short brake in any state
1-0
Reserved
RW
0h
8.6.4.27 REG62 8-Bit Control Register for SPM2 (offset = 62h) [reset = ]
Figure 44. REG62 8-Bit Control Register for SPM2
7
6
5
4
3
2
1
0
TI reserved
rw-0
PWMmaxDuty
_R_SEL0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34. REG62 8-Bit Control Register for SPM2 Field Descriptions
Bit
7-1
0
Field
Type
RW
Reset
0h
Description
Reserved
PWMmaxDuty_R_SEL0
RW
0h
PWM duty maximum setting in active brake mode (lower bit of
PWMmaxDuty_R_SEL[1:0])
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8.6.4.28 REG6B 8-Bit Control Register for DisProt (offset = 6Bh) [reset = ]
Figure 45. REG6B 8-Bit Control Register for DisProt
7
6
5
4
3
2
1
0
SCP_SPM
_OFF
SCP_SLED
_OFF
SCP_LOAD
_OFF
SCP_ACT
_OFF
SCP_STP_OFF
OCP_STP
_OFF
TI reserved
OVPPRE12V
_OFF
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 35. REG6B 8-Bit Control Register for DisProt Field Descriptions
Bit
Field
Type
Reset
Description
7
SCP_SPM_OFF
RW
0h
Control bit of short-circuit protection function for spindle block
0h = Enable SCP function
1h = Disable SCP function
Caution(1): TI recommends using it only for test purposes.
6
5
4
3
2
SCP_SLED_OFF
SCP_LOAD_OFF
SCP_ACT_OFF
SCP_STP_OFF
OCP_STP_OFF
RW
RW
RW
RW
RW
0h
0h
0h
0h
0h
For sled driver block
Caution(1): TI recommends using it only for test purposes.
For load driver block
Caution(1): TI recommends using it only for test purposes.
For actuator driver block
Caution(1): TI recommends using it only for test purposes.
For step driver block
Caution(1): TI recommends using it only for test purposes.
Control bit of overcurrent protection function for stepper block
0h = Enable OCP function
1h = Disable OCP function
Caution(1): TI recommends using it only for test purpose.
1
0
Reserved
RW
RW
0h
0h
OVPPRE12V_OFF
Disable short brake function at P12V pre-OVP condition.
0h = Enable function which perform short brake at 12-V pre-
OVP
1h = Disable short brake at 12-V pre-OVP
TI recommend to set to 0
(1) CAUTION: Device will be fatally damaged if short circuit occurs in the xxx_OFF = 1.
44
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8.6.4.29 REG6C 8-Bit Control Register for STPCfg (offset = 6Ch) [reset = ]
Figure 46. REG6C 8-Bit Control Register for STPCfg
7
6
5
4
3
2
1
0
TI Reserved
LDD_IUP
TI Reserved
STP_WIND
_HIZ
STP_WIND_H
rw-0
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 36. REG6C 8-Bit Control Register for STPCfg Field Descriptions
Bit
7-5
4-3
Field
Type
RW
Reset
0h
Description
Reserved
LDD_IUP
RW
0h
Extend LDD maximum current
00: 120 mA
01: 1.24× an initial value
10: 1.48× an initial value (*1)
11: 1.72× an initial value (*2)
*1) The LDD output time of the maximum current should maintain 50% or
less of the xsleep total ON time.
*2) The LDD output time of the maximum current should maintain 25% or
less of the xsleep total ON time.
2
1
Reserved
RW
RW
0h
0h
STP_WIND_HIZ
0h = Normal end detection
1h = When detecting BEMF, set STP1 and STP2 FET Hi-Z to reduce
mutual noise.
0
STP_WIND_H
RW
0h
0h = Normal end detection
1h = When detecting BEMF, set driving phase to Hi (detecting phase Hi-Z)
to reduce mutual noise.
8.6.4.30 REG6E 8-Bit Control Register for UtilCfg (offset = 6Eh) [reset = ]
Figure 47. REG6E 8-Bit Control Register for UtilCfg
7
6
5
4
3
2
1
0
GPOUT_HL
rw-0
GPOUT_ENA
rw-0
TI reserved
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 37. REG6E 8-Bit Control Register for UtilCfg Field Descriptions
Bit
Field
Type
Reset
Description
7
GPOUT_HL
RW
0h
GPOUT (general-purpose output) pin output selection
0h = Low output
1h = High output
Valid only if REG6F = 00h
6
GPOUT_ENA
Reserved
RW
RW
0h
0h
Enable monitor signal output to GPOUT pin
0h = No signal output, Hi-Z
1h = Output signal selected in REG6F with CMOS output
Output is logical OR when selected two more signals
5-0
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8.6.4.31 REG6F 8-Bit Control Register for MonitorSet (offset = 6Fh) [reset = ]
Figure 48. REG6F 8-Bit Control Register for MonitorSet
7
6
5
4
3
2
1
0
ACTTIMER
_FLT_MON
ENDDET
_MON
SIF
_TIMEOUTER
R
PWRERR
_MON
TSDERR_MON
OCPERR
_MON
TSDFAULT
_MON
TI Rsvd
_MON
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 38. REG6F 8-Bit Control Register for MonitorSet Field Descriptions
Bit
7
Field
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0h
Description
ACTTIMER_FLT_MON
MONITOR_MON
SIF_TIMEOUTERR_MON
PWRERR_MON
TSDERR_MON
SCPERR_MON
TSDFAULT_MON
Reserved
1h = ACTTIMER fault output to GPOUT pin
1h = ENDDET monitor output to GPOUT pin
1h = SIF timeout monitor output to GPOUT pin
1h = PWRERR monitor output to GPOUT pin
1h = TSDERR fault output to GPOUT pin
1h = OCPERR fault output to GPOUT pin
1h = TSDFAULT fault output to GPOUT pin
6
0h
5
0h
4
0h
3
0h
2
0h
1
0h
0
0h
46
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Voltage Monitoring
Power faults are reported in the UVLOMon register. Each UVLOMon bit initializes to 0 upon a cold power up.
After a fault is detected, the appropriate fault bit is latched high. Writing to the RST_ERRFLG (REG77) clears all
UVLOMon bits. Table 39 summarizes the power device faults and actions.
Table 39. Power Fault Monitor
DRIVER OUTPUT AT DETECTION
LATCHED
REGISTER
CRITERI
A
FAULT TYPE
POR
SPM
SLED
LOAD
STEP
ACT
LDD
P5V under
voltage
UVLO_P5V
UVLO_INT3P3
UVLO_P12V
Yes
Yes
<3.7 V
<2.7 V
<8.4 V
Hi-Z
Hi-Z
Hi-Z
Internal 3.3-V
under voltage
P12V under
voltage
Yes(1)
Yes
SIOV under
voltage
UVLO_SIOV
OVP_P5V
<2.0 V
>6.2 V
>14.9 V
Hi-Z
Hi-Z
P5V over voltage
P12V over
voltage
OVP_P12V
Hi-Z
—
—
—
(1) P12VMUTE_NORST = 0: force POR, P12VMUTE_NORST=1: no POR
9.1.2 Spindle Motor Driver Operating Sequence
When the VSPM is set to a positive DAC code, it enters into acceleration mode. Initial position sense (IS) mode
then operates, as the start-up circuits offer the start-up pattern sequence to the driver, then switch to spin-up
mode by detecting the rotor position using the BEMF signal from the spindle motor coil.
The spin-down and brake function are also controlled by the DAC value VSPM. When it has set the brake
command to the VSPM, the driver goes into active-brake mode, then switches to short-brake mode in slow
revolution speed, and then stops automatically. EXOR of a three-phase signal comprises the FG signal and is
output from the XFG pin as shown in Figure 49.
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RDY
XRSTIN
WRITE_ENABLE
XSLEEP
SPM_ENA
VSPM
XFG
VSPM[11:0] > 0
VSPM[11:0] < 0
0
brake
speed
>15ms
release
300ms
260rpm
time
Figure 49. Spindle Operating Sequence
Use the down-edge of the FG signal for monitoring FG frequency.
Short brake mode asserts after 300 ms if the FG signal stays L-level in deceleration.
This value is the nominal number of using a 12-poles motor.
The internal circuit starts 800 µs (typical) after the RDY pin changes to 'H'.ꢀRecommended marginal delay value
is 1 ms.
9.1.3 Auto Short Brake Function
The TPIC2050 provides an auto short brake function that selects a brake mode automatically by motor speed.
Auto short brake includes two modes: short brake and active brake. If a value of 0xF90 or less is set to the
VSPM, the brake mode automatically changes at rotation speed. This function enables low-power consumption
and silent braking. Figure 50 shows the relation between brake mode and speed. The over-speed protect
function suspends the SPM driver output at 15000 or more revolutions.
48
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Table 40. Brake Mode
APPROXIMATE ROTATION SPEED (RPM)(1)
11500 TO 5600 5600 TO 4000
2-phase short brake
Active brake
VSPM[11:0]
MODE
11500
4000 TO 0
0x000 to 0xFDD
0xFDC to 0xF90
Manual
Manual
3-phase short
Brake(2)
0xF8F to 0xADB
0xADA to 0x800
Auto short
Auto short
Free run
Free run
Active brake
Active brake
3-phase short brake(3)
(1) Typical value using a 12-pole motor
(2) Active brake is chosen when it does not exceed 6400 rpm once from a rotation start.
(3) Active brake is chosen when it does not exceed 4600 rpm once from a rotation start.
rpm
Hi-Z (over speed protecion)
15600
Free run
*1
11500
3-phase short
2-phase
short
auto
5600
4000
*1
auto
Active
( selectable 3-phaseshort )
0
800h
ADBh
F90h FDDh 000
VSPM[11:0]
Each threshold value has hysteresis.
Brake mode will change to specific mode at the threshold speed after it reaches a speed about 15% higher than a
threshold speed.
NOTE: These speed values are the nominal number of using a 12-pole motor. In applying to a 16-pole motor, the rotation
speed becomes 75% of indicated rpm values.
Figure 50. Brake Mode Selection
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9.1.4 Spindle PWM Control
The output PWM duty of the spindle is controlled by the DAC code (VSPM). The gain in acceleration setting is
always 14 times, but the maximum output is restricted to P12V voltage. A dead band with an output = 0 exists in
the width between ±0x52 focusing on zero.
PW M outputduty
100%
output (V)
P12V
(PWMmax
Duty_R_SEL)
37.5%
dead band
duty= 0%
25.0%
12.5%
speed up
slow down
0%
800h
FAEh
000
52h
7FFh
VSPM[11:0]
Figure 51. Spindle PWM Control
9.1.5 Spindle Driver Current Limiting Circuit
The current limit circuit monitors the RCS voltage at the ICOM pin and limits the output current by reducing the
PWM duty when detecting overcurrent conditions.
9.1.6 Sled Driver Part
The sled driver outputs the PWM pulse set as DAC code (VSLDx) with current feedback. The maximum output is
restricted to 880 mA at 0x7FF and 0x800. A dead band with an output = 0 exists in the width of ±0x33 focusing
on zero.
outputcurrent
reverse
forw ard
880m A
dead band
ISLEDxP
= ISLEDxN
ISLEDxP < ISLEDxN
ISLEDxP > ISLEDxN
0
FCDh
33h
800h
000
7FFh
VSLDx[11:0]
Figure 52. Sled Output Current
50
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Both outputs of SLED1/2 are 'H' when the input code is in the dead band.
9.1.7 Stepping Driver Part
The step driver outputs the PWM pulse, set as an 8-bit DAC code (VSTPx) using VSTP[11:4]. There is no
feedback monitor for output. The pulse width is output according to the P5V power supply voltage.
outputPW M duty
flow STPxN→STPxP
flow STPxP→STPxN
100%
dutySTPxN
dutySTPxP
0%
FF0h
020h
800h
000
VSTPx[11:4]
Figure 53. Step Output Duty
7F0h
9.1.8 Focus/Track/Tilt Driver Part
PW M output duty
100%
P5V
reverse
forw ard
ACT+ < ACT-
ACT+ > ACT-
0%
800h
000
7FFh
ACT(FCS/TRK/TLT)[11:0]
Figure 54. FCS/TRK/TLT Output Duty
9.1.9 Load Driver Part
The load driver outputs the voltage with the voltage feedback corresponding to the input DAC value. This
channel has power voltage compensation, and is thus suited for slot-in type load control. This channel becomes
active exclusively to other actuator channels. The load driver is shared with the TRK driver.
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PW M output duty
reverse
forw ard
P5V/P12V
100%
deadband
LOAD+
= LOAD-
LOAD+<LOAD-
LOAD+>LOAD-
0%
800h
FE0h 000 01Fh
VLOAD[11:0]
7FFh
Figure 55. Load Output Duty
9.1.10 End Detect Function
This device has end position detection for the sled and collimator lens. This function eliminates the position
switch at the PUH inner and collimator lens end positions. This function is enabled by ENDDET_ENA = 1, setting
the object actuator (ENDDET_SEL = 00: for sled / ENDDET_SEL = 01: for step). When this function is enabled,
internal logic detects the sled out zero-cross point, then the internal BEMF detect circuit measures the BEMF
level of the stepping motor. There are four threshold levels. If the BEMF is lower than the selected threshold, the
device recognizes the motor at stop and sets the ENDDET bit to 1. The ENDDET bit is then cleared at the BEMF
voltage exceed threshold.
ENDDET_ ENA= 1,ENDDET_ SEL= 00
1
ENDDET
I SLEDx
Sled m otor
BEMF
deadend
Figure 56. Timing of Sled End Detection
For the purpose of getting the correct stepping motor BEMF, choose a control frequency higher than 110 Hz (440
pps). This control frequency depends on the stepping motor characteristics.
52
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ENDDET_ ENA= 1,ENDDET_ SEL= 01
1
ENDDET
STP1
STP2
Step m otor
BEMF
deadend
Figure 57. Timing of Step End Detection
The recommended control speed is around 1200 pps for getting the correct BEMF level. This depends on the
stepping motor characteristic. Evaluate your condition appropriately.
9.1.11 Load Tray Lock Detect Function
The tray lock detect function detects an inserted obstacle when the tray opens and closes, using the load motor
BEMF. Adjusting TRAY_LOCKDET [2:0] (REG75) by the characteristic of a motor is required for an optimal
threshold level. The designer can set a threshold level from 100 to 400 mA, with a 50-mA step, using
TRAY_LOCKDET.
Observe the lock detection by reading the ENDDET (REG7F) flag where ENDDET_SEL = 2 or 3 is set.
ENDDET_ ENA= 1,ENDDET_ SEL= 10
1
ENDDET
threshold
(TRAY_ LOCKDET)
(forward)
Load m otor
current (filtered)
stop
(reverse)
Figure 58. Load Tray Lock Detect
9.1.12 Three-Beam Laser Diode Driver
The device has a circuit for the three-beam laser diode drivers containing Blu-ray™. The output is chosen with
LDD_MSEL (REG71), and the LD drive current is outputted by input 11-bit DAC code to VLDD[10:0] and
VLDDIN with analog input. The change in analog mode and digital mode is set up by LDD_AMODE (REG74).
The MSB of VLDD is the sign bit and is ignored if it set to 1. All output, including BD, DVD, and CD, has an
internal pulldown 3 kΩ.
The mode change delay circuit and LVP are integrated to prevent a rush of current when the mode changes.
When the LDD mode is changed, VLDD<10:0> is cleared to 0 to prevent the selected laser diode from breaking,
as LDD sets the current value according to each kind.
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Table 41. LDD Mode
LDD_MSEL[1:0]
ENABLE
BD
CURRENT OUTPUT
11
10
01
ILDD_BD
ILDD_DVD
ILDD_CD
DVD
CD
ILDD_ xxx
sourcecurrent
120m A
slope: 120mA / 0x7FF
120mA/3.0V
50m A
0m A
1.0 /0x2AA
2.0 /0x554
3.0 /0x7FF
200mV / 0x3F
VLDDIN [V] / VLDD[11:0]
Figure 59. VLDD vs Output Average Current
9.1.13 Monitor Signal on GPOUT
The device can output a specific signal to the GPOUT pin. To output a signal, choose a signal from REG6F by
enabling it first, then enabling GPOUT_ENA. When two or more signals are set for GPOUT, the output is a
logical sum.
9.1.14 Example Timing of Target Control System
The TPIC2050 is designed to meet the requirements for updating control data in 400 kHz. Table 42 lists
examples of the control system parameters. It takes 0.51 µs to transmit a 16-bit data packet to the TPIC2050
with a 35-MHz SCLK. Therefore, DSP can be sent in four packets at a 400-kHz interval. If the SCLK is lower
than 28.8 MHz, the user must reduce the packet quantity to less than three. For example, the Focus/Truck
command updates every 2.5 µs (400 kHz), and is able to send another two kinds of packets in this same slot.
Figure 60 shows an example of the control timing when using the TPIC2050.
Table 42. Example Timing of Target Control System
SIGNAL
Focus
Track
Tilt
BIT
12
12
12
10
10
12
12
8
UPDATE CYCLE (kHz)
400
400
100
100
100
100
—
Sled1
Sled2
Spindle
Load
Step1
Step2
40
8
40
54
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312KHz /3.2us(PW M 1cycle)
Track
Focus
Tilt
R
R
R
R
R
Sled1
Sled2
SPM
Load
Step1
Step2
400KHz / 2.5us
Control
register
100KHz /10us (1control cycle)
PWM cycle
DACcommand
RDACcommand w/statusread
Control register command
0.51us(SCLK:35MHz) for data transmit
Figure 60. Example DAC Control
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9.2 Typical Application
P12V
P5V
10uF
0.1uF
1
2
3
4
5
6
7
8
9
SLED1_ P
SLED1_ N
P12V_ 3
SLED2_ P
SLED2_ N
PGND_ 2
C10V
P5V_ 2 56
STP2_ N 55
STP2_ P 54
10uF
0.1uF
SLED COIL1
Step COIL2
Step COIL1
STP1_ N
53
STP1_ P
52
SLED COIL2
0.1uF
AGND
51
ISENSE 50
MCOM 49
RCS 0.1
CP1
0.1uF
0.1uF
ICOM2
CP2
48
47
46
45
44
43
Rdump 1K
W
P12V_ 2
V
10 CP3
GPOUT
XFG
11 GPOUT
12 XFG
Rdump 1K
Rdump 1K
READY
SSZ
ICOM1
U
13 RDY
14 SSZ
SCLK
SIMO
SOMI
15 SCLK
P12V_ 1 42
PGND_ 1 41
FCS_ N 40
FCS_ P 39
TRK_ N 38
TRK_ P 37
TLT_ P 36
TLT_ N 35
P5V_ 1 34
TEST3 33
16 SIMO
17 SOMI
FOCUS COIL
3.3V
18 SIOV
RESETIN
19 XRSTIN
20 TEST1
21 VLDDIN
22 CV3P3
23 AGND/DGND
24 A9P5V
25 ILDD_ BD
26 ILDD_ DVD
27 ILDD_ CD
28 CA5V
TRACKING COIL
TILT COIL
(open)
VLDDIN
0.1uF
High Frequency Current
Superimposition Modules
9.5V
10uF
32
(open)
TEST2
ILDD_ BD
ILDD_ DVD
P5V12L 31
LOAD_ N 30
LOAD_ P 29
ILDD_ CD
0.1uF
CLOAD_ N
CLOAD_ P
0.1uF
Figure 61. Example Application Circuit
9.2.1 Design Requirements
To begin the design process, determine the following:
1. Motor configuration: The user can use all motor channels or part of them.
2. Usage for ILDD: BD, DVD, or CD
3. RDY pin can be connected to Host CPU, then Host CPU can know the power supply status of TPIC2050.
9.2.2 Detailed Design Procedure
After power up on 5-V and 12-V supply, register can be changed following way and enabling motors.
1. Set WRITE_ENABLE = 1 on REG76 via SPI.
2. Set XSLEEP = 1 at REG70
3. Enable motor channel by ENA_XXX bits on REG70
4. Change the DAC settings for the motor on REG01-0B. Then, output channels start driving load.
56
Copyright © 2015, Texas Instruments Incorporated
TPIC2050
www.ti.com.cn
ZHCSEQ5 –AUGUST 2015
Typical Application (continued)
9.2.3 Application Curves
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
TRK+
TRKœ
Load+
Loadœ
-2047 -1535 -1023 -511
1
513 1025 1537 2049
-2047 -1535 -1023 -511
1
513 1025 1537 2049
DAC Code
DAC Code
D003
D004
Figure 62. TRK Driver: DAC Code vs Output On Duty
Figure 63. Load Driver: DAC Code vs Output On Duty
Copyright © 2015, Texas Instruments Incorporated
57
TPIC2050
ZHCSEQ5 –AUGUST 2015
www.ti.com.cn
10 Power Supply Recommendations
All driver channels should only be operated after the required power is supplied and stable.
To calculate the spindle motor driver overcurrent limit (ILimit), use Equation 4.
ILimit = Internal REF voltage / RCS = 194 mV / 0.1 Ω ≈ 1940 mA
(4)
The capacity of the decoupling capacitor requires a value over 10 μF to reduce the influence of the PWM
switching noise. The P5V pin must connect to a filter of 1 μF. Place a bypass capacitor (about 0.1 µF) near the
power pin P5V, P5V12L, or P12V) for PWM switching noise reduction on the power and GND lines.
The current flow to the driver circuits depends on the pattern layout, line impedance, and noise influence from
the supply line.
58
Copyright © 2015, Texas Instruments Incorporated
TPIC2050
www.ti.com.cn
ZHCSEQ5 –AUGUST 2015
11 Layout
11.1 Layout Guidelines
1. CV3P3V, CA5V, and C10V requires external capacitor. Because these are reference voltage for device,
locate the capacitor as close to device as possible. Keep away from noise source.
2. SCLK ground shielding is recommended.
11.2 Layout Example
Ço atÜ
Ço 3.3-ë supply
Ço atÜ
GPOUT
Ço atÜ
XFG
RDY
SSZ
Db5 {hield
SCLK
Ço atÜ
Db5 {hield
SIMO
SOMI
Ço atÜ
SIOV
XRTIN
Ço atÜ
Ço 3.3-ë supply
Ço atÜ
Db5
A. GND shield is recommended for SCLK.
Figure 64. Layout Example Between TPIC2050 and MPU
版权 © 2015, Texas Instruments Incorporated
59
TPIC2050
ZHCSEQ5 –AUGUST 2015
www.ti.com.cn
12 器件和文档支持
12.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 商标
E2E is a trademark of Texas Instruments.
Blu-ray is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPIC2050RDFDRG4
ACTIVE
HTSSOP
DFD
56
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-20 to 75
2050
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
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(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
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Addendum-Page 1
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