TPIC6A259DWRG4 [TI]
350mA/通道 8 位可寻址锁存器 | DW | 24 | -40 to 125;
| 型号： | TPIC6A259DWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 350mA/通道 8 位可寻址锁存器 | DW | 24 | -40 to 125 光电二极管 逻辑集成电路 锁存器 |
| 文件： | 总11页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
• Low r
. . . 1 Ω Typ
NE PACKAGE
(TOP VIEW)
DS(on)
• Output Short-Circuit Protection
• Avalanche Energy . . . 75 mJ
• Eight 350-mA DMOS Outputs
• 50-V Switching Capability
• Four Distinct Function Modes
• Low Power Consumption
DRAIN2
DRAIN3
S1
DRAIN1
DRAIN0
S0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
LGND
PGND
PGND
S2
V
CC
PGND
15 PGND
14
13
12
11
CLR
description
G
D
This power logic 8-bit addressable latch controls
open-drain DMOS-transistor outputs and is
designed for general-purpose storage appli-
cations in digital systems. Specific uses include
working registers, serial-holding registers, and
decoders or demultiplexers. This is a multi-
functional device capable of operating as eight
addressable latches or an 8-line demultiplexer
with active-low DMOS outputs. Each open-drain
DMOS transistor features an independent
chopping current-limiting circuit to prevent
damage in the case of a short circuit.
DRAIN4
DRAIN5
DRAIN7
DRAIN6
DW PACKAGE
(TOP VIEW)
DRAIN2
DRAIN3
S1
DRAIN1
DRAIN0
S0
1
24
23
22
21
20
19
18
17
16
15
14
2
3
LGND
PGND
PGND
PGND
PGND
S2
V
4
CC
PGND
PGND
PGND
PGND
CLR
5
6
7
Four distinct modes of operation are selectable by
controlling the clear (CLR) and enable (G) inputs
as enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
terminal is written into the addressed latch. The
addressed DMOS-transistor output inverts the
data input with all unaddressed DMOS-transistor
outputs remaining in their previous states. In the
memory mode, all DMOS-transistor outputs
remain in their previous states and are unaffected
by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latch,
enable G should be held high (inactive) while the
address lines are changing. In the 8-line
demultiplexing mode, the addressed output is
inverted with respect to the D input and all other
outputs are high. In the clear mode, all outputs are
high and unaffected by the address and data
inputs.
8
9
G
D
10
11
DRAIN4
DRAIN7
13 DRAIN6
DRAIN5 12
FUNCTION TABLE
EACH
OTHER
DRAIN
OUTPUT OF
ADDRESSED
DRAIN
INPUTS
CLR G
FUNCTION
D
H
H
L
L
H
L
X
L
H
Q
Q
Addressable
Latch
Memory
io
io
H
H
Q
Q
io
io
L
L
L
L
H
L
X
L
H
H
H
H
H
8-Line
Demultiplexer
L
H
Clear
LATCH SELECTION TABLE
SELECT INPUTS
DRAIN
ADDRESSED
S2 S1
S0
Separate power ground (PGND) and logic ground
(LGND) terminals are provided to facilitate
maximum system flexibility. All PGND terminals
are internally connected, and each PGND
terminal must be externally connected to the
power system ground in order to minimize
parasitic impedance. A single-point connection
between LGND and PGND must be made
externally in a manner that reduces crosstalk
between the logic and load circuits.
L
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
L
H
H
H
H
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
description (continued)
The TPIC6A259 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body, surface-mount
(DW) package. The TPIC6A259 is characterized for operation over the operating case temperature range of
–40°C to 125°C.
†
logic symbol
S0
S1
S2
G
0
0
7
8M
2
G8
Z9
D
CLR
Z10
9,0D
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
10,0R
9,1D
10,1R
9,2D
10,2R
9,3D
10,3R
9,4D
10,4R
9,5D
10,5R
9,6D
10,6R
9,7D
10,7R
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
logic diagram (positive logic)
D
CLR
G
DRAIN0
D
C1
S0
CLR
DRAIN1
D
C1
CLR
DRAIN2
S1
D
C1
CLR
DRAIN3
D
C1
CLR
DRAIN4
S2
D
C1
CLR
DRAIN5
D
C1
CLR
DRAIN6
D
C1
CLR
DRAIN7
D
C1
CLR
PGND
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL DRAIN OUTPUTS
V
CC
DRAIN
Input
25 V
12 V
R
SENSE
LGND
LGND
PGND
absolute maximum ratings over the recommended operating case temperature range (unless
†
otherwise noted)
Logic supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Logic input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Power DMOS drain-to-source voltage, V
I
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V
DS
Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
Pulsed drain current, each output, all outputs on, I , T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . 1.1 A
D
C
Continuous drain current, each output, all outputs on, I T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mA
D,
C
Peak drain current single output, T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 A
C
Single-pulse avalanche energy, E (see Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mJ
AS
Avalanche current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mA
AS
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
J
Operating case temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to LGND and PGND.
2. Each power DMOS source is internally connected to PGND.
3. Pulse duration ≤ 100 µs, and duty cycle ≤ 2%.
4. DRAIN supply voltage = 15 V, starting junction temperature (T ) = 25°C, L = 210 mH, and I
= 600 mA (see Figure 6).
AS
JS
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T = 125°C
C
POWER RATING
C
PACKAGE
POWER RATING
ABOVE T = 25°C
C
DW
NE
1750 mW
14 mW/°C
20 mW/°C
350 mW
2500 mW
500 mW
4
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TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
recommended operating conditions
MIN
MAX
UNIT
V
Logic supply voltage, V
4.5
5.5
CC
High-level input voltage, V
0.85 V
V
V
IH
CC
CC
0.15 V
Low-level input voltage, V
IL
Pulsed drain output current, T = 25°C, V
0
–1.8
10
V
CC
0.6
= 5 V (see Notes 3 and 5)
CC
A
C
Setup time, D high before G↑,t (see Figure 2)
su
Hold time, D high before G↑, t (see Figure 2)
ns
ns
ns
°C
5
h
Pulse duration, t (see Figure 2)
15
w
Operating case temperature, T
–40
125
C
electrical characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
CC
C
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
V
V
Drain-to-source breakdown voltage
I
I
= 1 mA
50
V
(BR)DSX
D
Source-to-drain diode forward
voltage
= 350 mA,
See Note 3
0.8
1.1
V
SD
F
I
I
I
High-level input current
Low-level input current
Logic supply current
V = V
CC
1
–1
5
µA
µA
IH
I
V = 0
I
IL
I
O
= 0,
V = V
or 0
0.5
0.8
mA
CC
I
CC
Output current at which chopping
starts
I
T
C
= 25°C,
See Note 5 and Figures 3 and 4
0.6
1.1
A
OK
V
V
= 0.5 V, I
= I ,
T = 85°C,
C
DS(on)
(nom)
D
I
Nominal current
350
mA
(nom)
= 5 V,
See Notes 5, 6, and 7
CC
DS
DS
V
V
I
= 40 V,
= 40 V,
T
T
T
T
= 25°C
= 125°C
= 25°C
= 125°C
0.1
0.2
1
1
5
C
C
C
C
I
D
Off-state drain current
µA
= 350 mA,
= 350 mA,
1.5
2.5
Static drain-to-source on-state
resistance
See Notes 5 and 6
and Figures 9 and 10
D
r
Ω
DS(on)
I
D
1.7
switching characteristics, V
= 5 V, T = 25°C
C
CC
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ns
t
t
t
t
t
t
Propagation delay time, high- to low-level output from D
30
125
60
PHL
Propagation delay time, low- to high-level output from D
Rise time, drain output
ns
PLH
C
= 30 pF,
I = 350 mA,
D
L
See Figures 1, 2, and 11
ns
r
Fall time, drain output
30
ns
f
Reverse-recovery-current rise time
Reverse-recovery time
100
300
ns
I
= 350 mA,
di/dt = 20 A/µs,
a
rr
F
See Notes 5 and 6 and Figure 5
ns
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit T – T to 10°C maximum.
J
C
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at T = 85°C.
C
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
MAX
10
UNIT
DW
NE
DW
NE
R
R
Thermal resistance, junction-to-case
All eight outputs with equal power
°C/W
θJC
θJA
10
50
Thermal resistance, junction-to-ambient
All eight outputs with equal power
°C/W
50
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
5 V
CLR
S0
5 V
24 V
0 V
5 V
I
D
V
CC
S0
S1
0 V
5 V
R
= 68 Ω
L
S1
S2
Word
0 V
5 V
S2
DUT
Output
Generator
(see Note A)
G
DRAIN
0 V
5 V
CLR
C
= 30 pF
L
D
LGND PGND
G
D
(see Note B)
0 V
5 V
0 V
24 V
TEST CIRCUIT
DRAIN5
DRAIN3
0.5 V
24 V
0.5 V
VOLTAGE WAVEFORMS
Figure 1. Typical Operation Mode
5 V
G
5 V
0 V
5 V
24 V
D
50%
50%
0 V
V
CLR
CC
t
t
PHL
PLH
Word
I
D
Generator
(see Note A)
24 V
D
G
90%
90%
Output
68 Ω
10%
10%
DUT
0.5 V
t
t
f
Word
Generator
(see Note A)
r
Output
= 30 pF
SWITCHING TIMES
DRAIN
LGND PGND
5 V
0 V
G
D
C
L
50%
(see Note B)
t
su
t
h
TEST CIRCUIT
5 V
0 V
50%
50%
t
w
INPUT SETUP AND HOLD WAVEFORMS
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
NOTES: A. The word generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, t = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
r
f
w
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
OUTPUT CURRENT
vs
REGION 1 CURRENT WAVEFORM
TIME FOR INCREASING LOAD RESISTANCE
1.5
1.25
1
I
OK
I
OK
(see Notes A
and B)
0.75
0.5
0
t
t
t
t
t
1
1
2
1
2
0.25
0
t
≈ 40 µs
1
t
≈ 2.5 ms
2
Region 2
Region 1
Time
Time
First output current pulses after turn-on in chopping mode
with resistive load.
NOTES: A. Figure 3 illustrates the output current characteristics of the device energizing a load having initially low, increasing resistance, e.g.,
an incandescent lamp. In region 1, chopping occurs and the peak current is limited to I . In region 2, output current is continuous.
OK
The same characteristics occur in reverse order when the device energizes a load having an initially high, decreasing resistance.
B. Region 1 duty cycle is approximately 2%.
Figure 3. Chopping-Mode Characteristics
OUTPUT CURRENT LIMIT
vs
CASE TEMPERATURE
1.5
V
CC
= 5.5 V
1.2
0.9
V
CC
= 4.5 V
0.6
0.3
0
– 50 – 25
0
25
50
75 100 125 150
T
C
– Case Temperature – °C
Figure 4
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
TP K
DRAIN
0.35 A
Circuit
Under
Test
2500 µF
250 V
di/dt = 20 A/µs
+
–
I
F
24 V
L = 1 mH
TP A
I
F
(see Note B)
0
25% of I
RM
t
2
t
1
t
3
Driver
I
RM
(see Note C)
R
G
t
V
a
GG
(see Note A)
50 Ω
t
rr
CURRENT WAVEFORM
TEST CIRCUIT
NOTES: A. The V
GG
amplitude and R are adjusted for di/dt = 20 A/µs. A V double-pulse train is used to set I = 0.35 A, where t = 10 µs,
GG F 1
G
t
= 7 µs, and t = 3 µs.
2
3
B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
C.
I
= maximum recovery current
RM
Figure 5. Reverse-Recovery-Current Test Circuit and Waveforms of Source-Drain Diode
5 V
15 V
t
w
t
I
†
av
5 V
0 V
V
CC
S2
S1
Input
1 Ω
See Note B
I
D
Word
Generator
(see Note A)
S0
= 600 mA
DUT
AS
L = 210 mH
G
D
I
D
V
DS
DRAIN
CLR
V
= 50 V
(BR)DSX
MIN
V
DS
LGND PGND
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
†
Non-JEDEC symbol for avalanche time.
NOTES: A. The word generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, Z = 50 Ω.
r
f
O
B. Input pulse duration, t , is increased until peak current I
= 600 mA.
w
AS
Energy test level is defined as E
= (I
× V
× t )/2 = 75 mJ.
AS
AS
(BR)DSX av
Figure 6. Single-Pulse Avalanche Energy Test Circuit and Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
0.7
0.6
0.5
0.9
0.8
0.7
0.6
V
CC
= 5 V
d = 50%
d = 20%
T
A
= 25°C
0.4
0.3
0.5
0.4
0.3
0.2
0.1
d = 80%
T
= 100°C
= 125°C
A
0.2
0.1
V
T
A
= 5 V
CC
= 25°C
T
A
d = t /t
w period
d = 1 ms/t
period
0
0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
N – Number of Outputs Conducting Simultaneously
N – Number of Outputs Conducting Simultaneously
Figure 7
Figure 8
STATIC DRAIN-SOURCE
ON-STATE RESISTANCE
vs
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
2
LOGIC SUPPLY VOLTAGE
2
V
= 5 V
CC
See Note A
1.75
1.5
1.25
1
1.75
T
= 125°C
= 25°C
C
T
T
= 125°C
= 25°C
C
1.5
Current Limit
1.25
1
T
C
C
0.75
0.5
0.75
0.5
0.25
0
T
= –40°C
C
T
C
= – 40°C
0.25
0
I
D
= 350 mA
See Note A
0
0.2
0.4
0.6
0.8
1
1.2
4
5
6
7
V
CC
– Logic Supply Voltage – V
I
D
– Drain Current – A
Figure 9
Figure 10
NOTE A: Technique should limit T – T to 10°C maximum.
J
C
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
SWITCHING TIME
vs
CASE TEMPERATURE
140
120
100
80
I
= 350 mA
D
See Note A
t
PLH
t
r
60
t
PHL
40
20
t
f
– 50
0
50
100
150
T
C
– Case Temperature – °C
NOTE A: Technique should limit T – T to 10°C maximum.
J
C
Figure 11
THERMAL INFORMATION
NE PACKAGE
TRANSIENT THERMAL IMPEDANCE
The single-pulse curve represents measured data. The curves
for various pulse durations are based on the following equation:
vs
ON TIME
100
10
1
t
t
t
w
w
Z
R
1 –
Z
t
t
c
w
JA
JA
t
c
c
d = 50%
Z
t
–Z
t
w
c
Where:
d = 20%
d = 10%
d = 5%
= the single-pulse thermal impedance
for t = t seconds
Z
t
w
w
Z
t
= the single-pulse thermal impedance
for t = t seconds
c
c
d = 2%
Z
t
t
c
= the single-pulse thermal impedance
for t = t + t seconds
w
w
c
d = t /t
w c
t
c
Single Pulse
t
w
I
D
0.1
0.001 0.01
0.1
1
10
100
1000
0
t – On Time – s
Figure 12
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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