TPIC6A596DWRG4 [TI]
用于增强级联、具有使能/关断功能的 8 位移位寄存器 | DW | 24 | -40 to 125;
| 型号： | TPIC6A596DWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于增强级联、具有使能/关断功能的 8 位移位寄存器 | DW | 24 | -40 to 125 移位寄存器 |
| 文件： | 总13页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPIC6A596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS094 – MARCH 2000
NE PACKAGE
(TOP VIEW)
Low r
. . . 1 Ω Typ
DS(on)
Output Short-Circuit Protection
Avalanche Energy . . . 75 mJ
DRAIN2
DRAIN3
SRCLR
G
DRAIN1
DRAN0
SER IN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
Eight 350-mA DMOS Outputs
50-V Switching Capability
V
CC
Enhanced Cascading for Multiple Stages
All Registers Cleared With Single Input
Low Power Consumption
PGND
PGND
RCK
PGND
15 PGND
14
13
12
11
LGND
SRCK
DRAIN4
DRAIN5
SER OUT
DRAIN7
DRAIN6
description
The TPIC6A596 is a monolithic, high-voltage,
high-current power logic 8-bit shift register
designed for use in systems that require relatively
high load power. The device contains a built-in
voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other medium-
current or high-voltage loads. Each open-drain
DMOS transistor features an independent
chopping current-limiting circuit to prevent
damage in the case of a short circuit.
DW PACKAGE
(TOP VIEW)
DRAIN2
DRAIN3
SRCLR
G
DRAIN1
DRAIN0
SER IN
1
24
23
22
21
20
19
18
17
16
15
14
2
3
V
4
CC
PGND
PGND
PGND
PGND
RCK
PGND
5
PGND
6
PGND
7
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit, D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shift-
register clock (SRCK) and the register clock
(RCK), respectively. The storage register
transfers data to the output buffer when shift-
PGND
8
LGND
9
SRCK
DRAIN4
SER OUT
DRAIN7
10
11
DRAIN5 12
13 DRAIN6
register clear (SRCLR) is high. When SRCLR is low, all registers in the device are cleared. When output enable
G is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data
from the storage register is transparent to the output buffers. The serial output (SER OUT) is clocked out of the
device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide
improved performance for applications where clock signals may be skewed, devices are not located near one
another, or the system must tolerate electromagnetic interference.
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and a 350-mA continuous sink
currentcapability. Whendataintheoutputbuffersislow, theDMOS-transistoroutputsareoff. Whendataishigh,
the DMOS-transistor outputs have sink current capability.
Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system
flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected
to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND
and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits.
The TPIC6A596 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount
(DW) package. The TPIC6A596 is characterized for operation over the operating case temperature range of
–40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS094 – MARCH 2000
†
logic symbol
EN3
C2
G
RCK
SRG8
R
SRCLR
SRCK
C1
1D
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
2
3
SER IN
2
3
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS094 – MARCH 2000
logic diagram (positive logic)
G
DRAIN0
RCK
D
SER IN
SRCK
D
C2
C1
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
CLR
CLR
SRCLR
D
D
C1
CLR
C2
CLR
D
D
C1
CLR
C2
CLR
D
D
C1
CLR
C2
CLR
D
D
C2
C1
CLR
CLR
D
D
C2
C1
CLR
CLR
D
D
C2
C1
CLR
CLR
D
D
DRAIN7
PGND
C1
CLR
C2
CLR
D
C1
CLR
SER OUT
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS094 – MARCH 2000
schematic of inputs and outputs
TYPICAL OF SERIAL OUT
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL DRAIN OUTPUTS
DRAIN
V
CC
V
CC
Input
25 V
SER OUT
12 V
R
SENSE
LGND
LGND
PGND
LGND
absolute maximum ratings over recommended operating case temperature range (unless
†
otherwise noted)
Logic supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Logic input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Power DMOS drain-to-source voltage, V
I
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V
DS
Continuous source-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Pulsed source-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
Pulsed drain current, each output, all outputs on, I
Continuous drain current, each output, all outputs on, I
T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . 1.1 A
Dn,
A
T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mA
A
Dn,
Peak drain current, single output, T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 A
A
Single-pulse avalanche energy, E (see Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mJ
AS
Avalanche current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mA
AS
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating case temperature range, T
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
C
J
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to LGND and PGND.
2. Each power DMOS source is internally connected to PGND.
3. Pulse duration ≤ 100 µs and duty cycle ≤ 2 %.
4. DRAIN supply voltage = 15 V, starting junction temperature (T ) = 25°C, L = 210 mH, I
= 600 mA (see Figure 6).
AS
JS
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T = 125°C
C
POWER RATING
C
PACKAGE
POWER RATING
ABOVE T = 25°C
C
DW
NE
1750 mW
14 mW/°C
20 mW/°C
350 mW
2500 mW
500 mW
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS094 – MARCH 2000
recommended operating conditions
MIN
MAX
UNIT
V
Logic supply voltage, V
CC
4.5
5.5
High-level input voltage, V
IH
0.85 V
V
V
CC
CC
0.15 V
Low-level input voltage, V
IL
Pulsed drain output current, T = 25°C, V
0
–1.8
10
V
CC
= 5 V (see Notes 3 and 5)
CC
0.6
A
C
Setup time, SER IN high before SRCK↑, t (see Figure 2)
su
Hold time, SER IN high after SRCK↑, t (see Figure 2)
ns
ns
ns
°C
10
h
Pulse duration, t (see Figure 2)
20
w
Operating case temperature, T
–40
125
C
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit T – T to 10°C maximum.
J
C
electrical characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
C
CC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Drain-to-source
breakdown voltage
V
V
I
I
= 1 mA
50
V
(BR)DSX
D
Source-to-drain diode
forward voltage
= 350 mA,
See Note 3
0.8
CC
1.1
V
V
SD
F
I
I
I
I
= –20 µA
= –4 mA
= 20 µA
= 4 mA
V
V
–0.1
–0.5
V
High-level output voltage,
SER OUT
OH
OH
OL
OL
CC
V
OH
OL
V
–0.2
0
CC
CC
0.1
0.5
1
Low-level output voltage,
SER OUT
V
V
0.2
I
I
High-level input current
Low-level input current
V = V
CC
µA
µA
IH
I
V = 0
–1
IL
I
Output current at which
chopping starts
I
I
I
T
= 25°C,
See Note 5 and Figures 3 and 4
0.6
0.8
0.5
1.3
1.1
5
A
O(chop)
CC
C
Logic supply current
I
f
= 0,
V = V
I
or 0
mA
mA
O
CC
Logic supply current at
frequency
= 5 MHz,
I
V
= 0,
C = 30 pF,
L
SRCK
O
CC(FRQ)
V = V
or 0,
= 5 V, See Figure 7
I
CC
CC
V
V
= 0.5 V,
= 5 V,
I
= I , T = 85°C,
DS(on)
(nom) D C
I
Nominal current
350
mA
(nom)
D
See Notes 5, 6, and 7
CC
DS
DS
V
V
= 40 V,
= 40 V,
T
T
= 25°C
0.1
0.2
1
1
5
C
C
I
Drain current, off-state
µA
= 125°C
I
I
= 350 mA,
= 350 mA,
T
T
= 25°C
1.5
2.5
Static drain-source
on-state resistance
D
C
C
See Notes 5 and 6 and
Figures 10 and 11
r
)
Ω
DS(on
= 125°C
1.7
D
NOTES: 5. Technique should limit T – T to 10°C maximum.
J
C
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at T = 85°C.
C
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS094 – MARCH 2000
switching characteristics, V
= 5 V, T = 25°C
C
CC
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ns
t
t
t
t
Propagation delay time, high-to-low-level output from G
Propagation delay time, low-to-high-level output from G
Rise time, drain output
30
125
60
PHL
ns
PLH
C
= 30 pF,
I = 350 mA,
D
L
See Figures 1, 2, and 12
ns
r
f
Fall time, drain output
30
ns
C
= 30 pF,
I
I
= 350 mA,
= 350 mA,
L
D
t
f
Propagation delay time, SRCK↓ to SEROUT
20
ns
pd
See Figure 2
C
= 30 pF,
L
D
Serial clock frequency
10
MHz
(SRCK)
See Note 8
t
t
Reverse-recovery-current rise time
Reverse-recovery time
100
300
ns
ns
I
= 350 mA,
di/dt = 20 A/µs,
a
F
See Notes 5 and 6 and Figure 5
rr
NOTES: 5. Technique should limit T – T to 10°C maximum.
J
C
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
8. This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second
stage. The clock period allows for SRCK → SEROUT propagation delay and setup time plus some timing margin.
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
MAX
10
UNIT
DW
NE
DW
NE
R
R
Thermal resistance, junction-to-case
Thermal resistance, junction-to-ambient
All eight outputs with equal power
°C/W
θJC
θJA
10
50
All eight outputs with equal power
°C/W
50
PARAMETER MEASUREMENT INFORMATION
5 V
24 V
7
6
5
4
3
2
1
0
5 V
SRCK
0 V
5 V
I
D
V
CC
SRCLR
SRCK
G
R
= 68 Ω
L
0 V
5 V
DUT
Output
SER IN
Word
Generator
(see Note A)
0 V
5 V
DRAIN
SER IN
RCK
G
RCK
C
= 30 pF
L
0 V
5 V
(see Note B)
SRCLR
0 V
LGND PGND
24 V
DRAIN 0, 1, 4, 5
DRAIN 2, 3, 6, 7
0.5 V
24 V
TEST CIRCUIT
0.5 V
VOLTAGE WAVEFORMS
NOTES: A. The word generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, t = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
r
f
w
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 1. Resistive Load Operation
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS094 – MARCH 2000
PARAMETER MEASUREMENT INFORMATION
5 V
0 V
G
50%
50%
t
PLH
t
PHL
24 V
90%
90%
Output
10%
10%
0.5 V
t
t
f
r
5 V
CC
24 V
SWITCHING TIMES
5 V
0 V
I
D
V
50%
SRCK
SRCLR
SRCK
R
= 68 Ω
L
t
su
DUT
Output
Word
t
h
Generator
(see Note A)
SER IN
RCK
DRAIN
5 V
0 V
SER IN
50%
50%
C
= 30 pF
L
(see Note B)
G
t
w
LGND PGND
INPUT SETUP AND HOLD WAVEFORMS
TEST CIRCUIT
50%
50%
SRCK
t
t
pd
pd
SER OUT
50%
50%
SER OUT PROPAGATION DELAY WAVEFORM
NOTES: A. The word generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, t = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
r
f
w
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS094 – MARCH 2000
PARAMETER MEASUREMENT INFORMATION
OUTPUT CURRENT
vs
REGION 1 CURRENT WAVEFORM
TIME FOR INCREASING LOAD RESISTANCE
1.5
I
OK
1.25
I
OK
(see Notes A and B)
1
0.75
0.5
0
t
t
t
t
t
1
1
2
1
2
0.25
t
≈ 40 µs
1
t
≈ 2.5 ms
2
0
Region 2
Region 1
Time
Time
First output current pulses after turn-on in chopping mode with
resistive load.
NOTES: A. Figure 3 illustrates the output current characteristics of the device energizing a load having initially low, increasing resistance, e.g.,
an incandescent lamp. In region 1, chopping occurs and the peak current is limited to I . In region 2, output current is continuous.
OK
The same characteristics occur in reverse order when the device energizes a load having an initially high, decreasing resistance.
B. Region 1 duty cycle is approximately 2%.
Figure 3. Chopping-Mode Characteristics
OUTPUT CURRENT LIMIT
vs
CASE TEMPERATURE
1.5
V
CC
= 5.5 V
1.2
0.9
V
CC
= 4.5 V
0.6
0.3
0
– 50 – 25
0
25
50
75 100 125 150
T
C
– Case Temperature – °C
Figure 4
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS094 – MARCH 2000
PARAMETER MEASUREMENT INFORMATION
TP K
DRAIN
0.35 A
Circuit
Under
Test
2500 µF
250 V
di/dt = 20 A/µs
+
–
I
F
24 V
L = 1 mH
I
F
(see Note B)
0
TP A
25% of I
RM
t
2
t
1
t
3
Driver
I
RM
(see Note C)
R
G
t
V
a
GG
(see Note A)
50 Ω
t
rr
CURRENT WAVEFORM
double-pulse train is used to set I = 0.35 A, where t = 10 µs,
TEST CIRCUIT
NOTES: A. The V
amplitude and R are adjusted for di/dt = 20 A/µs. A V
GG
GG
= 7 µs, and t = 3 µs.
G
F
1
t
2
3
B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
C.
I
= maximum recovery current
RM
Figure 5. Reverse-Recovery-Current Test Circuit and Waveforms of Source-Drain Diode
5 V
V
15 V
t
w
†
t
I
av
5 V
0 V
CC
1 Ω
SRCLR
SRCK
Input
I
D
See Note B
DUT
= 600 mA
210 mH
AS
SER IN
RCK
Word
Generator
(see Note A)
I
D
V
DRAIN
DS
V
= 50 V MIN
(BR)DSX
G
LGND PGND
V
DS
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT
VOLTAGE AND CURRENT WAVEFORMS
†
Non JEDEC symbol for avalanche time.
NOTES: A. The word generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, Z = 50 Ω.
r
f
O
B. Input pulse duration, t , is increased until peak current I
= 600 mA.
w
AS
Energy test level is defined as E
AS
= (I
× V
× t )/2 = 75 mJ.
(BR)DSX av
AS
Figure 6. Single-Pulse Avalanche Energy Test Circuit and Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS094 – MARCH 2000
TYPICAL CHARACTERISTICS
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
SUPPLY CURRENT
vs
FREQUENCY
0.7
0.6
0.5
4
V
= 5 V
V
CC
= 5 V
CC
3.5
3
T
JS
= –40°C to 125°C
T
A
= 25°C
2.5
2
0.4
0.3
T
= 100°C
= 125°C
A
1.5
1
0.2
0.1
T
A
0.5
0
0
0.1
1
10
100
1
2
3
4
5
6
7
8
N – Number of Outputs Conducting Simultaneously
f – Frequency – MHz
Figure 7
Figure 8
MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
DRAIN CURRENT
2
0.9
0.8
V
= 5 V
CC
See Note A
1.75
1.5
1.25
1
d = 50%
d = 20%
T
T
= 125°C
= 25°C
C
0.7
0.6
Current Limit
C
0.5
0.4
0.3
0.2
0.1
d = 80%
0.75
0.5
T
C
= – 40°C
V
T
A
= 5 V
CC
= 25°C
0.25
0
d = t /t
w period
d = 1 ms/t
period
3
0
0
0.2
0.4
0.6
0.8
1
1.2
1
2
4
5
6
7
8
I
D
– Drain Current – A
N – Number of Outputs Conducting Simultaneously
NOTE A: Technique should limit T – T to 10°C maximum.
J
C
Figure 9
Figure 10
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS094 – MARCH 2000
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
SWITCHING TIME
vs
CASE TEMPERATURE
vs
LOGIC SUPPLY VOLTAGE
2
140
120
100
80
I
= 350 mA
D
See Note A
1.75
1.5
t
T
= 125°C
= 25°C
PLH
C
1.25
1
T
C
t
0.75
r
60
T
C
= –40°C
0.5
0.25
0
t
PHL
40
20
I
= 350 mA
D
See Note A
t
f
– 50
0
T
50
100
150
4
5
6
7
– Case Temperature – °C
V
CC
– Logic Supply Voltage – V
C
Figure 11
Figure 12
NOTE A: Technique should limit T – T to 10°C maximum.
J
C
TYPICAL R
THERMAL RESISTANCE
vs
θJA
ON BOARD HEATSINK AREA
110
100
90
80
70
DW Package
PC Board
Copper Area
1oz Copper
60
50
NE Package
40
30
0
1
2
3
4
5
6
7
8
9
10
2
Copper Heatsink Area – cm
Figure 13
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A596
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS094 – MARCH 2000
THERMAL INFORMATION
NE PACKAGE
TRANSIENT THERMAL IMPEDANCE
The single-pulse curve represents measured data. The
curves for various pulse durations are based on the
following equation:
vs
ON TIME
100
10
1
t
t
t
w
w
Z
R
1 –
Z
t
t
c
w
JA
JA
t
c
c
d = 50%
Z
t
–Z
t
w
c
Where:
d = 20%
d = 10%
= the single-pulse thermal impedance
for t = t seconds
Z
t
w
w
d = 5%
Z
t
= the single-pulse thermal impedance
for t = t seconds
c
c
Z
t
t
c
= the single-pulse thermal impedance
for t = t + t seconds
w
w
c
d = 2%
d = t /t
w c
t
c
Single Pulse
t
w
I
D
0.1
0.001 0.01
0.1
1
10
100
1000
0
t – On Time – s
Figure 14
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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