TPIC6B259DWRG4 [TI]
150mA/通道 8 位可寻址锁存器 | DW | 20;
| 型号： | TPIC6B259DWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 150mA/通道 8 位可寻址锁存器 | DW | 20 光电二极管 逻辑集成电路 锁存器 |
| 文件： | 总11页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPIC6B259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 – APRIL 1994 – REVISED JULY 1995
Low r
. . . 5 Ω Typical
DS(on)
DW OR N PACKAGE
(TOP VIEW)
Avalanche Energy . . . 30 mJ
Eight Power DMOS-Transistor Outputs of
150-mA Continuous Current
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
V
CLR
CC
S0
500-mA Typical Current-Limiting Capability
Output Clamp Voltage . . . 50 V
Four Distinct Function Modes
Low Power Consumption
D
DRAIN0
DRAIN1
DRAIN2
DRAIN3
S1
DRAIN7
DRAIN6
15 DRAIN5
14
13
12
11
DRAIN4
G
description
GND
S2
GND
GND
This power logic 8-bit addressable latch controls
open-drain DMOS-transistor outputs and is
NC – No internal connection
designed
for
general-purpose
storage
FUNCTION TABLE
applications in digital systems. Specific uses
includeworkingregisters, serial-holdingregisters,
and decoders or demultiplexers. This is a multi-
functional device capable of storing single-line
data in eight addressable latches and 3-to-8
decoder or demultiplexer with active-low DMOS
outputs.
OUTPUT OF
ADDRESSED
DRAIN
EACH
OTHER
DRAIN
INPUTS
CLR G
FUNCTION
D
H
H
L
L
H
L
L
H
Q
Q
Addressable
Latch
io
io
H
H
X
Q
Q
Memory
io
io
L
L
L
L
H
L
L
H
H
H
8-Line
Demultiplexer
Four distinct modes of operation are selectable by
controlling the clear (CLR) and enable (G) inputs
as enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
terminal is written into the addressed latch. The
addressed DMOS-transistor output inverts the
data input with all unaddressed DMOS-transistor
outputs remaining in their previous states. In the
memory mode, all DMOS-transistor outputs
remain in their previous states and are unaffected
by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latch,
enable G should be held high (inactive) while the
addresslinesarechanging. Inthe3-to-8decoding
or demultiplexing mode, the addressed output is
inverted with respect to the D input and all other
L
H
X
H
H
Clear
LATCH SELECTION TABLE
SELECT INPUTS
DRAIN
ADDRESSED
S2 S1
S0
L
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
L
H
H
H
H
H = high level, L = low level
outputs are off. In the clear mode, all outputs are off and unaffected by the address and data inputs. When data
is low for a given output, the DMOS-transistor output is off. When data is high, the DMOS-transistor output has
sink-current capability.
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous
sink-current capability. Each output provides a 500-mA typical current limit at T = 25°C. The current limit
C
decreases as the junction temperature increases for additional device protection.
The TPIC6B259 is characterized for operation over the operating case temperature range of –40°C to 125°C.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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TPIC6B259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 – APRIL 1994 – REVISED JULY 1995
†
logic symbol
3
S0
S1
S2
G
0
8
8M 0/7
12
13
18
2
G8
Z9
D
19
CLR
Z10
9,0D
4
5
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
10,0R
9,1D
10,1R
9,2D
6
10,2R
9,3D
7
10,3R
9,4D
14
15
16
17
10,4R
9,5D
10,5R
9,6D
10,6R
9,7D
10,7R
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6B259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 – APRIL 1994 – REVISED JULY 1995
logic diagram (positive logic)
4
DRAIN0
3
S0
D
C1
CLR
5
DRAIN1
D
C1
CLR
6
DRAIN2
D
C1
8
S1
CLR
7
DRAIN3
D
C1
CLR
14
12
S2
DRAIN4
D
C1
CLR
15
DRAIN5
D
C1
CLR
16
DRAIN6
D
C1
CLR
18
D
17
DRAIN7
D
C1
13
G
CLR
9,10,11
GND
19
CLR
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6B259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 – APRIL 1994 – REVISED JULY 1995
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL DRAIN OUTPUTS
V
CC
DRAIN
50 V
Input
25 V
20 V
12 V
GND
GND
absolute maximum ratings over the recommended operating case temperature range (unless
†
otherwise noted)
Logic supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Logic input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Power DMOS drain-to-source voltage, V
I
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V
DS
Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Pulsed drain current, each output, all outputs on, I , T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 500 mA
D
C
Continuous drain current, each output, all outputs on, I , T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
D
C
Peak drain current single output, I , T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
DM
C
Single-pulse avalanche energy, E (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ
AS
Avalanche current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
AS
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipating Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
J
Operating case temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
4. DRAIN supply voltage = 15 V, starting junction temperature (T ) = 25°C, L = 200 mH, I
= 0.5 A (see Figure 4).
AS
JS
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T = 125°C
C
POWER RATING
C
PACKAGE
POWER RATING
ABOVE T = 25°C
C
DW
N
1389 mW
11.1 mW/°C
10.5 mW/°C
278 mW
1050 mW
263 mW
4
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TPIC6B259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 – APRIL 1994 – REVISED JULY 1995
recommended operating conditions
MIN
MAX
UNIT
V
Logic supply voltage, V
CC
4.5
5.5
High-level input voltage, V
IH
0.85 V
V
CC
Low-level input voltage, V
0.15 V
V
IL
Pulsed drain output current, T = 25°C, V
CC
= 5 V (see Notes 3 and 5)
CC
–500
20
500
mA
ns
ns
ns
°C
C
Setup time, D high before G↑, t (see Figure 2)
su
Hold time, D high after G↑, t (see Figure 2)
20
h
Pulse duration, t (see Figure 2)
40
w
Operating case temperature, T
–40
125
C
electrical characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
CC
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Drain-to-source breakdown
voltage
V
V
I
I
= 1 mA
50
V
(BR)DSX
D
Source-to-drain diode forward
voltage
= 100 mA
0.85
1
V
SD
F
I
I
High-level input current
Low-level input current
V
V
= 5.5 V,
= 5.5 V,
V = V
CC
1
–1
µA
µA
IH
CC
I
V = 0
I
IL
CC
All outputs off
All outputs on
20
100
300
I
I
I
Logic supply current
Nominal current
V
= 5.5 V
µA
mA
µA
CC
CC
150
V
= 0.5 V, I = I ,
T
T
= 85°C,
= 125°C
DS(on)
N
D
C
90
N
See Notes 5, 6, and 7
V
V
= 40 V,
= 40 V,
V
CC
V
CC
V
CC
V
CC
= 5.5 V
= 5.5 V,
= 4.5 V
= 4.5 V,
0.1
0.15
4.2
5
8
DS
Off-state drain current
DSX
DS
C
I
I
= 100 mA,
= 100 mA,
5.7
D
Static drain-to-source on-state
resistance
See Notes 5 and 6
and Figures 6 and 7
D
C
r
Ω
6.8
5.5
9.5
8
DS(on)
T
= 125°C
I
D
= 350 mA,
V
CC
= 4.5 V
switching characteristics, V
= 5 V, T = 25°C
C
CC
PARAMETER
TEST CONDITIONS
MIN
TYP
150
90
MAX
UNIT
ns
t
t
t
t
t
t
Propagation delay time, low-to-high-level output from D
PLH
Propagation delay time, high-to-low-level output from D
Rise time, drain output
ns
PHL
C
= 30 pF,
See Figures 1, 2, and 8
I = 100 mA,
D
L
200
200
100
300
ns
r
Fall time, drain output
ns
f
Reverse-recovery-current rise time
Reverse-recovery time
I
F
= 100 mA,
di/dt = 20 A/µs,
a
rr
ns
See Notes 5 and 6 and Figure 3
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit T – T to 10°C maximum.
J
C
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at T = 85°C.
C
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6B259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 – APRIL 1994 – REVISED JULY 1995
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
MAX
90
UNIT
DW package
R
Thermal resistance junction-to-ambient
All 8 outputs with equal power
°C/W
θJA
N package
95
PARAMETER MEASUREMENT INFORMATION
5 V
CLR
0 V
5 V
5 V
2
24 V
S0
0 V
5 V
3
I
D
V
CC
S0
S1
8
S1
S2
R
= 235 Ω
L
0 V
5 V
12
Word
Generator
(see Note A)
S2
DUT
Output
4–7,
14–17
13
19
18
G
0 V
5 V
DRAIN
CLR
C
= 30 pF
L
D
GND
9, 10, 11
(see Note B)
G
D
0 V
5 V
0 V
TEST CIRCUIT
24 V
DRAIN5
0.5 V
24 V
DRAIN3
0.5 V
VOLTAGE WAVEFORMS
NOTES: A. The word generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, t = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
r
f
w
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 1. Resistive-Load Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6B259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 – APRIL 1994 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
5 V
G
D
5 V
0 V
5 V
24 V
2
19
50%
50%
0 V
V
CLR
CC
t
PLH
t
PHL
Word
Generator
(see Note A)
18
13
I
D
24 V
0.5 V
D
G
90%
90%
Output
235 Ω
Output
10%
10%
DUT
t
Word
Generator
(see Note A)
t
f
r
4–7,
14–17
SWITCHING TIMES
DRAIN
GND
5 V
0 V
G
D
C
= 30 pF
L
50%
9, 10,11
(see Note B)
t
su
t
h
TEST CIRCUIT
5 V
0 V
50%
50%
t
w
INPUT SETUP AND HOLD WAVEFORMS
NOTES: A. The word generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, t = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
r
f
w
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
TP K
DRAIN
0.1 A
Circuit
Under
Test
2500 µF
250 V
di/dt = 20 A/µs
+
I
F
25 V
L = 1 mH
I
F
–
(see Note A)
0
TP A
25% of I
RM
t
2
t
t
1
3
Driver
I
RM
R
G
t
V
a
GG
(see Note B)
50 Ω
t
rr
CURRENT WAVEFORM
TEST CIRCUIT
NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
B. The V
amplitude and R are adjusted for di/dt = 20 A/µs. A V
double-pulse train is used to set I = 0.1 A, where t = 10 µs,
GG F 1
GG
= 7 µs, and t = 3 µs.
G
t
2
3
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6B259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 – APRIL 1994 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
5 V
15 V
t
w
2
t
I
av
12
8
V
5 V
CC
S2
S1
10.5 Ω
Input
See Note B
0 V
I
D
3
13
18
Word
Generator
(see Note A)
S0
= 0.5 A
DUT
AS
200 mH
V
4–7,
14–17
G
D
I
D
DRAIN
DS
19
CLR
V
= 50 V
(BR)DSX
MIN
V
DS
GND
9, 10, 11
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The word generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, Z = 50 Ω.
r
f
O
B. Input pulse duration, t , is increased until peak current I
= 0.5 A.
w
AS
Energy test level is defined as E = I
AS AS
× V
× t /2 = 30 mJ.
(BR)DSX av
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
PEAK AVALANCHE CURRENT
vs
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
TIME DURATION OF AVALANCHE
DRAIN CURRENT
10
4
18
V
= 5 V
CC
See Note A
T
C
= 25°C
16
14
12
10
T
C
= 125°C
2
1
8
6
4
0.4
T
C
= 25°C
0.2
0.1
T
= –40°C
C
2
0
0
100
200
300
400
500
600
700
0.1
0.2
0.4
1
2
4
10
I – Drain Current – mA
D
t
– Time Duration of Avalanche – ms
av
NOTE C: Technique should limit T – T to 10°C maximum.
J
C
Figure 5
Figure 6
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6B259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 – APRIL 1994 – REVISED JULY 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
SWITCHING TIME
vs
vs
LOGIC SUPPLY VOLTAGE
CASE TEMPERATURE
8
300
250
200
I
= 100 mA
I
= 100 mA
D
D
See Note A
See Note A
7
6
t
f
T
= 125°C
C
t
r
5
4
T
= 25°C
C
t
t
PLH
PHL
150
100
50
3
2
T
C
= – 40°C
1
0
–50 –25
0
25
50
75
100
125
4
4.5
5
5.5
6
6.5
7
T
C
– Case Temperature – °C
V
CC
– Logic Supply Voltage – V
Figure 7
Figure 8
NOTE D: Technique should limit T – T to 10°C maximum.
J
C
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6B259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 – APRIL 1994 – REVISED JULY 1995
THERMAL INFORMATION
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
0.5
0.45
0.4
V
CC
= 5 V
d = 10%
d = 20%
0.45
0.4
0.35
0.3
0.35
d = 50%
0.3
0.25
0.2
T
C
= 25°C
0.25
d = 80%
0.2
0.15
0.1
0.15
0.1
T
= 100°C
C
V
T
= 5 V
CC
= 25°C
T
3
= 125°C
C
C
d = t /t
w period
0.05
0.05
0
= 1 ms/t
period
0
1
2
3
4
5
6
7
8
1
2
4
5
6
7
8
N – Number of Outputs Conducting Simultaneously
N – Number of Outputs Conducting Simultaneously
Figure 9
Figure 10
10
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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