TPIC6C596PWG4 [TI]
POWER LOGIC 8-BIT SHIFT REGISTER; 功率逻辑8位移位寄存器
| 型号： | TPIC6C596PWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | POWER LOGIC 8-BIT SHIFT REGISTER |
| 文件： | 总18页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂ ꢃꢄ ꢃꢅ ꢆꢄ
ꢁꢇ ꢈ ꢉꢊ ꢋ ꢇꢌ ꢂ ꢃ ꢍ ꢎꢏꢂ ꢀ ꢐꢑꢂ ꢒ ꢀ ꢊ ꢉꢌ ꢂ ꢐ ꢀꢉ ꢊ
SLIS093C − MARCH 2000 − REVISED APRIL 2005
D, N, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
D
Low r
. . . 7 Ω Typ
DS(on)
Avalanche Energy . . . 30 mJ
Eight Power DMOS Transistor Outputs of
100-mA Continuous Current
V
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
CC
SER IN
SRCK
250-mA Current Limit Capability
ESD Protection . . . 2500 V
DRAIN0
DRAIN1
DRAIN2
DRAIN3
CLR
DRAIN7
DRAIN6
DRAIN5
Output Clamp Voltage . . . 33 V
Enhanced Cascading for Multiple Stages
All Registers Cleared With Single Input
Low Power Consumption
11 DRAIN4
10 RCK
G
9
SER OUT
†
logic symbol
description
8
EN3
C2
The TPIC6C596 is a monolithic, medium-voltage,
G
10
low-current power 8-bit shift register designed for
use in systems that require relatively moderate
load power such as LEDs. The device contains a
built-in voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other low-current or
medium-voltage loads.
RCK
SRG8
7
CLR
R
15
SRCK
C1
3
2
DRAIN0
1D
2
SER IN
4
5
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shift
register clock (SRCK) and the register clock
(RCK), respectively. The storage register trans-
fers data to the output buffer when shift register
clear (CLR) is high. When CLR is low, all registers
in the device are cleared. When output enable (G)
is held high, all data in the output buffers is held
low and all drain outputs are off. When G is held
6
11
12
13
14
9
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
low, data from the storage register is transparent to the output buffers. When data in the output buffers is low,
the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current
capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide
additional hold time for cascaded applications. This will provide improved performance for applications where
clock signals may be skewed, devices are not located near one another, or the system must tolerate
electromagnetic interference.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either V
or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
CC
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2000–2005, Texas Instruments Incorporated
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1
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SLIS093C − MARCH 2000 − REVISED APRIL 2005
description (continued)
Outputs are low-side, open-drain DMOS transistors with output ratings of 33 V and 100 mA continuous
sink-current capability. Each output provides a 250-mA maximum current limit at T = 25°C. The current limit
C
decreases as the junction temperature increases for additional device protection. The device also provides up
to 2500 V of ESD protection when tested using the human-body model and the 200-V machine model.
The TPIC6C596 is characterized for operation over the operating case temperature range of −40°C to 125°C.
logic diagram (positive logic)
8
G
10
RCK
3
CLR
7
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
GND
D
D
C2
15
2
SRCK
C1
CLR
CLR
4
SER IN
D
D
C1
CLR
C2
CLR
5
D
D
C1
CLR
C2
CLR
6
D
D
C1
CLR
C2
CLR
11
12
13
14
D
D
C2
C1
CLR
CLR
D
D
C2
C1
CLR
CLR
D
D
C2
C1
CLR
CLR
D
D
C1
CLR
C2
CLR
16
D
C1
CLR
9
SER OUT
2
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SLIS093C − MARCH 2000 − REVISED APRIL 2005
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL DRAIN OUTPUTS
V
CC
DRAIN
33 V
Input
25 V
20 V
12 V
GND
GND
absolute maximum ratings over recommended operating case temperature range (unless
†
otherwise noted)
Logic supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Logic input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Power DMOS drain-to-source voltage, V
I
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V
DS
Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Pulsed drain current, each output, all outputs on, I , T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 250 mA
D
C
Continuous drain current, each output, all outputs on, I , T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
D
C
Peak drain current single output, I ,T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
DM
C
Single-pulse avalanche energy, E (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ
AS
Avalanche current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
AS
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
J
Operating case temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
4. DRAIN supply voltage = 15 V, starting junction temperature (T ) = 25°C, L = 1.5 H, I
= 200 mA (see Figure 4).
JS
AS
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T = 125°C
C
POWER RATING
C
PACKAGE
POWER RATING
ABOVE T = 25°C
C
D
N
1087 mW
8.7 mW/°C
11.7 mW/°C
217 mW
1470 mW
294 mW
PW
1372 mW
10.976 mW/°C
274 mW
3
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SLIS093C − MARCH 2000 − REVISED APRIL 2005
recommended operating conditions
MIN
MAX
UNIT
V
Logic supply voltage, V
CC
4.5
5.5
High-level input voltage, V
IH
0.85 V
CC
V
Low-level input voltage, V
IL
0.15 V
CC
V
Pulsed drain output current, T = 25°C, V
CC
= 5 V, all outputs on (see Notes 3 and 5 and Figure 11)
250
125
mA
ns
ns
ns
°C
C
Setup time, SER IN high before SRCK↑, t (see Figure 2)
su
15
Hold time, SER IN high after SRCK↑, t (see Figure 2)
15
40
h
Pulse duration, t (see Figure 2)
w
Operating case temperature, T
−40
C
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit T − T to 10°C maximum.
J
C
electrical characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
CC
C
PARAMETER
TEST CONDITIONS
MIN
TYP
37
MAX
UNIT
V
V
V
Drain-to-source breakdown voltage
Source-to-drain diode forward voltage
I
I
I
I
I
I
= 1 mA
33
(BR)DSX
D
= 100 mA
0.85
4.49
4.2
1.2
V
SD
F
= −20 µA,
= −4 mA,
= 20 µA,
= 4 mA,
V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 4.5 V
= 4.5 V
= 4.5 V
4.4
4
OH
OH
OL
OL
V
High-level output voltage, SER OUT
Low-level output voltage, SER OUT
V
V
OH
OL
0.005
0.3
0.1
0.5
1
V
I
I
High-level input current
Low-level input current
V
= 5.5 V,
= 5.5 V,
V = V
CC
µA
µA
IH
CC
CC
I
V
V = 0
I
−1
IL
All outputs off
All outputs on
20
200
500
I
I
I
Logic supply current
V
= 5.5 V
µA
mA
mA
CC
CC
150
f
= 5 MHz,
C = 30 pF,
L
SRCK
All outputs off,
Logic supply current at frequency
Nominal current
1.2
5
CC(FRQ)
N
See Figures 2 and 6
I = I ,
N
V
= 0.5 V,
DS(on)
= 85°C,
D
90
0.1
T
C
See Notes 5, 6 and 7
V
= 30 V,
V
V
= 5.5 V
= 5.5 V,
0.2
0.3
DS
DS
CC
I
Off-state drain current
µA
V
= 30 V,
= 125°C
DSX
CC
0.15
T
C
I
V
= 50 mA,
D
6.5
9.9
6.8
9
12
10
= 4.5 V
CC
I
T
V
= 50 mA,
D
See Notes 5 and 6
and Figures 7 and 8
= 125°C,
CC
r
Static drain-source on-state resistance
Ω
C
DS(on)
= 4.5 V
I
V
= 100 mA,
D
= 4.5 V
CC
NOTES: 5. Technique should limit T − T to 10°C maximum.
J
C
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at T = 85°C.
C
4
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SLIS093C − MARCH 2000 − REVISED APRIL 2005
switching characteristics, V
= 5 V, T = 25°C
C
CC
PARAMETER
TEST CONDITIONS
MIN
TYP
80
MAX
UNIT
ns
t
t
t
t
Propagation delay time, low-to-high-level output from G
Propagation delay time, high-to-low-level output from G
Rise time, drain output
PLH
50
ns
PHL
C
= 30 pF,
I = 75 mA,
D
L
See Figures 1, 2, and 9
100
80
ns
r
f
Fall time, drain output
ns
C
= 30 pF,
I
I
= 75 mA,
= 75 mA,
L
D
t
f
Propagation delay time, SRCK↓ to SEROUT
15
ns
pd
See Figure 2
C
= 30 pF,
L
D
Serial clock frequency
10
MHz
(SRCK)
See Note 8
t
t
Reverse-recovery-current rise time
Reverse-recovery time
100
120
a
I
= 100 mA,
di/dt = 10 A/µs,
F
ns
See Notes 5 and 6 and Figure 3
rr
NOTES: 5. Technique should limit T − T to 10°C maximum.
J
C
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
8. This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second
stage. The clock period allows for SRCK → SEROUT propagation delay and setup time plus some timing margin.
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
MAX
115
85
UNIT
D package
N package
PW package
R
Thermal resistance, junction-to-ambient
All 8 outputs with equal power
°C/W
θJA
108
PARAMETER MEASUREMENT INFORMATION
5 V
15 V
7
6
5
4
3
2
1
0
5 V
SRCK
1
0 V
5 V
I
D
7
V
CC
CLR
G
R
= 200 Ω
L
15
0 V
5 V
SRCK
3−6,
11−14
DUT
Output
SER IN
Word
Generator
(see Note A)
2
0 V
5 V
DRAIN
SER IN
10
8
RCK
C
= 30 pF
RCK
G
L
0 V
5 V
(see Note B)
CLR
0 V
GND
16
15 V
0.5 V
DRAIN1
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The word generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, t = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
r
f
w
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 1. Resistive-Load Test Circuit and Voltage Waveforms
5
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SLIS093C − MARCH 2000 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
5 V
0 V
G
50%
50%
5 V
15 V
t
PLH
t
PHL
1
24 V
90%
90%
Output
7
V
CC
10%
10%
CLR
I
D
0.5 V
R
= 200 Ω
L
15
t
t
f
r
SRCK
SER IN
3−6,
11−14
DUT
Output
Word
SWITCHING TIMES
2
Generator
(see Note A)
DRAIN
5 V
0 V
10
8
C
= 30 pF
50%
L
SRCK
RCK
G
(see Note B)
GND
t
su
t
h
16
TEST CIRCUIT
5 V
0 V
SER IN
50%
50%
t
w
INPUT SETUP AND HOLD WAVEFORMS
50%
50%
SRCK
t
t
pd
pd
SER OUT
50%
50%
SER OUT PROPAGATION DELAY WAVEFORM
NOTES: A. The word generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, t = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
r
f
w
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
6
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SLIS093C − MARCH 2000 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
TP K
DRAIN
0.1 A
Circuit
Under
Test
2500 µF
250 V
di/dt = 10 A/µs
+
−
I
F
15 V
L = 0.85 mH
TP A
I
F
(see Note A)
0
25% of I
RM
t
2
t
1
t
3
Driver
I
RM
R
G
t
V
a
GG
(see Note B)
50 Ω
t
rr
TEST CIRCUIT
CURRENT WAVEFORM
NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
B. The V
amplitude and R are adjusted for di/dt = 10 A/µs. A V double-pulse train is used to set I = 0.1 A, where t = 10 µs,
GG
G
GG F 1
t
2
= 7 µs, and t = 3 µs.
3
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode
5 V
15 V
t
w
t
1
av
7
V
5 V
0 V
CC
30 Ω
CLR
Input
I
15
2
D
See Note B
SRCK
DUT
I
= 200 mA
1.5 H
V
AS
Word
Generator
(see Note A)
SER IN
3−6,
11−14
I
D
10
8
DRAIN
DS
RCK
G
V
= 33 V
(BR)DSX
MIN
GND
V
DS
16
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT
VOLTAGE AND CURRENT WAVEFORMS
NOTES: A. The word generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, Z = 50 Ω.
r
f
O
B. Input pulse duration, t , is increased until peak current I
= 200 mA.
w
AS
Energy test level is defined as E = I
AS AS
× V × t /2 = 30 mJ.
(BR)DSX av
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
7
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ꢀ ꢁ ꢂꢃ ꢄ ꢃ ꢅꢆ ꢄ
ꢁ ꢇꢈ ꢉꢊ ꢋ ꢇꢌꢂ ꢃ ꢍ ꢎꢏꢂ ꢀ ꢐ ꢑꢂ ꢒꢀ ꢊꢉ ꢌ ꢂꢐ ꢀꢉ ꢊ
SLIS093C − MARCH 2000 − REVISED APRIL 2005
TYPICAL CHARACTERISTICS
PEAK AVALANCHE CURRENT
vs
SUPPLY CURRENT
vs
TIME DURATION OF AVALANCHE
FREQUENCY
1
6
5
4
3
2
1
0
T
C
= 25°C
V
= 5 V
= −40C° to 125°C
CC
T
C
0.1
0.01
0.1
1
10
0.1
1
10
100
t
− Time Duration of Avalanche − ms
f − Frequency − MHz
av
Figure 5
Figure 6
STATIC
DRAIN-TO-SOURCE ON-STATE RESISTANCE
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
vs
DRAIN CURRENT
LOGIC SUPPLY VOLTAGE
30
25
20
15
10
5
12
10
8
V
= 5 V
I = 50 mA
D
See Note A
CC
See Note A
T
= 125°C
C
T
= 125°C
C
T
C
= 25°C
6
4
T
= 25°C
C
T
= − 40°C
C
2
T
= −40°C
C
0
0
4.0
50
70
90
I
110 130 150 170 190
− Drain Current − mA
250
4.5
5.0
5.5
6.0
6.5
7.0
V
− Logic Supply Voltage − V
D
CC
Figure 7
Figure 8
NOTE A: Technique should limit T − T to 10°C maximum.
J
C
8
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ꢀꢁ ꢂ ꢃꢄ ꢃꢅ ꢆꢄ
ꢁꢇ ꢈ ꢉꢊ ꢋ ꢇꢌ ꢂ ꢃ ꢍ ꢎꢏꢂ ꢀ ꢐꢑꢂ ꢒ ꢀ ꢊ ꢉꢌ ꢂ ꢐ ꢀꢉ ꢊ
SLIS093C − MARCH 2000 − REVISED APRIL 2005
TYPICAL CHARACTERISTICS
SWITCHING TIME
vs
CASE TEMPERATURE
140
120
100
80
I
= 75 mA
D
t
See Note A
r
t
f
t
PLH
60
t
PHL
40
20
0
−50
−25
0
25
50
75
100
125
T
C
− Case Temperature − °C
Figure 9
NOTE A: Technique should limit T − T to 10°C maximum.
J
C
9
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ꢀ ꢁ ꢂꢃ ꢄ ꢃ ꢅꢆ ꢄ
ꢁ ꢇꢈ ꢉꢊ ꢋ ꢇꢌꢂ ꢃ ꢍ ꢎꢏꢂ ꢀ ꢐ ꢑꢂ ꢒꢀ ꢊꢉ ꢌ ꢂꢐ ꢀꢉ ꢊ
SLIS093C − MARCH 2000 − REVISED APRIL 2005
THERMAL INFORMATION
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
0.25
0.20
0.15
0.10
0.05
0.00
0.30
0.25
0.20
0.15
0.10
0.05
0.00
V
CC
= 5 V
d = 10%
d = 20%
d = 50%
T
= 25°C
C
d = 80%
T
= 100°C
C
V
= 5 V
T
= 125°C
CC
= 25°C
C
T
C
d = t /t
w period
= 1 ms/t
period
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
N − Number of Outputs Conducting Simultaneously
N − Number of Outputs Conducting Simultaneously
Figure 10
Figure 11
10
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ꢀꢁ ꢂ ꢃꢄ ꢃꢅ ꢆꢄ
ꢁꢇ ꢈ ꢉꢊ ꢋ ꢇꢌ ꢂ ꢃ ꢍ ꢎꢏꢂ ꢀ ꢐꢑꢂ ꢒ ꢀ ꢊ ꢉꢌ ꢂ ꢐ ꢀꢉ ꢊ
SLIS093C − MARCH 2000 − REVISED APRIL 2005
THERMAL INFORMATION
†
D PACKAGE
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
10
DC Conditions
d = 0.5
1
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
0.01
0.001
0.0001
Single Pulse
t
c
t
w
I
D
0
0.0001
0.001
0.01
0.1
1
10
t
− Pulse Duration − s
w
†
Device mounted on FR4 printed-circuit board with no heat sink
NOTES: (t) = r(t) R
Z
θA
θJA
t
w
= pulse duration
= cycle time
t
c
d = duty cycle = t /t
w c
Figure 12
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jul-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPIC6C596D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
16
16
40
40
TBD
CU NIPDAU Level-1-220C-UNLIM
Contact TI Distributor
or Sales Office
TPIC6C596DG4
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
TPIC6C596DR
ACTIVE
ACTIVE
SOIC
SOIC
D
D
16
16
2500
1
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
TPIC6C596DRG4
Green (RoHS
& no Sb/Br)
Request Free Samples
TPIC6C596DRQ1
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
TPIC6C596N
TPIC6C596PW
TPIC6C596PWG4
ACTIVE
ACTIVE
ACTIVE
PDIP
N
16
16
16
25
90
90
Pb-Free (RoHS)
TBD
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Request Free Samples
Purchase Samples
TSSOP
TSSOP
PW
PW
Green (RoHS
& no Sb/Br)
TPIC6C596PWR
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
2000
2000
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
Purchase Samples
TPIC6C596PWRG4
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jul-2010
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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相关型号：
TPIC71004TDCAQ1
IC SPECIALTY ANALOG CIRCUIT, PDSO48, ROHS COMPLIANT, PLASTIC, HTSSOP-48, Analog IC:Other
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