TPIC6C596 [TI]

POWER LOGIC 8-BIT SHIFT REGISTER; 功率逻辑8位移位寄存器
TPIC6C596
型号: TPIC6C596
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

POWER LOGIC 8-BIT SHIFT REGISTER
功率逻辑8位移位寄存器

移位寄存器
文件: 总12页 (文件大小:195K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TPIC6C596  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS093 – MARCH 2000  
D OR N PACKAGE  
(TOP VIEW)  
Low r  
. . . 7 Typ  
DS(on)  
Avalanche Energy . . . 30 mJ  
Eight Power DMOS Transistor Outputs of  
100-mA Continuous Current  
V
GND  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
CC  
SER IN  
DRAIN0  
DRAIN1  
DRAIN2  
DRAIN3  
CLR  
SRCK  
250-mA Current Limit Capability  
ESD Protection . . . 2500 V  
DRAIN7  
DRAIN6  
DRAIN5  
Output Clamp Voltage . . . 33 V  
Enhanced Cascading for Multiple Stages  
All Registers Cleared With Single Input  
Low Power Consumption  
11 DRAIN4  
10 RCK  
G
9
SER OUT  
logic symbol  
description  
8
EN3  
C2  
The TPIC6C596 is a monolithic, medium-voltage,  
low-current power 8-bit shift register designed for  
use in systems that require relatively moderate  
load power such as LEDs. The device contains a  
built-in voltage clamp on the outputs for inductive  
transient protection. Power driver applications  
include relays, solenoids, and other low-current or  
medium-voltage loads.  
G
10  
RCK  
SRG8  
7
R
CLR  
15  
SRCK  
C1  
3
2
DRAIN0  
1D  
2
SER IN  
4
5
DRAIN1  
DRAIN2  
DRAIN3  
DRAIN4  
DRAIN5  
DRAIN6  
DRAIN7  
SER OUT  
This device contains an 8-bit serial-in, parallel-out  
shift register that feeds an 8-bit D-type storage  
register. Data transfers through both the shift and  
storage registers on the rising edge of the shift  
register clock (SRCK) and the register clock  
(RCK), respectively. The storage register trans-  
fers data to the output buffer when shift register  
clear (CLR) is high. When CLR is low, all registers  
in the device are cleared. When output enable (G)  
is held high, all data in the output buffers is held  
low and all drain outputs are off. When G is held  
6
11  
12  
13  
14  
9
2
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
low, data from the storage register is transparent to the output buffers. When data in the output buffers is low,  
the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current  
capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide  
additional hold time for cascaded applications. This will provide improved performance for applications where  
clock signals may be skewed, devices are not located near one another, or the system must tolerate  
electromagnetic interference.  
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These  
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,  
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated  
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device  
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,  
preferably either V  
or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for  
CC  
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC6C596  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS093 – MARCH 2000  
description (continued)  
Outputs are low-side, open-drain DMOS transistors with output ratings of 33 V and 100 mA continuous  
sink-current capability. Each output provides a 250-mA maximum current limit at T = 25°C. The current limit  
C
decreases as the junction temperature increases for additional device protection. The device also provides up  
to 2500 V of ESD protection when tested using the human-body model and 200 V machine model.  
The TPIC6C596 is characterized for operation over the operating case temperature range of 40°C to 125°C.  
logic diagram (positive logic)  
8
G
10  
RCK  
3
CLR  
7
DRAIN0  
DRAIN1  
DRAIN2  
DRAIN3  
DRAIN4  
DRAIN5  
DRAIN6  
DRAIN7  
GND  
D
D
C2  
15  
2
SRCK  
C1  
CLR  
CLR  
4
SER IN  
D
D
C1  
CLR  
C2  
CLR  
5
D
D
C1  
CLR  
C2  
CLR  
6
D
D
C1  
CLR  
C2  
CLR  
11  
12  
13  
14  
D
D
C2  
C1  
CLR  
CLR  
D
D
C2  
C1  
CLR  
CLR  
D
D
C2  
C1  
CLR  
CLR  
D
D
C1  
CLR  
C2  
CLR  
16  
D
C1  
CLR  
9
SER OUT  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC6C596  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS093 – MARCH 2000  
schematic of inputs and outputs  
EQUIVALENT OF EACH INPUT  
TYPICAL OF ALL DRAIN OUTPUTS  
V
CC  
DRAIN  
33 V  
Input  
25 V  
20 V  
12 V  
GND  
GND  
absolute maximum ratings over recommended operating case temperature range (unless  
otherwise noted)  
Logic supply voltage, V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V  
CC  
Logic input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V  
Power DMOS drain-to-source voltage, V  
I
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V  
DS  
Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA  
Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA  
Pulsed drain current, each output, all outputs on, I , T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 250 mA  
D
C
Continuous drain current, each output, all outputs on, I , T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA  
D
C
Peak drain current single output, I ,T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA  
DM  
C
Single-pulse avalanche energy, E (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ  
AS  
Avalanche current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA  
AS  
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table  
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 150°C  
J
Operating case temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 125°C  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
C
Storage temperature range, T  
stg  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. All voltage values are with respect to GND.  
2. Each power DMOS source is internally connected to GND.  
3. Pulse duration 100 µs and duty cycle 2%.  
4. DRAIN supply voltage = 15 V, starting junction temperature (T ) = 25°C, L = 1.5 H, I  
= 200 mA (see Figure 4).  
AS  
JS  
DISSIPATION RATING TABLE  
T
25°C  
DERATING FACTOR  
T = 125°C  
C
POWER RATING  
C
PACKAGE  
POWER RATING  
ABOVE T = 25°C  
C
D
N
1087 mW  
8.7 mW/°C  
11.7 mW/°C  
217 mW  
1470 mW  
294 mW  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC6C596  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS093 – MARCH 2000  
recommended operating conditions  
MIN  
MAX  
UNIT  
V
Logic supply voltage, V  
CC  
4.5  
5.5  
High-level input voltage, V  
IH  
0.85 V  
V
CC  
Low-level input voltage, V  
0.15 V  
V
IL  
Pulsed drain output current, T = 25°C, V  
CC  
= 5 V, all outputs on (see Notes 3 and 5 and Figure 11)  
CC  
250  
mA  
ns  
ns  
ns  
°C  
C
Setup time, SER IN high before SRCK, t (see Figure 2)  
su  
Hold time, SER IN high after SRCK, t (see Figure 2)  
15  
15  
40  
h
Pulse duration, t (see Figure 2)  
w
Operating case temperature, T  
40  
125  
C
NOTES: 3. Pulse duration 100 µs and duty cycle 2%.  
5. Technique should limit T – T to 10°C maximum.  
J
C
electrical characteristics, V  
= 5 V, T = 25°C (unless otherwise noted)  
CC  
C
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
37  
MAX  
UNIT  
V
V
V
Drain-to-source breakdown voltage  
Source-to-drain diode forward voltage  
I
I
I
I
I
I
= 1 mA  
33  
(BR)DSX  
D
= 100 mA  
0.85  
4.49  
4.2  
1.2  
V
SD  
F
= 20 µA,  
= 4 mA,  
= 20 µA,  
= 4 mA,  
V
CC  
V
CC  
V
CC  
V
CC  
= 4.5 V  
= 4.5 V  
= 4.5 V  
= 4.5 V  
4.4  
4
OH  
OH  
OL  
OL  
V
High-level output voltage, SER OUT  
Low-level output voltage, SER OUT  
V
V
OH  
OL  
0.005  
0.3  
0.1  
0.5  
1
V
I
I
High-level input current  
Low-level input current  
V
= 5.5 V,  
= 5.5 V,  
V = V  
CC  
µA  
µA  
IH  
CC  
CC  
I
V
V = 0  
I
–1  
IL  
All outputs off  
All outputs on  
20  
200  
500  
I
Logic supply current  
V
CC  
= 5.5 V  
µA  
CC  
150  
f
= 5 MHz,  
C = 30 pF,  
L
SRCK  
All outputs off,  
I
Logic supply current at frequency  
Nominal current  
1.2  
5
mA  
mA  
CC(FRQ)  
N
See Figures 2 and 6  
I = I ,  
N
V
T
= 0.5 V,  
DS(on)  
= 85°C,  
D
I
90  
0.1  
See Notes 5, 6 and 7  
C
V
= 30 V,  
V
V
= 5.5 V  
= 5.5 V,  
5
8
DS  
DS  
CC  
I
Off-state drain current  
µA  
V
T
= 30 V,  
= 125°C  
DSX  
CC  
0.15  
C
I
V
= 50 mA,  
D
6.5  
9.9  
6.8  
9
12  
10  
= 4.5 V  
CC  
I
T
V
= 50 mA,  
D
See Notes 5 and 6  
and Figures 7 and 8  
r
Static drain-source on-state resistance  
= 125°C,  
DS(on)  
C
= 4.5 V  
CC  
I
V
= 100 mA,  
D
= 4.5 V  
CC  
NOTES: 5. Technique should limit T – T to 10°C maximum.  
J
C
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.  
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a  
voltage drop of 0.5 V at T = 85°C.  
C
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC6C596  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS093 – MARCH 2000  
switching characteristics, V  
= 5 V, T = 25°C  
C
CC  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
80  
MAX  
UNIT  
ns  
t
t
t
t
Propagation delay time, low-to-high-level output from G  
Propagation delay time, high-to-low-level output from G  
Rise time, drain output  
PLH  
50  
ns  
PHL  
C
= 30 pF,  
I = 75 mA,  
D
L
See Figures 1, 2, and 9  
100  
80  
ns  
r
f
Fall time, drain output  
ns  
C
= 30 pF,  
I
I
= 75 mA,  
= 75 mA,  
L
D
t
f
Propagation delay time, SRCKto SEROUT  
15  
ns  
pd  
See Figure 2  
C
= 30 pF,  
L
D
Serial clock frequency  
10  
MHz  
(SRCK)  
See Note 8  
t
t
Reverse-recovery-current rise time  
Reverse-recovery time  
100  
120  
a
I
= 100 mA,  
di/dt = 10 A/µs,  
F
ns  
See Notes 5 and 6 and Figure 3  
rr  
NOTES: 5. Technique should limit T – T to 10°C maximum.  
J
C
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.  
8. This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second  
stage. The clock period allows for SRCK SEROUT propagation delay and setup time plus some timing margin.  
thermal resistance  
PARAMETER  
TEST CONDITIONS  
MIN  
MAX  
115  
85  
UNIT  
D package  
N package  
R
Thermal resistance, junction-to-ambient  
All 8 outputs with equal power  
°C/W  
θJA  
PARAMETER MEASUREMENT INFORMATION  
5 V  
15 V  
7
6
5
4
3
2
1
0
5 V  
SRCK  
1
0 V  
5 V  
I
D
7
V
CC  
CLR  
G
R
= 200 Ω  
L
15  
0 V  
5 V  
SRCK  
3–6,  
1114  
DUT  
Output  
SER IN  
Word  
Generator  
(see Note A)  
2
0 V  
5 V  
DRAIN  
SER IN  
10  
8
RCK  
C
= 30 pF  
RCK  
G
L
0 V  
5 V  
(see Note B)  
CLR  
0 V  
GND  
16  
15 V  
0.5 V  
DRAIN1  
VOLTAGE WAVEFORMS  
TEST CIRCUIT  
NOTES: A. The word generator has the following characteristics: t 10 ns, t 10 ns, t = 300 ns, pulsed repetition rate (PRR) = 5 kHz,  
r
f
w
Z
C
= 50 .  
O
L
B.  
includes probe and jig capacitance.  
Figure 1. Resistive-Load Test Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC6C596  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS093 – MARCH 2000  
PARAMETER MEASUREMENT INFORMATION  
5 V  
0 V  
G
50%  
50%  
5 V  
15 V  
t
PLH  
t
PHL  
1
24 V  
90%  
90%  
Output  
7
V
CC  
10%  
10%  
CLR  
I
D
0.5 V  
R
= 200 Ω  
L
15  
t
t
f
r
SRCK  
SER IN  
3–6,  
1114  
DUT  
Output  
Word  
SWITCHING TIMES  
2
Generator  
(see Note A)  
DRAIN  
5 V  
0 V  
10  
8
C
= 30 pF  
50%  
L
SRCK  
RCK  
G
(see Note B)  
GND  
t
su  
t
h
16  
TEST CIRCUIT  
5 V  
0 V  
SER IN  
50%  
50%  
t
w
INPUT SETUP AND HOLD WAVEFORMS  
50%  
50%  
SRCK  
t
t
pd  
pd  
SER OUT  
50%  
50%  
SER OUT PROPAGATION DELAY WAVEFORM  
NOTES: A. The word generator has the following characteristics: t 10 ns, t 10 ns, t = 300 ns, pulsed repetition rate (PRR) = 5 kHz,  
r
f
w
Z
C
= 50 .  
O
L
B.  
includes probe and jig capacitance.  
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC6C596  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS093 – MARCH 2000  
PARAMETER MEASUREMENT INFORMATION  
TP K  
DRAIN  
0.1 A  
Circuit  
Under  
Test  
2500 µF  
250 V  
di/dt = 10 A/µs  
+
I
F
15 V  
L = 0.85 mH  
TP A  
I
F
(see Note A)  
0
25% of I  
RM  
t
2
t
1
t
3
Driver  
I
RM  
R
G
t
V
a
GG  
(see Note B)  
50 Ω  
t
rr  
TEST CIRCUIT  
CURRENT WAVEFORM  
NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the  
TP A test point.  
B. The V  
amplitude and R are adjusted for di/dt = 10 A/µs. A V  
double-pulse train is used to set I = 0.1 A, where t = 10 µs,  
GG F 1  
GG  
= 7 µs, and t = 3 µs.  
G
t
2
3
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode  
5 V  
15 V  
t
w
t
1
av  
7
V
5 V  
0 V  
CC  
30 Ω  
CLR  
Input  
I
15  
2
D
See Note B  
SRCK  
DUT  
I
= 200 mA  
1.5 H  
V
AS  
Word  
Generator  
(see Note A)  
SER IN  
3–6,  
1114  
I
D
10  
8
DRAIN  
DS  
RCK  
G
V
= 33 V  
(BR)DSX  
MIN  
GND  
V
DS  
16  
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT  
VOLTAGE AND CURRENT WAVEFORMS  
NOTES: A. The word generator has the following characteristics: t 10 ns, t 10 ns, Z = 50 .  
r
f
O
B. Input pulse duration, t , is increased until peak current I  
= 200 mA.  
w
AS  
Energy test level is defined as E = I  
AS AS  
× V  
× t /2 = 30 mJ.  
(BR)DSX av  
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC6C596  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS093 – MARCH 2000  
TYPICAL CHARACTERISTICS  
PEAK AVALANCHE CURRENT  
vs  
SUPPLY CURRENT  
vs  
TIME DURATION OF AVALANCHE  
FREQUENCY  
1
6
5
4
V
= 5 V  
= 40°C to 125°C  
CC  
T
C
= 25°C  
T
C
0.4  
0.2  
0.1  
3
2
0.04  
1
0
0.02  
0.01  
0.1  
0.2  
0.4  
1
2
4
10  
0.1  
1
10  
100  
t
– Time Duration of Avalanche – ms  
f – Frequency – MHz  
av  
Figure 5  
Figure 6  
DRAIN-TO-SOURCE ON-STATE RESISTANCE  
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE  
vs  
vs  
LOGIC SUPPLY VOLTAGE  
DRAIN CURRENT  
30  
25  
20  
15  
12  
I
= 50 mA  
D
V
= 5 V  
CC  
See Note A  
See Note A  
T
= 125°C  
C
10  
8
T
= 125°C  
C
T
C
= 25°C  
6
4
10  
T = 25°C  
C
T
= – 40°C  
C
5
0
2
0
T
= 40°C  
C
50  
70  
90  
110 130 150 170 190 250  
4
4.5  
5
5.5  
6
6.5  
7
V
CC  
– Logic Supply Voltage – V  
I
D
– Drain Current – mA  
Figure 7  
Figure 8  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC6C596  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS093 – MARCH 2000  
TYPICAL CHARACTERISTICS  
SWITCHING TIME  
vs  
CASE TEMPERATURE  
140  
120  
100  
I
= 75 mA  
D
t
See Note A  
r
t
r
t
80  
60  
40  
PLH  
t
PHL  
20  
0
–50 –25  
0
25  
50  
75  
100  
125  
T
C
– Case Temperature – °C  
Figure 9  
NOTE A: Technique should limit T – T to 10°C maximum.  
J
C
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC6C596  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS093 – MARCH 2000  
THERMAL INFORMATION  
MAXIMUM PEAK DRAIN CURRENT  
OF EACH OUTPUT  
MAXIMUM CONTINUOUS  
DRAIN CURRENT OF EACH OUTPUT  
vs  
NUMBER OF OUTPUTS CONDUCTING  
SIMULTANEOUSLY  
vs  
NUMBER OF OUTPUTS CONDUCTING  
SIMULTANEOUSLY  
0.3  
0.25  
0.2  
0.25  
0.2  
V
CC  
= 5 V  
d = 10%  
d = 20%  
d = 50%  
0.15  
T
C
= 25°C  
0.15  
d = 80%  
0.1  
0.05  
0
T
= 100°C  
C
0.1  
V
T
= 5 V  
CC  
= 25°C  
T
= 125°C  
C
0.05  
0
C
d = t /t  
w period  
= 1 ms/t  
period  
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
N – Number of Outputs Conducting Simultaneously  
N – Number of Outputs Conducting Simultaneously  
Figure 10  
Figure 11  
10  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TPIC6C596  
POWER LOGIC 8-BIT SHIFT REGISTER  
SLIS093 – MARCH 2000  
THERMAL INFORMATION  
D PACKAGE  
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE  
vs  
PULSE DURATION  
10  
DC Conditions  
d = 0.5  
1
d = 0.2  
d = 0.1  
0.1  
d = 0.05  
d = 0.02  
d = 0.01  
0.01  
0.001  
Single Pulse  
t
c
t
w
I
D
0
0.0001  
0.0001  
0.001  
0.01  
0.1  
– Pulse Duration – s  
1
10  
t
w
Device mounted on FR4 printed-circuit board with no heat sink  
NOTES: (t) = r(t) R  
Z
θA θJA  
t
w
= pulse duration  
t = cycle time  
c
d = duty cycle = t /t  
w c  
Figure 12  
11  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
Customers are responsible for their applications using TI components.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
intellectual property right of TI covering or relating to any combination, machine, or process in which such  
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.  
Copyright 2000, Texas Instruments Incorporated  

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