TPIC9201PWPRG4 [TI]
MICROCONTROLLER POWER SUPPLY AND MULTIPLE LOW-SIDE DRIVER; 微控制器电源和多低侧驱动器
| 型号： | TPIC9201PWPRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MICROCONTROLLER POWER SUPPLY AND MULTIPLE LOW-SIDE DRIVER |
| 文件： | 总20页 (文件大小：697K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPIC9201
MICROCONTROLLER POWER SUPPLY
AND MULTIPLE LOW-SIDE DRIVER
www.ti.com
SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
1
FEATURES
APPLICATIONS
•
Electrical Appliances
2
•
Eight Low-Side Drivers With Internal Clamp for
Inductive Loads and Current Limiting for Self
Protection
–
–
–
–
–
–
Air Conditioning Units
Ranges
Dishwashers
Refrigerators
Microwaves
Washing Machines
–
Seven Outputs Rated at 150 mA and
Controlled Through Serial Interface
–
One Output Rated at 150 mA and
Controlled Through Serial Interface and
Dedicated Enable Pin
•
General-Purpose Interface Circuits, Allowing
Microcontroller Interface to Relays, Electric
Motors, LEDs, and Buzzers
•
•
•
5-V ± 5% Regulated Power Supply With
200-mA Load Capability at VIN Max of 18 V
Internal Voltage Supervisory for Regulated
Output
N OR PWP PACKAGE
(TOP VIEW)
Serial Communications for Control of Eight
Low-Side Drivers
1
20
ZVS
SYN
VIN
2
3
4
19
18
17
OUT1
OUT2
OUT3
•
•
Enable/Disable Input for OUT1
5VOUT
SCLK
NCS
MOSI
5-V or 3.3-V I/O Tolerant for Interface to
Microcontroller
5
16
15
14
13
12
11
OUT4
OUT5
OUT6
OUT7
OUT8
GND
•
•
Programmable Power-On Reset Delay Before
RST Asserted High, Once 5 V Is Within
Specified Range (6 ms Typ)
6
7
RST
RDELAY
EN1
8
Programmable Deglitch Timer Before RST
Asserted Low (40 µs Typ)
9
10
GND
•
•
Zero-Voltage Detection Signal
Thermal Shutdown for Self Protection
DESCRIPTION/ORDERING INFORMATION
The power supply provides regulated 5-V output to power the system microcontroller and drive eight low-side
switches. The ac zero-detect circuitry is monitoring the crossover voltage of the mains ac supply. The resultant
signal is a low-frequency clock output on the ZVS terminal, based on the ac-line cycle. This information allows
the microcontroller to reduce in-rush current by powering loads on the ac-line peak voltage.
A serial communications interface controls the eight low-side outputs; each output has an internal snubber circuit
to absorb the energy in the inductor at turn OFF. Alternatively, the system can use a fly-back diode to VIN to help
recirculate the energy in an inductive load at turn OFF.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TPIC9201N
TOP-SIDE MARKING
PDIP – N
Tube of 20
TPIC9201N
–40°C to 125°C
Reel of 2000
Tube of 70
TPIC9201PWPR
PowerPAD™ – PWP
IC9201
TPIC9201PWP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2008, Texas Instruments Incorporated
TPIC9201
MICROCONTROLLER POWER SUPPLY
AND MULTIPLE LOW-SIDE DRIVER
www.ti.com
SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
PINOUT CONFIGURATION
NO.
1
NAME
ZVS
I/O
DESCRIPTION
Zero-voltage synchronization
O
2
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
GND
O
O
O
O
O
O
O
O
I
Low-side output 1
3
Low-side output 2
4
Low-side output 3
5
Low-side output 4
6
Low-side output 5
7
Low-side output 6
8
Low-side output 7
9
Low-side output 8
10(1)
11(1)
12
13
14(2)
15
16
17
18
19
20
Ground
GND
I
Ground
EN1
I
Enable/disable for OUT1
Power-up reset delay
Power-on reset output (open drain, active low)
Serial data input
RDELAY
RST
O
I/O
I
MOSI
NCS
I
Chip select
SCLK
5VOUT
VIN
I
Serial clock for data synchronization
Regulated output
O
I
Unregulated input voltage source
AC zero detect input
SYN
I
(1) Terminals 10 and 11 are fused internally in the lead frame for the 20-pin PDIP package.
(2) Terminal 14 can be used as an input or an output.
2
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SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
FUNCTIONAL BLOCK DIAGRAM
OUT1
EN1
Enables
OUT1
OUT1
Enable
100 kW
OUT1 at
150 mA
6 V
Gate Control
for Outputs
1 Through 8
OUT2
OUT2
OUT2 at 150 mA
100 kW
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT3 at 150 mA
OUT4 at 150 mA
OUT5 at 150 mA
OUT6 at 150 mA
OUT7 at 150 mA
OUT8 at 150 mA
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
NCS
NCS
Parallel
Register
SCLK
Serial
Register
SCLK
100 kW
MOSI
MOSI
20 W
(2 W)
100 kW
VIN
10 V
7–18 V
PMOS
5VOUT
Gate Drive
and Control
Optional, dependent
on heat-management
implementation
5 V
Bandgap
Ref
Comp
(see Note A)
–
+
GND
5 kΩ
GND
Vref
Voltage
Supervisor
RST
Vref
RST
Iconst
6 V
RDELAY
ZVS
RDELAY
ZVS
S
R
2 kΩ
2 kΩ
SYN
10 kΩ
Q
SYN
12 kΩ
A. The resistor and Zener diode are required if there is insufficient thermal-management allocation.
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SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
DETAILED DESCRIPTION
The 5-V regulator is powered from VIN, and the regulated output is within 5 V ± 5% over the operating conditions.
The open-drain power-on reset (RST) pin remains low until the regulator exceeds the set threshold, and the timer
value set by the capacitor on the reset delay (RDELAY) pin expires. If both of these conditions are satisfied, RST is
asserted high. This signifies to the microcontroller that serial communications can be initiated to the TPIC9201.
The serial communications is an 8-bit format, with data transfer synchronized using a serial clock from the
microcontroller. A single register controls all the outputs (one bit per output). The default value is zero (OFF). If
an output requires pulse width modulation (PWM) function, the register must be updated at a rate faster than the
desired PWM frequency. OUT1 can be controlled by serial input from the microcontroller or with the dedicated
enable (EN1) pin. If EN1 is pulled low or left open, the serial input through the shift register controls OUT1. If
EN1 is pulled high, OUT1 always is turned on, and the serial input for OUT1 is ignored.
The SYN input translates the image of the mains voltage through the secondary of the transformer. The SYN
input has a resistor to protect from high currents into the IC. The zero-voltage synchronization output translates
the ac-line cycle frequency into a low-frequency clock, which can be used for a timing reference and to help
power loads on the ac-line peak voltage (to reduce in-rush currents).
If RST is asserted, all outputs are turned OFF internally, and the input register is reset to all zeroes. The
microcontroller must write to the register to turn the outputs ON again.
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TPIC9201
MICROCONTROLLER POWER SUPPLY
AND MULTIPLE LOW-SIDE DRIVER
www.ti.com
SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
Absolute Maximum Ratings(1)
MIN
MAX
24
UNIT
VIN
VI(unreg)
Unregulated input voltage(2) (3)
Logic input voltage(2) (3)
V
SYN
24
EN1, MOSI, SCLK, and NCS
RST and RDELAY
OUT1–OUT8
7
VI(logic)
V
7
VO
Low-side output voltage
Output current limit(4)
16.5
V
OUTn = ON and shorted to VIN
with low impedance
ILIMIT
350
mA
N package
69
33
θJA
Thermal impedance, junction to ambient(5)
°C/W
PWP package
N package
54
θJC
θJP
PD
Thermal impedance, junction to case(5)
Thermal impedance, junction to thermal pad(5)
Continuous power dissipation(6)
°C/W
°C/W
W
PWP package
PWP package
N package
20
1.4
1.8
3.7
2
PWP package
ESD
TA
Electrostatic discharge(7)
Operating ambient temperature range
Storage temperature range
Lead temperature
kV
°C
°C
°C
–40
–65
125
125
260
Tstg
Tlead
Soldering, 10 s
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Absolute negative voltage on these pins must not go below –0.5 V.
(4) Not more than one output should be shorted at a time, and duration of the short circuit should not exceed 1 ms.
(5) The thermal data is based on using 1-oz copper trace with JEDEC 51-5 test board for PWP and JEDEC 51-7 test board for N.
(6) The data is based on ambient temperature of 25°C max.
(7) The Human-Body Model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
Dissipation Ratings
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 125°C
POWER RATING
PACKAGE
N
1812 mW
3787 mW
14.5 mW/°C
30.3 mW/°C
362 mW
757 mW
PWP
Recommended Operating Conditions
MIN
7
MAX
18
UNIT
VIN
VI(unreg)
Unregulated input voltage
V
SYN
0
18
VI(logic)
TA
Logic input voltage
EN1, MOSI, SCLK, NCS, RST, and RDELAY
0
5.25
125
V
Operating ambient temperature
–40
°C
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SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
Electrical Characteristics
TA = –40°C to 125°C, VIN = 7 V to 18 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
Supply Voltage and Current
(2)
VIN
Input voltage
7
18
3
V
Enable = ON, OUT1–OUT8 = Off
Enable = ON, OUT1–OUT8 = On
IVIN
Input supply current
mA
5
Logic Inputs (MOSI, NCS, SCLK, and EN1)
VIL
Logic input low level
Logic input high level
IIL = 100 µA
IIL = 100 µA
0.8
V
VIH
2.4
Reset (RST)
VOL
Low-level logic output
High-level logic output
Disabling reset threshold
Enabling reset threshold
Threshold hysteresis
IOL = 1.6 mA
0.4
4.5
V
V
V
V
V
(3)
VOH
5-kΩ pullup to VCC
5-V regulator ramps up
5-V regulator ramps down
VCC – 0.8
VH
4.25
3.75
0.5
VL
3.3
VHYS
0.12
Reset Delay (RDELAY
)
IOUT
TDW
TUP
Output current
18
3
28
6
48
µA
ms
µs
Reset delay timer
C = 47 nF
C = 47 nF
Reset capacitor to low level
45
Output (OUT1–OUT8)
VOL
IOH
Output ON
IOUTn = 150 mA
0.4
5
0.7
2
V
Output leakage
VOH = Max of 16.5 V
µA
Regulator Output (5VOUT
)
I5VOUT = 5 mA to 200 mA, VIN = 7 V to 18 V,
C5VOUT = 1 µF
5VOUT Output supply
4.75
200
5.25
V
I5VOUT limit Output short-circuit current
5VOUT = 0 V
mA
Thermal Shutdown
TSD
Thermal shutdown
Hysteresis
150
20
°C
°C
THYS
Zero Voltage Synchronization (ZVS)
VSYNTH
ISYN
tD
Transition threshold
Input activating current
Transition time
0.4
10
0.75
1.1
2
V
RZV = 10 kΩ, VSYN = 24 V
mA
µs
Rising and falling
(1) All typical values are at TA = 25°C.
(2) There are external high-frequency noise-suppression capacitors and filter capacitors on VIN
.
(3) VCC is the pullup resistor voltage.
6
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AND MULTIPLE LOW-SIDE DRIVER
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SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
Output Control Register
MSB
LSB
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
0
0
0
0
0
0
0
0
INn = 0: Output OFF
INn = 1: Output ON
To operate the output in PWM mode, the output control register must be updated at a rate twice the desired
PWM frequency of the output. Maximum PWM frequency is 5 kHz. The register is updated every 100 µs.
ENABLE TRUTH TABLE
SERIAL INPUT
FOR OUT1
EN1
OUT1
Open
H
L
On
Off
On
Off
On
On
Open
L
L
H
L
H
H
H
L
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SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
Serial Communications Interface
The serial communications is an 8-bit format, with data transfer synchronized using a serial clock from the
microcontroller (see Figure 1). A single register controls all the outputs. The signal gives the instruction to control
the output of TPIC9201.
The NCS signal enables the SCLK and MOSI data when it is low. After NCS is set low for T1, synchronization
clock and data begin to transmit and, after the 8-bit data has been transmitted, NCS is set high again to disable
SCLK and MOSI and transfer the serial data to the control register. SCLK must be held low when NCS is in the
high state.
T2
T3
T8
T1
T4
T5
T1
NCS
SCLK
1
2
3
4
5
6
7
8
MSB
IN8
LSB
IN1
MOSI
XXX
IN7
IN6
IN5
IN4
IN3
IN2
T6
T7
Figure 1. Serial Communications
8
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AND MULTIPLE LOW-SIDE DRIVER
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SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
Timing Requirements
TA = –40°C to 125°C, VIN = 7 V to 18 V (unless otherwise noted)
MIN
TYP
MAX
UNIT
MHz
ns
fSPI
T1
T2
T3
T4
T5
T6
T7
T8
SPI frequency
4
Delay time, NCS falling edge to SCLK rising edge
Delay time, NCS falling edge to SCLK falling edge
Pulse duration, SCLK high
10
80
ns
60
ns
Pulse duration, SCLK low
60
ns
Delay time, last SCLK falling edge to NCS rising edge
Setup time, MOSI valid before SCLK edge
Hold time, MOSI valid after SCLK edge
Time between two words for transmitting
80
ns
10
ns
10
ns
170
ns
Reset Delay (RDELAY
)
The RDELAY output provides a constant current source to charge an external capacitor to approximately 6.5 V.
The external capacitor is selected to provide a delay time, based on the current equation for a capacitor,
I = C(Δv/Δt) and a 28-µA typical output current.
Therefore, the user should select a 47-nF capacitor to provide a 6-ms delay at 3.55 V.
I = C(Δv/Δt)
28 µA = C × (3.55 V/6 ms)
C = 47 nF
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SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
APPLICATION INFORMATION
Buzzer Driver
Relꢁy Driver
Relꢁy Driver
Relꢁy Driver
Relꢁy Driver
Fꢁn Driver
MOSI
SCLK
NCS
MCU/DSP
8 Ouapuas
Fꢁn Driver
Fꢁn Driver
ZVS
TPIC9201
RST
5VOUT 5ꢀ ꢁa 200 ꢂm
EN1
SYN (mC Zero-Cross
Deaeca Inpua)
Resea Delꢁy
DC Inpua 7 V ao 18 V
GND (´2)
Figure 2. Typical Application
Display
(LED/LCD/VFD)
Keypad
LED LED
Water
Supply
Valve
Filters
AC
Water
Outlet
Softener
Supply
Volume
Sensor
M
Power
Switch
Water-Level
Sensor
Controller
Driver
Optical
Sensor
SYN
VIN
ZVS
Zero-Cross
Detection
Temperature
Sensor
(Optional)
5VOUT
RST
Regulator
+
~
~
POR/SYS
-
Cover
Switch
TPIC9201
Figure 3. Washing-Machine Application
10
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AND MULTIPLE LOW-SIDE DRIVER
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SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
PCB Layout
To maximize the efficiency of this package for application on a single-layer or multilayer PCB, certain guidelines
must be followed when laying out this part on the PCB.
The following information is to be used as a guideline only.
For further information, see the PowerPAD concept implementation document.
Application Using a Multilayer PCB
In a multilayer board application, the thermal vias are the primary method of heat transfer from the package
thermal pad to the internal ground plane (see Figure 4 and Figure 5).
The efficiency of this method depends on several factors: die area, number of thermal vias, thickness of copper,
etc. (see the PowerPAD™ Thermally Enhanced Package Technical Brief, literature number SLMA002).
Solder Pad (Land Pattern)
Package Thermal Pad
Thermal Vias
Package Outline
Figure 4. Package and PCB Land Configuration for a Multilayer PCB
Power Pad
Package Solder Pad
Component Traces
1.5038–1.5748-mm
Component Trace
(2-oz Cu)
2 Plane
1.0142–1.0502-mm
Ground Plane
(1-oz Cu)
Thermal Via
4 Plane
1.5748 mm
0.5246–0.5606-mm
Power Plane
(1-oz Cu)
Thermal Isolation
Power Plane Only
0.0–0.071-mm Board Base
and Bottom Pad
Package Solder Pad
(Bottom Trace)
Figure 5. Multilayer Board (Side View)
Application Using a Single-Layer PCB
In a single-layer board application, the thermal pad is attached to a heat spreader (copper area) by using the low
thermal-impedance attachment method (solder paste or thermal-conductive epoxy). With either method, it is
advisable to use as much copper trace area as possible to dissipate the heat.
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SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
CAUTION:
If the attachment method is not implemented correctly, the functionality of the
product cannot be ensured. Power-dissipation capability is adversely affected if
the device is incorrectly mounted onto the circuit board.
Use as Much Copper Area
as Possible for Heat Spread
Package Thermal Pad
Package Outline
Figure 6. Layout Recommendations for a Single-Layer PCB
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SLIS115D–APRIL 2005–REVISED FEBRUARY 2008
Recommended Board Layout
6,5 SMOC
5,85
SMOC = Solder Mask Over Copper
SMO = Solder Mask Opening
1
0,65
0,27 (´20)
3,7 SMO
Figure 7. Recommended Board Layout for PWP
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jan-2008
PACKAGING INFORMATION
Orderable Device
TPIC9201N
Status (1)
NRND
NRND
NRND
NRND
NRND
NRND
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
N
20
20
20
20
20
20
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TPIC9201NE4
PDIP
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TPIC9201PWP
TPIC9201PWPG4
TPIC9201PWPR
TPIC9201PWPRG4
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
PWP
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPIC9201PWPR
HTSSOP PWP
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 20
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
TPIC9201PWPR
2000
Pack Materials-Page 2
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