TPL0202-10MRTER [TI]
256-TAPS DUAL CHANNEL DIGITAL POTENTIOMETER WITH SPI INTERFACE AND NONVOLATILE MEMORY; 256抽头双通道数字具有SPI接口的和非易失性存储器电位器
| 型号： | TPL0202-10MRTER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 256-TAPS DUAL CHANNEL DIGITAL POTENTIOMETER WITH SPI INTERFACE AND NONVOLATILE MEMORY |
| 文件： | 总30页 (文件大小：948K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPL0202
www.ti.com
SLIS135C –DECEMBER 2010–REVISED JUNE 2012
256-TAPS DUAL CHANNEL DIGITAL POTENTIOMETER WITH SPI INTERFACE AND NON-
VOLATILE MEMORY
Check for Samples: TPL0202
1
FEATURES
MicroQFN - RUC PACKAGE
(TOP VIEW)
•
Dual Channel, 256-Position Resolution
HA WA
•
•
Non-volatile Memory Stores Wiper Settings
14 13
1
2
3
4
5
12
11 N.C.
2mm x 2mm, 14-pin MicroQFN or 3mm x 3mm,
16-pin QFN Packages
VDD
SCLK
DIN
LA
•
•
•
10 kΩ End-to-End Resistance (TPL0202-10)
10
9
N.C.
N.C.
HB
Fast Power-up Response Time: <100µs
CS
±1 LSB INL, ±0.5 LSB DNL (Voltage-Divider
Mode)
6
7
8
GND
•
12 ppm/°C Ratiometric Temperature
Coefficient
LB WB
QFN - RTE PACKAGE
(TOP VIEW)
•
•
•
SPI-Compatible Serial Interface
2.7 V to 5.5 V Single-Supply Operation
Operating Temperature Range From
-40°C to +85°C
12 11 10
9
LA
13
14
8
N.C.
GND
N.C.
•
ESD Performance Tested Per JESD 22
WA
–
2000-V Human Body Model
(A114-B, Class II)
7
6
5
EP
HA
15
16
N.C.
N.C.
APPLICATIONS
1
2
3
4
•
Adjustable Gain Amplifiers and Offset
Trimming
•
•
•
•
Adjustable Power Supplies
Precision Calibration of Set Point Thresholds
Sensor Trimming and Calibration
Mechanical Potentiometer Replacement
DESCRIPTION
The TPL0202 is a two channel, linear-taper digital potentiometer with 256 wiper positions. Each potentiometer
can be used as a three-terminal potentiometer or as a two-terminal rheostat. The TPL0202-10 has an end-to-end
resistance of 10kΩ.
The TPL0202 has non-volatile memory (EEPROM) which can be used to store the wiper position. The internal
registers of the TPL0202 can be accessed using a SPI-compatible digital interface.
The TPL0202 is available in a 14-pin MicroQFN (2mm x 2mm) and 16-pin QFN (3mm x 3mm) package with a
specified temperature range of -40°C to +85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPL0202
SLIS135C –DECEMBER 2010–REVISED JUNE 2012
www.ti.com
ORDERING INFORMATION
TA
PACKAGE(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RTE
QFN – RUC
TPL0202-10MRTER
TPL0202-10RUCR
ZUR
TBD
–40°C to 85°C
Tape and reel
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Table 1. Summary of Features
Feature
# of Potentiometers
TPL0202-10
2
Digital Interface
SPI
Steps
256
Non-Volatile
Linear
Wiper Memory
Taper
End-to-end Resistance
End-to-end Resistance Tolerance
Wiper Resistance
Smallest Package Size
10kΩ
20%
25 Ω (typ)
MicroQFN (RUC): 4 mm2
FUNCTIONAL BLOCK DIAGRAM
VDD
HA
HB
SCLK
DIN
VOLATILE
SPI INTERFACE
WA
REGISTERS
CS
WB
NON-VOLATILE
REGISTERS
GND
LA
LB
2
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Product Folder Link(s): TPL0202
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SLIS135C –DECEMBER 2010–REVISED JUNE 2012
DIGITAL POTENTIOMETER CONFIGURATIONS
VOLTAGE DIVIDER MODE
VH
VHW
VHW = (VH – VL) x (1 – (D/256))
VH - VL
W
VWL = (VH – VL) x D/256
VWL
Where D = Decimal Value of Wiper Code
VL
RHEOSTAT MODE A
H
H (Floating)
RWL = RTOT x D/256
RTOT
OR
RTOT
W
W
Where D = Decimal Value of Wiper Code
RWL
RWL
L
L
RHEOSTAT MODE B
H
H
RHW
RHW
RHW = RTOT x (1 – (D/256))
RTOT
OR
RTOT
Where D = Decimal Value of Wiper Code
W
W
L
L (Floating)
Figure 1. DPOT Configurations
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SLIS135C –DECEMBER 2010–REVISED JUNE 2012
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Table 2. PIN DESCRIPTION TABLE
16 RTE
14 RUC
I/O
DESCRIPTION
I/O
DESCRIPTION
Supply Voltage
NO.
1
NAME
N.C.
SCLK
DIN
CS
NO.
1
NAME
VDD
SCLK
DIN
CS
Not internally connected
SPI Clock
Power
Input
Input
Input
Ground
I/O
2
Input
Input
Input
2
SPI Clock
SPI Input
3
SPI Input
3
4
SPI Chip Select (Active Low)
Not internally connected
Not internally connected
Ground
4
SPI Chip Select (Active Low)
Ground
5
N.C.
N.C.
GND
N.C.
N.C.
LB
5
GND
LB
6
6
Low terminal of Potentiometer B
Wiper terminal of Potentiometer B
High terminal of Potentiometer B
Not internally connected
7
Ground
7
WB
I/O
8
Not internally connected
Not internally connected
Low terminal of Potentiometer B
Wiper terminal of Potentiometer B
High terminal of Potentiometer B
Low terminal of Potentiometer A
Wiper terminal of Potentiometer A
High terminal of Potentiometer A
Not internally connected
8
HB
I/O
9
9
N.C.
N.C.
N.C.
LA
10
11
12
13
14
15
16
I/O
I/O
I/O
I/O
I/O
I/O
10
11
12
13
14
Not internally connected
WB
Not internally connected
HB
I/O
I/O
I/O
Low terminal of Potentiometer A
Wiper terminal of Potentiometer A
High terminal of Potentiometer A
LA
WA
WA
HA
HA
N.C
Exposed Thermal Pad.
Can be connected to GND or left
unconnected.
EP
EP
4
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SLIS135C –DECEMBER 2010–REVISED JUNE 2012
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5
VDD
5.5
5.5
0.8
±2
UNIT
V
VDD,GND
2.7
VH, VL, VW Terminal Voltage Range
0
2.4
V
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
VIH
Voltage Input High (SCLK, DIN, CS)
V
0.7 × VDD
0
VIL
IW
Voltage Input Low (SCLK, DIN, CS)
Wiper Current
V
mA
°C
TA
Ambient Temperature
–40
85
ABSOLUTE MAXIMUM RATINGS(1)(2)(3)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VDD to GND
–0.3
7
V
Supply voltage range
All other pins
to GND
–0.3 VDD + 0.3
IL
IW
IH
Pulse Current
±20
±2
mA
mA
Continuous Current
TPL0202-10
θJA
RTE package
RUC package
56.4
Package Thermal Impedance(4)
Storage temperature range
°C/W
°C
216.7
Tstg
–65
150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
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ELECTRICAL CHARACTERISTICS
VDD = 2.7V to 5.5V, TA=-40°C to 85°C (unless otherwise noted). Typical values are at VDD=5V, TA=25°C (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
End-to-end Resistance
RTOT
(Between H and L
Terminals)
8
10
12
kΩ
VH, VL
RH, RL
RW
Terminal voltage range
Terminal resistance
Wiper resistance
0
VDD
200
100
V
Ω
60
25
22
18
Ω
(1)(2)
CH, CL
Terminal capacitance
Wiper capacitance
pF
pF
(1)(2)
CW
VH = VSS to VDD, VL = Floating
OR
VL = VSS to VDD, VH = Floating
Terminal Leakage
Current
ILKG
0.1
1
µA
Resistance temperature
coefficient
TCR
Input Code = 0x80h
132
0.1
ppm/°C
%
Channel-to-channel
resistance match
RTOT,MATCH
Voltage Divider Mode
INL(3)(4)
DNL(3)(5)
ZSERROR
FSERROR
Integral non-linearity
–1
–0.5
0
1
0.5
5
LSB
LSB
LSB
LSB
Differential non-linearity
Zero-scale error
(6)(7)
(6)(8)
2
Full-scale error
–5
–2
0
Channel-to-Channel
matching
Wiper at the same tap position, same voltage all H and
the same voltage at all L terminals
(6)(9)
VMATCH
TCV
–2
2
LSB
Ratiometric
temperature coefficient
Wiper set at mid-scale
12
ppm/°C
Wiper set at mid-scale
CLOAD = 10 pF
BW
Bandwidth
2000
0.4
kHz
µS
TSW
Wiper setting time
VH = 1 VRMS at 1 kHz,
VL = VDD/2,
Measurement at W
Total harmonic
distortion
THD
0.03
–94
%
fH = 1 kHz,
VL = GND,
XTALK
Crosstalk
dB
Measurement at W
(1) Terminal and Wiper Capacitance extracted from self admittance of three port network measurement
I
i
Y =
ii
Vk =0 for k¹i
V
i
(2) Digital Potentiometer Macromodel
H
CH
R
TOTAL
W
CW
CL
L
(3) LSB = (VMEAS[code 255] – VMEAS[code 0]) / 255
(4) INL = ((VMEAS[code x] – VMEAS[code 0]) / LSB) - [code x]
(5) DNL = ((VMEAS[code x] – VMEAS[code x-1]) / LSB) – 1
(6) IDEAL_LSB = (VH-VL) / 256
(7) ZSERROR = VMEAS[code 0] / IDEAL_LSB
(8) FSERROR = [(VMEAS[code 255] – (VH-VL)) / IDEAL_LSB] + 1
(9) VMATCH = (VMEAS_A[code x] – VMEAS_B[code x]) / IDEAL_LSB
6
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SLIS135C –DECEMBER 2010–REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7V to 5.5V, TA=-40°C to 85°C (unless otherwise noted). Typical values are at VDD=5V, TA=25°C (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RHEOSTAT MODE (Measurements between W and L with H not connected, or between W and H with L not connected)
(10)(11)
RINL
Integral non-linearity
Differential non-linearity
Offset
–1.5
–0.5
0
1.5
0.5
7
LSB
LSB
LSB
RDNL(10)(12)
(13)(14)
ROFFSET
2.5
Channel-to-Channel
matching
(13)(15)
RMATCH
RBW
–2
2
LSB
Code = 0x00h,
L Floating,
Input applied to W,
Measure at H, CLOAD = 10 pF
Bandwidth
400
kHz
(10) RLSB = (RMEAS[code 255] – RMEAS[code 0]) / 255
(11) RINL =( (RMEAS[code x] – RMEAS[code 0]) / RLSB) - [code x]
(12) RDNL =( (RMEAS[code x] – RMEAS[code x-1]) / RLSB )– 1
(13) IDEAL_RLSB = RTOT / 256
(14) ROFFSET = RMEAS[code 0] / IDEAL_RLSB
(15) RMATCH = (RMEAS_A[code x] – RMEAS_B[code x]) / IDEAL_RLSB
OPERATING CHARACTERISTICS
VDD = 2.7V to 5.5V, VH= VDD, VL= GND, TA= -40°C to 85°C (unless otherwise noted). Typical values are at VDD= 5V, TA= 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDD(STBY)
IDD
IIN-DIG
VPOR
VDD supply current during standby Digital Inputs = VDD or GND
1
5
µA
VDD supply current during write
cycle only
Digital Inputs = VDD or GND
400
1
µA
µA
V
Digital pins leakage current
(SCLK, DIN, CS inputs)
–1
Minimum VDD at which memory
recall occurs
Power-on recall voltage
2
EEPROM Specification
EEPROM endurance
100,000
100
Cycles
Years
ms
EEPROM retention
TA = 85 °C
tBUSY
tACC
tWO
Write NV register busy time
Read NV register access time
20
40
ns
Write wiper register to output
delay
40
ns
tD
Power-up Response Time (VDD
above VPOR to wiper register value
recall completed)
35
100
µs
Serial Interface Specifications (SCLK, DIN, CS Inputs)
VIH
Input high voltage
VDD = 3.6 V to 5.5 V
VDD = 2.7 V to 3.6 V
SCLK, DIN, CS inputs
SCLK, DIN, CS inputs
2.4
0.7 × VDD
0
5.5
5.5
0.8
V
VIL
Input low voltage
Pin capacitance
V
CIN
7
pF
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UMNAITX
SPI INTERFACE TIMING REQUIREMENTS
VDD = 2.7V to 5.5V, VH= VDD, VL= GND, TA= -40°C to 85°C (unless otherwise noted)
MIN
TYP
fSCLK
tSCP
tSCH
tSCL
tCSS
tCSH
tDS
SLCK frequency
5
MHz
SCLK period
200
80
80
80
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK high time
SCLK low time
CS fall to SCLK rise setup time
SCLK rise to CS hold time
DIN to SCLK setup time
DIN hold after SCLK rise to CS fall
SCLK rise to CS fall
CS rise to SCLK rise hold
CS pulse width high
50
0
tDH
tCS0
tCS1
tCSW
20
80
200
8
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SLIS135C –DECEMBER 2010–REVISED JUNE 2012
TYPICAL PERFORMANCE CURVES
STANDBY CURRENT
vs
SUPPLY CURRENT
vs
TEMPERATURE
DIGITAL INPUT VOLTAGE
10000
1000
100
2.5
2
V
= 5 V
DD
V
= 5 V
DD
1.5
1
V
= 2.7 V
V
= 2.7 V
DD
DD
10
0.5
0
1
0
-40
-15
10
35
60
85
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
T
- Free-Air Temperature - °C
A
V - Input Voltage - V
I
VOLTAGE DIVIDER MODE DNL
vs
VOLTAGE DIVIDER MODE INL
vs
TEMPERATURE (VDD = 5V)
TEMPERATURE (VDD = 5V)
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
T
= 85°C
V
= 5 V
A
DD
V
= 5 V
DD
T
T
= 25°C
A
= -40°C
A
-0.1
T
= 85°C
A
-0.2
-0.3
T
T
= 25°C
A
= -40°C
A
-0.1
0
0
32
64
96
128 160 192 224
32
64
96
128 160 192 224
Digital Code
Digital Code
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TYPICAL PERFORMANCE CURVES (continued)
VOLTAGE DIVIDER MODE INL
vs
VOLTAGE DIVIDER MODE DNL
vs
SUPPLY VOLTAGE (25°C)
SUPPLY VOLTAGE (25°C)
0.4
0.3
0.3
0.2
0.1
0
5.5 V
5 V
2.7 V
0.2
0.1
-0.1
0
-0.2
-0.3
5.5 V
5 V
2.7 V
-0.1
0
32
64
96
128 160 192 224
0
32
64
96
128 160 192 224
Digital Code
Digital Code
VOLTAGE DIVIDER MODE ZS ERROR
VOLTAGE DIVIDER MODE FS ERROR
vs
vs
TEMPERATURE
TEMPERATURE
4
3
2
0
-1
-2
5.5 V
2.7 V
5 V
5 V
5.5 V
2.7 V
1
0
-3
-4
-40
-15
10
35
60
85
-40
-15
10
35
60
85
T
- Free-Air Temperature - °C
T
- Free-Air Temperature - °C
A
A
10
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SLIS135C –DECEMBER 2010–REVISED JUNE 2012
TYPICAL PERFORMANCE CURVES (continued)
VOLTAGE DIVIDER MODE
RHEOSTAT MODE RINL
vs
vs
DIGITAL CODE
TEMPERATURE (VDD = 5V)
400
300
200
0.4
0.3
0.2
0.1
0
V
= 5 V
DD
T
= 85°C
A
T
T
= 25°C
A
= -40°C
A
2.7 V
5 V
-0.1
100
-0.2
-0.3
5.5 V
0
16
80
144
Digital Code
208
0
32
64
96
128 160 192 224
Digital Code
RHEOSTAT MODE RDNL
vs
RHEOSTAT MODE RINL
vs
TEMPERATURE (VDD = 5V)
SUPPLY VOLTAGE (25°C)
0.6
0.4
0.2
0
0.4
0.2
0
V
= 5 V
T
= 85°C
DD
A
5.5 V
5 V
2.7 V
T
T
= 25°C
A
= -40°C
A
-0.2
-0.4
-0.2
-0.4
0
32
64
96
128 160 192 224
0
32
64
96
128 160 192 224
Digital Code
Digital Code
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TYPICAL PERFORMANCE CURVES (continued)
RHEOSTAT MODE RINL
vs
RHEOSTAT MODE TC
vs
SUPPLY VOLTAGE (25°C)
DIGITAL CODE
0.4
0.2
0
600
500
400
300
200
5.5 V
5 V
2.7 V
2.7 V
5 V
5.5 V
-0.2
-0.4
100
0
16
80
144
Digital Code
208
0
32
64
96
128 160 192 224
Digital Code
RHEOSTAT MODE OFFSET ERROR
vs
TEMPERATURE
WIPER AND TERMINAL RESISTANCE (VDD = 2.7V)
130
5
4
3
2
V
= 2.7 V
DD
120
110
100
90
2.7 V
85°C, LB
85°C, LA
25°C, LB
25°C, LA
80
-40°C, LB
-40°C, LA
70
5 V
60
50
5.5 V
40
85°C, WB
85°C, WA
25°C, WB
25°C, WA
30
-40°C, WB
-40°C, WA
1
0
20
10
0
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
-40
-15
10
35
60
85
V - Input Voltage - V
I
T
- Free-Air Temperature - °C
A
12
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SLIS135C –DECEMBER 2010–REVISED JUNE 2012
TYPICAL PERFORMANCE CURVES (continued)
END-END RESISTANCE CHANGE
vs
WIPER AND TERMINAL RESISTANCE (VDD = 5V)
TEMPERATURE
1.5
1
130
120
110
100
90
V
= 5 V
DD
2.7 V
0.5
0
-40°C, LB
-40°C, LA
85°C, LB
85°C, LA
25°C, LB
25°C, LA
80
5 V
70
5.5 V
60
50
-0.5
-1
40
30
20
25°C, WB
25°C, WA
85°C, WB
85°C, WA
-40°C, WB
-40°C, WA
10
0
0
-1.5
1.5
0.5
1
2
2.5
3
3.5
4
4.5
5
-40
-15
10
35
60
85
V - Input Voltage - V
T
- Free-Air Temperature - °C
I
A
MIDSCALE WIPER GLITCH (CODE 7Fh to 80h)
VDD= 5V, VH= VDD, VL= GND, CLOAD= 10pF
TPOR (POWER-UP RESPONSE TIME)
NON-VOLATILE MEMORY = 40h
2.57
2.56
2.55
2.54
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
VDD
2.53
2.52
Wiper
2.51
2.50
2.46
1.0
0.5
2.48
2.47
0.0
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
10 20 30 40 50 60 70 80 90 100
t - Time - mS
t - Time - mS
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SPI DIGITAL INTERFACE
The TPL0202 uses a 3-wire SPI-compatible serial data interface. This write-only interface has three inputs: chip-
select (CS), data clock (SCLK), and data input (DIN). Drive CS low to enable the serial interface and clock data
synchronously into the shift register on each SCLK rising edge. The WRITE commands (C1, C0 = 00 or 01)
require 16 clock cycles to clock in the command, address, and data. The COPY commands (C1, C0 = 10 or 11)
can use either eight clock cycles to transfer only command and address bits or 16 clock cycles, with the device
disregarding 8 data bits. After loading data into the shift register, drive CS high to latch the data into the
appropriate potentiometer control register and disable the serial interface. Keep CS low during the entire serial
data stream to avoid corruption of the data.
Register Map
CLOCK EDGE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
–
–
C1
C0
–
–
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write Wiper
Register A
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Write Wiper
Register B
Write Wiper
Register A and
B
0
0
0
0
0
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Write NV
Register A
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Write NV
Register B
Write NV
Register A and
B
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
1
1
1
0
D7
–
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
Copy Wiper
Register A to
NV Register A
Copy Wiper
Register B to
NV Register B
–
–
–
–
–
–
–
–
Copy Both
Wiper
Registers to
NV Registers
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Copy NV
Register A to
Wiper Register
A
Copy NV
Register B to
Wiper Register
A
Copy Both NV
Registers to
Wiper
Registers
Digital Interface Format
The data format consists of three elements: command bits, address bits, and data bits. The command bits (C1
and C0) indicate the action to be taken such as changing or storing the wiper position. The address bits (A1 and
A0) specify which potentiometer the command affects and the 8 data bits (D7 to D0) specify the wiper position.
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SLIS135C –DECEMBER 2010–REVISED JUNE 2012
Write-Wiper Register (Command 00)
Data written to the write-wiper registers (C1, C0 = 00) controls the wiper positions. The 8 data bits (D7 to D0)
indicate the position of the wiper. If DIN = 0x00h, the wiper moves to the position closest to the L terminal. If
DIN=0xFFh, the wiper moves to the position closest to the H terminal. This command writes data to the volatile
RAM, leaving the NV registers unchanged. When the device powers up, the data stored in the NV registers
transfers to the volatile wiper register, moving the wiper to the stored position
Write-NV Register (Command 01)
This command (C1, C0 = 01) stores the position of the wipers to the NV registers for use at power-up.
Alternatively, the “copy wiper register to NV register” command can be used to store the position of the wipers to
the NV registers. Writing to the NV registers does not affect the position of the wipers.
Copy Wiper Register to NV Register (Command 10)
This command (C1, C0 = 10) stores the current position of the wiper to the NV register, for use at power-up. This
command may affect one potentiometer at a time, or both simultaneously, depending on the state of A1 and A0.
Alternatively, the “write NV register” command can be used to store the current position of the wiper to the NV
register.
Copy NV Register to Wiper Register (Command 11)
This command (C1, C0 = 11) restores the wiper position to the previously stored position in the NV register. This
command may affect one potentiometer at a time, or both simultaneously, depending on the state of A1 and A0.
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIN
C1
C0
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
A) 16-clock cycle Data Write Sequence
CS
SCLK
DIN
3
5
1
2
4
6
7
8
C1
C0
A1
A0
B) 8-clock cycle Data Move/Copy Sequence
Figure 2. Digital Interface Write Sequence
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CS
tCSW
tCS0
tCS1
tCSS
tSCH
tSCL
tSCP
tCSH
SCLK
DIN
tDS
tDH
Figure 3. Digital Interface Timing Diagram
APPLICATION EXAMPLE
5V
WA
½ TPL0202 to Nullify Offset Voltage
LA
HA
1
7
3
2
VIN
+
8
TLE2027
VOUT
-
4
R1
HB
LB
½ TPL0202 to Adjust Gain
WB
Figure 4. Offset Voltage and Gain Adjustment
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SLIS135C –DECEMBER 2010–REVISED JUNE 2012
IDEAL RESISTANCE VALUES
H
RHW
RWL = RTOT x D/256
RTOT
W
RHW = RTOT x (1 –(D/256))
RWL
Where D = Decimal Value of Wiper Code
Below table shows the ideal values for DPOT with end-to End resistance of 10kΩ. The absolute values of
resistance can vary significantly but the Ratio (Rhw/Rwl) is extremely accurate.
10 kΩ
Step
Binary
RHW/RWL
RHW (kΩ)
0.00
0.39
0.78
1.17
1.56
1.95
2.34
2.73
3.13
3.52
3.91
4.30
4.69
5.08
5.47
5.86
6.25
6.64
7.03
7.42
7.81
8.20
8.59
8.98
9.38
9.77
10.16
10.55
10.94
11.33
11.72
12.11
12.50
RWL (kΩ)
100.00
99.61
99.22
98.83
98.44
98.05
97.66
97.27
96.88
96.48
96.09
95.70
95.31
94.92
94.53
94.14
93.75
93.36
92.97
92.58
92.19
91.80
91.41
91.02
90.63
90.23
89.84
89.45
89.06
88.67
88.28
87.89
87.50
0
0
0.00
0.00
0.01
0.01
0.02
0.02
0.02
0.03
0.03
0.04
0.04
0.04
0.05
0.05
0.06
0.06
0.07
0.07
0.08
0.08
0.08
0.09
0.09
0.10
0.10
0.11
0.11
0.12
0.12
0.13
0.13
0.14
0.14
1
1
2
10
3
11
4
100
5
101
6
110
7
111
8
1000
1001
1010
1011
1100
1101
1110
1111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
100000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
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10 kΩ
Step
Binary
RHW/RWL
RHW (kΩ)
12.89
13.28
13.67
14.06
14.45
14.84
15.23
15.63
16.02
16.41
16.80
17.19
17.58
17.97
18.36
18.75
19.14
19.53
19.92
20.31
20.70
21.09
21.48
21.88
22.27
22.66
23.05
23.44
23.83
24.22
24.61
25.00
25.39
25.78
26.17
26.56
26.95
27.34
27.73
28.13
28.52
28.91
29.30
29.69
30.08
30.47
30.86
31.25
RWL (kΩ)
87.11
86.72
86.33
85.94
85.55
85.16
84.77
84.38
83.98
83.59
83.20
82.81
82.42
82.03
81.64
81.25
80.86
80.47
80.08
79.69
79.30
78.91
78.52
78.13
77.73
77.34
76.95
76.56
76.17
75.78
75.39
75.00
74.61
74.22
73.83
73.44
73.05
72.66
72.27
71.88
71.48
71.09
70.70
70.31
69.92
69.53
69.14
68.75
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
0.15
0.15
0.16
0.16
0.17
0.17
0.18
0.19
0.19
0.20
0.20
0.21
0.21
0.22
0.22
0.23
0.24
0.24
0.25
0.25
0.26
0.27
0.27
0.28
0.29
0.29
0.30
0.31
0.31
0.32
0.33
0.33
0.34
0.35
0.35
0.36
0.37
0.38
0.38
0.39
0.40
0.41
0.41
0.42
0.43
0.44
0.45
0.45
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RHW/RWL
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10 kΩ
Step
Binary
RHW (kΩ)
31.64
32.03
32.42
32.81
33.20
33.59
33.98
34.38
34.77
35.16
35.55
35.94
36.33
36.72
37.11
37.50
37.89
38.28
38.67
39.06
39.45
39.84
40.23
40.63
41.02
41.41
41.80
42.19
42.58
42.97
43.36
43.75
44.14
44.53
44.92
45.31
45.70
46.09
46.48
46.88
47.27
47.66
48.05
48.44
48.83
49.22
49.61
50.00
RWL (kΩ)
81
82
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
10000000
68.36
67.97
67.58
67.19
66.80
66.41
66.02
65.63
65.23
64.84
64.45
64.06
63.67
63.28
62.89
62.50
62.11
61.72
61.33
60.94
60.55
60.16
59.77
59.38
58.98
58.59
58.20
57.81
57.42
57.03
56.64
56.25
55.86
55.47
55.08
54.69
54.30
53.91
53.52
53.13
52.73
52.34
51.95
51.56
51.17
50.78
50.39
50.00
0.46
0.47
0.48
0.49
0.50
0.51
0.51
0.52
0.53
0.54
0.55
0.56
0.57
0.58
0.59
0.60
0.61
0.62
0.63
0.64
0.65
0.66
0.67
0.68
0.70
0.71
0.72
0.73
0.74
0.75
0.77
0.78
0.79
0.80
0.82
0.83
0.84
0.86
0.87
0.88
0.90
0.91
0.92
0.94
0.95
0.97
0.98
1.00
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
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10 kΩ
Step
Binary
RHW/RWL
RHW (kΩ)
50.39
50.78
51.17
51.56
51.95
52.34
52.73
53.13
53.52
53.91
54.30
54.69
55.08
55.47
55.86
56.25
56.64
57.03
57.42
57.81
58.20
58.59
58.98
59.38
59.77
60.16
60.55
60.94
61.33
61.72
62.11
62.50
62.89
63.28
63.67
64.06
64.45
64.84
65.23
65.63
66.02
66.41
66.80
67.19
67.58
67.97
68.36
68.75
RWL (kΩ)
49.61
49.22
48.83
48.44
48.05
47.66
47.27
46.88
46.48
46.09
45.70
45.31
44.92
44.53
44.14
43.75
43.36
42.97
42.58
42.19
41.80
41.41
41.02
40.63
40.23
39.84
39.45
39.06
38.67
38.28
37.89
37.50
37.11
36.72
36.33
35.94
35.55
35.16
34.77
34.38
33.98
33.59
33.20
32.81
32.42
32.03
31.64
31.25
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
10000001
10000010
10000011
10000100
10000101
10000110
10000111
10001000
10001001
10001010
10001011
10001100
10001101
10001110
10001111
10010000
10010001
10010010
10010011
10010100
10010101
10010110
10010111
10011000
10011001
10011010
10011011
10011100
10011101
10011110
10011111
10100000
10100001
10100010
10100011
10100100
10100101
10100110
10100111
10101000
10101001
10101010
10101011
10101100
10101101
10101110
10101111
10110000
1.02
1.03
1.05
1.06
1.08
1.10
1.12
1.13
1.15
1.17
1.19
1.21
1.23
1.25
1.27
1.29
1.31
1.33
1.35
1.37
1.39
1.42
1.44
1.46
1.49
1.51
1.53
1.56
1.59
1.61
1.64
1.67
1.69
1.72
1.75
1.78
1.81
1.84
1.88
1.91
1.94
1.98
2.01
2.05
2.08
2.12
2.16
2.20
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RHW/RWL
www.ti.com
10 kΩ
Step
Binary
RHW (kΩ)
69.14
69.53
69.92
70.31
70.70
71.09
71.48
71.88
72.27
72.66
73.05
73.44
73.83
74.22
74.61
75.00
75.39
75.78
76.17
76.56
76.95
77.34
77.73
78.13
78.52
78.91
79.30
79.69
80.08
80.47
80.86
81.25
81.64
82.03
82.42
82.81
83.20
83.59
83.98
84.38
84.77
85.16
85.55
85.94
86.33
86.72
87.11
87.50
RWL (kΩ)
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
10110001
10110010
10110011
10110100
10110101
10110110
10110111
10111000
10111001
10111010
10111011
10111100
10111101
10111110
10111111
11000000
11000001
11000010
11000011
11000100
11000101
11000110
11000111
11001000
11001001
11001010
11001011
11001100
11001101
11001110
11001111
11010000
11010001
11010010
11010011
11010100
11010101
11010110
11010111
11011000
11011001
11011010
11011011
11011100
11011101
11011110
11011111
11100000
30.86
30.47
30.08
29.69
29.30
28.91
28.52
28.13
27.73
27.34
26.95
26.56
26.17
25.78
25.39
25.00
24.61
24.22
23.83
23.44
23.05
22.66
22.27
21.88
21.48
21.09
20.70
20.31
19.92
19.53
19.14
18.75
18.36
17.97
17.58
17.19
16.80
16.41
16.02
15.63
15.23
14.84
14.45
14.06
13.67
13.28
12.89
12.50
2.24
2.28
2.32
2.37
2.41
2.46
2.51
2.56
2.61
2.66
2.71
2.76
2.82
2.88
2.94
3.00
3.06
3.13
3.20
3.27
3.34
3.41
3.49
3.57
3.65
3.74
3.83
3.92
4.02
4.12
4.22
4.33
4.45
4.57
4.69
4.82
4.95
5.10
5.24
5.40
5.56
5.74
5.92
6.11
6.31
6.53
6.76
7.00
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10 kΩ
Step
Binary
RHW/RWL
RHW (kΩ)
87.89
88.28
88.67
89.06
89.45
89.84
90.23
90.63
91.02
91.41
91.80
92.19
92.58
92.97
93.36
93.75
94.14
94.53
94.92
95.31
95.70
96.09
96.48
96.88
97.27
97.66
98.05
98.44
98.83
99.22
99.61
RWL (kΩ)
12.11
11.72
11.33
10.94
10.55
10.16
9.77
9.38
8.98
8.59
8.20
7.81
7.42
7.03
6.64
6.25
5.86
5.47
5.08
4.69
4.30
3.91
3.52
3.13
2.73
2.34
1.95
1.56
1.17
0.78
0.39
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
11100001
11100010
11100011
11100100
11100101
11100110
11100111
11101000
11101001
11101010
11101011
11101100
11101101
11101110
11101111
11110000
11110001
11110010
11110011
11110100
11110101
11110110
11110111
11111000
11111001
11111010
11111011
11111100
11111101
11111110
11111111
7.26
7.53
7.83
8.14
8.48
8.85
9.24
9.67
10.13
10.64
11.19
11.80
12.47
13.22
14.06
15.00
16.07
17.29
18.69
20.33
22.27
24.60
27.44
31.00
35.57
41.67
50.20
63.00
84.33
127.00
255.00
22
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): TPL0202
TPL0202
www.ti.com
SLIS135C –DECEMBER 2010–REVISED JUNE 2012
REVISION HISTORY
Changes from Revision B (August, 2011) to Revision C
Page
•
•
Updated QFN pin out diagram. ............................................................................................................................................. 1
Updated Pin Description Table. ............................................................................................................................................ 4
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Link(s): TPL0202
PACKAGE OPTION ADDENDUM
www.ti.com
27-Apr-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPL0202-10MRTER
TPL0202-10RUCR
ACTIVE
WQFN
QFN
RTE
RUC
16
14
3000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
PREVIEW
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Apr-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPL0202-10MRTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Apr-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RTE 16
SPQ
Length (mm) Width (mm) Height (mm)
370.0 355.0 55.0
TPL0202-10MRTER
3000
Pack Materials-Page 2
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相关型号：
TPL0202-10RUCR
256-TAPS DUAL CHANNEL DIGITAL POTENTIOMETER WITH SPI INTERFACE AND NONVOLATILE MEMORY
TI
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