TPL5110QDDCRQ1 [TI]
具有手动复位功能和 MOS 驱动器的汽车 AEC-Q100 毫微功耗系统计时器
| DDC | 6 | -40 to 125;
| 型号： | TPL5110QDDCRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有手动复位功能和 MOS 驱动器的汽车 AEC-Q100 毫微功耗系统计时器 | DDC | 6 | -40 to 125 驱动 驱动器 |
| 文件： | 总30页 (文件大小：1925K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPL5110-Q1
ZHCSG15A –FEBRUARY 2017 –REVISED SEPTEMBER 2021
用于电源门控的毫微级功耗系统计时器TPL5110-Q1 AEC-Q100
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
– 器件温度等级1：-40°C 至125°C 环境工作温度
范围
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C5
• 提供功能安全
TPL5110-Q1 毫微级计时器是一种集成了 MOSFET 驱
动器且通过 AEC-Q100 认证的低功耗计时器，非常适
合占空比或电池供电型应用中的电源门控。TPL5110-
Q1 的电流消耗仅为 35nA，可用于支持电源线路，并
大幅降低系统睡眠期间的总待机电流。利用这一节能特
性可以明显缩小电池尺寸，使得 TPL5111 成为能量采
集或无线传感器应用的理想选择。TPL5110-Q1 可提供
100ms 至 7200s 的可选计时间隔，适用于电源门控应
用。此外，TPL5110-Q1 还具有独特的单次触发功能，
计时器可仅在一个周期内为 MOSFET 供电。
TPL5110-Q1 采用6 引脚SOT23 封装。
– 可帮助进行功能安全系统设计的文档
• 电压为2.5V 时，电流消耗为35nA（典型值）
• 电源电压范围为1.8V 至5.5V
• 可选计时间隔：100ms 至7200s
• 计时器精度：1%（典型值）
• 可通过电阻选择时间间隔
• 手动为MOSFET 上电
• 单次触发功能
• TPL5x10Q 系列AEC-Q100 毫微级功耗系统计时
器：
器件信息(1)
封装尺寸（标称值）
器件型号
TPL5110-Q1
封装
SOT23 (6)
3.00mm x 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– TPL5010-Q1：具备可编程延迟范围的看门狗功
能
µC
VOUT
– TPL5110-Q1：具有可编程延迟范围和单次触发
特性的MOS 驱动器
TPL5110-Q1
EN/
ONE_SHOT
VIN
VDD
VDD
Battery
POWER MANAGEMENT
GND
DRV
DELAY/
M_DRV
DONE
GPIO
2 应用
REXT
GND
GND
• 电动汽车
• 电池供电型系统
• 离合器执行器电路
• 车门把手电路
• 智能钥匙
简化版应用原理图
• 远程电流传感器
• 入侵者检测
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS681
TPL5110-Q1
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ZHCSG15A –FEBRUARY 2017 –REVISED SEPTEMBER 2021
Table of Contents
7.4 Device Functional Modes............................................9
7.5 Programming.............................................................11
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 17
9 Power Supply Recommendations................................18
10 Layout...........................................................................19
10.1 Layout Guidelines................................................... 19
10.2 Layout Example...................................................... 19
11 Device and Documentation Support..........................20
11.1 接收文档更新通知................................................... 20
11.2 支持资源..................................................................20
11.3 Trademarks............................................................. 20
11.4 Electrostatic Discharge Caution..............................20
11.5 术语表..................................................................... 20
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Ratings..............................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................7
6.7 Typical Characteristics................................................8
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Feature Description.....................................................9
Information.................................................................... 21
4 Revision History
Changes from Revision * (February 2017) to Revision A (September 2021)
Page
• 向特性部分添加了功能安全要点........................................................................................................................ 1
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Device Comparison Table
表5-1. TPL5x10Q Family of AEC-Q100 Nano- Power System Timers
PART NUMBER
SUPPLY CURRENT (Typ)
SPECIAL FEATURES
Low Power Timer
Watchdog Function
Programmable Delay Range
Manual Reset
TPL5010-Q1
35 nA
Low Power Timer
MOS-Driver
TPL5110-Q1
35 nA
Programmable Delay Range
Manual Reset
One-Shot Feature
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5 Pin Configuration and Functions
TPL5110-Q1
EN/
ONE_SHOT
1
2
3
VDD
6
5
4
GND
DRV
DELAY/
M_DRV
DONE
图5-1. SOT-23 6-Lead DDC Top View
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
APPLICATION INFORMATION
NO.
1
NAME
VDD
P
G
I
Supply voltage
Ground
2
GND
3
DELAY/
M_DRV
Time interval set and manual
MOSFET Power ON
Resistance between this pin and GND is used to
select the time interval. The manual MOSFET power
ON switch is also connected to this pin.
4
5
6
DONE
DRV
I
O
I
Logic Input for watchdog
functionality
Digital signal driven by the µC to indicate successful
processing.
Power Gating output signal
generated every tIP
The Gate of the MOSFET is connected to this pin.
When DRV = LOW, the MOSFET is ON.
EN/
ONE_SHOT
Selector of mode of operation
When EN/ONE_SHOT = HIGH, the TPL5110-Q1
works as a TIMER. When EN/ONE_SHOT = LOW,
the TPL5110-Q1 turns on the MOSFET one time for
the programmed time interval. The next power on of
the MOSFET is enabled by the manual power ON.
(1) G= Ground, P= Power, O= Output, I= Input.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-5
MAX
6.0
UNIT
V
Supply voltage (VDD-GND)
Input voltage at any pin(3)
Input Current on any pin
Storage temperature, Tstg
Junction temperature, TJ(2)
VDD + 0.3
+5
V
mA
°C
-65
150
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC
board.
(3) The voltage between any two pins should not exceed 6V.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human Body Model, per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JADEC JS-001 specification.
6.3 Recommended Operating Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
MAX
5.5
UNIT
V
Supply Voltage (VDD-GND)
Temperature Range
125
°C
–40
6.4 Thermal Information
TPL5110-Q1
THERMAL METRIC(1)
SOT-23
6 PINS
163
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
26
57
Junction-to-top characterization parameter
Junction-to-board characterization parameter
7.5
57
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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MAX(2) UNIT
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6.5 Electrical Characteristics
Specifications are for TA= 25°C, VDD-GND=2.5 V, unless otherwise stated.(1)
PARAMETER
TEST CONDITIONS
MIN(2)
TYP(3)
POWER SUPPLY
IDD
Supply current(4)
Operation mode
35
50
nA
µA
Digital conversion of external resistance
(Rext)
200
400
TIMER
tIP
Time interval Period(5)
1650 selectable Time Min time interval
100
7200
±0.6%
±25
ms
s
intervals
Max time interval
Time interval Setting Accuracy(7)
Excluding the precision of Rext
Time interval Setting Accuracy over
supply voltage
ppm/V
1.8V ≤VDD ≤5.5V
tOSC
Oscillator Accuracy
0.5%
–0.5%
Oscillator Accuracy over
temperature(5)
150
ppm/°C
%/V
–40°C ≤TA≤125°C
1.8V ≤VDD ≤5.5V
Oscillator Accuracy over supply
voltage(5)
±0.4
Oscillator Accuracy over life time(6)
Minimum DONE Pulse width (5)
DRV Pulse width
±0.24%
100
tDONE
tDRV
ns
DONE signal not received
tIP–
50ms
t_Rext
Time to convert Rext (5)
100
ms
DIGITAL LOGIC LEVELS
VIH
Minimum Logic High Threshold
DONE pin
0.7xVDD
0.3xVDD
V
V
VIL
Maximum Logic Low Threshold
DONE pin
Iout = 100 µA
Iout = 1 mA
V
V
V
V
V
VDD–0.3
VDD–0.7
VOH
Logic output High Level DRV pin
Logic output Low Level DRV pin
0.3
0.7
Iout = –100 µA
Iout = –1 mA
VOL
VIHM_DRV
Minimum Logic High Threshold
DELAY/M_DRV pin (5)
1.5
(1) Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the
electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits
beyond which the device may be permanently degraded, either mechanically or electrically.
(2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through
correlations using statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(4) The supply current excludes load and pull-up resistor current. Input pins are at GND or VDD.
(5) This parameter is specified by design and/or characterization and is not tested in production.
(6) Operational life time test procedure equivalent to10 years.
(7) The accuracy for time interval settings below 1second is ±100ms.
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6.6 Timing Requirements
MIN(3)
NOM(4)
50
MAX(3) UNIT
trDRV
tfDRV
Rise Time DRV(2)
Fall Time DRV(2)
DONE to DRV delay
Capacitive load 50 pF
Capacitive load 50 pF
Min delay(1)
ns
ns
ns
50
tDDONE
100
tDRV
20
Max delay (1)
tM_DRV
tDB
Minimum Valid manual MOSFET
Power ON
Observation time 30ms
ms
ms
De-bounce manual MOSFET Power
ON
20
(1) from DRV falling edge.
(2) This parameter is specified by design and/or characterization and is not tested in production.
(3) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through
correlations using statistical quality control (SQC) method.
(4) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
VDD
EN/
ONE_SHOT
ttDDONE
t
tDONE
DONE
t tDRV
t
t tDRV + tDBt
trDRV
t tIPt
DRV
tfDRV
t tIP
t
tR_EXT
DELAY/
M_DRV
ttM_DRV
图6-1. TPL5110-Q1 Timing
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6.7 Typical Characteristics
100
100
90
80
70
60
50
40
30
20
TA= -40°C
TA= 25°C
VDD= 1.8V
VDD= 2.5V
VDD= 3.3V
VDD= 5.5V
90
80
70
60
50
40
30
20
TA= 70°C
TA= 105°C
TA = 125°C
1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-40
-25
-10
5
20
35
50
65
80
95
110
125
Supply Voltage (V)
D00
Temperature (°C)
.
.
图6-2. IDD vs. VDD
图6-3. IDD vs. Temperature
2
1.5
1
2
1.5
1
TA= -40°C
VDD= 1.8V
VDD= 2.5V
VDD= 3.3V
VDD= 5.5V
TA= 25°C
TA= 70°C
TA= 105°C
TA= 125°C
0.5
0
0.5
0
-0.5
-1
-0.5
-1
1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-40
-25
-10
5
20
35
50
65
80
95
110
125
Supply Voltage (V)
Temperature (°C)
A.
.
.
图6-4. Oscillator Accuracy vs. VDD
图6-5. Oscillator Accuracy vs. Temperature
1000
100
10
40%
35%
30%
25%
20%
15%
10%
5%
POR
REXT READING
1
TIMER MODE
0.1
0.01
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
Time (s)
Accuracy (%)
.
.
number of observations >20000
1s < tIP ≤7200s
图6-7. Time Interval Setting Accuracy
图6-6. IDD vs. Time
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7 Detailed Description
7.1 Overview
The TPL5110-Q1 is a timer with power gating feature. It is ideal for use in power-cycled applications and
provides selectable timing from 100ms to 7200s.
Once configured in timer mode (EN/ONE_SHOT= HIGH) the TPL5110-Q1 periodically sends out a DRV signal to
a MOSFET to turn on the µC. If the µC replies with a DONE signal within the programmed time interval (tDRV) the
TPL5110-Q1 turns off the µC, otherwise the TPL5110-Q1 keeps the µC in the on state for a time equal to tDRV
.
The TPL5110-Q1 can work also in a one-shot mode (EN/ONE_SHOT= LOW). In this mode the DRV signal is
sent out just one time at the power on of the TPL5110-Q1 to turn on the µC. If the µC replies with a DONE signal
within the programmed time interval (tDRV) the TPL5110-Q1 turns off the µC, otherwise the TPL5110-Q1 keeps
the µC in the on state for a time equal to tDRV
.
7.2 Functional Block Diagram
VDD
EN/
ONE_SHOT
LOW FREQUENCY
OSCILLATOR
FREQUENCY
DIVIDER
LOGIC
CONTROL
DRV
DONE
DELAY/
M_DRV
DECODER
&
MANUAL RESET
DETECTOR
GND
7.3 Feature Description
The TPL5110-Q1 implements a periodical power gating feature or one shot power gating according to the EN/
ONE_SHOT voltage. A manual MOSFET Power ON function is realized by momentarily pulling the DELAY/
M_DRV pin to VDD.
7.3.1 DRV
The gate of the MOSFET is connected to the DRV pin. When DRV= LOW, the MOSFET is turned ON. The pulse
generated at DRV is equal to the selected time interval period, minus 50ms. It is shorter in the case of a DONE
signal received from the µC. If the DONE signal is not received within the programmed time interval (minus
50ms), the DRV signal will be high for the last 50ms of the time interval in order to turn off the MOSFET before
the next cycle starts.
The default value (after resistance reading) is HIGH. The signal is sent out from the TPL5110-Q1 when the
programmed time interval starts. When the DRV is LOW, the manual power ON signal is ignored.
7.3.2 DONE
The DONE pin is driven by a µC to signal that the µC is working properly. The TPL5110-Q1 recognizes a valid
DONE signal as a low to high transition; if two or more DONE signals are received within the time interval, only
the first DONE signal is processed. The minimum DONE signal pulse length is 100ns. When the TPL5110-Q1
receives the DONE signal it asserts DRV logic HIGH.
7.4 Device Functional Modes
7.4.1 Start-Up
During start-up, after POR, the TPL5110-Q1 executes a one-time measurement of the resistance attached to the
DELAY/M_DRV pin in order to determine the desired time interval for DRV. This measurement interval is tR_EXT
.
During this measurement a constant current is temporarily flowing into REXT
.
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Once the reading of the external resistance is completed the TPL5110-Q1 enters automatically in one of the 2
modes according to the EN/ONE_SHOT value. The EN/ONE_SHOT pin must be hard wired to GND or VDD
according to the required mode of operation.
ttIPt
ttIPt
ttDRV
t
FORCED
DRV RISING
DRV
MISSED
DONE
DONE
EN/
ONE_SHOT
DELAY/
M_DRV
RESISTANCE
READING
POR
图7-1. Start-Up - Timer Mode
7.4.2 Timer Mode
During timer mode (EN/ONE_SHOT = HIGH), the TPL5110-Q1 asserts periodic DRV pulses according to the
programmed time interval. The length of the DRV pulses is set by the receiving of a DONE pulse from the uC.
See 图7-1.
7.4.3 One-Shot Mode
During one-shot mode (EN/ONE_SHOT = LOW), the TPL5110-Q1 generates just one pulse at the DRV pin
which lasts according to the programmed time interval. In one-shot mode, other DRV pulses can be triggered
using the DELAY/M_DRV pin. If a valid manual power ON occurs when EN/ONE_SHOT is LOW, the TPL5110-
Q1 generates just one pulse at the DRV pin. The duration of the pulse is set by the programmed time interval.
Also in this case, if a DONE signal is received within the programmed time interval (minus 50ms), the MOSFET
connected to the DRV pin is turned off. See 图7-2 and 图7-3.
ttIP
t
DRV
DONE
EN/
ONE_SHOT
DELAY/
M_DRV
RESISTANCE
READING
POR
图7-2. Start-Up One-Shot Mode, (DONE Received Within tIP)
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ttIPt
ttDRV
t
FORCED
DRV RISING
DRV
MISSED
DONE
DONE
EN/
ONE_SHOT
DELAY/
M_DRV
RESISTANCE
READING
POR
图7-3. Start-Up One-Shot Mode, (No DONE Received Within tIP)
7.5 Programming
7.5.1 Configuring the Time Interval with the DELAY/M_DRV Pin
The time interval between 2 adjacent DRV pulses (falling edges, in timer mode) is selectable through an external
resistance (REXT) between the DELAY/M_DRV pin and ground. The resistance (REXT) must be in the range
between 500Ωand 170kΩ. At least a 1% precision resistance is recommended. See section 节 7.5.3 on how to
set the time interval using REXT
.
7.5.2 Manual MOSFET Power ON Applied to the DELAY/M_DRV Pin
If VDD is connected to the DELAY/M_DRV pin, the TPL5110-Q1 recognizes this as a manual MOSFET Power
ON condition. In this case the time interval is not set. If the manual MOSFET Power ON is asserted during the
POR or during the reading procedure, the reading procedure is aborted and is re-started as soon as the manual
MOSFET Power ON switch is released. A pulse on the DELAY/M_DRV pin is recognized as a valid manual
MOSFET Power ON only if it lasts at least 20ms (observation time is 30ms). The manual MOSFET Power ON
may be implemented using a switch (momentary mechanical action).
If the DRV is already LOW (MOSFET ON) the manual MOSFET Power ON is ignored.
ttIPt
ttIPt
DRV
DONE
EN/
ONE_SHOT
ttM_DRV
t
ttM_DRV
t
ttDB
t
ttM_DRVt
DELAY/
M_DRV
IGNORED M_DRV
DRV ALREADY LOW
VALID M_DRV
NOT VALID M_DRV
图7-4. Manual MOSFET Power ON in Timer Mode
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ttIPt
DRV
DONE
EN/
ONE_SHOT
ttM_DRV
t
ttDB
t
ttM_DRVt
DELAY/
M_DRV
VALID M_DRV
NOT VALID M_DRV
图7-5. Manual MOSFET Power ON in One-Shot Mode
7.5.2.1 DELAY/M_DRV
A resistance in the range between 500Ωand 170kΩmust to be connected to the DELAY/M_DRV pin in order to
select a valid time interval. At the POR and during the reading of the resistance, the DELAY/M_DRV is
connected to an analog signal chain through a mux. After the reading of the resistance, the analog circuit is
switched off and the DELAY/M_DRV is connected to a digital circuit.
In this state, a logic HIGH applied to the DELAY/M_DRV pin is interpreted by the TPL5110-Q1 as a manual
power ON. The manual power ON detection is provided with a de-bounce feature (on both edges) which makes
the TPL5110-Q1 insensitive to the glitches on the DELAY/M_DRV.
The M_DRV must stay high for at least 20ms to be valid. Once a valid signal at DELAY/M_DRV is understood as
a manual power on, the DRV signal will be asserted in the next 10ms. Its duration will be according to the
programmed time interval (minus 50ms), or less if the DONE is received.
A manual power ON signal resets all the counters. The counters will restart as soon as a valid manual power ON
signal is recognized and the signal at DELAY/M_DRV pin is asserted LOW. Due to the asynchronous nature of
the manual power ON signal and its arbitrary duration, the LOW status of the DRV signal may be affected by an
uncertainty of about ±5ms.
An extended assertion of a logic HIGH at the DELAY/M_DRV pin will turn on the MOSFET for a time longer than
the programmed time interval. DONE signals received while the DELAY/M_DRV is HIGH are ignored. If the DRV
is already LOW (MOSFET ON) the manual power ON is ignored.
7.5.2.2 Circuitry
The manual Power ON may be implemented using a switch (momentary mechanical action). The TPL5110-Q1
offers 2 possible approaches according to the power consumption constraints of the application.
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µC
VOUT
VIN
TPL5110-Q1
EN/
ONE_SHOT
VDD
VDD
Battery
POWER MANAGEMENT
GND
DRV
DELAY/
M_DRV
DONE
GPIO
REXT
GND
GND
图7-6. Manual MOSFET Power ON with SPST Switch
For use cases that do not require the lowest power consumption, using a single pole single throw switch may
offer a lower cost solution. The DELAY/M_DRV pin may be directly connected to VDD with REXT in the circuit.
The current drawn from the supply voltage during the manual power ON is given by VDD/REXT
.
µC
VOUT
TPL5110-Q1
EN/
ONE_SHOT
VIN
VDD
VDD
Battery
POWER MANAGEMENT
GND
DRV
DELAY/
M_DRV
DONE
GPIO
REXT
GND
GND
图7-7. Manual MOSFET Power ON with SPDT Switch
The manual MOSFET Power ON function may also be asserted by switching DELAY/M_DRV from REXT to VDD
using a single pole double throw switch, which will provide a lower power solution for the manual power ON,
because no current flows.
7.5.3 Selection of the External Resistance
In order to set the time interval, the external resistance REXT is selected according the following formula:
2
≈
∆
’
÷
- b + b - 4a
2a
(
c -100 T
)
REXT =100
∆
«
÷
◊
(1)
Where:
• T is the desired time interval in seconds.
• REXT is the resistance value to use in Ω.
• a,b,c are coefficients depending on the range of the time interval.
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表7-1. Coefficients for 方程式1
Time Interval
Range (s)
SET
a
b
c
1
2
3
4
5
0.2253
-0.1284
0.1972
0.2617
0.3177
-20.7654
46.9861
570.5679
-2651.8889
692.1201
1 <T≤5
5 <T≤10
-19.3450
-56.2407
-136.2571
10 <T≤100
100 <T≤1000
T> 1000
5957.7934
34522.4680
EXAMPLE
Required time interval: 8s
The coefficient set to be selected is the number 2. The formula becomes
2
≈
’
÷
46.9861- 46.9861 +4*0.1284
(
-2561.8889-100*8
)
∆
REXT =100
∆
«
÷
2*0.1284
◊
(2)
The resistance value is 10.18 kΩ.
The following Look-Up-Tables contain example values of tIP and their corresponding value of REXT
.
表7-2. First 9 Time Intervals
Parallel of two 1% tolerance resistors,
tIP (ms)
Resistance (Ω)
Closest real value (Ω)
(kΩ)
100
200
300
400
500
600
700
800
900
500
500
1.0 // 1.0
-
1000
1500
2000
2500
3000
3500
4000
4500
1000
1500
2000
2500
3000
3500
4000
4501
2.43 // 3.92
-
4.42 // 5.76
5.36 // 6.81
4.75 // 13.5
6.19 // 11.3
6.19 // 16.5
表7-3. Most Common Time Intervals Between 1s to 2h
Closest Real Value
Parallel of Two 1% Tolerance Resistors,
tIP
Calculated Resistance (kΩ)
(kΩ)
(kΩ)
1s
2s
5.20
6.79
5.202
6.788
7.628
8.306
8.852
9.223
9.673
10.180
10.68
11.199
14.405
16.778
18.748
7.15 // 19.1
12.4 // 15.0
12.7// 19.1
14.7 // 19.1
16.5 // 19.1
18.2 // 18.7
19.1 // 19.6
11.5 // 8.87
17.8 // 26.7
15.0 // 44.2
16.9 // 97.6
32.4 // 34.8
22.6 // 110.0
3s
7.64
4s
8.30
5s
8.85
6s
9.27
7s
9.71
8s
10.18
10.68
11.20
14.41
16.78
18.75
9s
10s
20s
30s
40s
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表7-3. Most Common Time Intervals Between 1s to 2h (continued)
Closest Real Value
Parallel of Two 1% Tolerance Resistors,
Calculated Resistance (kΩ)
(kΩ)
(kΩ)
50s
1min
2min
3min
4min
5min
6min
7min
8min
9min
10min
20min
30min
40min
50min
1h
20.047
22.02
29.35
34.73
39.11
20.047
22.021
29.349
34.729
39.097
42.887
46.301
49.392
52.224
54.902
57.437
77.579
92.233
104.625
115.331
124.856
149.398
170.00
28.7 // 66.5
40.2 // 48.7
35.7 // 165.0
63.4 // 76.8
63.4 // 102.0
54.9 // 196.0
75.0 // 121.0
97.6 // 100.0
88.7 // 127.0
86.6 // 150.0
107.0 // 124.0
140.0 // 174.0
182.0 // 187.0
130.0 // 536.00
150.0 // 499.00
221.0 // 287.00
165.0 // 1580.0
340.0 // 340.0
42.90
46.29
49.38
52.24
54.92
57.44
77.57
92.43
104.67
115.33
124.91
149.39
170.00
1h30min
2h
7.5.4 Quantization Error
The TPL5110-Q1 can generate 1650 discrete timer intervals in the range of 100ms to 7200s. The first 9 intervals
are multiples of 100ms. The remaining 1641 intervals cover the range between 1s to 7200s. Because they are
discrete intervals, there is a quantization error associated with each value.
The quantization error can be evaluated according to the following formula:
(
TDESIRED -TADC
)
Err =100
TDESIRED
(3)
Where:
»
…
ÿ
Ÿ
⁄
≈
’
1
R D2
R D
∆
∆
÷
÷
T ADC = INT
a
+ b
+ c
2
100
100
100
«
◊
(4)
(5)
R
»
ÿ
EXT
R D = INT
…
Ÿ
⁄
100
REXT is the resistance calculated with 方程式1 and a,b,c are the coefficients of the equation listed in 表7-1.
7.5.5 Error Due to Real External Resistance
REXT is a theoretical value and may not be available in standard commercial resistor values. It is possible to
closely approach the theoretical REXT using two or more standard values in parallel. However, standard values
are characterized by a certain tolerance. This tolerance will affect the accuracy of the time interval.
The accuracy can be evaluated using the following procedure:
1. Evaluate the min and max values of REXT (REXT_MIN, REXT_MAX with 方程式1 using the selected commercial
resistance values and their tolerances.
2. Evaluate the time intervals (TADC_MIN[REXT_MIN], TADC_MAX[REXT_MAX]) with 方程式4.
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3. Find the errors using 方程式3 with TADC_MIN, TADC_MAX
.
The results of the formula indicate the accuracy of the time interval.
The example below illustrates the procedure.
• Desired time interval , T_desired = 600s,
• Required REXT, from 方程式1, REXT= 57.44kΩ.
From 表 7-3, REXT can be built with a parallel combination of two commercial values with 1% tolerance:
R1=107kΩ, R2=124kΩ. The uncertainty of the equivalent parallel resistance can be found using:
2
2
u
u
R2
≈
∆
’
÷
≈
∆
’
÷
R1
uR =R//
+
//
R1
R2
«
◊
«
◊
(6)
(7)
Where uRn (n=1,2) represent the uncertainty of a resistance,
Tolerance
uR =Rn
n
3
The uncertainty of the parallel resistance is 0.82%, meaning the value of REXT may range between REXT_MIN
56.96 kΩand REXT_MAX = 57.90 kΩ.
=
=
Using these value of REXT, the digitized timer intervals calculated with 方程式 4 are respectively TADC_MIN
586.85 s and TADC_MAX = 611.3 s, giving an error range of -1.88% / +2.19%. The asymmetry of the error range is
due to the quadratic transfer function of the resistance digitizer.
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8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
In battery powered applications one design constraint is the need for low current consumption. The TPL5110-Q1
is suitable in applications where there is a need to monitor environmental conditions at a fixed time interval.
Often in these applications a watchdog or other internal timer in a µC is used to implement a wakeup function.
Typically, the power consumption of these functions is not optimized. Using the TPL5110-Q1 to implement a
periodical power gating of the µC or of the entire system the current consumption will be only tens of nA.
8.2 Typical Application
The TPL5110-Q1 can be used in environment sensor nodes such as humidity and temperature sensor node.
The sensor node has to measure the humidity and the temperature and transmit the data through a low power
RF micro such as the CC2531. Since the temperature and the humidity in home application do not change so
fast, the measurement and the transmission of the data can be done at very low rate, such as every 30 seconds.
The RF micro should spend most of the time in counting the elapsed time, but using the TPL5110-Q1 it is
possible to complete turn off the RF micro and extend the battery life. The TPL5110-Q1 will turn on the RF micro
when the programmed time interval elapses or for debug purpose with the manual MOSFET Power ON switch.
DC-DC
BOOST
VIN
VOUT
ENB
GND
CC2531
Rp
100k
Rp
100k
RF
TPL5110-Q1
EN/
ONE_SHOT
HDC1000
VDD
VDD
VDD
GND
DRV
SCL
SDA
GND
SCL
+
DELAY/
M_DRV
Lithium
ion battery
DONE
GPIO
SDA
GND
-
图8-1. Sensor Node
8.2.1 Design Requirements
The Design is driven by the low current consumption constraint. The data are usually acquired on a rate which is
in the range between 30s and 60s. The highest necessity is the maximization of the battery life. The TPL5110-
Q1 helps achieve this goal because it allows turning off the RF micro.
8.2.2 Detailed Design Procedure
When the focal constraint is the battery life, the selection of a low power voltage regulator and low leakage
MOSFET to power gate the µC is mandatory. The first step in the design is the calculation of the power
consumption of each device in the different mode of operations. An example is the HDC1000, in measurement
mode the RF micro is in normal operation and transmission. The different modes offer the possibility to select the
appropriate time interval which respect the application constraint and maximize the life of the battery.
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8.2.3 Application Curve
Without TPL5110-Q1
With TPL5110-Q1
Time
图8-2. Effect of TPL5110-Q1 on Current Consumption
9 Power Supply Recommendations
The TPL5110-Q1 requires a voltage supply within 1.8 V and 5.5 V. A multilayer ceramic bypass X7R capacitor of
0.1μF between VDD and GND pin is recommended.
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10 Layout
10.1 Layout Guidelines
The DELAY/M_DRV pin is sensitive to parasitic capacitance. It is suggested that the traces connecting the
resistance on this pin to GROUND be kept as short as possible to minimize parasitic capacitance. This
capacitance can affect the initial set up of the time interval. Signal integrity on the DRV pin is also improved by
keeping the trace length between the TPL5110-Q1 and the gate of the MOSFET short to reduce the parasitic
capacitance. The EN/ONE_SHOT needs to be tied to GND or VDD with short traces.
10.2 Layout Example
图10-1. Layout
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11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
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提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPL5110QDDCRQ1
TPL5110QDDCTQ1
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
13ZX
13ZX
Samples
Samples
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2022
OTHER QUALIFIED VERSIONS OF TPL5110-Q1 :
Catalog : TPL5110
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPL5110QDDCRQ1
TPL5110QDDCTQ1
SOT-
23-THIN
DDC
DDC
6
6
3000
250
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
23-THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPL5110QDDCRQ1
TPL5110QDDCTQ1
SOT-23-THIN
SOT-23-THIN
DDC
DDC
6
6
3000
250
208.0
208.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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