TPS1641 [TI]
具有输出功率限制功能的 2.7V 至 40V、152mΩ、1.8A 电子保险丝;
| 型号： | TPS1641 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有输出功率限制功能的 2.7V 至 40V、152mΩ、1.8A 电子保险丝 电子 |
| 文件： | 总39页 (文件大小：2888K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS1641
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
TPS1641x 具有输入至输出短路检测功能的40V、1.8A 功率和
电流限制型电子保险丝
1 特性
3 说明
• 工作电压范围(IN)：
TPS1641x 系列是具有精确功率限值或电流限值的集成
电子保险丝器件。该器件系列通过集成的过流保护、过
压保护、输入至输出短路检测和过热保护提供强大的保
护功能。
– 4.5V 至40V（功率限制器件）
– 2.7V 至40V（电流限制器件）
• 输出端可耐受高达-1V 的负电压
• 超低导通电阻：RON = 152mΩ（典型值）
• 2W 至64W 功率限制
TPS16410、TPS16411、TPS16414 和 TPS16415 器
件在 15W 下为负载提供 ±5% 的功率限制，并且还针
对瞬态过载或过流事件提供可配置的消隐时间。
TPS16410、TPS16411、TPS16414 和 TPS16415 可
用于低功耗电路 (LPC)，从而实现符合 IEC60335 和
UL60730 标准的 15W 功率限制。TPS1641x 器件可针
对相邻引脚短路和引脚短路到GND 故障提供保护。
• 0.03A 至1.8A 电流限制
• FLT 引脚上的IN 到OUT 短路检测和指示
• 用于诊断和驱动外部PFET 的FLT 输出
• 15W 时±5% 精确功率限制（功率限制器件）
• 1A 时±6% 精确电流限制（电流限制器件）
• 可配置的过压保护
PLC 和 DCS 模块中的背板电源保护等应用通过 ILIM
引脚上的电阻器配置电流限制。TPS16412 、
TPS16413、TPS16416 和 TPS16417 器件在 1A 时为
负载提供 ±6% 的电流限制，而且还通过 dVdT 引脚提
供输出压摆率控制，以便在上电时为大容性负载充电。
• 可配置过流保护(IOCP
)
• 可针对瞬态电流配置消隐时间
• 通过外部FET 提供高达60V 的过压保护
• 可调节输出压摆率控制(dVdt)，用于提供浪涌电流
保护
• 使能和关断控制
TPS1641x 具有输入至输出短路检测功能，并会在 FLT
引脚上指示输入至输出短路。FLT 引脚既可作为数字输
入提供给MCU，也可用于驱动外部PFET。
• IOCP 引脚上的输出负载电流监控
• 具有热关断功能的过热保护(OTP)
• 小尺寸: QFN 3 × 3mm，0.5mm 间距
此类器件的额定工作结温范围为–40°C 至+125°C。
2 应用
封装信息
封装(1)
• 冰箱和冷冻柜
• 烤箱
• 洗碗机
封装尺寸（标称值）
器件型号
TPS1641x
VSON (10)
3.00mm × 3.00mm
• HVAC 阀门和传动器控制
• 呼吸机
• 麻醉给药系统
(1) 有关所有的可用封装，请参阅数据表末尾的可订购产品附录。
Configurable Blanking time and
magnuitude for Transient Loads
Vcc
VOUT
OUT
tPDLYt
IN
COUT
CIN
PLIM
152 m
POUT
TPS1641x
EN/SHDN
FLT
IOCP
IOCP/IMON
PDLY/IDLY
PLIM/ILIM
OVP
IOUT = PLIM/VOUT
IOUT
ROCP
dVdT
GND
CDLY
RPLIM
PDLY = Duration of Transient Load
IOCP = Maximum magnitude of Transient Load
可针对瞬态负载配置消隐时间
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
Table of Contents
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Typical Application: 15-W Power Limiting for
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements..................................................8
7.7 Typical Characteristics................................................9
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................13
Low Power Circuits (LPCs)......................................... 23
9.3 System Examples..................................................... 26
9.4 Best Design Practices...............................................27
9.5 Power Supply Recommendations.............................27
9.6 Layout....................................................................... 28
10 Device and Documentation Support..........................30
10.1 接收文档更新通知................................................... 30
10.2 支持资源..................................................................30
10.3 Trademarks.............................................................30
10.4 静电放电警告.......................................................... 30
10.5 术语表..................................................................... 30
11 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2022) to Revision B (April 2023)
Page
• 在整个文档中添加了有关新器件型号的信息....................................................................................................... 1
• Added recommendations for new device variants............................................................................................19
Changes from Revision * (June 2022) to Revision A (December 2022)
Page
• 将器件状态从预告信息 更改为量产数据 ............................................................................................................ 1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
2
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
5 Device Comparison Table
Part Number
Power or Current Limit
Fault Behavior
IN-OUT Short
Detection
TPS16410
TPS16411
TPS16412
TPS16413
TPS16414
TPS16415
TPS16416
TPS16417
Power limit
Power limit
Current limit
Current limit
Power limit
Power limit
Current limit
Current limit
Auto-retry
Latch-off
Auto-retry
Latch-off
Auto-retry
Latch-off
Auto-retry
Latch-off
Y
Y
Y
Y
N
N
N
N
See IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413) section for recommended
device variants.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
6 Pin Configuration and Functions
10
1
10
IN
OUT
IN
1
OUT
Vcc
OVP
Vcc
OVP
IOCP/IMON
IOCP/IMON
PowerPADTM
GND
PowerPADTM
GND
PLIM
dVdT
PDLY
ILIM
dVdT
IDLY
FLT
FLT
6
EN/SHDN
5
6
EN/SHDN
5
TPS16412, TPS16413,
TPS16416, TPS16417
TPS16410, TPS16411,
TPS16414, TPS16415
图6-2. TPS16412, TPS16413, TPS16416 and
图6-1. TPS16410, TPS16411, TPS16414 and
TPS16417 10-Pin DRC VSON Package (Top View)
TPS16415 10-Pin DRC VSON Package (Top View)
表6-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
1
IN
P
P
I
Power input for internal FET.
Vcc
OVP
2
Supply input for internal circuits of the device.
3
Overvoltage protection input. This pin can be connected to GND for disabling OVP.
Active low fault output. See the FLT Pin Indication for Different Events section for different
FLT pin indications.
FLT
4
5
O
I
EN/SHDN
PDLY
Enable or shutdown input.
TPS16410, TPS16411: Input for blanking time for power limiting. Connect a capacitor to
set PDLY blanking time.
6
I/O
TPS16412, TPS16413: Input for blanking time for current limiting. Connect a capacitor to
set IDLY blanking time.
IDLY
Output slew control input. Connect a capacitor to set the output slew rate. If not used, this
pin can be left open.
dVdT
7
8
I/O
I/O
PLIM
ILIM
TPS16410, TPS16411: Power limit input. Connect a resistor to set PLIM setpoint.
TPS16412, TPS16413: Current limit input. Connect a resistor to set ILIM setpoint.
Overcurrent protection input and current monitoring output for output current. Output
current can be sensed by reading voltage on this pin. Connect a resistor to set IOCP set-
point and for reading output current.
IOCP/IMON
OUT
9
I/O
P
10
Power output from internal FET.
GND connection for the device.
PowerPAD™ must be connected to GND of input power supply.
PowerPAD/GND
G
—
Connect PowerPAD to GND plane on PCB using multiple vias for enhanced thermal
performance.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
4
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
67
UNIT
V
Vcc, FLT
OVP
Input Voltage
Input Voltage
62
V
IN, IN-OUT,
IOCP
Input Voltage
Input Voltage
Input Voltage
42
42
V
V
V
–0.3
–1
OUT
EN/SHDN,
PDLY/IDLY
5.5
–0.3
dVdT, PLIM/
ILIM
Input Voltage
5.5
V
–0.3
IIOCP,IPDLY,IPLIM
IdVdT, IILIM
,
Internally
Limited
Source Current
Junction temperature
150
TTSD
150
°C
°C
°C
–40
–40
–65
TJ
Transient Junction Temperature
Storage temperature
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±1500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
0
NOM
MAX
60
UNIT
Vcc
FLT
IN
Supply voltage
V
V
V
V
V
Input Voltage
60
Input Voltage (TPS16410, TPS16411, TPS16414, TPS16415)
Input Voltage (TPS16412, TPS16413, TPS16416, TPS16417)
Input Voltage
4.5
2.7
0
40
IN
40
OUT
40
EN/SHDN,
OVP
Input Voltage
0
5.5
V
PDLY/IDLY External capacitor
0.012
0.01
6.34
12.4
5.1
10
5
µF
µF
kΩ
kΩ
kΩ
dVdT
IOCP
PLIM
ILIM
External capacitor
External resistor
External resistor
External resistor
80.6
412
348
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
7.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
125
UNIT
TJ
Junction temperature
°C
–40
7.4 Thermal Information
TPS1641
THERMAL METRIC(1)
DRC (VSON)
10 PINS
43.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
50.0
15.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.1
ΨJT
15.8
ΨJB
RθJC(bot)
2.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
–40°C ≤TA = TJ ≤+125°C, VIN = 3 V to 40 V (TPS16412, TPS16413, TPS16416, TPS16417), VIN = 4.5 V to 40 V
(TPS16410, TPS16411, TPS16414, TPS16415), Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open,
COUT = 100 nF, CIN = 10 nF CdVdT = Open, PDLY/IDLY = Open. , EN/SHDN = Open
(Allvoltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING INPUT AND SUPPLY VOLTAGE
Vcc
VIN
Operating Supply voltage
Operating Input voltage
VIN
4.5
60
40
V
V
TPS16410, TPS16411,
TPS16414 ,TPS16415
TPS16412, TPS16413, TPS16416,
TPS16417
VIN
IQ
Operating Input voltage
2.7
40
V
EN/SHDN = 2 V, Vcc = 40 V, VIN = Open,
RILIM or RPLIM = Open
Operting Supply curent (Vcc)
1.2
14
2.1
mA
EN/SHDN = GND, Vcc = 40 V, VIN
=
IQSD
Shutdown Supply current (Vcc)
IN Leakage Current in ON State
Open, RILIM or RPLIM = Open, RIOCP
Open
=
36
µA
EN/SHDN = 2 V, VIN = Vcc = 40 V, Open,
RILIM or RPLIM = Open
IINLKG
0.025
0.7
0.52
2.8
mA
µA
EN/SHDN = GND,VIN = Vcc = 40 V,
RILIM or RPLIM = Open, RIOCP = Open
IINLKG-SD IN Leakage Current in Shutdown
OVER-VOLTAGE PROTECTION (OVP) INPUT
VOVPR
VOVPF
IOVP
OVP rising threshold
OVP falling threshold
OVP leakage current
1.48
1.34
1.53
1.40
1.58
1.46
V
V
nA
0 V ≤VOVP ≤4 V
–350
–265
–200
EN/SHDN INPUT
VENR
VENF
IEN
Enable rising threshold
1.2
V
V
Enable falling threshold
Enable leakage current
0.59
µA
V
0 V ≤VEN ≤4 V
–10
VEN-Open Open circuit Enable Voltage
4.9
IEN = 0.1 µA, VCC ≥5 V
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
6
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
7.5 Electrical Characteristics (continued)
–40°C ≤TA = TJ ≤+125°C, VIN = 3 V to 40 V (TPS16412, TPS16413, TPS16416, TPS16417), VIN = 4.5 V to 40 V
(TPS16410, TPS16411, TPS16414, TPS16415), Vcc = VIN, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open,
COUT = 100 nF, CIN = 10 nF CdVdT = Open, PDLY/IDLY = Open. , EN/SHDN = Open
(Allvoltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT POWER LIMITING (PLIM)
POUT
POUT
POUT
Output Power Limit
Output Power Limit
Output Power Limit
3
12.94
34
3.66
13.69
37
4.5
14.44
39.8
W
W
W
RPLIM = 26.7 kΩ
RPLIM = 95.3 kΩ, –40°C ≤TA ≤+85°C
RPLIM = 255 kΩ, –40°C ≤TA ≤+85°C
OUTPUT CURRENT LIMITING (ILIM)
IOUT
IOUT
IOUT
Output Current Limit
Output Current Limit
Output Current Limit
0.024
0.918
1.671
0.032
0.987
1.77
0.039
1.035
1.881
A
A
A
RILIM = 332 kΩ
RILIM = 10 kΩ, –40°C ≤TA ≤+85°C
RILIM = 5.49 kΩ, –40°C ≤TA ≤+85°C
POWER OUTPUT (OUT)
RON
RON
RON
IN to OUT On resistance
96
153
153
260
215
160
–40°C ≤TJ ≤125°C
0°C ≤TJ ≤85°C
mΩ
mΩ
mΩ
µA
IN to OUT On resistance
IN to OUT On resistance
TJ = 25°C
153
ILKG-OUT Output Leakage current in OFF state
VIN = 40 V, VOUT = 0 V, EN = Low
–15
–1.2
CURRENT MONITORING OUTPUT (IMON)
GIMON
Gain : IMON/IOUT
IOUT = 0.05 to 1.8 A
IOUT = 0.3 to 0.8 A
45
50
55
µA/A
µA
OSIMON IMON Offset current
0.05
0.8
–0.8
OVER CURRENT PROTECTION (IOCP) AND SHORT CIRCUIT PROTECTION (ISCP)
IOCP
IOCP
Over curret protection set-point
Over curret protection set-point
2.11
0.95
2.23
1.01
2.35
1.07
A
A
RIOCP = 7.32 kΩ
RIOCP = 16.2 kΩ
1.9 ×
IOCP
IFasttrip
ISCP
Fast Trip protection threshold
Short circuit protection threshold
Internal Current Limit
A
A
A
6.7
ILIM-
TPS16410, TPS16411, TPS16414,
TPS16415
0.81 ×
IOCP
Internal
THERMAL PROTECTION and SHUTDOWN (TTSD)
TTSD
Thermal shutdown temperature
155
12
°C
°C
Thermal shutdown temperature
hysteresis
TTSD-hyst
Output slew rate control (dVdT)
IdVdT
dVdT charging current
dVdT Gain
1.78
2
2.23
µA
GdVdT
50
V/V
FLT Output (FLTb) (Open Drain Output)
RFLTb Fault pin pull down resistance
IFLTb-LKG Fault pin leakage current
73
Ω
0.005
1
µA
FLT is High, VFLT ≤25 V
–1
IN to OUT Short Detection (TPS16410, TPS16411, TPS16412 , TPS16413)
Rshort Resistance for IN to OUT short detection
30
mΩ
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
7.6 Timing Requirements
–40°C ≤TA = TJ ≤+125°C, VIN = 3 V to 40 V (TPS16412, TPS16413), VIN = 4.5 V to 40 V (TPS16410, TPS16411), VCC
VIN, VEN = 2 V, RILIM = 5.49 kΩ RPLIM = 255 kΩ RIOCP = 7.32 kΩ , FLT = Open, COUT = 100 nF, CIN = 10 nF CdVdT = Open,
PDLY = Open.
=
(Allvoltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Enable/SHDN and Vcc Input
tON_DLY
Turn on delay with VCC
Enable on delay
VEN = VENR + 0.1 V , RLOAD = Open
Fast turn-on with Enable when
500
270
µs
µs
tEN_ON_DLY
device is not in shutdown, VEN
VENR + 0.1 V , RLOAD = Open
=
VEN < VENF to VOUT = 0.9 × VIN, ,
RLOAD = 100
tEN_OFF_DLY
Enable off delay
1.2
µs
tLOW_SHDN
Min low pulse for entering shutdown RLOAD = 100
24
ms
OVP Input
tOVP_ENTRY_DLY
OVP entry delay
OVP exit delay
VOVP = VOVPR + 25 mV to FLT Low
0.75
0.6
µs
µs
VOVP = VOVPF - 25 mV to to FLT
High
tOVP_EXIT_DLY
Over Current Protection and Short-circuit protection
tFASTTRIP_DLY
tSCP_DLY
Fast Trip protection delay
IFASTTRIP < IOUT < ISCP to FET OFF
IOUT = ISCP + 500 mA to FET OFF
5.65
280
µs
ns
Short-Circuit protection delay
Power Limiting
IOUT < IOCP, POUT = 1.2 x PLIM,
CDLY = 12 nF
tPDLY
Blanking time before power limiting
Power Limit response time
PowerLimit Duration
6.5
ms
µs
s
IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY
= OPEN
tPLIM-RES
215
2 x
tPDLY
tPLIM-DUR
Current Limiting
tIDLY
IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY
= 12 nF
Blanking time before current limiting
Current Limit response time
Current Limit Duration
6.5
ms
µs
s
IOUT < IOCP, IOUT = 1.2 x ILIM, CDLY
= OPEN
tILIM-RES
tILIM-DUR
280
2 x
tPDLY
Auto-Retry and Thermal Shutdown
tRETRY Retry Delay
8 x
tPDLY
s
Output Ramp Control (dVdT)
tdVdT Output Ramp Time
CdVdT = Open, VIN = VCC = 24 V
105
µs
IN to OUT Short (TPS16410, TPS16411, TPS16412, TPS16413) and FLT Output
tIN_OUT_Short_Detec IN to OUT short detection time
IN-OUT Short to FLT Low
135
20
ms
ms
when FET is ON
t
tIN_OUT_Short_Detec IN to OUT short detection time
IN-OUT Short to FLT Low
when FET is OFF
t
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
8
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
7.7 Typical Characteristics
1.35
1.3
50
45
40
35
30
25
20
15
10
5
(VCC = 4.5 V )
(VCC = 12 V )
(VCC = 40 V )
(VCC = 24 V )
(VCC = 4.5 V )
(VCC = 12 V )
(VCC = 24 V )
(VCC = 40 V )
1.25
1.2
1.15
1.1
1.05
1
0.95
0.9
-40
0
-20
0
20
40
60
80
100 120 140
16
24
32
40
TA(C)
48
56
64
72
TA (C)
图7-1. IQ-ON vs Temperature
图7-2. IQSD vs Temperature
5000
(VIN = 4.5 V )
(VIN = 12 V )
(VIN = 24 V )
(VIN = 40 V )
2000
1000
500
200
100
50
20
10
5
2
1
-40
-20
0
20
40
60
80
100 120 140
TA (C)
图7-3. ILKG-VIN vs Temperature
图7-4. ILKG-VIN-SD vs Temperature
240
220
200
180
160
140
120
100
49.81
49.8
(IOUT = 0.5 A)
(IOUT = 1.7 A)
49.79
49.78
49.77
49.76
49.75
49.74
49.73
49.72
49.71
49.7
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
图7-6. GdVdT vs Temperature
图7-5. RDS-ON vs Temperature
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
7.7 Typical Characteristics (continued)
-2.0375
-2.04
49.8
49.6
49.4
49.2
49
(IOUT = 1 A )
(IOUT = 1.8 A )
-2.0425
-2.045
-2.0475
-2.05
-2.0525
-2.055
-2.0575
-2.06
48.8
-2.0625
48.6
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
TA (C)
60
80
100 120 140
TA (C)
图7-7. IdVdT vs Temperature
图7-8. GIMON vs Temperature
3
2.5
2
3
2.4
1.8
1.2
0.6
0
ILIM (RILIM = 332 k)
ILIM (RILIM = 10 k)
ILIM (RILIM = 5.49 k)
(RIOCP = 16.2 k)
(RIOCP = 7.32 k)
1.5
1
0.5
-60
-30
0
30
60
90
120
150
-60
-30
0
30
60
90
120
150
TA (C)
TA (C)
图7-9. IOCP vs Temperature
图7-10. Output Current Limit vs Temperature for TPS16412 and
TPS16413
14
12
10
8
6.56
CDLY = 12 nF
6.54
RPLIM = 26.7 k
RPLIM = 95.3 k
6.52
6.5
6.48
6.46
6.44
6.42
6.4
6
4
2
-40
-40
-20
0
20
40
60
80
100 120 140
-20
0
20
40
60
80
100 120 140
Temperature (C)
TA (C)
图7-12. TDLY vs Temperature
图7-11. Output Power Limit vs Temperature for TPS16410 and
TPS16411 with VIN = 12 V
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
10
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
7.7 Typical Characteristics (continued)
40
35
200
100
50
TA = -40C
TA = 25C
TA = 85C
TA = 105C
TA = 125C
RPLIM = 26.7 k
RPLIM = 95.3 k
RPLIM = 255 k
30
25
20
15
10
5
20
10
5
2
1
0.5
0.2
0.1
0
-40
0
2.5
5
7.5
10 12.5
15
17.5
20
22.5
-20
0
20
40
TA (C)
60
80
100 120 140
Power Dissipation (W)
图7-14. Thermal Shutdown Time vs Power Dissipation with VIN
图7-13. Output Power Limit vs Temperature for TPS16410 and
= 12 V
TPS16411 with VIN = 24 V
200
100
50
TA = -40C
TA = 25C
TA = 85C
TA = 105C
TA = 125C
20
10
5
2
1
0.5
0.2
0.1
0.05
0
5
10
15
20
25
30
35
40
45
Power Dissipation (W)
图7-15. Thermal Shutdown Time vs Power Dissipation with VIN = 24 V
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
8 Detailed Description
8.1 Overview
The TPS1641x is an integrated eFuse with accurate power limit or current limit. The device integrates an NFET
with RON of 152 mΩ. TPS16410, TPS16411, TPS16414 and TPS16415 provide power limiting whereas the
TPS16412, TPS16413, TPS16416 and TPS16417 provide current limiting. The TPS16410, TPS16411,
TPS16414 and TPS16415 can provide 15-W accurate power limiting for low power circuit (LPCs) as per
IEC60335 and UL60730 standards. TPS16410, TPS16411, TPS16412 and TPS16413 also provide IN to OUT
short detection and its indication on FLT output. IN to OUT short detection eliminates the need of additional
eFuse or power limiting circuit in case of IN to OUT short test for IEC60335, UL60730, and similar standards.
FLT can be used as input for MCU or it can be used to drive an external PFET. TPS1641x devices also provide
protection from adjacent pin short and pin short to GND faults.
The TPS1641x device also provide configurable blanking time (IDLY or PDLY) and overcurrent protection (IOCP)
for transient loads. Load such as motors need higher current for start-up. Blanking time is useful for providing
higher current for start-up of loads such as motors.
TPS1641x devices have overvoltage protection (OVP), overtemperature protection, and adjustable output slew
rate control (dvdt). Vcc and FLT are rated up to 60 V and can provide protection up to 60 V with an external
PFET.
8.2 Functional Block Diagram
VIN
IOUT
VOUT
IN to OUT
Short
Detection
TPS1641x
IN-OUT
Short
IOUT
IN
OUT
Sense
Isink
Thermal Shutdown
IOCP/IMON
Pass FET Drive and
Control
TSD
Over-Current
Protection
–
+
Vcc
Internal
Regulator
IOCP_REF
VINT
–
+
IOUT
Short-Circuit
ISCP Protection
VINT
FLT
–
+
PLIM/ILIM
IOUT
IN-OUT Short
OVP
Ifast-trip
ILIM/PLIM Timeout
TSD
Power or Current
Limiting
Delay
–
+
VINT
POUT
OR
IOUT
Over-Voltage
Protection
V(OVPR)
V(OVPF)
VINT
–
OVP
Power or
Current Limiting
+
PDLY/IDLY
V(ENR)
–
VINT
VINT
EN/SHDN
Output Slew Rate
Control (dVOUT/dt)
GdVdt
V(ENF)
+
Pulse Duration
Detection
IdVdt
dVdt
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
12
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
8.3 Feature Description
8.3.1 Enable and Shutdown Input (EN/SHDN)
The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than
tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the
quiescent current of the device is reduced to IQSD from Vcc supply.
While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and
FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the
enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is
not in shutdown. See the 节7.5 for VENR and VENF thresholds and the 节7.6 for tLow_SHDN, tEN_OFF_dly, and
tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of the
device for fast turn-on and turn-off of internal FET. 图8-1 illustrates the EN/SHDN input in the TPS1641x
devices. 图8-2 shows the start-up of the device with enable input.
VINT
ON
+
OFF
VENR
VENF
EN/SHDN
EN/SHDN
TPS1641x
图8-1. EN/SHDN in TPS1641x Devices
VIN = 12 V
图8-2. Turn-On with Enable
8.3.2 Overvoltage Protection (OVP)
The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A
resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The
device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and as
the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the 节 7.5
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
table for VOVPF and VOVPR and 节7.6 for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage protection input. 图
8-3 illustrates the OVP input in TPS1641x devices. 图8-4 shows the overvoltage response.
VIN
VINT
R1
R2
OVP
+
OVP
VOVPR
VOVPF
TPS1641x
图8-3. OVP Input in TPS1641x
图8-4. Overvoltage Protection Response for IN Voltage 12 V to 40 V
Vcc and FLT pins of the device are rated up to 60 V, and the FLT pin can be used to drive an external PFET
transistor and provide protection from 60-V overvoltage at input as shown in 图8-5.
* Optional TVS Diode
CPH6354 or
similar
Vcc
VOUT
COUT
OUT
IN
CIN
+
–
TPS1641x
EN/SHDN
FLT
IOCP
IDLY/PDLY
ILIM/PLIM
R1
OVP
R2
ROCP
GND
CDLY
RLIM
图8-5. Overvoltage (up to 60 V) Protection with External PFET
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
14
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
To disable the overvoltage input, connect OVP to GND. If the OVP pin is left open, the device turns off the
internal FET.
图8-6. Overvoltage Response with External PFET
图8-7. Hot Plugin with External PFET for 60-V
for IN Voltage from 12 V to 60 V
Input
8.3.3 Output Slew Rate and Inrush Current Control (dVdt)
During hot plug events or while trying to charge a large output capacitance, there can be a large inrush current.
If the inrush current is not managed properly, it can damage the input connectors and cause the system power
supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during turn-on is
directly proportional to the load capacitance and rising slew rate. 方程式 1 can be used to find the output slew
rate (SR) required to limit the inrush current (IINRUSH) for a given output capacitance (COUT).
I
INRUSH
SR =
(1)
C
OUT
A capacitance can be added to the dVdt pin to control the rising slew rate and lower the inrush current during
turn-on. The required CdVdt capacitance to produce a given slew rate can be calculated using 方程式2.
I
× G
dVdt
dVdt
C
=
(2)
dVdt
SR
The fastest output slew rate is achieved by leaving the dVdt pin open. If dVdt pin is connected to GND, the
device will not power up the output. 图 8-8 illustrates the output slew rate control in the TPS1641x devices. 图
8-9 shows the output slew rate control response of the device.
VINT
Idvdt
Idvdt/Cdvdt
dvdt
Gdvdt
Cdvdt
Output Slew
Rate (SR) =
TPS1641x
[Gdvdt × Idvdt]/Cdvdt
图8-8. Output Slew Rate Control in the TPS1641x
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
图8-9. Output Slew Rate Control with VIN = 12 V, CdVdt = 150 nF, and COUT = 470 μF
8.3.4 Active Current Limiting (ILIM) With the TPS16412, TPS16413, TPS16416, and TPS16417
The TPS16412, TPS16413, TPS16416, and TPS16417 devices respond to output overcurrent or overload
conditions by actively limiting the current. The devices first provide a blanking time configured by capacitance on
the IDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the end of this
blanking time, the devices limit current to ILIM value. ILIM can be set by connecting resistor on ILIM pin. RILIM
can be calculated by 方程式3.
0.984 A
I
=
× 10 kΩ
(3)
LIM
R
ILIM
If the output current exceeds IOCP, the device goes into current limiting. During current limiting, if the output
current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts IDLY timer when IOUT
>
ILIM. 图 8-10 illustrates the current limiting behavior for IOUT < IOCP and for IOCP ≤ IOUT < Ifast-trip. During current
limiting, if the output current goes below ILIM (IOUT < ILIM), the device resets the IDLY timer and restarts the
IDLY timer when IOUT > ILIM.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
16
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
图8-10. Current Limiting for IOUT < IOCP
图8-11. IOCP ≤IOUT < Ifast-trip
During the current limiting, the device dissipates a power of (VIN – VOUT) × IOUT and the device gets heated up.
If the junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the
internal FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of
tILIM-DUR. After the internal FET is turned off, the TPS16412 and TPS16416 auto-retry while the TPS16413 and
TPS16417 latch off. If ILIM pin is connected to GND or left open, the device turns-off the internal FET. If the IDLY
pin is left open or connected to GND, device provides tILIM-DUR = 155 ms unless the device enters thermal
shutdown. 表8-1 summarizes the device behavior for different output currents.
表8-1. Current Limiting and Overload Protection With TPS16412, TPS16413, TPS16416, and TPS16417
Output Current (IOUT
)
Device Response
IOUT < ILIM
The device provides current up to ILIM.
The device provides current up to IOCP for a duration of IDLY and then limits current to ILIM for a
maximum duration of tILIM-DUR.
I
LIM ≤IOUT < IOCP
The device limits current to ILIM for a maximum duration of tILIM-DUR
.
I
OCP ≤IOUT < Ifast-trip
fast-trip ≤IOUT < ISCP
SCP ≤IOUT
The device turns off the internal FET after a delay of tfast-trip.
I
The device turns off the internal FET after a delay of tSCP_dly
.
I
8.3.5 Active Power Limiting (PLIM) With the TPS16410, TPS16411, TPS16414, and TPS16415
The TPS16410, TPS16411, TPS16414, and TPS16415 devices respond to output overcurrent or overload
conditions by actively limiting the output power. The devices first provide a blanking time configured by
capacitance on PDLY pin. During this blanking time, the device can provide a current up to IOCP value. After the
end of this blanking time, the devices limit power to PLIM value. Power limit can be set by connecting a resistor
on the PLIM pin. During power limiting, if the output power goes below PLIM (POUT < PLIM), the device resets
the PDLY timer and restarts the PDLY timer when POUT > PLIM. Use 方程式 4 to calculate the value of resistor
for power limiting. The device is rated for 1.8-A continuous current, TI recommends to set PLIM < VIN × 1.8 A
and PLIM < 0.9 × VOUT × IOCP
13.82 W
95.3 kΩ
P
=
× R
(4)
LIM
PLIM
图 8-12 illustrates the power limiting in the TPS16410 and TPS16411 devices for IOUT < IOCP and IOCP ≤ IOUT
Ifast-trip
<
.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
图8-12. Power Limiting (IOUT < IOCP
)
图8-13. Power Limiting (IOCP ≤IOUT < Ifast-trip)
During power limiting, the device dissipates a power of (VIN –VOUT) × IOUT and the device gets heated up. If the
junction temperature of device reaches thermal shutdown temperature (TTSD), the device turns off the internal
FET. If the device does not go into thermal shutdown, the internal FET is turned off after a duration of tPLIM-DUR
.
After the internal FET is turned off, the TPS16410 and TPS16414 devices auto-retry while the TPS16411 and
TPS16415 device latch off. If PLIM is connected to GND or left open, the device turns-off the internal FET. If the
PDLY pin is left open or connected to GND, device provides tPLIM-DUR = 155 ms unless the device enters thermal
shutdown. 表8-2 summarizes the device behavior for different output power and current.
表8-2. Power Limiting and Overload Response in TPS16410, TPS16411, TPS16414, and TPS16415
Devices
Output Power (POUT) or Output
Device Response
Current (IOUT
)
POUT < PLIM
The device provides power up to PLIM.
The device provides current up to IOCP for a duration of PDLY and then limits power to PLIM for
PLIM ≤POUT
a maximum duration of tPLIM-DUR
The device limits current to PLIM for a maximum duration of tPLIM-DUR
The device turns off the internal FET after a delay of tfast-trip
The device turns off the internal FET after a delay of tSCP_dly
.
and IOUT < IOCP
.
I
OCP ≤IOUT < Ifast-trip
.
I
fast-trip ≤IOUT < ISCP
SCP ≤IOUT
.
I
8.3.5.1 Internal Current Limit for the TPS16410 and TPS16411
In power limiting devices, there is an internal current limit. If during power up, the output current exceeds
overcurrent protection setpoint (IOCP), these devices limit current to 0.81 × IOCP
TPS16410, TPS16411, TPS16414, and TPS16415 devices also limit the output current if PLIM is set to more
than (VOUT × IOCP) and IOUT exceeds IOCP
.
.
8.3.6 Overcurrent Protection (IOCP) and Blanking Time (IDLY or PDLY) for Transient Loads
In TPS1641x devices, the overcurrent protection set-point can be configured by connecting a resistor on IOCP
pin. The resistor value for overcurrent can be calculated by 方程式5.
2.25 A
I
=
× 7.32 kΩ
(5)
OCP
R
IOCP
If the IOCP pin is left open or connected to GND, the device turns off the internal FET.
The devices also provide blanking time for overload or overcurrent events. This blanking time can be configured
by connecting a capacitor on IDLY or PDLY, and the blanking time can be calculated by 方程式6.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
18
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
If IDLY/PDLY pin is left open or connected to GND, device disables the blanking time and directly goes into
power or current limiting.
6.5 ms
12 nF
Blanking Time IDLY or PDLY =
× CDLY
(6)
8.3.7 Fast-Trip and Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When an output short-
circuit is detected and output current reaches ISCP level, the device turns off the internal FET after a delay of
tSCP_dly
.
In case of fast input transients, the current through internal FET rises rapidly, but these transients can lead to
false turn-off of internal FET due to excessive flow of current through internal FET. To prevent false tripping
during these input transients, the device includes fast-trip comparator, which turns off the internal FET if the
output current exceeds Ifast-trip for a duration of tfast-trip. 图8-14 shows the short-circuit response of the device.
图8-14. Short-Circuit Response with VIN = 12 V
8.3.8 Analog Load Current Monitor (IMON) on the IOCP Pin
The device allows the system to monitor the output load current accurately by providing an analog current on the
IOCP/IMON pin, which is proportional to the current through the FET. The resistor on IOCP/IMON pin converts
this current into voltage and this voltage can be used for monitoring the output current. Output current can be
calculated from voltage at IOCP/IMON pin by using 方程式7.
V
−
G
OS
× R
IOCP
IOCP
IMON
× R
I
=
(7)
OUT
IMON
IOCP
8.3.9 IN to OUT Short Detection (TPS16410, TPS16411, TPS16412, and TPS16413)
TPS16410, TPS16411, TPS16412, and TPS16413 devices include short detection across IN and OUT pins. If
the device detects a resistance less than Rshort across IN and OUT pins, the device asserts the FLT pin low. See
the 节7.5 for Rshort and 节7.6 for tIN_OUT_Short_Detect
.
At start-up, the device keeps FLT low and the internal FET off. The device detects for short across IN to OUT
before turning on the internal FET. If device does not detect any short across IN to OUT, the device de-asserts
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
the FLT and enables the internal FET. After start-up, the device detects for short across IN to OUT at regular
intervals and asserts the FLT pin after a delay of tIN_OUT_Short_Detect. After the device detects IN to OUT short, it
latches off. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch, keep EN/SHDN pin
low for duration more than tLow_SHDN. 图 8-15 illustrates the response of device for IN to OUT short. In case of
switching loads on output of device, see 表 8-3 for recommended device variants based on switching load
frequency fSW (in kHz) and ripple load current IRipple (in mAp-p).
表8-3. Recommended Device Variants
Switching Load Frequency
(IRipple / fSW) < 2
(IRipple / fSW) ≥2
0 to 5 Hz
TPS16410, TPS16411, TPS16412 , TPS16413, TPS16414, TPS16415, TPS16416, or TPS16417
TPS16410, TPS16411, TPS16412 , TPS16413,
TPS16414, TPS16415, TPS16416, or TPS16417
> 5 Hz
TPS16414, TPS16415, TPS16416, or TPS16417
图8-15. IN to OUT Short Detection for VIN = 12 V
8.3.10 Thermal Shutdown and Overtemperature Protection
During power or current limiting, there is a power dissipation [(VIN – VOUT) × IOUT] in the internal FET of the
device. Due to this power dissipation, the temperature (TJ) of device increases. When the device temperature
increases above TTSD, it shuts down. After the thermal shutdown, the TPS16411, TPS16413, TPS16415, and
TPS16417 remain latched. To reset the latch, toggle EN/SHDN or recycle the Vcc supply. To reset the latch,
keep EN/SHDN pin low for duration more than tLow_SHDN
.
After thermal shutdown, the TPS16410, TPS16412, TPS16414, and TPS16416 devices wait for temperature to
go below [TTSD –TTSD-hyst] and then the device restarts after a delay of tretry
.
8.3.11 Fault Response and Indication (FLT)
FLT is an open-drain output to indicate the overvoltage, IN to OUT short, overtemperature, current limit, and
power limit events. 表 8-4 summarizes the state of FLT pin under different events. To prevent excessive
dissipation in device during adjacent pin short test (FLT to EN/SHDN), pull up the FLT pin with a resistor (RFLT
)
such that sink current into FLT pin is less than 3 mA. 图 8-16 shows the connection diagram for FLT pin with a
pullup resistor.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
20
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
TPS1641x
IN
FLT
IFLT < 3 mA
EN
图8-16. FLT Output in the TPS1641x
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
表8-4. FLT Pin Indication for Different Events
Retry Delay With IDLY/PDLY Retry Delay With Capacitor
= Open or GND for
TPS16410, TPS16412,
TPS16414, and TPS16416
on IDLY/PDLY pin for
TPS16410, TPS16412,
TPS16414, and TPS16416
Event, Condition
FLT Pin
(1)
Overvoltage protection (VOVP > VOVPR
)
Low
Low
NA
NA
IN to short detection (TPS16410, TPS16411,
TPS16412, and TPS16413)
No retry, latch off
No retry, latch off
Thermal shutdown (TJ > TTSD
)
Low
Low
620 ms
620 ms
8 × tPDLY/IDLY
8 × tPDLY/IDLY
After current or power limiting timeout
(1) For overvoltage protection, device turns on the FET as VOVP falls below VOVPF
8.4 Device Functional Modes
The device can be brought into low power shutdown mode by bringing the EN/SHDN pin low. In low power
shutdown mode, the internal blocks of devices are shut down and it takes IQSD from VCC supply. See the Enable
and Shutdown Input (EN/SHDN) section for details.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
22
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
TPS1641x devices include power limiting or current limiting for a low power circuit (as per IEC60335 and
UL60730 standards) in appliances, HVAC actuators, and medical equipment. TPS1641x devices also have IN to
OUT short detection for internal FET for IN-OUT short testing during IEC60335 or UL60730 certifications. The
TPS16410 and TPS16411 have an accurate power limiting feature while the TPS16412 and TPS16413 have an
accurate current limiting feature. For transient current required for start-up of motors or actuators, TPS1641x
devices have a configurable overcurrent protection threshold (IOCP) and configurable blanking time (IDLY/
PDLY). For start-up with big capacitance (< 1 mF) on output, the TPS1641x include dVdT feature to control the
output slew rate and limiting the inrush current during power up. The output current can be monitored from IOCP
or IMON pin, by sensing the voltage on this pin.
9.2 Typical Application: 15-W Power Limiting for Low Power Circuits (LPCs)
The TPS16410 and TPS16411 can be used for 15-W power limiting for low-power circuits in IEC60335 and
UL60730 standards. The output power limit can be configured by a resistor on the PLIM pin. 图 9-1 provides a
typical application circuit for 15-W power limiting.
Vcc
VIN = 18 to
32V
OUT
VOUT
IN
COUT
470 µF
CIN
100 nF
TPS16410
TPS16411
EN/SHDN
FLT
IOCP/IMON
1 M
R1
PDLY
OVP
CDLY
12 nF
16.2 k
R4
PLIM
dVdT
47 k
R2
GND
95.3 k
R3
CdVdt
150 nF
图9-1. 15-W Power Limiting for Low-Power Circuits
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
9.2.1 Design Requirements
表9-1. Design Parameters
Parameter
Value
18 V to 32 V
≤15 W
1 A
VIN
POUT
Overcurrent protection
Output capacitance (COUT
IINRUSH
)
470 μF
≤350 mA
6.5 ms
Blanking time for transients (PDLY)
9.2.2 Detailed Design Procedure
9.2.2.1 Setting Overvoltage Setpoints
Input overvoltage protection setpoints can be set by connecting resistors (R1, R2) from the IN pin to OVP pin.
The value of resistors can be calculated using 方程式 8 and 方程式 9. To set the OVP rising setpoint to 32 V, R1
= 1 MΩ and R2 = 47 kΩ are selected.
V
×
R1 + R2
OVPR
OVP Rising Setpoint =
OVP Falling Setpoint =
(8)
(9)
R2
V
×
R1 + R2
OVPF
R2
9.2.2.2 Setting the Output Overcurrent Setpoint (IOCP)
To set the output overcurrent setpoint, a resistor (R4) is required on the IOCP pin. To calculate the value of this
resistor (R4), use 方程式5. For IOCP = 1 A, R4 is selected as 16.2 kΩ.
9.2.2.3 Setting the Output Power Limit
For setting the output power limit, a resistor (R3) is required on the PLIM pin. To calculate the value of power
limit, use 方程式4. To keep output power limit ≤15 W, R3 was selected as 95.3 kΩ.
9.2.2.4 Monitoring the Output Current
The output current can be monitored on IOCP or IMON by reading the voltage on this pin. The output current
can be calculated using 方程式7.
9.2.2.5 Limiting the Inrush Current and Setting the Output Slew Rate
For charging the large capacitors on output, the output slew rate can be controlled by using a capacitor on dVdt
pin. The value of inrush current can be estimated by 方程式 10. To keep the inrush current below 350 mA, CdVdt
is selected as 150 nF.
I
× G
× C
dVdt
dVdt OUT
I
=
(10)
INRUSH
C
dVdt
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
24
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
9.2.3 Application Curves
图9-2. Overvoltage Protection up to 40 V
图9-3. Inrush Current Control for Hot Plugin at
Input
图9-4. Output Short-Circuit Protection
图9-5. 15-W Power Limiting with TPS16410 (IOUT
IOCP
<
)
图9-6. 15-W Power Limiting with TPS16410 (IOCP
≤
图9-7. IN to OUT Short Detection with VIN = 24 V
IOUT < Ifast-trip
)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
图9-8. Power-Up Into Short
9.3 System Examples
9.3.1 Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter
For systems using a DC/DC converter or a flyback converter, the device can be used for accurate power or
current limiting (±5%) at the output. For additional protection, the device has a fault pin and it is asserted in case
of overvoltage, overcurrent or overpower, IN-short detection and thermal shutdown events. The fault can be
used to turn-off the DC/DC converter or flyback converter providing the power to input of TPS1641 for the load.
The device has separate Vcc pin for powering itself and it can remain on with Vcc supply. 图 9-9 illustrates the
application at the output of DC/DC or flyback converter.
VOUT
Vcc
OUT
+
Vcc
EN
OUT
≥VIN
DC -DC
Converter
–
EN/SHDN
VIN
IN
TPS1641x
R1
OUT
IOCP
IDLY/PDLY
ILIM/PLIM
OVP
R2
Vcc
ROCP
FLT
GND
CDLY
RLIM
Flyback Converter
图9-9. Accurate Power or Current Limiting at the Output of DC/DC or Flyback Converter
Copyright © 2023 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
9.4 Best Design Practices
• Use CIN ≥10 nF for decoupling Vcc and IN pins.
• Do not leave the OVP, PLIM/ILIM, and IOCP/IMON pins open or floating.
• Connect the PowerPAD of the device to GND on the PCB.
• Do not connect the EN/SHDN pin to voltage more than 5 V.
9.5 Power Supply Recommendations
• Use 4.5 V ≤VIN ≤40 V for the TPS16410 and TPS16411.
• Use 2.7 V ≤VIN ≤40 V for the TPS16412 and TPS16413.
• Use VIN ≤VCC ≤60 V.
• Pull up FLT with voltage ≤60 V. Use a pullup resistor to keep current into the FLT pin < 3 mA.
9.5.1 Transient Protection
In the case of a short-circuit and overload current limit when the device interrupts current flow, the input
inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. 图9-10 illustrates the transient protection circuit.
Typical methods for addressing transients include:
• Minimize lead length and inductance into and out of the device.
• Use a large PCB GND plane.
• Connect a Schottky diode (D2) from the OUT pin ground to absorb negative spikes. The OUT pin has an
absolute maximum rating of –1 V for negative transient spikes on output.
• Connect a low-ESR capacitor larger than 1 μF at the OUT pin very close to the device.
• Use a low-value ceramic capacitor CIN = 0.1 μF to absorb the energy and dampen the transients. The
approximate value of input capacitance can be estimated with 方程式11.
L
IN
V
= V + I ×
LOAD
(11)
IN − SPIKE
IN
C
IN
• Some applications require additional Transient Voltage Suppressor (TVS) to keep transients below the
absolute maximum rating of the device. A TVS can help to absorb the excessive energy dump and prevent it
from creating very fast transient voltages on the input of the device. Use a suitable TVS to clamp the transient
voltage below the absolute maximum rating of the device.
Vcc
VOUT
COUT
OUT
IN
D2*
CIN
D1*
TPS1641x
EN/SHDN
FLT
IOCP/IMON
PDLY/IDLY
PLIM/ILIM
OVP
ROCP
dVdT
GND
CDLY
RPLIM
TVS D1* and Schottky D2* are optional diodes for transient protection on the input and output.
图9-10. Transient Protection with TPS1641x
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
9.6 Layout
9.6.1 Layout Guidelines
• High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
• The GND (PowerPAD) pin must be tied to the PCB ground plane at the terminal of the IC with the shortest
possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a
separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a
quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be
connected to the system power ground plane using a star connection.
• The optimal placement of the decoupling capacitor (CIN) is closest to the IN and GND pins of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN pin, and the GND
pin of the IC.
• Locate the following support components close to their connection pins:
– RILM or RPLM
– RIOCP
– CDLY
– CdVdT
– Resistors for OVP
• Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for these components to the device must be as short as possible to reduce parasitic effects on the
current limit, overcurrent blanking interval, and soft-start timing.
• Because the bias current on ILM pin directly controls the overcurrent protection behavior of the device, the
PCB routing of this node must be kept away from any noisy (switching) signals.
• Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, TI recommends a protection Schottky diode to address negative transients due to
switching of inductive loads. TI recommends to add a ceramic decoupling capacitor (COUT) of 1 μF or greater
between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to
minimize the loop area formed by the Schottky diode and bypass-capacitor connection, the OUT pin, and the
GND pin of the IC.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
28
Submit Document Feedback
Product Folder Links: TPS1641
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
9.6.2 Layout Example
ROCP
RPLIM/ILIM
CdVdT
COUT
15 mm
TPS1641x
CIN
12 mm
Top Layer
图9-11. Layout Example
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TPS1641
English Data Sheet: SLVSGF4
TPS1641
www.ti.com.cn
ZHCSO95B –JUNE 2022 –REVISED MAY 2023
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.3 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
10.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSGF4
30
Submit Document Feedback
Product Folder Links: TPS1641
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS16410DRCR
TPS16411DRCR
TPS16412DRCR
TPS16413DRCR
TPS16414DRCR
TPS16415DRCR
TPS16416DRCR
TPS16417DRCR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
T16410
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
T16411
T16412
T16413
T16414
T16415
T16416
T16417
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS16410DRCR
TPS16411DRCR
TPS16412DRCR
TPS16413DRCR
TPS16414DRCR
TPS16415DRCR
TPS16416DRCR
TPS16417DRCR
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
3000
3000
3000
3000
3000
3000
3000
3000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS16410DRCR
TPS16411DRCR
TPS16412DRCR
TPS16413DRCR
TPS16414DRCR
TPS16415DRCR
TPS16416DRCR
TPS16417DRCR
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
3000
3000
3000
3000
3000
3000
3000
3000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPS16410DRCR
具有输出功率限制功能的 2.7V 至 40V、152mΩ、1.8A 电子保险丝 | DRC | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS16411DRCR
具有输出功率限制功能的 2.7V 至 40V、152mΩ、1.8A 电子保险丝 | DRC | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS16412DRCR
具有输出功率限制功能的 2.7V 至 40V、152mΩ、1.8A 电子保险丝 | DRC | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS16413DRCR
具有输出功率限制功能的 2.7V 至 40V、152mΩ、1.8A 电子保险丝 | DRC | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS16414DRCR
具有输出功率限制功能的 2.7V 至 40V、152mΩ、1.8A 电子保险丝 | DRC | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS16415DRCR
具有输出功率限制功能的 2.7V 至 40V、152mΩ、1.8A 电子保险丝 | DRC | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS16416DRCR
具有输出功率限制功能的 2.7V 至 40V、152mΩ、1.8A 电子保险丝 | DRC | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS16417DRCR
具有输出功率限制功能的 2.7V 至 40V、152mΩ、1.8A 电子保险丝 | DRC | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS1653
TPS16530 58-V, 4.5-A eFuse With Pulse Current Support for Load TransientsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS16530
TPS16530 58-V, 4.5-A eFuse With Pulse Current Support for Load TransientsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS16530PWPR
TPS16530 58-V, 4.5-A eFuse With Pulse Current Support for Load TransientsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TPS16530RGER
TPS16530 58-V, 4.5-A eFuse With Pulse Current Support for Load TransientsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明