TPS16530PWPR [TI]
TPS16530 58-V, 4.5-A eFuse With Pulse Current Support for Load Transients;
| 型号： | TPS16530PWPR |
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TEXAS INSTRUMENTS |
| 描述： | TPS16530 58-V, 4.5-A eFuse With Pulse Current Support for Load Transients |
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TPS1653
SLVSG57 – AUGUST 2021
TPS16530 58-V, 4.5-A eFuse With Pulse Current Support for Load Transients
1 Features
3 Description
•
4.5-V to 58-V operating voltage,
67-V absolute maximum
The TPS16530 is an easy to use, positive 58-V,
4.5-A eFuse with a 31-mΩ integrated FET. Protection
for the load, source and eFuse itself are provided
along with adjustable features such as accurate
overcurrent protection, fast short circuit protection,
output slew rate control and undervoltage lockout.
PGOOD can be used for enable and disable control
of the downstream DC-DC converters.
•
•
•
Integrated 58-V, 31-mΩ RON Hot-Swap FET
0.6-A to 4.5-A adjustable current limit (± 7%)
IPC9592B clearance for 56-V operation (20-pin
HTSSOP)
2x pulse current support for load transients
Low quiescent current, 21-µA in shutdown
Adjustable UVLO cut off with ± 2% accuracy
Adjustable output slew rate control for inrush
current limiting
•
•
•
•
The enable pin provides external control for enabling
and disabling the internal FET. The shutdown pin
can be used for putting the device in low power
shutdown mode. For system status monitoring and
downstream load control, the device provides fault
and a precise current monitor output. The MODE
pin allows flexibility to configure the device between
the two current-limiting fault responses (latch off and
auto-retry).
– Charges large and unknown capacitive loads
through thermal regulation during device power
up
•
•
Power Good Output (PGOOD)
Selectable overcurrent fault response options
between Auto-Retry and Latch Off (MODE)
Analog current monitor (IMON) output (± 6%)
Available in easy-to-use 20-pin HTSSOP and
24-pin VQFN packages
•
•
The devices are available in 20-pin HTSSOP
and 24-pin VQFN packages and are specified over a
–40°C to +125°C temperature range.
2 Applications
Device Information(1)
•
•
•
•
Power amplifier protection in telecom radios
Medical equipment
Fire alarm control panels
Industrial printers
PART NUMBER
TPS16530
PACKAGE
BODY SIZE (NOM)
4.00 mm × 4.00 mm
6.50 mm × 4.40 mm
VQFN (24)
TPS16530
HTSSOP (20)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
IN
OUT
VIN
VOUT
COUT
UVLO
CIN
31 m
PGOOD
FLT
TPS16530
ON/OFF Control
SHDN
IMON
dVdT
ILIM
EN
MODE
RILIM
GND
Simplified Schematic
Pulse Current Support
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS1653
SLVSG57 – AUGUST 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Timing Requirements .................................................7
6.7 Typical Characteristics................................................9
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................13
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................21
9 Application and Implementation..................................22
9.1 Application Information............................................. 22
9.2 Typical Application.................................................... 22
9.3 System Examples..................................................... 25
10 Power Supply Recommendations..............................26
10.1 Transient Protection................................................26
11 Layout...........................................................................27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 28
12 Device and Documentation Support..........................30
12.1 Documentation Support.......................................... 30
12.2 Receiving Notification of Documentation Updates..30
12.3 Support Resources................................................. 30
12.4 Trademarks.............................................................30
12.5 Electrostatic Discharge Caution..............................30
12.6 Glossary..................................................................30
13 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
August 2021
*
Initial Release
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5 Pin Configuration and Functions
IN
IN
1
2
3
4
OUT
20
OUT
OUT
19
18
17
18
17
OUT
OUT
1
2
3
4
5
6
IN
P_IN
N.C
IN
IN
N.C
PGOOD
5
6
16
15
14
N.C
N.C
P_IN
16
15
PGOOD
N.C
PowerPadTM
PowerPAD™
FLT
UVLO
N.C
7
8
IMON
14
13
FLT
EN
SHDN
MODE
13
12
IMON
UVLO
GND
9
10
11
dVdT
ILIM
Figure 5-2. TPS16530 PWP Package 20-Pin
HTSSOP Top View
Figure 5-1. TPS16530 RGE Package 24-Pin VQFN
Top View
Table 5-1. Pin Functions
PIN
TPS16530
HTSSOP
TYPE
DESCRIPTION
NAME
VQFN
1
2
1
2
3
4
IN
P
Power Input. Connects to the DRAIN of the internal FET.
—
5
P_IN
P
I
Supply voltage of the device. Always connect P_IN to IN directly.
Input for setting the programmable undervoltage lockout threshold. An
undervoltage event turns off the internal FET and asserts FLT to indicate
the power-failure. If not used, this pin can be connected to IN or P_IN.
UVLO
6
6
Active low enable pin. If not used, this pin can be connected to GND. Do not
leave this pin open or floating.
EN
7
8
8
9
I
GND
—
Connect GND to system ground
A capacitor from this pin to GND sets output voltage slew rate. Leaving this
pin floating enables device power up in thermal regulation resulting in fast
output charge. See the Hot Pug-In and In-Rush Current Control section.
dVdT
9
10
I/O
A resistor from this pin to GND sets the overload limit. See Overload and
Short Circuit Protection section.
ILIM
10
11
11
12
I/O
I
Mode selection pin for Overload fault response. See the Device Functional
Modes section.
MODE
Shutdown pin. Pulling SHDN low makes the device to enter into low power
shutdown mode. Cycling SHDN pin voltage resets the device that has latched
off due to a fault condition.
SHDN
12
13
I
Analog current monitor output. This pin sources a scaled down ratio of
current through the internal FET. A resistor from this pin to GND converts
current to proportional voltage. If unused, leave this pin floating.
IMON
FLT
13
14
14
15
O
O
Fault event indicator. It is an open drain output. If unused, leave floating or
connect to GND.
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Table 5-1. Pin Functions (continued)
PIN
TPS16530
HTSSOP
TYPE
DESCRIPTION
NAME
VQFN
Active High. A high indicates that the internal FET is enhanced. PGOOD
PGOOD
16
16
O
P
goes low when the internal FET is turned OFF during a fault or when SHDN
is pulled low. If PGOOD is unused then connect to GND or leave it floating.
17
18
—
3
18
19
20
5
OUT
Power Output of the device
4
7
15
19
20
21
22
23
24
17
—
—
—
—
—
—
Internally Not connected. Can be connected to other pins (P_IN, OUT, GND)
for enhanced thermal performance.
N.C
—
—
Connect the PowerPAD to GND plane for heat sinking. Do not use the
PowerPAD as the only electrical connection to GND.
PowerPAD™
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
UNIT
V
IN, P_IN, OUT, UVLO, FLT, PGOOD
Input Voltage
67
5.5
10
EN, dVdT, IMON, MODE, SHDN, ILIM Input Voltage
IFLT, IdVdT, IPGOOD
Sink current
mA
IdVdT, IILIM , IMODE, ISHDN
Source current
Internally limited
Operating Junction temperature
Transient junction temperature
Storage temperature
–40
–40
–65
150
T(TSD)
150
TJ
°C
Tstg
(1)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
0
NOM
MAX
58
58
4
UNIT
IN, P_IN
OUT, UVLO, PGOOD, FLT
Input Voltage
V
EN, dVdT, IMON, MODE
0
SHDN
ILIM
0
5
Resistance
Resistance
4
30
kΩ
IMON
IN, P_IN, OUT
dVdT
1
0.1
10
–40
µF
nF
°C
External Capacitance
TJ
Operating Junction temperature
25
125
6.4 Thermal Information
TPS16530
THERMAL METRIC(1)
RGE (VQFN)
PWP (HTSSOP)
UNIT
24 PINS
32.1
26
20 PINS
31.2
22.5
8.9
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
9.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.3
0.3
ΨJB
9.7
8.8
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6.4 Thermal Information (continued)
TPS16530
THERMAL METRIC(1)
RGE (VQFN)
24 PINS
3
PWP (HTSSOP)
20 PINS
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.9
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
–40°C ≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 58 V, V(SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN,
C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE
V(IN), V(P_IN)
IQ(ON)
Operating input voltage
Supply current
4.5
58
1.7
60
V
Enabled: V(SHDN) = 2 V
1.38
21
mA
µA
IQ(OFF)
V(SHDN) = 0 V
UNDERVOLTAGE LOCKOUT (UVLO) INPUT
V(UVLOR)
V(UVLOF)
I(UVLO)
UVLO threshold voltage, rising
UVLO threshold voltage, falling
UVLO Input leakage current
1.176
1.09
1.2
1.122
30
1.224
1.15
150
V
V
0 V ≤ V(UVLO) ≤ 58 V
–150
nA
Enable (EN) INPUT
V(ENR)
Enable threshold voltage, rising
Enable threshold voltage, falling
Enable Input leakage current
1.25
150
V
V
V(ENF)
0.65
I(EN)
0 V ≤ V(EN) ≤ 4 V
–150
13.5
nA
CURRENT LIMIT PROGRAMMING (ILIM)
I(OL)
Over Load current limit
R(ILIM) = 30 kΩ, V(IN) – V(OUT) = 1 V
R(ILIM) = 9 kΩ, V(IN) – V(OUT) = 1 V
R(ILIM) = 4.02 kΩ, V(IN) – V(OUT) = 1 V
4 kΩ < R(ILIM) < 30 kΩ
0.54
1.84
0.6
2
0.66
2.16
A
A
A
A
A
A
I(OL)
Over Load current limit
I(OL)
Over Load current limit
4.185
4.5
4.815
I(OL_Pulse)
I(FASTRIP)
I(SCP)
Transient Pulse Over current limit
Fast-trip comparator threshold
Short Circuit Protect current
2 × I(OL)
3 × I(OL)
45
PASS FET OUTPUT (OUT)
RON
RON
IN to OUT total ON resistance
0.6 A ≤ I(OUT) ≤ 4.5 A,TJ = 25°C
0.6 A ≤ I(OUT) ≤ 4.5 A,TJ = 85°C
26
33
30.44
30.44
34.5
45
mΩ
mΩ
IN to OUT total ON resistance
IN to OUT total ON resistance
0.6 A ≤ I(OUT) ≤ 4.5 A, –40°C ≤ TJ ≤
+125°C
RON
19
53
mΩ
OUTPUT RAMP CONTROL (dVdT)
I(dVdT)
dVdT charging current
V(dVdT) = 0 V
1.775
23.5
3.8
2
25
2.225
26
µA
V/V
V
GAIN(dVdT)
V(dVdTmax)
R(dVdT)
dVdT to OUT gain
V(OUT) /V(dVdT)
dVdT maximum capacitor voltage
dVdT discharging resistance
4.17
16.6
4.75
26.6
10
Ω
LOW IQ SHUTDOWN (SHDN) INPUT
V(SHDN)
Open circuit voltage
I(SHDN) = 0.1 µA
2.48
0.8
2.7
3.3
2
V
V
SHDN threshold voltage for low IQ
shutdown, falling
V(SHUTF)
V(SHUTR)
I(SHDN)
SHDN threshold rising
Leakage current
V
V(SHDN) = 0 V
–10
µA
CURRENT MONITOR OUTPUT (IMON)
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6.5 Electrical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 58 V, V(SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN,
C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
25.66
26.22
TYP
27.9
27.9
MAX UNIT
30.14 µA/A
29.58 µA/A
GAIN(IMON)
Gain factor I(IMON):I(OUT)
0.6 A ≤ I(OUT) ≤ 2 A
2 A ≤ I(OUT) ≤ 4.5 A
0 V ≤ V(FLT) ≤ 58 V
0 V ≤ V(PGOOD) ≤ 58 V
FAULT FLAG (FLT): ACTIVE LOW
R(FLT) FLT Pull-down resistance
I(FLT) FLT Input leakage current
POWER GOOD (PGOOD)
R(PGOOD) PGOOD Pull-down resistance
I(PGOOD) PGOOD Input leakage current
THERMAL PROTECTION
T(J_REG) Thermal regulation set point
36
74
30
130
150
Ω
–150
nA
36
74
130
150
Ω
–150
nA
136
145
165
11
154
ºC
ºC
ºC
Thermal shutdown (TSD) threshold,
rising
T(TSD)
T(TSDhyst)
TSD hysteresis
Mode selection
MODE
MODE = Open
Latch
MODE_SEL
Auto –
Retry
MODE = Short to GND
6.6 Timing Requirements
–40°C ≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 58 V, V(SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN,
C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
UVLO INPUT (UVLO)
UVLO↑ (100 mV above V(UVLOR)) to
V(OUT) = 100 mV, C(dVdT) ≥ 10
nF, [C(dVdT) in nF]
742 +
49.5 x
C(dVdT)
UVLO_ton(dly)
UVLO switch turnon delay
µs
UVLO_toff(dly)
tUVLO_FLTdly)
UVLO switch turnoff delay
UVLO↓(20 mV below V(UVLOF)) to FLT↓
UVLO↑ to FLT ↑ delay
9
11
16
µs
µs
UVLO to fault de-assertion delay
500
617
700
ENABLE INPUT (EN)
EN_tOFF(dly)
Enable turn-off delay
EN↑ (20 mV above V(OVPR)) to FLT↓
8.5
11
14
µs
µs
150 +
49.5 x
C(dVdT)
EN↓ (100 mV below V(OVPF)) to FET
ON C(dVdT) ≥ 10 nF, [C(dVdT) in nF]
EN_ton(dly)
Enable turn-on delay
SHUTDOWN CONTROL INPUT (SHDN)
tSD(dly)
SHUTDOWN entry delay
SHDN↓ (below V(SHUTF)) to FET OFF
0.8
1
1.5
µs
CURRENT LIMIT
tFASTTRIP(dly)
tFASTTRIP(dly)
tCL_ILIM(dly)
Hot-short response time
Soft short response
I(OUT) > I(SCP)
1
3.2
µs
µs
I(FASTTRIP) < I(OUT) < I(SCP)
2.2
4.5
Maximum duration in current limit
129
162
202
ms
Maximum duration in 2x Pulse current
limiting
tCB(dly)
I(OL) < I(OUT) ≤ I(2xOL)
20
25.5
1.3
31
ms
ms
tCL_ILIM_FLT(dly)
FLT delay in current limit
1.09
1.6
OUTPUT RAMP CONTROL (dVdT)
C(dVdT) = Open, 10% to 90%
V(OUT), C(OUT) = 1 µF; V(IN) = 24V
t(FASTCHARGE)
Output ramp time in fast charging
350
495
700
µs
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6.6 Timing Requirements (continued)
–40°C ≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 58 V, V(SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN,
C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
C(dVdT) = 22 nF, 10% to 90%
V(OUT), V(IN) = 24V
t(dVdT)
Output ramp time
8.35
ms
POWER GOOD (PGOOD)
tPGOODR
PGOOD delay (deglitch) time
Rising edge
Falling edge
8
8
11.5
10
13
13
ms
ms
tPGOODF
PGOOD delay (deglitch) time
FAULT FLAG (FLT)
FLT assertion delay in Pulse over
current limiting
tCB_FLT(dly)
Delay from I(OUT) > I(OL) to FLT↓.
MODE = GND
22
25.5
30
ms
THERMAL PROTECTION
t(TSD_retry)
Retry delay in TSD
Thermal Regulation timeout
500
1
648
1.3
800
1.6
ms
s
t(Treg_timeout)
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6.7 Typical Characteristics
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = V(P_IN) = 24 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN, C(OUT) = 1
μF, C(dVdT) = OPEN. (Unless stated otherwise)
48
TA = 125C
TA = 85C
TA = 25C
TA = -40C
45
42
39
36
33
30
27
24
21
18
15
12
9
6
0
5
10 15 20 25 30 35 40 45 50 55 60
VIN (V)
Figure 6-1. On-Resistance vs Temperature Across Load Current
Figure 6-2. Input Supply Current vs Supply Voltage in Shutdown
1.46
5
TA = 125C
4.5
TA = 85C
TA = 25C
TA = -40C
1.44
1.42
1.4
4
3.5
3
RILIM = 30k
RILIM = 18k
RILIM = 9k
RILIM = 4.02k
1.38
1.36
1.34
1.32
1.3
2.5
2
1.5
1
0.5
0
0
5
10 15 20 25 30 35 40 45 50 55 60
VIN (V)
-40
-20
0
20
40
60
80
100 120 140
Temperature (C)
Figure 6-3. Input Supply Current vs Supply Voltage During
Normal Operation
Figure 6-4. Overload Current Limit vs Temperature
IOUT = 4.5 A
Figure 6-5. Current Monitor Gain vs Output Current
Figure 6-6. IMON Offset vs Temperature
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6.7 Typical Characteristics (continued)
–40°C ≤ TA = TJ ≤ +125°C, V(IN) = V(P_IN) = 24 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN, C(OUT) = 1
μF, C(dVdT) = OPEN. (Unless stated otherwise)
2000
1000
500
2000
1000
500
TA = -40C
TA = 0C
TA = 25C
TA = 85C
TA = 125C
TA = -40C
TA = 0C
TA = 25C
TA = 85C
TA = 125C
200
100
50
200
100
50
20
10
5
20
10
5
2
1
2
1
0.5
0.5
0.2
0.2
5 6 7 8 10
20 30 40 50 70 100
Power Dissipation (W)
200 300 500
4
5 6 7 8 10
20 30 40 50 70 100
Power Dissipation (W)
200 300400
Taken on HTSSOP with 110 cm2 copper connected to
Exposed PAD
Taken on VQFN device with 95 cm2 copper connected to
Exposed PAD
Figure 6-8. Thermal Shutdown Time vs Power Dissipation for
PWP Package
Figure 6-7. Thermal Shutdown Time vs Power Dissipation for
RGE Package
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7 Parameter Measurement Information
V(OUT)
VUVLO
V(UVLOF)-0.02 V
0.1 V
VUVLO
FLT
V(UVLOR)+0.1V
10%
time
0
time
0
UVLO_tON(dly)
UVLO_toff(dly)
V(ENR)+0.02V
V(EN)
V(OUT)
0.1 V
FLT
VEN
V(ENF)-0.02 V
10%
0
0
time
time
EN_tOFF(dly)
EN_tON(dly)
V(OUT)
I(FASTRIP)
I(OL)
I(OUT)
I(OUT)
2×IOL
IOL
tCL_ILIM(dly)
0
tCL_ILIM(dly)
time
0
tCB(dly)
tFASTRIP(dly)
Figure 7-1. Timing Waveforms
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8 Detailed Description
8.1 Overview
The TPS16530 is a 58-V industrial eFuse. The device provides robust protection for all systems and applications
powered from 4.5 V to 58 V. For hot-pluggable boards, the device provides hot-swap power management with
in-rush current control and programmable output voltage slew rate features using the dVdT pin. Load, source
and device protections are provided with many programmable features including overcurrent and undervoltage.
The precision overcurrent limit (±7% at 6 A) helps to minimize over design of the input power supply, while the
fast response short circuit protection 1 µs (typical) immediately isolates the faulty load from the input supply
when a short circuit is detected.
The device provides precise monitoring of voltage bus for brown-out and overvoltage conditions and asserts fault
signal for the downstream system. The device's overall threshold accuracy of 2% ensures tight supervision of
bus, eliminating the need for a separate supply voltage supervisor chip.
Additional features of the TPS16530 include:
•
•
±6% current monitor output (IMON) for health monitoring of the system
A choice of latch off or automatic restart mode response during current limit and thermal fault using MODE
pin
•
•
•
•
•
PGOOD indicator output
Over temperature protection to safely shutdown in the event of an overcurrent event
De-glitched fault reporting for faults
Enable and Disable control from an MCU using EN pin
Low power shutdown using SHDN pin
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8.2 Functional Block Diagram
OUT
IN
P_IN
31 m
Charge
Pump
Current
Sense
P_IN
+
+
PORb
X27.9 µ
IMON
4.3 V
4.2 V
CP
UVLO
5 V
Gate Control Logic
Current Limit Amp
UVLOb
1.2 V
1.12 V
SWEN
Fast-Trip Comp
(Threshold= 45A)
Timeout
tCB(dly)
tCL_ILIM(dly)
ILIM
TSD
Thermal
Shutdown
OLR
Open/ Short
detect
EN
+
EN
SHDNb
1.25 V
0.65 V
4.17V
Ramp Control
2µA
25x
SWEN
FLT
* Only for Latch Mode
dVdT
70
SET
UVLOb
PORb
S
Q
16
TSD
CLR
R
Q
SHDNb
GND
PORb
Fault Latch
Gate Enhanced
(HS_FET)
PGOOD
11.5 ms
10 ms
1.2 Meg
SET
S
R
Q
Q
MODE
3V
2.7V
Overload fault response
(Auto-Retry/Latch-off)
select detection
65
OLR
10 µsec
0.8V
CLR
UVLOb
SHDNb
+
SHDNb
TPS16530
SHDN
8.3 Feature Description
8.3.1 Hot Plug-In and In-Rush Current Control
The devices are designed to control the inrush current upon insertion of a card into a live backplane
or other "hot" power source. This limits the voltage sag on the backplane’s supply voltage and prevents
unintended resets of the system power. The controlled start-up also helps to eliminate conductive and radiative
interferences. An external capacitor connected from the dVdT pin to GND defines the slew rate of the output
voltage at power-on. The fastest output slew rate of 24V/500 µs can be achieved by leaving dVdT pin floating.
The inrush current can be calculated using Equation 1.
dV
dT
V(IN)
tdVdT
I = Cì
í I(INRUSH) = C(OUT) ì
(1)
where
tdVdT = 20.8 × 103 × V(IN) × C(dVdT)
(2)
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Figure 8-1 illustrates in-rush current control performance of the device during Hot Plug-In.
VIN
VOUT
PGOOD
IIN
CdVdT = 100 nF
COUT = 1000 µF
RILIM = 4.02 kΩ
Figure 8-1. Hot Plug In and Inrush Current Control at 24-V Input
8.3.1.1 Thermal Regulation Loop
The average power dissipation within the eFuse during power up with a capacitive load can be calculated using
Equation 3.
PD(INRUSH) = 0.5ì V(IN) ìI(INRUSH)
(3)
System designs requiring to charge large output capacitors rapidly may result in an operating point that exceeds
the power dissipation versus time boundary limits of the device defined by Figure 6-7 characteristic curve. This
may result in increase in junction temperature beyond the device's maximum allowed junction temperature.
To keep the junction temperature within the operating range, the thermal regulation control loop regulates the
junction temperature at T(J_REG) , 145°C (typical) by controlling the inrush current profile and thereby limiting
the power dissipation within the device automatically. An internal 1.3 sec (typical), t(Treg_timeout) timer starts from
the instance the thermal regulation operation kicks in. If the output does not power up within this time then the
internal FET is turned OFF. Subsequent operation of the device depends on the MODE configuration (Auto-Retry
or latch OFF) setting as per the Table 8-2. The maximum time-out of 1.3 sec (typical) in thermal regulation loop
operation ensures that the device and the system board does not heat up during steady fault conditions such as
wake up with output short-circuit. This scheme ensures reliable power up operation.
Thermal regulation control loop is internally enabled during power up by V(IN), UVLO cycling and turn ON using
SHDN control. Figure 8-2 illustrates performance of the device operating in thermal regulation loop during power
up by V(IN) with a large output capacitor. The Thermal regulation loop gets disabled internally after the power up
sequence when the internal FET's gate gets fully enhanced or when the t(Treg_timeout) of 1.3 sec (typical) time is
elapsed.
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CdVdT = Open
VIN = 35 V
RILIM = 4.02 kΩ
Figure 8-2. Thermal Regulation Loop Response During Power Up With 4.7-mF Capacitive Load
8.3.2 Undervoltage Lockout (UVLO)
The TPS16530 device features an accurate ± 2% adjustable undervoltage lockout functionality. When the
voltage at UVLO pin falls below V(UVLOF) during input undervoltage fault, the internal FET quickly turns off and
FLT is asserted. The UVLO comparator has a hysteresis of 78 mV (typical). To set the input UVLO threshold,
connect a resistor divider network from IN supply to UVLO terminal to GND as shown in Figure 8-3. If the
Under-Voltage Lock-Out function is not needed, the UVLO terminal must be connected to the IN terminal. UVLO
terminal must not be left floating.
V(IN)
IN
P_IN
R1
UVLO
+
UVLOb
1.2 V
R2
1.12 V
Figure 8-3. UVLO Thresholds Set by R1 and R2
8.3.3 Overload and Short Circuit Protection
The device monitors the load current by sensing the voltage across the internal sense resistor. The FET current
is monitored during start-up and normal operation.
8.3.3.1 Overload Protection
The TPS16530 device features accurate overload current limiting and fast short circuit protection feature. The
device supports a pulse current up to 9A (2 × IOL) for transient loads. Table 8-1 describes the overload response
of TPS16530 device.
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Table 8-1. Overload Response of TPS16530 Device
Output Current
Overload or Over-Current Response
IOUT < IOL
No action. Device provides current up-to IOL
Device provides current up to 2 × IOL for a duration of tCB(dly) and then limits current to IOL for a
maximum duration of tCL_ILIM(dly)
Device limits current to 2 × IOL for a maximum duration of tCB(dly) and then limits current to IOL for a
maximum duration of tCL_ILIM(dly)
.
IOL ≤ IOUT < 2 × IOL
2 × IOL ≤ IOUT < 3 × IOL
3 × IOL ≤ IOUT
.
.
Device provides fast trip protection or short circuit protection and turns off the internal FET. See the
Short Circuit Protection section.
The power dissipation across the device during this operation will be [(VIN – VOUT) × IOL] for IOUT < 2 × IOL or
[(VIN – VOUT) × 2 × IOL] for 2 × IOL < IOUT < 3 × IOLand this could heat up the device and eventually enter into
thermal shutdown.
For current limit of IOL, the maximum duration for current limiting is tCL_ILIM(dly), 162 msec (typical). For current
limit of 2 × IOL, the maximum duration for current limiting is tCB(dly), 25 msec (typical) .
If the thermal shutdown occurs before this time the internal FET turns OFF and the device operates either in
auto-retry or latch off mode based on MODE pin configuration in Table 8-2. Set the current limit using Equation
4.
18
IOL
=
RILIM
(4)
where
•
•
I(OL) is the overload current limit in Ampere
R(ILIM) is the current limit resistor in kΩ
During the overload current limiting, if the overload condition exists for more than tCL_ILIM_FLT(dly), 1.3 msec
(typical), the FLT asserts to warn of impending turnoff of the internal FETs due to the subsequent thermal
shutdown event or due to tCL_ILIM(dly) timer expiry. The FLT signal remains asserted until the fault condition is
removed and the device resumes normal operation. Figure 8-4 shows the device behavior in case of overload
event. The device provides a pulse current of 7 A for a duration of 25 ms and then turns off the internal FET due
to thermal shutdown before the expiry of tCL_ILIM(dly)
.
The 2 × I(OL) pulse current support is activated only after PGOOD goes high. If PGOOD is in low state such as
during start-up operation or during auto-retry cycles, the 2 × I(OL) pulse current support is not activated and the
device limits the current at I(OL) level.
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VIN = 58 V
ILIM = 4.5 A
IOUT = 4 A to 7 A
Figure 8-4. Pulse Current Support
The TPS16530 device feature ILIM pin short and open fault detection and protection. The internal FET is turned
OFF when ILIM pin is detected short or open to GND and it remains OFF till the ILIM pin fault is removed.
8.3.3.2 Short Circuit Protection
During a transient output short circuit event, the current through the device increases rapidly. As the current-limit
amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip
comparator. The fast-trip comparator architecture is designed for fast turn OFF tFASTTRIP(dly) = 1 µs (typical)
with I(SCP) = 45 A of the internal FET during an output short circuit event. The fast-trip threshold is internally
set to I(FASTTRIP). The fast-trip circuit holds the internal FET off for only a few microseconds, after which the
device turns back on slowly, allowing the current-limit loop to regulate the output current to I(OL). Then the device
functions similar to the overload condition. Figure 8-5 illustrates output hot-short performance of the device.
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VOUT
IIN
IMON
FLTb
VIN = 50 V
RILIM = 18 kΩ
Figure 8-5. Output Hot-Short Response
The fast-trip comparator architecture has a supply line noise immunity resulting in a robust performance in noisy
environments. This performance is achieved by controlling the turn OFF time of the internal FET based on
the overcurrent level, I(FASTTRIP), through the device. The higher the overcurrent, the faster the turn OFF time,
tFASTTRIP(dly). At Overload current level in the range of IFASTTRIP < IOUT < ISCP, the fast-trip comparator response
is 3.2 µs (typical).
8.3.3.2.1 Start-Up With Short-Circuit On Output
When the device is started with short-circuit on the output, the current begins to limit at I(OL). Due to high
power dissipation of VIN × I(OL) within the device the junction temperature increases. Subsequently, the thermal
regulation control loop limits the load current to regulate the junction temperature at T(J_REG), 145°C (typical)
for a duration off t(Treg_timeout), 1.25 sec (typical). Subsequent operation of the device depends on the MODE
configuration (Auto-Retry or latch OFF) setting as per Table 8-2. FLT gets asserted after t(Treg_timeout) and
remains asserted till the output short-circuit is removed. Figure 8-6 illustrates the behavior of the device in this
condition.
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VIN = 58 V
ILIM = 4.5 A
Figure 8-6. Start-Up With Short on Output
8.3.4 Current Monitoring Output (IMON)
The TPS16530 device features an accurate analog current monitoring output. A current source at IMON terminal
is internally configured to be proportional to the current flowing from IN to OUT. This current can be converted
into a voltage using a resistor R(IMON) from IMON terminal to GND terminal. The IMON voltage can be used as
a means of monitoring current flow through the system. The maximum voltage (V(IMONmax) for monitoring the
current is limited to 4 V. This limit puts a limitation on maximum value of R(IMON) resistor and is determined by
Equation 5.
V
(
IMON
)
= I
[
(
OUT
)
ìGAIN
(
IMON
)
ìR
(
IMON
)
]
(5)
Where,
•
•
GAIN(IMON) is the gain factor I(IMON):I(OUT) = 27.9 μA/A (typical)
I(OUT) is the load current
See Figure 6-5 for IMON gain versus load current (0.01 to 4.5 A) and Figure 6-6 for IMON Offset versus
Temperature plots. Figure 6-6 illustrates IMON performance.
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VIN
VOUT
IMON
IIN
Figure 8-7. IMON Response During a Load Step
The IMON pin must not have a bypass capacitor to avoid delay in the current monitoring information.
8.3.5 FAULT Response (FLT)
The FLT open-drain output asserts (active low) under the faults events such as undervoltage, overload, current
limiting, ILIM pin short and thermal shutdown conditions. The device is designed to eliminate false reporting by
using an internal "de-glitch" circuit for fault conditions without the need for an external circuitry. FLT can be left
open or connected to GND when not used.
8.3.6 Power Good Output (PGOOD)
The devices feature an open drain Power good (PGOOD) indicator output. PGOOD can be used for enable and
disable control of the downstream loads like DC/DC converters. PGOOD goes high when the internal FET’s gate
is enhanced. It goes low when the internal FET turns OFF during a fault event or when SHDN is pulled low
or when EN is pulled high. There is a deglitch of 11.5 msec (typical), tPGOODR, at the rising edge and 10 msec
(typical), tPGOODF, on falling edge. PGOOD is a rated for 58 V and can be pulled to IN or OUT through a resistor.
8.3.7 IN, P_IN, OUT and GND Pins
Connect a minimum of 0.1-µF capacitor across IN and GND. Connect P_IN and IN together. Do not leave any of
the IN and OUT pins unconnected.
8.3.8 Thermal Shutdown
The device has a built-in overtemperature shutdown circuitry designed to protect the internal FET if the junction
temperature exceeds T(TSD), 165°C (typical). After the thermal shutdown event, depending upon the mode of
fault response configured as shown in Table 8-2, the device either latches off or commences an auto-retry cycle
of 648 msec (typical), t(TSD_retry) after TJ < [T(TSD) – 11°C]. During the thermal shutdown, the fault pin FLT pulls
low to indicate a fault condition.
8.3.9 Low Current Shutdown Control (SHDN)
The internal and the external FET and hence the load current can be switched off by pulling the SHDN pin below
a 0.8-V threshold with a micro-controller GPIO pin or can be controlled remotely with an opto-isolator device.
The device quiescent current reduces to 21 μA (typical) in shutdown state. To assert SHDN low, the pull down
must have sinking capability of at least 10 µA. To enable the device, SHDN must be pulled up to at least 2 V.
Once the device is enabled, the internal FET turns on with dVdT mode.
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8.3.10 Enable Input (EN)
The EN pin can be used to turn-on or turn-off the internal FET. EN can be used with a 1.8-V Digital IO of FPGA
or MCU. For rising and falling thresholds of EN pin. See VENR and VENF in Electrical Characteristics. After the EN
is made low, the output ramps with slew rate configured by dVdT pin.
EN pin does not reset the latch in latch mode (MODE = Open) and making EN pin high asserts the FLT pin. See
the Parameter Measurement Information for the behavior of FLT with EN pin.
8.4 Device Functional Modes
The TPS16530 device respond differently to overload with MODE pin configurations. Table 8-2 lists the
operational differences.
Table 8-2. Device Operational Differences Under Different MODE Configurations
MODE Pin Configuration
Current Limiting, Over Current Fault and Thermal Shutdown Operation
Active Current limiting for a maximum duration of tCL_ILIM(dly). There after Latches OFF. Latch
reset by toggling SHDN or UVLO low to high or power cycling IN.
Open
Active Current limiting for a maximum duration of tCL_ILIM(dly). There after auto-retries after a
Shorted to GND
delay of t(TSD_retry)
.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS16530 is a 58-V eFuse, typically used for Hot-Swap and Power rail protection applications. The device
operates from 4.5 V to 58 V with programmable current limit, undervoltage protections. The device aids in
controlling in-rush current and provides current limiting for systems such as telecom radios and industrial
printers. The device also provides robust protection for multiple faults on the system rail.
The Detailed Design Procedure section can be used to select component values for the device.
9.2 Typical Application
VIN : 20 - 50V
VOUT
IN
OUT
COUT
100 µF
P_IN
31m
R1
887 k
PGOOD
FLT
UVLO
TPS16530
R2
63.4 k
SHDN
IMON
ILIM
EN
RIMON
30 k
dVdT
22 nF
RILIM
18 k
MODE
GND
Figure 9-1. 20 V–50 V, 1-A eFuse Protection Circuit for Telecom Radios
9.2.1 Design Requirements
Table 9-1 shows the Design Requirements for TPS16530.
Table 9-1. Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
20 V–50 V
18 V
V(IN)
Input voltage range
V(UV)
I(LIM)
COUT
I(INRUSH)
Undervoltage lockout set point
Overload Current limit
Output capacitor
1 A
100 µF
Inrush Current limit
300 mA
9.2.2 Detailed Design Procedure
9.2.2.1 Programming the Current-Limit Threshold R(ILIM) Selection
The R(ILIM) resistor at the ILIM pin sets the overload current limit, which can be set using Equation 6.
18
R(ILIM
=
= 18kW
)
IOL
(6)
where
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•
ILIM = 1 A
Choose the closest standard 1% resistor value: R(ILIM) = 18 kΩ
9.2.2.2 Undervoltage Lockout and Overvoltage Set Point
The Undervoltage Lockout (UVLO) trip point are adjusted using an external voltage divider network of R1 and R2
connected between IN, UVLO, and GND pins of the device. The values required for setting the undervoltage are
calculated by solving V(UVLOR) = R2 / (R1+R2) × V(UV_IN)
.
For minimizing the input current drawn from the power supply, {I(R12) = V(IN) / (R1 + R2 )}, TI recommends to use
higher value resistance for R1 and R2.
However, the leakage current due to external active components connected at resistor string can add error to
these calculations. So, the resistor string current, I(R12) must be chosen to be 20 times greater than the leakage
current of UVLO pin.
Choose the closest standard 1% resistor values: R1 = 887 kΩ, R2 = 63.4 kΩ.
9.2.2.3 Setting Output Voltage Ramp Time (tdVdT
)
Use Equation 1 and Equation 2 to calculate required C(dVdT) for achieving an inrush current of 300 mA. C(dVdT)
= 22 nF. Figure 9-2 and Figure 9-3 illustrate the inrush current limiting performance during 50-V hot-plug in
condition.
9.2.2.3.1 Support Component Selections RPGOOD and C(IN)
The RPGOOD serves as pull-up for the open-drain output. The current sink by this pin must not exceed 10 mA
(see the Absolute Maximum Ratings table). TI recommends typical resistance value in the range of 10 kΩ to
100 kΩ for RPGOOD. Figure 9-6 illustrates the power up performance of the system. The CIN is a local bypass
capacitor to suppress noise at the input. TI recommends a minimum of 0.1 µF for C(IN)
.
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9.2.3 Application Curves
VIN
VIN
VOUT
VOUT
PGOOD
PGOOD
IIN
IIN
Figure 9-2. Hot-Plug In at 50-V Supply with No
Load
Figure 9-3. Hot-Plug In at 50-V Supply with 60-Ω
Load
VOUT
IIN
IMON
FLTb
Figure 9-5. Output Hot-short Performance with 50-
V Input Supply
ILIM = 4.5 A
Figure 9-4. Overload Performance During Load
Step from 4 A to 7 A
SHDNb
SHDNb
VOUT
VOUT
PGOOD
PGOOD
IIN
IIN
Figure 9-6. Turn ON Using SHDN Control
Figure 9-7. Turn OFF Using SHDN Control
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9.3 System Examples
9.3.1 48-V Power Amplifier Protection for Telecom Radios
With the TPS16530, a simple 48-V power supply path protection can be realized for telecom radios. Figure
9-8 shows the simplified schematic for this. For start-up with negative gate voltage drive at GaN FETs, TI
recommends to use appropriate resistors for biasing the gate of GaN FETs to keep VOUT > –0.2 V and IOUT < 70
μA from TPS16530.
VOUT
IN
OUT
48V-52V
D
UVLO
CIN
31 m
G
GaN
FET
PGOOD
FLT
S
TPS16530
SHDN
IMON
dVdT
ILIM
EN
RIMON
MODE
RILIM
GND
Figure 9-8. TPS16530 Configured for 48-V Power Amplifier Protection
Protection features with this configuration include:
•
•
Accurate current limiting with pulse current support
Inrush current control with 24-V/500-µs output voltage slew rate
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10 Power Supply Recommendations
The TPS16530 eFuse is designed for the supply voltage range of 4.5 V ≤ VIN ≤ 58 V. If the input supply is
located more than a few inches from the device, TI recommends an input ceramic bypass capacitor higher than
0.1 μF. Power supply must be rated higher than the current limit set to avoid voltage droops during overcurrent
and short circuit conditions.
10.1 Transient Protection
In case of short circuit and overload current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the
input or output of the device. These transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include:
•
•
•
•
Minimizing lead length and inductance into and out of the device
Using large PCB GND plane
Use of a Schottky diode across the output and GND to absorb negative spikes
A low value ceramic capacitor (C(IN) to approximately 0.1 μF) to absorb the energy and dampen the
transients.
The approximate value of input capacitance can be estimated with Equation 7.
L IN
( )
Vspike Absolute = V IN + I Load
( ) )
´
(
)
(
C IN
( )
(7)
where
•
•
•
•
V(IN) is the nominal supply voltage
I(LOAD) is the load current
L(IN) equals the effective inductance seen looking into the source
C(IN) is the capacitance present at the input
Some applications may require additional Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device. These transients can occur during positive and
negative surge tests on the supply lines. In such applications, TI recommends to place at least 1 µF of input
capacitor.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 10-1.
Input
Output
COUT
IN
OUT
P_IN
*
31 m
*
R1
R2
PGOOD
FLT
UVLO
TPS16530
SHDN
EN
IMON
ILIM
dVdT
CdVdT
MODE
RILIM
GND
* Optional components needed for suppression of transients
Figure 10-1. Circuit Implementation with Optional Protection Components for TPS16530
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11 Layout
11.1 Layout Guidelines
•
•
•
•
For all the applications, a 0.1 µF or higher value ceramic decoupling capacitor is recommended between IN
terminal and GND.
High current carrying power path connections must be as short as possible and must be sized to carry at
least twice the full-load current. See Figure 11-1 and Figure 11-2 for a typical PCB layout example.
Locate all the TPS16530 device support components R(ILIM), C(dVdT), R(IMON), UVLO resistors close to the
device pin. Connect the other end of the component to the GND with shortest trace length.
The trace routing for the R(ILIM) component to the device must be as short as possible to reduce parasitic
effects on the current limit accuracy. These traces must not have any coupling to switching signals on the
board.
•
•
Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT and GND pins.
Thermal Considerations: When properly mounted, the PowerPAD package provides significantly greater
cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board GND plane
directly under the device. Other planes, such as the bottom side of the circuit board, can be used to increase
heat sinking in higher current applications.
Copyright © 2021 Texas Instruments Incorporated
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www.ti.com
11.2 Layout Example
Top Layer
Bottom layer GND plane
Top Layer GND Plane
Via to Bottom Layer
BOTTOM Layer GND Plane
High
Frequency
Bypass cap
D2
D1
VOUT PLANE
OUT
OUT
IN
IN
N.C
PGOOD
N.C
P_IN
N.C
FLT
UVLO
IMON
TOP Layer
GND Plane
BOTTOM Layer GND Plane
Figure 11-1. PCB Layout Example With QFN Package With a 2-Layer PCB
Copyright © 2021 Texas Instruments Incorporated
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www.ti.com
BOTTOM Layer GND Plane
High
Frequency
Bypass cap
COUT
D2
D1
VIN PLANE
VOUT PLANE
IN
IN
OUT
OUT
OUT
N.C
IN
P_IN
PGOOD
FLT
N.C
UVLO
N.C
IMON
EN
SHDN
MODE
GND
ILIM
dVdT
Top Layer
TOP Layer
GND Plane
Bottom layer GND plane
Top Layer GND Plane
BOTTOM Layer GND Plane
Via to Bottom Layer
Figure 11-2. Typical PCB Layout Example With HTSSOP Package With a 2-Layer PCB
Copyright © 2021 Texas Instruments Incorporated
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
•
TPS1653 Design Calculator
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
PowerPAD™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS16530PWPR
TPS16530RGER
ACTIVE
ACTIVE
HTSSOP
VQFN
PWP
RGE
20
24
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
TPS16530
NIPDAU
TPS
16530
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Aug-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Aug-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS16530PWPR
TPS16530RGER
HTSSOP PWP
VQFN RGE
20
24
2000
3000
330.0
330.0
16.4
12.4
6.95
4.25
7.0
1.4
8.0
8.0
16.0
12.0
Q1
Q2
4.25
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Aug-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS16530PWPR
TPS16530RGER
HTSSOP
VQFN
PWP
RGE
20
24
2000
3000
853.0
367.0
449.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0020T
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
3
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
0.1 C
A
PIN 1 INDEX
AREA
18X 0.65
SEATING
20
PLANE
1
2X
6.6
6.4
5.85
NOTE 3
10
11
0.30
20X
4.5
4.3
0.19
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 1.15 MAX
NOTE 5
11
10
2X 0.3 MAX
NOTE 5
0.25
1.2 MAX
GAGE PLANE
21
2.96
2.21
0.15
0.05
0.75
0.50
THERMAL
PAD
0 -8
A
15
DETAIL A
TYPICAL
1
20
2.96
2.16
4224598/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0020T
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.96)
METAL COVERED
BY SOLDER MASK
20X (1.5)
SYMM
1
20
20X (0.45)
(R0.05) TYP
(1.3)
TYP
(6.5)
NOTE 9
21
SYMM
(2.96)
SOLDER MASK
DEFINED PAD
18X (0.65)
10
11
(1.3) TYP
SEE DETAILS
(
0.2) TYP
VIA
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
15.000
SOLDER MASK DETAILS
4224598/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0020T
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.96)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
20X (1.5)
1
20
20X (0.45)
(R0.05) TYP
SYMM
21
(2.96)
BASED ON
0.125 THICK
STENCIL
18X (0.65)
11
10
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.31 X 3.31
2.96 X 2.96 (SHOWN)
2.70 X 2.70
0.125
0.15
0.175
2.50 X 2.50
4224598/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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