TPS1H000AQDGNRQ1 [TI]
具有可调节电流限制的 40V、1Ω、汽车类单通道智能高侧开关 | DGN | 8 | -40 to 125;
| 型号： | TPS1H000AQDGNRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调节电流限制的 40V、1Ω、汽车类单通道智能高侧开关 | DGN | 8 | -40 to 125 开关 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总33页 (文件大小：2451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS1H000-Q1
ZHCSH03C –AUGUST 2017–REVISED JUNE 2019
TPS1H000-Q1 40V、1Ω 单通道智能高侧开关
1 特性
2 应用
1
•
•
符合汽车应用 应用
具有符合 AEC-Q100 标准的下列结果：
•
•
•
•
•
单通道 LED 驱动器
单通道高侧中继驱动器
车身照明
–
–
–
器件温度 1 级：–40°C 至 125°C 的环境运行温
度范围
高级驾驶员辅助系统 (ADAS) 传感器
一般电阻、电感和电容负载
器件人体放电模型 (HBM) 静电防护 (ESD) 分类
等级 H2
3 说明
器件 CDM ESD 分类等级 C4B
•
•
•
•
单通道 1000mΩ 智能高侧开关
宽工作电压：3.4V - 40V
TPS1H000-Q1 器件是受到全面保护的单通道高侧电源
开关，具有集成式 1000mΩ NMOS 功率 FET。
低待机电流：<500nA
可调节电流限制可通过限制浪涌或过载电流来提高系统
可靠性。高精度电流限制可增强过载保护，从而简化前
沿电源设计。除电流限制以外的 其他可配置特性 能够
在功能、成本和热耗散方面提供相应的设计灵活性。
可调节电流限制（利用外部电阻器）
–
–
≥150mA 时：±15%
≥300mA 时：±10%
•
可配置电流限制后的行为
该器件支持对数字状态输出进行全面诊断。在开启和关
闭状态下皆可进行开路负载检测。无论是否具有
MCU，该器件都能正常运行。“独立”模式支持在隔离型
系统中使用此器件。
–
–
–
“保持”模式
“闭锁”模式（具有可调节的延迟时间）
“自动重试”模式
•
•
支持独立操作（无需 MCU）
器件信息(1)
保护：
–
–
–
–
GND 短路和过载
器件型号
封装
封装尺寸（标称值）
热关断和热振荡
TPS1H000-Q1
HVSSOP (8)
3.00mm × 3.00mm
用于电感负载的负电压钳位
GND 损耗和电池损耗
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
•
诊断:
–
–
–
过载和 GND 短路检测
开路负载和电池短路检测（开启或关闭状态下）
热关断和热振荡
典型方框图
“自动重试”模式下的电流限制保护
3.4 V to 40 V
Supply Voltage
VS
Up to 40 V
Up to 40 V
LED Strings
Relays
IN
DIAG_EN
FAULT
CL
OUT
Sub Module:
Cameras, Sensors
General Resistive, Capacitive,
Inductive Loads
DELAY
GND
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDO6
TPS1H000-Q1
ZHCSH03C –AUGUST 2017–REVISED JUNE 2019
www.ti.com.cn
目录
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 20
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application ................................................. 22
Power Supply Recommendations...................... 23
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
8
9
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 器件和文档支持 ..................................................... 25
11.1 接收文档更新通知 ................................................. 25
11.2 社区资源................................................................ 25
11.3 商标....................................................................... 25
11.4 静电放电警告......................................................... 25
11.5 Glossary................................................................ 25
12 机械、封装和可订购信息....................................... 25
7
4 修订历史记录
Changes from Revision B (March 2018) to Revision C
Page
•
已更改 IN is high and DIAG_EN is high to IN is low and DIAG_EN is low in the Standby Mode section .......................... 21
Changes from Revision A (August 2017) to Revision B
Page
•
•
Added Footnote 2 to the Electrical Characteristics table........................................................................................................ 6
已添加 reverse current protection information to the Reverse-Current Protection section .................................................. 19
Changes from Original (August 2017) to Revision A
Page
•
•
•
•
•
•
•
•
更改了多处位置：“特性”、“应用”和“说明”部分中进行了多处更改 ........................................................................................... 1
Added typical characteristic graphs........................................................................................................................................ 8
Changed text in the second paragraph of the Overview section ........................................................................................ 10
Changed the links for references to 表 2 and 表 3. ............................................................................................................. 14
Added a row to 表 3 ............................................................................................................................................................. 15
Changed text references to 图 24 and 图 25........................................................................................................................ 17
Added application curves and explanatory text.................................................................................................................... 23
Changed "ground pad" to "thermal pad" in Layout Guidelines ............................................................................................ 24
2
Copyright © 2017–2019, Texas Instruments Incorporated
TPS1H000-Q1
www.ti.com.cn
ZHCSH03C –AUGUST 2017–REVISED JUNE 2019
5 Pin Configuration and Functions
DGN PowerPAD™ Package
8-Pin HVSSOP With Exposed Thermal Pad
Top View
IN
DIAG_EN
FAULT
CL
1
2
3
4
8
7
6
5
VS
OUT
GND
Thermal
Pad
DELAY
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
4
CL
O
I/O
I
Adjustable current limit. Connect to device GND if external current limit is not used.
Function configuration when in current limit; internal pullup
Enable the diagnostic function
DELAY
DIAG_EN
FAULT
GND
5
2
3
O
—
I
Open-drain diagnostic status output. Leave floating if not used
Ground pin
6
IN
1
Input control for output activation; internal pulldown
Output, source of the high-side switch, connected to the load
Power supply, drain for the high-side switch.
OUT
7
O
I
VS
8
Thermal pad
—
—
Thermal pad. Connect to device GND or leave floating.
Copyright © 2017–2019, Texas Instruments Incorporated
3
TPS1H000-Q1
ZHCSH03C –AUGUST 2017–REVISED JUNE 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)(2)
MIN
—
MAX
42
—
250
VS
—
7
UNIT
V
Supply voltage VS pin
Reverse polarity voltage
Current on GND
t < 400 ms
(3)
t < 1 minute
t < 2 minutes
–36
–100
–0.3
–10
–0.3
–60
–0.3
–30
–0.3
—
V
mA
V
Voltage on IN and DIAG_EN pins
Current on IN and DIAG_EN pins
Voltage on DELAY pin
Current on DELAY pin
Voltage on FAULT pin
Current on FAULT pin
Voltage on CL pin
mA
V
—
7
mA
V
10
7
mA
V
Current on CL pin
6
mA
V
Voltage on OUT pin
—
42
Inductive load switch-off energy dissipation
single pulse(4)
—
40
mJ
Operating junction temperature
Storage temperature, Tstg
–40
–65
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground.
(3) Reverse polarity condition: VIN = 0 V, reverse current < IR(2), GND pin 1-kΩ resistor in parallel with diode.
(4) Test condition: VVS = 13.5 V, L = 300 mH, TJ = 150°C. FR4 2s2p board, 2 × 70-μm Cu, 2 × 35-μm Cu. 600 mm2 thermal pad copper
area.
6.2 ESD Ratings
VALUE
UNIT
All pins except VS, OUT,
and GND
±2000
Human-body model (HBM), per AEC
Q100-002(1)
V(ESD)
Electrostatic discharge
V
Pins VS, OUT, and GND
±3000
±750
Charged-device model (CDM), per AEC Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
4
NOM
MAX
40
40
5
UNIT
V
VS
Operating voltage
Voltage on IN and DIAG_EN pins
Voltage on FAULT pin
0
V
0
V
Io,nom
TJ
Nominal dc load current
Operating junction temperature
0
1
A
–40
150
°C
4
Copyright © 2017–2019, Texas Instruments Incorporated
TPS1H000-Q1
www.ti.com.cn
ZHCSH03C –AUGUST 2017–REVISED JUNE 2019
6.4 Thermal Information
TPS1H000-Q1
THERMAL METRIC(1)
DGN (HVSSOP)
UNIT
8 PINS
49.7
50.2
21.4
0.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
21.5
7.1
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.5 Electrical Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
OPERATING VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VVS(nom)
VVS(uvr)
VVS(uvf)
V(uv,hys)
Nominal operating voltage
Undervoltage restart
4
3.5
3
40
4
V
V
V
V
VVS rising
3.7
3.2
0.5
Undervoltage shutdown
VVS falling
3.4
Undervoltage shutdown, hysteresis
OPERATING CURRENT
VVS = 13.5 V, VIN = 5 V, VDIAG_EN
0 V, IOUT = 0.1 A, ICL = 0.5 A.
=
I(op) Nominal operating current
5
0.5
3
mA
µA
VVS = 13.5 V, VIN = VDIAG_EN = VCL
VOUT = 0 V, TJ = 25 °C
=
=
I(off)
Standby current
VVS = 13.5 V, VIN = VDIAG_EN = VCL
VOUT = 0 V, TJ = 125 °C
Standby current with diagnostics
enabled
VVS = 13.5 V, VIN = 0 V, VDIAG_EN
5 V
=
I(off,diag)
t(off,deg)
Ilkg(out)
3
mA
ms
µA
IN from high to low, if deglitch time≥
t(off,deg), the device enters into
standby mode.
Standby-mode deglitch time(1)
12.5
VVS = 13.5 V, VIN = VDIAG_EN = VOUT
= 0 V
Output leakage current in off-state
3
POWER STAGE
VVS ≥ 3.5 V, TJ = 25°C
VVS ≥ 3.5 V, TJ = 150°C
CL pin connected to GND
1000
60%
rDS(on)
On-state resistance
mΩ
2000
1.8
ICL(int)
Internal current limit
1
A
Current-limit value percentage during
thermal shutdown
ICL(TSD)
Drain−to−source voltage internally
clamped
VDS(clamp)
45
65
V
OUTPUT DIODE CHARACTERISTICS
VF
Drain−to-source diode voltage
IN = 0, IOUT = −0.15 A
0.3
0.7
1
1
V
A
Continuous reverse current from
source to drain during a short-to-
battery condition(1)
IR(1)
t < 60 s, VIN= 0 V, TJ = 25°C.
Continuous reverse current from
source to drain during a reverse-
polarity condition(1)
t < 60 s, VIN= 0 V, TJ = 25°C. GND
pin 1-kΩ resistor in parallel with
diode.
IR(2)
1
A
V
LOGIC INPUT (IN, DIAG_EN)
VIH Logic high-level voltage
2
(1) Value specified by design, not subject to production test
Copyright © 2017–2019, Texas Instruments Incorporated
5
TPS1H000-Q1
ZHCSH03C –AUGUST 2017–REVISED JUNE 2019
www.ti.com.cn
Electrical Characteristics (continued)
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIL
Logic low-level voltage
0.8
400
850
V
IN. VIN = 5 V
150
350
Rpd,in
Logic-pin pulldown resistor
kΩ
DIAG_EN. VVS = VDIAG_EN = 5 V
DIAGNOSTICS
Loss of ground output leakage
Ilkg(loss,GND)
100
450
µA
µs
current
VIN = 5 V, VDIAG_EN = 5 V, when IOUT
td(ol,on)
Open-load deglitch time in on-state
< I(ol,on), duration longer than td(ol,on)
,
200
1
300
5
open load is detected.
VIN = 5 V, VDIAG_EN = 5 V, when IOUT
Open-load detection threshold in on-
state
I(ol,on)
< I(ol,on), duration longer than td(ol,on)
,
8
2.6
mA
V
open load is detected.
VIN = 0 V, VDIAG_EN = 5 V, when
VVS – VOUT < V(ol,off), duration longer
than td(ol,off), open load is detected.
Open-load detection threshold in off-
state
V(ol,off)
1.4
VIN = 0 V, VDIAG_EN = 5 V, when
VVS – VOUT < V(ol,off), duration longer
than td(ol,off), open load is detected.
td(ol,off)
Open-load deglitch time in off-state
Off-state output sink current
200
–70
300
450
µs
VIN = 0 V, VDIAG_EN = 5 V, VVS
VOUT = 13.5 V
=
I(ol,off)
µA
VFAULT
tFAULT
T(SD)
FAULT low output voltage
IFAULT = 2 mA
0.2
V
FAULT signal holding time(1)
Thermal shutdown threshold(1)
Thermal shutdown status reset(1)
Thermal swing shutdown threshold(1)
8.5
175
155
60
ms
°C
°C
°C
T(SD,rst)
T(sw)
Hysterisis for resetting the thermal
shutdown and swing(1)
T(hys)
10
°C
CURRENT LIMIT AND DELAY CONFIGURATION
K(CL)
Current-limit current ratio(1)
600
0.8
Current-limit internal threshold
voltage(1)
VCL(th)
V
I
I
I
limit ≥ 0.05 A， VVS – VOUT ≥ 2.5V
–20%
–15%
20%
15%
External current limit accuracy(2)
limit ≥ 0.15 A ， VVS – VOUT ≥ 2.5V
limit ≥ 0.3 A, Ilimit < 1 A， VVS – VOUT
dK(CL)/K(CL) (IOUT – ICL × K(CL)) × 100 / (ICL
K(CL)
×
)
–10%
10%
≥ 2.5V
Delay pin charging current in latch-off
mode(1)
Idl(chg)
Vdl(th)
Vdl(ref)
tdl1
4.5
µA
V
Pulling up threshold in auto-retry
mode
2.7
Internal reference voltage in latch-off
mode
Internal fixed delay time(1)
1.45
400
V
300
500
µs
ms
Adjustable delay time by external
capacitor on DELAY pin(1)
Connect with 3.3 uF capacitor as the
maximum value.
tdl2
1000
IN low to high, VDIAG_EN = 5 V, the
deglitch time from IN rising edge to
FAULT reporting out.
300
80
500
180
(1)
tCL(deg)
Deglitch time when current limit
µs
IN keeps high, VDIAG_EN = 5 V, the
deglitch time from CL start-point to
FAULT reporting out.
thic(on)
thic(off)
On-time when in auto-retry mode(1)
Off-time when in auto-retry mode(1)
35
40
1
45
ms
s
0.8
1.2
(2) External current limit accuracy is only applicable to overload conditions greater than 1.5 x the current limit setting
6
Copyright © 2017–2019, Texas Instruments Incorporated
TPS1H000-Q1
www.ti.com.cn
ZHCSH03C –AUGUST 2017–REVISED JUNE 2019
6.6 Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Turnon delay time, IN rising edge to VVS = 13.5 V, VDIAG_EN = 5 V, IOUT
10% of VOUT = 0.1 A
td(on)
20
50
90
µs
Turnoff delay time, IN falling edge to VVS = 13.5 V, VDIAG_EN = 5 V, IOUT
td(off)
20
0.1
0.3
50
90
0.6
0.9
µs
90% of VOUT
= 0.1 A
Slew rate on, VOUT from 10% to
90%
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT
= 0.1 A
dV/dt(on)
dV/dt(off)
V/µs
V/µs
VVS = 13.5 V, VDIAG_EN = 5 V, IOUT
= 0.1 A
Slew rate off, VOUTfrom 90% to 10%
VIN
90%
90%
dV/dt(off)
dV/dt(on)
VOUT
td(on)
10%
10%
td(off)
图 1. Output Delay Characteristics
Open Load
Open Load
IN
FAULT
td(ol,off)
td(ol,on)
图 2. Open-Load Blanking-Time Characteristic
版权 © 2017–2019, Texas Instruments Incorporated
7
TPS1H000-Q1
ZHCSH03C –AUGUST 2017–REVISED JUNE 2019
www.ti.com.cn
6.7 Typical Characteristics
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
VVS Rising
VVS Falling
IN High
IN Low
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D001
D002
图 3. UVLO Voltage Threshold
图 4. IN Voltage Threshold
1.7
1
0.9
0.8
0.7
0.6
DIAG_EN High
DIAG_EN Low
1.6
1.5
1.4
1.3
1.2
1.1
1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D003
D004
图 5. DIAG_EN Voltage Threshold
图 6. Body-Diode Forward Voltage
55
54
53
52
51
50
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
rDS(on)_3.5V
rDS(on)_13.5V
rDS(on)_40V
0.9
0.8
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D005
D006
图 7. Drain-to-Source Clamp Voltage
图 8. FET On-Resistance
8
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TPS1H000-Q1
www.ti.com.cn
ZHCSH03C –AUGUST 2017–REVISED JUNE 2019
Typical Characteristics (接下页)
-1.5
3.5
3
-2
-2.5
-3
2.5
2
-3.5
-4
1.5
1
-4.5
-5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D007
D008
IOUT = 50 mA
IOUT = 150 mA
图 9. Current-Limit Accuracy at 50 mA
图 10. Current-Limit Accuracy at 150 mA
3
2.5
2
0
-0.5
-1
-1.5
-2
1.5
1
-2.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (°C)
D009
D010
IOUT = 300 mA
图 11. Current-Limit Accuracy at 300 mA
IOUT = 1 A
图 12. Current-Limit Accuracy at 1 A
版权 © 2017–2019, Texas Instruments Incorporated
9
TPS1H000-Q1
ZHCSH03C –AUGUST 2017–REVISED JUNE 2019
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS1H000-Q1 device is a smart high-side switch, with an internal charge pump and single-channel
integrated NMOS power FET. The adjustable current-limit function greatly improves the reliability of the
whole system. Full diagnostic features enable intelligent control of the load.
The external high-accuracy current limit allows setting the current-limit value for the application. When
overcurrent occurs, the device improves system reliability by clamping the inrush current effectively. The
TPS1H000-Q1 device can also save system cost by reducing the size of PCB traces and connectors, and
the capacity of the preceding power stage. The TPS1H000-Q1 device allows three modes when a current
limit occurs. Through the configuration on the DELAY pin, users can set the output to any of three modes:
hold the current consistently, latch off immediately, or retry automatically. The configurable behaviors during
current limit provide design flexibility that considers functionality, cost, and thermal dissipation.
The TPS1H000-Q1 device supports full diagnostics with the digital status output. High-accuracy and low-
threshold open-load detection enables real-time on-state monitoring. The TPS1H000-Q1 device also
supports operation without an MCU, the standalone mode, which allows the system to implement the full
functionality locally.
The TPS1H000-Q1 device is a smart high-side switch for a wide variety of resistive, inductive, and capacitive
loads, including LEDs, relays, and sub-modules.
7.2 Functional Block Diagram
VS
VDS Clamp
Internal Reference
Charge Pump
Gate Driver
IN
DIAG_EN
FAULT
Diagnostics
& Protection
Thermal Monitor
OUT
ON/OFF State
Open Load Detection
Short to GND & Overload
Current Limit
GND
CL
DELAY
10
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7.3 Feature Description
7.3.1 Current Limit
A high-accuracy current limit allows high reliability of the design. It protects the load and the power supply from
overstressing during short-circuit-to-GND or power-up conditions. The current limit can also save system cost by
reducing the size of PCB traces and connectors, and the capacity of the preceding power stage.
When a current-limit threshold is reached, a closed loop activates immediately. The output current is clamped at
the set value, and a fault is reported out. The device heats up due to the high power dissipation on the power
FET.
The device has two current-limit thresholds.
•
Internal current limit – The internal current limit is fixed at ICL(int). Tie the CL pin directly to the device GND for
large-transient-current applications.
•
External adjustable current limit – An external resistor is used to set the current-limit threshold. Use 公式 1 to
calculate R(CL). VCL(th) is the internal band-gap voltage. K(CL) is the ratio of the output current and the current-
limit set value. K(CL) is constant across temperature and supply voltage. The external adjustable current limit
allows the flexibility to set the current-limit value by application.
V
ìK
CL(th)
(CL)
R
=
CL
I
OUT
(1)
Note that if using a GND network which causes a level shift between the device GND and board GND, the CL
pin must be connected to the device GND.
For better protection from a hard short-to-GND condition (when the IN pin is enabled, a short to GND occurs
suddenly), the device implements a fast-trip protection to turn off the output before the current-limit closed loop is
set up. The fast-trip response time is less than 1 µs, typically. With this fast response, the device can achieve
better inrush current-suppression performance.
vs
IOUT/K(CL)
Internal Current Limit
-
+
-
+
+
IOUT
VCL(th)
OUT
External Current Limit
-
+
VCL(th)
CL
图 13. Current Limit
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Feature Description (接下页)
7.3.2 DELAY Pin Configuration
When a current limit occurs, the TPS1H000-Q1 device supports three different behaviors of the output.
表 1. Current Limit Configurations
DELAY
CONFIGURATION
MODE
OUTPUT CURRENT BEHAVIOR
FAULT RECOVERY
When hitting a current limit, the output current
holds at the setting current. The device enters into
FAULT clears when IN turns low for
duration longer than tFAULT OR when the
current limit is removed when IN is high.
a
Connect to GND
directly
Holding
thermal shutdown mode when TJ > T(SD)
.
When hitting a current limit, the output current
holds at the setting current, but latches off after a
preset DELAY time (tdl1+ tdl2). tdl1 is the default
delay time; tdl2 is a capacitor-configurable delay
time.
Connect to GND
through a capacitor
FAULT clears when IN turns low for a
duration longer than tFAULT.
Latch-off
The output stays latched off regardless of whether
the current limit is removed. The output recovers
only when IN is toggling.
When hitting a current limit, the output current
holds at the setting current, but periodically comes
FAULT clears when IN turns low for
duration longer than tFAULT OR when the
current limit is removed for thic(on)
a
Auto-retry
External pullup
on for thic(on) and turns off for thic(off)
.
7.3.2.1 Holding Mode
Holding mode is active when the DELAY pin connects to GND directly. When hitting a current limit, the output
current holds at the setting current. The device enters into thermal shutdown mode when TJ > T(SD)
.
DELAY
TPS1H000-Q1
图 14. Holding Mode Connection
I
OUT
t
CL(deg)
Holding the current
VFAULT
Current Limit
图 15. Holding Mode Example
7.3.2.2 Latch-Off Mode
Latch-off mode is active when the DELAY pin connects to GND through a capacitor. When hitting a current limit,
the output current holds at the setting current, but latches off after a preset DELAY time (tdl1+ tdl2). tdl1 is the
default delay time, tdl2 is a configurable delay time set by a capacitor. The output stays latched off regardless of
whether the current limit is removed. The output recovers only when IN is toggling.
tdl2 can be calculated by 公式 2. The Idl(chg)is the device charging current in latch-off mode, Vdl(ref) is the internal
reference voltage in latch off mode, tdl2 is the user-setting delay time, and CDELAY is the capacitor connected on
the DELAY pin.
12
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Idl chg ì t dl2
(
)
CDELAY
=
Vdl ref
(2)
DELAY
TPS1H000-Q1
图 16. Latch-Off-Mode Connection
I
OUT
tdl2
t
CL(deg) tdl1
Latch off
VFAULT
Current Limit
图 17. Latch-Off-Mode Example
7.3.2.3 Auto-Retry Mode
Auto-retry mode is active when the DELAY pin is externally pulled up. The pullup voltage must be higher than
Vdl(th). When hitting the current limit, the output current holds at the setting current, but periodically comes on for
thic(on) and turns off for thic(off)
.
DELAY
TPS1H000-Q1
图 18. Auto-Retry-Mode Connection
I
OUT
tCL(deg)
tCL(deg)
thic(on)
thic(on)
t
hic(off)
thic(off)
VFAULT
Current Limit
图 19. Auto-Retry-Mode Example
7.3.3 Standalone Operation
In a typical application, the TPS1H000-Q1 device is controlled by a microcontroller. The device also supports
standalone operation. IN and DIAG_EN have a 40-V maximum dc rating, and can be connected to the VS pin
directly. In auto-retry mode, the DELAY pin can also be connected to the VS pin through a 100-kΩ resistor.
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3.4V - 40V
VS
IN
8
7
6
5
1
2
3
DIAG_EN
OUT
GND
Load
Tab
FAULT
CL
DELAY
4
图 20. Standalone Operation in Latch-Off Mode
3.4V - 40V
VS
IN
8
7
6
5
1
2
3
DIAG_EN
OUT
GND
Load
Tab
FAULT
CL
DELAY
4
图 21. Standalone Operation in Auto-Retry Mode
7.3.4 Fault Truth Table
The DIAG_EN pin enables or disables the diagnostic functions. If multiple devices are used, but the ADC
resource is limited in the microcontroller, the microcontroller can use GPIOs to set DIAG_EN high to enable the
diagnostics of one device while disabling the diagnostics of the other devices by setting DIAG_EN low. In
addition, the device can keep the power consumption to a minimum by setting DIAG_EN and IN low.
表 2 applies when the DIAG_EN pin is enabled. 表 3 applies when the DIAG_EN pin is disabled.
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表 2. Fault Truth Table
CONDITION
IN
L
OUT
CRITERION
FAULT
FAULT RECOVERY
L
H
L
—
—
H
H
L
Normal
—
H
H
Overload or short to GND
Current limit triggered.
See 表 1.
FAULT clears when IN turns low
for a duration longer than tFAULT
OR FAULT clears when the open
load is removed.
.
H
L(1)
H
H
H
IOUT < l(ol,on)
L
L
L
Open load or short to
battery
FAULT clears when IN is toggling
OR FAULT clears when the open
load is removed.
VVS – VOUT < V(ol,off)
FAULT clears when IN turns low
for a duration longer than tFAULT.
OR FAULT clears when thermal
shutdown quits.
Thermal shutdown
triggered
Thermal shutdown
Thermal swing
—
FAULT clears when IN turns low
for a duration longer than tFAULT
OR FAULT clears when thermal
swing quits.
.
H
—
Thermal swing triggered
L
(1) An external pullup is required for open-load detection.
表 3. DIAG_EN Disabled Condition
DIAG_EN
IN
PROTECTIONS AND DIAGNOSTICS
Diagnostics disabled, full protections
Diagnostics disabled, no protection
ON
LOW
OFF
7.3.5 Full Diagnostics
7.3.5.1 Short-to-GND and Overload Detection
When the output is on, a short to GND or an overload condition causes overcurrent. If the overcurrent triggers
either the internal or external current-limit threshold, a fault condition is reported out as FAULT pin = low.
7.3.5.2 Open-Load Detection
7.3.5.2.1 Output On
When the output is on, if the current flowing through the output IOUT < l(ol,on), the device recognizes an open-load
fault. For open-load detection in output on, no external circuitry is required.
7.3.5.2.2 Output Off
When the output is off, if a load is connected, the output is pulled down to GND. But if an open load occurs, the
output voltage is close to the supply voltage (VVS – VOUT < V(ol,off)), and the device recognizes an open-load fault.
There is always a leakage current I(ol,off) present on the output due to the internal logic control path or external
humidity, corrosion, and so forth. So an external pullup resistor is recommended to offset the leakage current
when an open load is detected. The recommended pullup resistance is 15 kΩ.
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Open Load Detection in Off-State
V(ol,off)
Vds
R(pullup)
Load
图 22. Open-Load Detection in Output Off
7.3.5.3 Short-to-Battery Detection
Short-to-battery has the same detection mechanism and behavior as open-load detection, in both the on-state
and off-state.
7.3.5.4 Thermal Fault Detection
To protect the device in severe power stressing cases, the device implements two types of thermal fault
detection, absolute temperature protection (thermal shutdown) and dynamic temperature protection (thermal
swing).
Thermal behaviors after Short to GND
IN
T(SD)
TJ
T(hys)
T(SD,rst)
T(hys)
T(SW)
ICL
ICL(TSD)
IOUT
FAULT
图 23. Thermal Behavior Diagram
7.3.5.4.1 Thermal Shutdown
Thermal shutdown is active when the absolute temperature TJ > T(SD). When thermal shutdown occurs, the
output turns off.
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7.3.5.4.2 Thermal Swing
Thermal swing activates when the power FET temperature is increasing sharply, that is, when ΔT = T(FET)
–
T(Logic) > T(sw), then the output turns off. The output automatically recovers and the fault signal clears when ΔT =
T(FET) – T(Logic) < T(sw) – T(hys). The thermal swing function improves the device reliability when subjected to
repetitive fast thermal variation.
7.3.5.4.3 Fault Report Holding
When using PWM dimming, FAULT is easily cleared by the PWM falling edge. Even if the fault condition remains
all the time, FAULT is discontinuous. To avoid this unexpected fault report behavior, the device implements fault-
report holding time. 图 24 shows a typical issue when PWM dimming, the FAULT is cleared unexpectedly even
when the short-to-GND still exists. The TPS1H000-Q1 device with fault-report holding function allows the right
behavior as shown in 图 25.
Short-to-GND
IN
Fault cleared
FAULT
图 24. Without Fault-Report Holding
Short-to-GND
IN
Fault not cleared
t < tFAULT
FAULT
图 25. With Fault-Report Holding
7.3.6 Full Protections
7.3.6.1 UVLO Protection
The device monitors the supply voltage, VVS, to prevent unpredicted behaviors when VVS is too low. When VVS
falls down to VVS(uvf), the device shuts down. When VVS rises up to VVS(uvr), the device turns on.
7.3.6.2 Inductive Load Switching Off Clamp
When switching an inductive load off, the inductive reactance tends to pull the output voltage negative. Excessive
negative voltage could cause the power FET to break down. To protect the power FET, an internal clamp
between drain and source is implemented, namely VDS(clamp)
.
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VS
VDS(clamp)
-
L
OUT
R
GND
+
图 26. Drain-to-Source Clamping Structure
IN
VVS
VOUT
VDS(clamp)
IOUT
t(decay)
图 27. Inductive-Load Switching-Off Diagram
7.3.6.3 Loss-of-GND Protection
When loss of GND occurs, the output is shut down regardless of whether the IN pin is high or low. The device
can protect against two ground-loss conditions, loss of device GND and loss of module GND.
7.3.6.4 Loss-of-Power-Supply Protection
When loss of supply occurs, the output is shut down regardless of whether the IN pin is high or low. For a
resistive or a capacitive load, loss of supply has no risk. But for a charged inductive load, the current is driven
from all the logic control pins to maintain the inductance current. To protect the system in this condition, TI
recommends protection with an external free-wheeling diode.
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Vs
VS
IOs
MCU
High-side Switch
OUT
D
L
图 28. Protection for Loss of Power Supply
7.3.6.5 Reverse-Current Protection
Reverse current occurs in two conditions: short to supply and reverse polarity.
•
When a short to the supply occurs, there is only reverse current through the body diode. IR(1) specifies the
limit of the reverse current.
•
In a reverse-polarity condition, there are reverse currents through the body diode and the device GND pin.
IR(2) specifies the limit of the reverse current.
To protect the device, TI recommends two types of external circuitry.
•
•
Adding a blocking diode (method 1). Both the device and load are protected when in reverse polarity.
Adding a GND network (method 2). The reverse current through the device GND is blocked. The reverse
current through the FET is limited by the load itself. TI recommends a resistor in parallel with the diode as a
GND network. The recommended configuration is a 1-kΩ resistor in parallel with a >100-mA diode. The
reverse current protection diode in the GND network forward voltage should be less than 0.6 V in any
circumstances. In addition a minimum resistance of 4.7 K is recommended on the I/O pins.
Load
图 29. Reverse-Current External Protection, Method 1
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Load
图 30. Reverse-Current External Protection, Method 2
7.3.6.6 MCU I/O Protection
TI recommends series resistors to protect the microcontroller, for example, 4.7-kΩ when using a 3.3-V
microcontroller and 10-kΩ for a 5-V microcontroller.
IOs
MCU
TPS1H000-Q1
Load
图 31. MCU I/O External Protection
7.4 Device Functional Modes
7.4.1 Working Modes
The device has three working modes, the normal mode, the standby mode, and the standby mode with
diagnostics, as shown in 图 32.
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Device Functional Modes (接下页)
Standby Mode
(IN low, DIAG_EN low)
DIAG_EN low
AND
IN high to low
AND
DIAG_EN high to low
t > t(off,deg)
IN low to high
DIAG_EN low to high
Standby Mode
With DIAG
IN low to high
Normal Mode
(IN high)
(IN low, DIAG_EN high)
IN high to low
AND
DIAG_EN high
AND
t > t(off,deg)
图 32. Working Modes
7.4.1.1 Normal Mode
When IN is high, the device enters normal mode.
7.4.1.2 Standby Mode
When IN is low and DIAG_EN is low, the device enters standby mode with ultralow power consumption.
7.4.1.3 Standby Mode With Diagnostics
When IN is low and DIAG_EN is high, the device enters standby mode with diagnostics. The device still supports
open-load and short-to-battery detection even when IN is low.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS1H000-Q1 device is a smart high-side switch, with an internal charge pump and single-channel
integrated NMOS power FET. The adjustable current-limit function greatly improves the reliability of the whole
system. Full diagnostic features enable intelligent control of the load. The TPS1H000-Q1 device can be used for
a wide variety of resistive, inductive, and capacitive loads, including LEDs, relays, and sub-modules.
8.2 Typical Application
图 33 shows an example of how to design the external circuitry parameters.
Supply Voltage
R(SER)
VS
IN
R(SER)
General Resistive, Capacitive,
Inductive Loads
DIAG_EN
OUT
3.3/5V
R(pullup)
MCU
R(SER)
FAULT
DELAY
C(DELAY)
GND
CL
R(CL)
图 33. Typical Application Circuitry
8.2.1 Design Requirements
•
•
•
•
VVS range from 6 V to 18 V
Nominal current of 100 mA
Expected current limit value of 500 mA
Thermal sensitive system, when current limit occurs, the output latches off after 0.2 s. The 0.2 s is to ensure
the safe start-up for a capacitive load, clamping the inrush current but without latch-off during start-up.
•
Full diagnostics with 5-V MCU, including on-state open-load detection, short-to-GND or overcurrent detection,
and thermal shutdown detection
8.2.2 Detailed Design Procedure
To set the adjustable current limit value at 500 mA, calculate R(CL) as follows:
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Typical Application (接下页)
VCL(th) ìK(CL)
0.8ì 600
R(CL)
=
=
= 960 ꢀ
IOUT
0.5
(3)
(4)
To set the adjustable latch-off delay at 0.2 s, calculate C(DELAY) as follows:
tdl = tCL(deg) + tdl1 + tdl2 = 0.2 ö tdl2
Idl(chg) ì tdl2
4.5ì0.2
1.45
CDELAY
=
=
ì10-6 = 0.62 mF
Vdl(ref)
TI recommends R(SER) = 10 kΩ for a 5-V MCU, and R(pullup) = 10 kΩ as the pullup resistor.
8.2.3 Application Curves
The following curves are test examples of hard short conditions. The load is 0.1 A and the current limit value is
0.5 A. 图 34 shows a waveform of the latch-off mode. 图 35 shows a waveform of the auto-retry mode.
Load = 0.1 A
Current limit = 0.5
A
Load = 0.1 A
Current limit = 0.5
A
图 34. Hard-Short Condition in Latch-Off Mode
图 35. Hard-Short Condition in Auto-Retry Mode
9 Power Supply Recommendations
The device can be used for both 12-V and 24-V applications. The normal power supply connection is a 12-V or
24-V system.
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10 Layout
10.1 Layout Guidelines
To prevent thermal shutdown, TJ must be less than 175°C. If the output current is very high, the power
dissipation may be large. However, the PCB layout is very important. Good PCB design can optimize heat
transfer, which is absolutely essential for the long-term reliability of the device.
•
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-
flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when there are not any heat sinks attached to the PCB on the other side of the board opposite the
package.
•
•
Add as many thermal vias as possible directly under the package thermal pad to optimize the thermal
conductivity of the board.
All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
10.2 Layout Example
1
8
VS
OUT
GND
IN
2
3
7
6
DIAG_EN
Thermal Pad
FAULT
CL
4
5
DELAY
图 36. Layout Example
24
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11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是适用于指定器件的最新数据。数据如有变更，恕不另行通知，
且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查看左侧的导航面板。
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25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS1H000AQDGNRQ1
ACTIVE
HVSSOP
DGN
8
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
17SX
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS1H000AQDGNRQ1 HVSSOP DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HVSSOP DGN
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
TPS1H000AQDGNRQ1
8
2500
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.846
1.646
4225480/B 12/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
(1.89)
9
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225480/B 12/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(1.89)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
0.125
0.15
0.175
1.33 X 1.60
4225480/B 12/2022
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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