TPS2041B_08 [TI]
CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES; 限流配电开关
| 型号： | TPS2041B_08 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES |
| 文件： | 总49页 (文件大小：1993K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
DGN−8
DRB−8
DBV−5
D−16
D−8
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES
1
FEATURES
APPLICATIONS
•
Heavy Capacitive Loads
2
•
70-mΩ High-Side MOSFET
•
Short-Circuit Protections
•
•
•
500-mA Continuous Current
Thermal and Short-Circuit Protection
TPS2041B/TPS2051B
TPS2041B/TPS2051B
TPS2042B/TPS2052B
D AND DGN PACKAGES
(TOP VIEW)
D AND DGN PACKAGES
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
Accurate Current Limit
(0.75 A min, 1.25 A max)
OUT
GND
OC
GND
IN
1
2
3
4
8
7
6
5
OUT
OUT
OUT
OC
GND
IN
1
2
3
4
8
7
6
5
OC1
IN
OUT1
OUT2
OC2
†
IN
†
EN1
•
•
•
•
•
•
Operating Range: 2.7 V to 5.5 V
0.6-ms Typical Rise Time
†
†
EN
EN2
EN
TPS2043B/TPS2053B
D PACKAGE
(TOP VIEW)
TPS2044B/TPS2054B
D PACKAGE
(TOP VIEW)
Undervoltage Lockout
TPS2042B/TPS2052B
DRB PACKAGES
(TOP VIEW)
Deglitched Fault Report (OC)
No OC Glitch During Power Up
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
IN1
OC1
OUT1
OUT2
OC2
OC3
OUT3
NC
GND
IN1
OC1
OUT1
OUT2
OC2
1
8
7
6
5
OC1
GND
IN
†
†
EN1
EN1
2
3
OUT1
OUT2
OC2
†
†
EN2
GND
EN2
GND
Maximum Standby Supply Current:
1-µA (Single, Dual) or 2-µA (Triple, Quad)
†
OC3
EN1
†
4
IN2
†
IN2
†
OUT3
OUT4
OC4
EN2
EN3
EN3
•
•
•
Ambient Temperature Range: -40°C to 85°C
UL Recognized, File Number E169910
NC
†
NC
EN4
†All enable inputs are active high for the TPS205xB series.
NC − No connect
Additional UL Recognition for TPS2042B and
TPS2052B for Ganged Configuration
DESCRIPTION
The TPS204xB/TPS205xB power-distribution switches are intended for applications where heavy capacitive
loads and short circuits are likely to be encountered. These devices incorporates 70-mΩ N-channel MOSFET
power switches for power-distribution systems that require multiple power switches in a single package. Each
switch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to
control the power-switch rise times and fall times to minimize current surges during switching. The charge pump
requires no external components and allows operation from supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the device limits the output current
to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When
continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction
temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal
shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains
off until valid input voltage is present. This power-distribution switch is designed to set current limit at 1 A
typically.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2008, Texas Instruments Incorporated
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTION AND ORDERING INFORMATION
(2)
TYPICAL
SHORT-
CIRCUIT
CURRENT
LIMIT
PACKAGED DEVICES(1)
RECOMMENDED
MAXIMUM
CONTINUOUS
LOAD CURRENT
NUMBER OF
SWITCHES
TA
ENABLE
MSOP (DGN)
SOIC (D)
SOT-23 (DBV)
SON (DRB)
AT 25°C
Active low
Active high
Active low
Active high
Active low
Active high
Active low
Active high
Single
Single
Dual
TPS2041BDGN
TPS2041BD
TPS2051BD
TPS2042BD
TPS2052BD
TPS2043BD
TPS2053BD
TPS2044BD
TPS2054BD
TPS2041BDBV
TPS2051BDBV
TPS2051BDGN
TPS2042BDGN
TPS2042BDRB
TPS2052BDRB
Dual
TPS2052BDGN
-40°C to
85°C
0.5 A
1 A
Triple
Triple
Quad
Quad
--
--
--
--
(1) The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2042BDR)
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
(2)
Input voltage range, VI(IN), VI(INx)
-0.3 V to 6 V
-0.3 V to 6 V
-0.3 V to 6 V
-0.3 V to 6 V
Internally limited
See Dissipation Rating Table
-40°C to 125°C
-65°C to 150°C
260°C
(2)
Output voltage range, VO(OUT), VO(OUTx)
Input voltage range, VI(EN), VI(ENx), VI(EN), VI(ENx)
Voltage range, VI(/OC), VI(OCx)
Continuous output current, IO(OUT), IO(OUTx)
Continuous total power dissipation
Operating virtual junction temperature range, TJ
Storage temperature range, Tstg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds
Human body model MIL-STD-883C
Electrostatic discharge (ESD) protection
2 kV
Charge device model (CDM)
500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
DISSIPATING RATING TABLE
THERMAL
RESISTANCE, θJA
T
A ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
1712.3 mW
585.82 mW
898.47 mW
285 mW
DGN-8
D-8
17.123 mW/°C
5.8582 mW/°C
8.9847 mW/°C
2.85 mW/°C
941.78 mW
322.20 mW
494.15 mW
155 mW
684.93 mW
234.32 mW
359.38 mW
114 mW
D-16
DBV-5
DRB-8 (Low-K)(1)
DRB-8 (High-K)(2)
270 °CW
60 °CW
370 mW
3.71 mW/°C
203 mW
148 mW
1600 mW
16.67 mW/°C
916 mW
866 mW
(1) Soldered PowerPAD on a standard 2-layer PCB without vias for thermal pad. See TI application note SLMA002 for further details.
(2) Soldered PowerPAD on a standard 4-layer PCB with vias for thermal pad. See TI application note SLMA002 for further details.
2
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Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
RECOMMENDED OPERATING CONDITIONS
MIN
2.7
0
MAX
5.5
UNIT
V
Input voltage, VI(IN), VI(INx)
Input voltage, VI(EN), VI(ENx), VI(EN), VI(ENx)
Continuous output current, IO(OUT), IO(OUTx)
Operating virtual junction temperature, TJ
5.5
V
0
500
125
mA
°C
-40
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.5 A, VI(/ENx) = 0 V (unless otherwise noted)
PARAMETER
POWER SWITCH
TEST CONDITIONS(1)
MIN TYP MAX UNIT
Static drain-source on-state
resistance, 5-V operation
and 3.3-V operation
D and DGN packages
DBV package only
70 135
VI(IN) = 5 V or 3.3 V, IO = 0.5 A,
-40°C ≤ TJ ≤ 125°C
mΩ
95 140
Static drain-source on-state
resistance, 2.7-V
rDS(on)
VI(IN) = 2.7 V, IO = 0.5 A,
-40°C ≤ TJ ≤ 125°C
D and DGN packages
75 150 mΩ
49(3) mΩ
operation(2)
Static drain-source on-state VI(IN) = 5 V, IO = 1.0 A, OUT1 and OUT2
resistance, 5-V operation
DGN package,
TPS2042B/52B
connected, 0°C ≤ TJ ≤ 70°C
VI(IN) = 5.5 V
0.6
0.4
1.5
1
(2)
tr
Rise time, output
VI(IN) = 2.7 V
VI(IN) = 5.5 V
VI(IN) = 2.7 V
CL = 1 µF,
RL = 10 Ω
TJ = 25°C
ms
0.05
0.05
0.5
0.5
tf(2)
Fall time, output
ENABLE INPUT EN AND ENx
VIH
VIL
II
High-level input voltage
Low-level input voltage
Input current
2.7 V ≤ VI(IN) ≤ 5.5 V
2.7 V ≤ VI(IN) ≤ 5.5 V
VI(ENx) = 0 V or 5.5 V
CL = 100 µF, RL = 10 Ω
CL = 100 µF, RL = 10 Ω
2
V
0.8
0.5
3
-0.5
µA
ms
(2)
ton
toff
Turnon time
(2)
Turnoff time
10
CURRENT LIMIT
TJ = 25°C
0.75
0.7
1
1
1.25
1.3
VI(IN) = 5 V, OUT connected to GND,
device enabled into short-circuit
-40°C ≤ TJ ≤ 125°C
IOS
Short-circuit output current
A
VI(IN) = 5 V, OUT1 and OUT2 connected to
GND, device enabled into short-circuit,
measure at IN
0°C ≤ TJ ≤ 70°C
TPS2042B/52B,
DGN package
1.5(3)
SUPPLY CURRENT (TPS2041B, TPS2051B)
TJ = 25°C
0.5
0.5
43
1
5
No load on OUT, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
Supply current, low-level output
Supply current, high-level output
µA
µA
-40°°C ≤ TJ ≤ 125°C
TJ = 25°C
60
70
No load on OUT, VI(ENx) = 0 V,
or VI(ENx) = 5.5 V
-40°C ≤ TJ ≤ 125°C
43
OUT connected to ground, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
VI(OUTx) = 5.5 V, IN = ground(2)
Leakage current
-40°C ≤ TJ ≤ 125°C
1
0
µA
µA
Reverse leakage current
TJ = 25°C
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
(2) Not tested in production, specified by design.
(3) Estimated value. Final value pending characterization.
Copyright © 2004–2008, Texas Instruments Incorporated
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3
Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.5 A, VI(/ENx) = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN TYP MAX UNIT
SUPPLY CURRENT (TPS2042B, TPS2052B)
TJ = 25°C
0.5
0.5
50
50
1
1
5
Supply current, low-level output
Supply current, high-level output
No load on OUT, VI(ENx) = 5.5 V
µA
µA
-40°C ≤ TJ ≤ 125°C
TJ = 25°C
70
90
No load on OUT, VI(ENx) = 0 V
-40°C ≤ TJ ≤ 125°C
-40°C ≤ TJ ≤ 125°C
TJ = 25°C
Leakage current
OUT connected to ground, VI(ENx) = 5.5 V
VI(OUTx) = 5.5 V, IN = ground(4)
µA
µA
Reverse leakage current
0.2
SUPPLY CURRENT (TPS2043B, TPS2053B)
TJ = 25°C
0.5
0.5
65
2
10
90
Supply current, low-level output
Supply current, high-level output
No load on OUT, VI(ENx) = 0 V
µA
µA
-40°C ≤ TJ ≤ 125°C
TJ = 25°C
No load on OUT, VI(ENx) = 5.5 V
-40°C ≤ TJ ≤ 125°C
-40°C≤ TJ ≤ 125°C
TJ = 25°C
65 110
Leakage current
OUT connected to ground, VI(ENx) = 0 V
VI(OUTx) = 5.5 V, INx = ground(4)
1
µA
µA
Reverse leakage current
0.2
SUPPLY CURRENT (TPS2044B, TPS2054B)
TJ = 25°C
0.5
0.5
2
No load on OUT, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
Supply current, low-level output
µA
µA
-40°C ≤ TJ ≤ 125°C
TJ = 25°C
10
75 110
75 140
No load on OUT, VI(ENx) = 0 V,
or VI(ENx) = 5.5 V
Supply current, high-level output
Leakage current
-40°C ≤ TJ ≤ 125°C
OUT connected to ground, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
VI(OUTx) = 5.5 V, INx = ground(4)
-40°C≤ TJ ≤ 125°C
1
µA
µA
Reverse leakage current
UNDERVOLTAGE LOCKOUT
Low-level input voltage, IN, INx
Hysteresis, IN, INx
TJ = 25°C
0.2
2
4
2.5
75
V
TJ = 25°C
mV
OVERCURRENT OC and OCx
Output low voltage, VOL(/OCx)
Off-state current(4)
IO(OCx) = 5 mA
0.4
1
V
VO(OCx) = 5 V or 3.3 V
OCx assertion or deassertion
µA
ms
OC deglitch(4)
8
15
THERMAL SHUTDOWN(5)
Thermal shutdown threshold(4)
Recovery from thermal shutdown(4)
Hysteresis(4)
135
125
°C
°C
°C
10
(4) Not tested in production, specified by design.
(5) The thermal shutdown only reacts under overcurrent conditions.
4
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Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
DEVICE INFORMATION
Terminal Functions (TPS2041B and TPS2051B)
TERMINAL
D AND DGN PACKAGE
DBV PACKAGE
TPS2041B TPS2051B
I/O
DESCRIPTION
NAME
EN
TPS2041B
TPS2051B
4
–
–
4
4
–
I
I
Enable input, logic low turns on power switch
Enable input, logic high turns on power switch
Ground
EN
–
2
5
3
1
4
2
5
3
1
GND
IN
1
1
2, 3
5
2, 3
5
I
Input voltage
OC
OUT
O
O
Overcurrent open-drain output, active-low
Power-switch output
6, 7, 8
6, 7, 8
Functional Block Diagram (TPS2041B and TPS2051B)
(See Note A)
CS
OUT
IN
Charge
Pump
Current
EN
Driver
Limit
(See Note B)
OC
UVLO
Deglitch
Thermal
Sense
GND
Note A: Current sense
Note B: Active low (EN) for TPS2041B; Active high (EN) for TPS2051B
Copyright © 2004–2008, Texas Instruments Incorporated
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Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
Terminal Functions (TPS2042B and TPS2052B)
TERMINAL
D, DGN, and DRB PACKAGES
I/O
DESCRIPTION
NAME
EN1
EN2
EN1
EN2
GND
IN
TPS2042B
TPS2052B
3
4
-
-
I
I
I
I
Enable input, logic low turns on power switch IN-OUT1
Enable input, logic low turns on power switch IN-OUT2
Enable input, logic high turns on power switch IN-OUT1
Enable input, logic high turns on power switch IN-OUT2
Ground
-
3
4
1
2
8
5
7
6
-
1
2
8
5
7
6
I
Input voltage
OC1
OC2
OUT1
OUT2
O
O
O
O
Overcurrent, open-drain output, active low, IN-OUT1
Overcurrent, open-drain output, active low, IN-OUT2
Power-switch output, IN-OUT1
Power-switch output, IN-OUT2
Internally connected to GND; used to heat-sink the part to the circuit board
traces. Should be connected to GND pin.
PowerPAD™
-
-
Functional Block Diagram (TPS2042B and TPS2052B)
OC1
Thermal
Deglitch
Sense
GND
EN1
(See Note B)
Current
Driver
Limit
Charge
Pump
(See Note A)
CS
OUT1
OUT2
UVLO
(See Note A)
IN
CS
Charge
Pump
Current
Driver
Limit
OC2
EN2
(See Note B)
Thermal
Sense
Deglitch
Note A: Current sense
Note B: Active low (ENx) for TPS2042B; Active high (ENx) for TPS2052B
6
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Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
Terminal Functions (TPS2043B and TPS2053B)
TERMINAL
I/O
DESCRIPTION
NAME
EN1
EN2
EN3
EN1
EN2
EN3
GND
IN1
TPS2043B TPS2053B
3
4
--
--
I
I
I
I
I
I
Enable input, logic low turns on power switch IN1-OUT1
Enable input, logic low turns on power switch IN1-OUT2
Enable input, logic low turns on power switch IN2-OUT3
Enable input, logic high turns on power switch IN1-OUT1
Enable input, logic high turns on power switch IN1-OUT2
Enable input, logic high turns on power switch IN2-OUT3
Ground
7
--
--
3
--
4
--
7
1, 5
2
1, 5
2
I
I
Input voltage for OUT1 and OUT2
IN2
6
6
Input voltage for OUT3
NC
8, 9, 10
16
13
12
15
14
11
8, 9, 10
16
13
12
15
14
11
No connection
OC1
OC2
OC3
OUT1
OUT2
OUT3
O
O
O
O
O
O
Overcurrent, open-drain output, active low, IN1-OUT1
Overcurrent, open-drain output, active low, IN1-OUT2
Overcurrent, open-drain output, active low, IN2-OUT3
Power-switch output, IN1-OUT1
Power-switch output, IN1-OUT2
Power-switch output, IN2-OUT3
Copyright © 2004–2008, Texas Instruments Incorporated
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7
Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
Functional Block Diagram (TPS2043B and TPS2053B)
OC1
Thermal
GND
Sense
Deglitch
EN1
(See Note B)
Current
Limit
Driver
(See Note A)
CS
CS
OUT1
OUT2
UVLO
(See Note A)
IN1
Current
Limit
Driver
OC2
EN2
(See Note B)
Thermal
Sense
Deglitch
Charge
Pump
VCC
Selector
(See Note A)
IN2
CS
OUT3
OC3
Current
Limit
EN3
Driver
(See Note B)
UVLO
Deglitch
Thermal
Sense
GND
Note A: Current sense
Note B: Active low (ENx) for TPS2043B; Active high (ENx) for TPS2053B
8
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Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
Terminal Functions (TPS2044B and TPS2054B)
TERMINAL
I/O
DESCRIPTION
NAME
EN1
EN2
EN3
EN4
EN1
EN2
EN3
EN4
GND
IN1
TPS2044B TPS2054B
3
4
-
-
I
I
I
I
I
I
I
I
Enable input, logic low turns on power switch IN1-OUT1
Enable input, logic low turns on power switch IN1-OUT2
Enable input, logic low turns on power switch IN2-OUT3
Enable input, logic low turns on power switch IN2-OUT4
Enable input, logic high turns on power switch IN1-OUT1
Enable input, logic high turns on power switch IN1-OUT2
Enable input, logic high turns on power switch IN2-OUT3
Enable input, logic high turns on power switch IN2-OUT4
Ground
7
-
8
-
-
3
-
4
-
7
-
8
1, 5
2
1, 5
2
I
Input voltage for OUT1 and OUT2
IN2
6
6
I
Input voltage for OUT3 and OUT4
OC1
OC2
OC3
OC4
OUT1
OUT2
OUT3
OUT4
16
13
12
9
16
13
12
9
O
O
O
O
O
O
O
O
Overcurrent, open-drain output, active low, IN1-OUT1
Overcurrent, open-drain output, active low, IN1-OUT2
Overcurrent, open-drain output, active low, IN2-OUT3
Overcurrent, open-drain output, active low, IN2-OUT4
Power-switch output, IN1-OUT1
15
14
11
10
15
14
11
10
Power-switch output, IN1-OUT2
Power-switch output, IN2-OUT3
Power-switch output, IN2-OUT4
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TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
Functional Block Diagram (TPS2044B and TPS2054B)
OC1
Thermal
Sense
GND
Deglitch
EN1
(See Note B)
Current
Driver
Limit
(See Note A)
CS
OUT1
OUT2
UVLO
Power Switch
(See Note A)
IN1
CS
Current
Limit
Driver
OC2
OC3
EN2
(See Note B)
Thermal
Sense
Deglitch
VCC
Selector
Charge
Pump
Thermal
Sense
Deglitch
EN3
(See Note B)
Current
Limit
Driver
(See Note A)
CS
OUT3
OUT4
UVLO
Power Switch
CS
(See Note A)
IN2
Current
Limit
Driver
OC4
EN4
(See Note B)
Thermal
Sense
Deglitch
GND
Note A: Current sense
Note B: Active low (ENx) for TPS2044B; Active high (ENx) for TPS2054B
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TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
PARAMETER MEASUREMENT INFORMATION
OUT
t
f
t
r
R
L
C
L
V
90%
10%
O(OUT)
90%
10%
TEST CIRCUIT
50%
90%
50%
50%
50%
V
V
I(EN)
I(EN)
t
off
t
off
t
on
t
on
90%
V
V
O(OUT)
O(OUT)
10%
10%
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
R
C
T
A
= 10 W,
= 1 mF
= 255C
L
L
V
V
V
V
I(EN)
I(EN)
I(EN)
I(EN)
5 V/div
5 V/div
R
C
T
= 10 W,
= 1 mF
= 255C
L
L
V
O(OUT)
2 V/div
V
A
O(OUT)
2 V/div
t − Time − 500 ms/div
t − Time − 500 ms/div
Figure 2. Turnon Delay and Rise Time With 1-µF Load
Figure 3. Turnoff Delay and Fall Time With 1-µF Load
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TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
R
C
T
= 10 W,
= 100 mF
= 255C
L
L
V
V
I(EN)
V
V
I(EN)
I(EN)
I(EN)
A
5 V/div
5 V/div
R = 10 W,
L
V
O(OUT)
C = 100 mF
L
2 V/div
T = 255C
A
V
O(OUT)
2 V/div
t − Time − 500 ms/div
Figure 5. Turnoff Delay and Fall Time With 100-µF Load
t − Time − 500 ms/div
Figure 4. Turnon Delay and Rise Time With 100-µF Load
V = 5 V,
I
V
V
V
V
I(EN)
I(EN)
R = 10 W,
L
I(EN)
I(EN)
T = 255C
A
5 V/div
5 V/div
220 mF
470 mF
I
O(OUT)
I
O(OUT)
500 mA/div
500 mA/div
100 mF
t − Time − 500 ms/div
t − Time − 500 ms/div
Figure 6. Short-Circuit Current,
Device Enabled Into Short
Figure 7. Inrush Current With Different
Load Capacitance
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TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
PARAMETER MEASUREMENT INFORMATION (continued)
V
O(OC)
V
O(OC)
2 V/div
2 V/div
I
I
O(OUT)
O(OUT)
500 mA/div
500 mA/div
t − Time − 2 ms/div
Figure 8. 3-Ω Load Connected to Enabled Device
t − Time − 2 ms/div
Figure 9. 2-Ω Load Connected to Enabled Device
TYPICAL CHARACTERISTICS
TURNON TIME
vs
INPUT VOLTAGE
TURNOFF TIME
vs
INPUT VOLTAGE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
3.3
3.2
3.1
3
C = 100 mF,
C = 100 mF,
L
R = 10 W,
L
T = 255C
A
L
R = 10 W,
L
T = 255C
A
2.9
2.8
0.1
0
2
3
4
5
6
2
3
4
5
6
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 10.
Figure 11.
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TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
RISE TIME
vs
INPUT VOLTAGE
FALL TIME
vs
INPUT VOLTAGE
0.25
0.2
0.6
0.5
0.4
C
R
T
= 1 mF,
= 10 W,
= 255C
C
R
T
= 1 mF,
= 10 W,
= 255C
L
L
L
L
A
A
0.15
0.1
0.3
0.2
0.05
0
0.1
0
2
3
4
5
6
2
3
4
5
6
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 12.
Figure 13.
TPS2041B/2051B
TPS2042B/TPS2052B
SUPPLY CURRENT, OUTPUT ENABLED
SUPPLY CURRENT, OUTPUT ENABLED
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
60
50
40
30
20
70
60
50
40
30
20
10
0
V = 5.5 V
I
V = 5.5 V
I
V = 5 V
I
V = 5 V
I
V = 3.3 V
I
V = 2.7 V
I
V = 2.7 V
I
V = 3.3 V
I
10
0
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 14.
Figure 15.
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Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
TYPICAL CHARACTERISTICS (continued)
TPS2043B/TPS2053B
SUPPLY CURRENT, OUTPUT ENABLED
vs
TPS2044B/2054B
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
90
80
70
60
50
40
30
20
120
100
80
V = 5.5 V
I
V = 5.5 V
I
V = 5 V
I
V = 5 V
I
V = 3.3 V
I
60
V = 2.7 V
I
V = 2.7 V
I
40
V = 3.3 V
I
20
0
10
0
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 16.
Figure 17.
TPS2041B/2051B
SUPPLY CURRENT, OUTPUT DISABLED
vs
TPS2042B/TPS2052B
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
0.5
0.45
0.4
0.5
V = 5.5 V
I
V = 5.5 V
I
0.45
0.4
V = 5 V
I
V = 5 V
I
0.35
0.3
0.35
0.3
V = 3.3 V
I
V = 3.3 V
I
V = 2.7 V
I
V = 2.7 V
I
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0.05
0
0
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 18.
Figure 19.
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TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
TPS2043B/TPS2053B
SUPPLY CURRENT, OUTPUT DISABLED
vs
TPS2044B/2054B
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
0.5
0.45
0.4
0.5
0.45
0.4
V = 5.5 V
I
V = 5.5 V
I
V = 5 V
I
V = 5 V
I
0.35
0.3
0.35
0.3
V = 2.7 V
I
V = 3.3 V
I
V = 3.3 V
I
V = 2.7 V
I
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0.05
0
0
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 20.
Figure 21.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
SHORT-CIRCUIT OUTPUT CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.08
1.06
1.04
1.02
1.0
120
100
80
I
O
= 0.5 A
V = 2.7 V
I
V = 2.7 V
I
V = 3.3 V
I
V = 3.3 V
I
60
0.98
0.96
0.94
V = 5 V
I
V = 5 V
I
40
V = 5.5 V
I
20
0
0.92
0.9
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 22.
Figure 23.
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Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
TYPICAL CHARACTERISTICS (continued)
THRESHOLD TRIP CURRENT
THRESHOLD TRIP CURRENT
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
2
1.8
1.6
1.4
2
1.8
1.6
1.4
TPS2041B,
T
= 255C
A
T
= 255C
A
TPS2042B,
TPS2051B,
TPS2052B
Load Ramp = 1A/10 ms
Load Ramp = 1A/10 ms
TPS2043B,
TPS2044B,
TPS2053B,
TPS2054B
1.2
1
1.2
1
2.5
3
3.5
4
4.5
5
5.5
6
2.5
3
3.5
4
4.5
5
5.5
6
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 24.
Figure 25.
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
2.3
100
V = 5 V,
I
T = 255C
A
UVLO Rising
UVLO Falling
80
60
40
2.26
2.22
2.18
20
0
2.14
2.1
0
2.5
5
7.5
10
12.5
−50
0
50
100
150
Peak Current − A
T − Junction Temperature − 5C
J
Figure 26.
Figure 27.
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TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
APPLICATION INFORMATION
POWER-SUPPLY CONSIDERATIONS
TPS2042B
2
Power Supply
IN
7
2.7 V to 5.5 V
Load
Load
OUT1
0.1 µF
0.1 µF
0.1 µF
22 µF
22 µF
8
OC1
EN1
OC2
3
5
6
OUT2
4
EN2
GND
1
Figure 28. Typical Application (Example, TPS2042B)
A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the
output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit transients.
OVERCURRENT
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 14 through Figure 17). The TPS204xB/TPS205xB
senses the short and immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current
mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 18 through Figure 21). The TPS204xB/TPS205xB is capable of delivering current up to the
current-limit threshold without damaging the device. Once the threshold has been reached, the device switches
into its constant-current mode.
OC RESPONSE
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition
is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or
overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a
momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit.
The TPS204xB/TPS205xB is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch
eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch
is turned off due to an overtemperature shutdown.
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TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
V+
R
pullup
TPS2042B
GND
OC1
OUT1
OUT2
OC2
IN
EN1
EN2
Figure 29. Typical Circuit for the OC Pin (Example, TPS2042B)
POWER DISSIPATION AND JUNCTION TEMPERATURE
The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large
currents. The thermal resistances of these packages are high compared to those of power packages; it is good
design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the
N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read rDS(on) from Figure 22. Using this value, the power
dissipation per switch can be calculated by:
PD = rDS(on) × I2
Multiply this number by the number of switches being used. This step renders the total power dissipation from
the N-channel MOSFETs.
Finally, calculate the junction temperature:
TJ = PD × RθJA + TA
Where:
TA= Ambient temperature °C
RθJA = Thermal resistance
PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
THERMAL PROTECTION
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The TPS204xB/TPS205xB implements a thermal sensing to monitor the operating
junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction
temperature rises due to excessive power dissipation. Once the die temperature rises to approximately 140°C
due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the
power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled
approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or
input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown
or overcurrent occurs.
UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input
voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the
switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and
voltage overshoots.
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TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
UNIVERSAL SERIAL BUS (USB) APPLICATIONS
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
•
•
•
•
•
Hosts/self-powered hubs (SPH)
Bus-powered hubs (BPH)
Low-power, bus-powered functions
High-power, bus-powered functions
Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The
TPS204xB/TPS205xB can provide-power distribution solutions to many of these classes of devices.
HOST/SELF-POWERED AND BUS-POWERED HUBS
Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports (see Figure 30 and Figure 31). This power supply must provide from 5.25 V to 4.75 V to the
board side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to
have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are
desktop PCs, monitors, printers, and stand-alone hubs.
Power Supply
Downstream
USB Ports
3.3 V 5 V
TPS2041B
D+
D−
2, 3
0.1 µF
IN
6, 7, 8
V
BUS
OUT
0.1 µF
120 µF
GND
5
4
OC
EN
USB
Control
GND
1
Figure 30. Typical One-Port USB Host / Self-Powered Hub
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TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
Downstream
USB Ports
D+
Power Supply
D−
3.3 V
5 V
V
BUS
+
TPS2044B
33 µF
GND
2
IN1
IN2
15
OUT1
6
D+
D−
0.1 µF
14
11
V
BUS
OUT2
OUT3
+
33 µF
GND
16
OC1
EN1
OC2
EN2
OC3
EN3
OC4
EN4
3
D+
D−
13
4
USB
Controller
V
BUS
+
12
7
33 µF
10
GND
OUT4
9
D+
D−
8
V
GND GND
BUS
+
33 µF
GND
1
5
Figure 31. Typical Four-Port USB Host / Self-Powered Hub
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are
required to power up with less than one unit load. The BPH usually has one embedded function, and power is
always available to the controller of the hub. If the embedded function and hub require more than 100 mA on
power up, the power to the embedded function may need to be kept off until enumeration is completed. This can
be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the
embedded function is not necessary if the aggregate power draw for the function and controller is less than one
unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 µF at power up, the device must implement inrush current limiting (see Figure 32).
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Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
Power Supply
D+
D−
3.3 V
TPS2042B
2
8
IN
V
BUS
7
10 µF
0.1 µF
Internal
Function
OUT1
GND
0.1 µF
10 µF
OC1
EN1
OC2
EN2
3
5
USB
Control
6
4
OUT2
GND
Internal
Function
0.1 µF
10 µF
1
Figure 32. High-Power Bus-Powered Function (Example, TPS2042B)
USB POWER-DISTRIBUTION REQUIREMENTS
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
•
•
Hosts/self-powered hubs must:
–
–
Current-limit downstream ports
Report overcurrent conditions on USB VBUS
Bus-powered hubs must:
–
–
–
Enable/disable power to downstream ports
Power up at <100 mA
Limit inrush current (<44 Ω and 10 µF)
•
Functions must:
–
–
Limit inrush currents
Power up at <100 mA
The feature set of the TPS204xB/TPS205xB allows them to meet each of these requirements. The integrated
current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and
controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input
ports for bus-powered functions (see Figure 33 through Figure 36).
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Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
TUSB2041B
Hub Controller
SN75240
Tie to TPS2041B EN Input
BUSPWR
GANGED
Downstream
Ports
Upstream
Port
A
B
C
D
DP1
DM1
D +
D −
DP0
DM0
D +
D −
Ferrite Beads
A
B
C
D
GND
5 V
†
GND
SN75240
DP2
DM2
TPS2041B
33 µF
5-V Power
Supply
OC
IN
EN
OUT
DP3
DM3
5 V
D +
D −
A
B
C
D
1 µF
Ferrite Beads
TPS76333
IN
SN75240
GND
DP4
DM4
0.1 µF
4.7 µF
V
CC
3.3 V
GND
5 V
†
4.7 µF
TPS2041B
PWRON1
EN
OC
IN
GND
33 µF
OVRCUR1
0.1 µF
0.1 µF
0.1 µF
OUT
D +
D −
TPS2041B
48-MHz
Crystal
PWRON2
EN
OC
IN
XTAL1
XTAL2
Ferrite Beads
OVRCUR2
GND
5 V
†
OUT
Tuning
Circuit
TPS2041B
PWRON3
EN
OC
IN
33 µF
OVRCUR3
OCSOFF
GND
OUT
D +
D −
TPS2041B
Ferrite Beads
PWRON4
EN
OC
IN
GND
OVRCUR4
0.1 µF
OUT
5 V
†
33 µF
†
USB rev 1.1 requires 120 µF per hub.
Figure 33. Hybrid Self / Bus-Powered Hub Implementation, TPS2041B/TPS2051B
Copyright © 2004–2008, Texas Instruments Incorporated
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Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
TUSB2040
Hub Controller
SN75240
BUSPWR
GANGED
Tie to TPS2041B EN Input
Downstream
Ports
Upstream
Port
A
B
C
D
DP1
DM1
D +
D −
DP0
DM0
D +
D −
Ferrite Beads
A
B
C
D
GND
5 V
†
GND
SN75240
DP2
DM2
TPS2041B
OC EN
IN OUT
1 µF
33 µF
5-V Power
Supply
DP3
DM3
5 V
D +
D −
A
B
C
D
Ferrite Beads
TPS76333
IN
SN75240
GND
DP4
DM4
0.1 µF
4.7 µF
V
CC
3.3 V
GND
5 V
†
4.7 µF
TPS2042B
PWRON1
GND
EN1
OC1
OUT1
OUT2
33 µF
OVRCUR1
PWRON2
OVRCUR2
48-MHz
Crystal
EN2
OC2
XTAL1
XTAL2
D +
D −
IN
0.1 µF
Ferrite Beads
Tuning
Circuit
GND
5 V
†
TPS2042B
EN1
PWRON3
OUT1
OCSOFF
GND
OC1 OUT2
EN2
OVRCUR3
33 µF
PWRON4
OC2
IN
OVRCUR4
D +
D −
0.1 µF
Ferrite Beads
GND
5 V
†
33 µF
†
USB rev 1.1 requires 120 µF per hub.
Figure 34. Hybrid Self / Bus-Powered Hub Implementation, TPS2042B/TPS2052B
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Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
TUSB2040
Hub Controller
1/2 SN75240
BUSPWR
GANGED
Tie to TPS2041B EN Input
Downstream
Ports
Upstream
Port
A
B
C
D
DP1
DM1
D +
D −
DP0
DM0
D +
D −
Ferrite Beads
A
B
C
D
GND
5 V
†
GND
SN75240
DP2
DM2
TPS2041B
47 µF
5-V Power
Supply
OC
IN
EN
OUT
DP3
DM3
5 V
D +
D −
A
B
C
D
1 µF
Ferrite Beads
TPS76333
IN
1/2 SN75240
GND
0.1 µF
4.7 µF
V
3.3 V
GND
CC
5 V
†
4.7 µF
TPS2053B
PWRON1
GND
EN1
OC1
OUT1
47 µF
OUT2
IN1
OVRCUR1
PWRON2
OVRCUR2
EN2
OC2
D +
D −
48-MHz
Crystal
XTAL1
XTAL2
0.1 µF
Ferrite Beads
GND
5 V
†
PWRON3
EN3
OC3
Tuning
Circuit
OUT3
IN2
OVRCUR3
47 µF
OCSOFF
GND
0.1 µF
GND
GND
†
USB rev 1.1 requires 120 µF per hub.
Figure 35. Hybrid Self / Bus-Powered Hub Implementation, TPS2043B/TPS2053B
Copyright © 2004–2008, Texas Instruments Incorporated
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Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
TUSB2040
Hub Controller
SN75240
BUSPWR
GANGED
Tie to TPS2041B EN Input
Downstream
Ports
Upstream
Port
A
B
C
D
DP1
DM1
D +
D −
DP0
DM0
D +
D −
Ferrite Beads
A
B
C
D
GND
5 V
†
GND
SN75240
DP2
DM2
TPS2041B
33 µF
5-V Power
Supply
OC
IN
EN
DP3
DM3
5 V
OUT
D +
D −
A
B
C
D
1 µF
Ferrite Beads
TPS76333
IN
SN75240
GND
DP4
DM4
0.1 µF
4.7 µF
V
CC
3.3 V
GND
5 V
†
4.7 µF
TPS2044B
PWRON1
GND
EN1
OC1
OUT1
OUT2
33 µF
OVRCUR1
PWRON2
OVRCUR2
EN2
OC2
D +
D −
IN1
48-MHz
Crystal
XTAL1
XTAL2
0.1 µF
Ferrite Beads
GND
5 V
†
Tuning
Circuit
EN3
OC3
PWRON3
OUT3
OUT4
OVRCUR3
33 µF
PWRON4
EN4
OC4
OCSOFF
GND
OVRCUR4
IN2
D +
D −
0.1 µF
Ferrite Beads
GND1
GND2
GND
5 V
†
33 µF
†
USB rev 1.1 requires 120 µF per hub.
Figure 36. Hybrid Self / Bus-Powered Hub Implementation, TPS2044B/TPS2054B
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Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
www.ti.com .................................................................................................................................................. SLVS514J–APRIL 2004–REVISED DECEMBER 2008
GENERIC HOT-PLUG APPLICATIONS
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS204xB/TPS205xB, these devices can
be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of
the TPS204xB/TPS205xB also ensures that the switch is off after the card has been removed, and that the
switch is off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for every
insertion of the card or module.
PC Board
TPS2042B
Power
Supply
Block of
Circuitry
OC1
GND
2.7 V to 5.5 V
IN
OUT1
OUT2
0.1 µF
EN1
EN2
1000 µF
Optimum
OC2
Block of
Circuitry
Overcurrent Response
Figure 37. Typical Hot-Plug Implementation (Example, TPS2042B)
By placing the TPS204xB/TPS205xB between the VCC input and the rest of the circuitry, the input power reaches
these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow
voltage ramp at the output of the device. This implementation controls system surge currents and provides a
hot-plugging mechanism for any device.
DETAILED DESCRIPTION
Power Switch
The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the
power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a
minimum current of 500 mA.
Charge Pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
little supply current.
Driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage.
Enable (ENx)
The logic enable pin disables the power switch and the bias for the charge pump, driver, and other circuitry to
reduce the supply current. The supply current is reduced to less than 1 µA or 2 µA when a logic high is present
on EN. A logic zero input on EN restores bias to the drive and control circuits and turns the switch on. The
enable input is compatible with both TTL and CMOS logic levels.
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TPS2041B, TPS2042B
TPS2043B, TPS2044B, TPS2051B
TPS2052B, TPS2053B, TPS2054B
SLVS514J–APRIL 2004–REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
Enable (ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current. The supply current is reduced to less than 1 µA or 2 µA when a logic low is present on ENx.
A logic high input on ENx restores bias to the drive and control circuits and turns the switch on. The enable input
is compatible with both TTL and CMOS logic levels.
Overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A
10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown
occurs, the OCx is asserted instantaneously.
Current Sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its
saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.
Thermal Sense
The TPS204xB/TPS205xB implements a thermal sensing to monitor the operating temperature of the power
distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises. When the die
temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns
off the switch, thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the
device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on
until the fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an
overtemperature shutdown or overcurrent occurs.
Undervoltage Lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
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Product Folder Link(s): TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2009
PACKAGING INFORMATION
Orderable Device
TPS2041BD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
5
5
5
5
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2041BDBVR
TPS2041BDBVRG4
TPS2041BDBVT
TPS2041BDBVTG4
TPS2041BDG4
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2041BDGN
MSOP-
Power
PAD
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2041BDGN-ASY
TPS2041BDGNG4
TPS2041BDGNR
OBSOLETE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
DGN
8
8
8
8
TBD
Call TI
Call TI
MSOP-
Power
PAD
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ACTIVE
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2041BDGNRG4
ACTIVE
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2041BDR
TPS2041BDRG4
TPS2042BD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2042BDG4
TPS2042BDGN
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2042BDGNG4
TPS2042BDGNR
TPS2042BDGNRG4
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
8
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2042BDR
ACTIVE
ACTIVE
SOIC
D
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2042BDRBR
SON
DRB
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2009
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPS2042BDRBT
TPS2042BDRG4
TPS2043BD
SON
DRB
8
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
D
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
16
16
16
16
16
16
16
16
8
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2043BDG4
TPS2043BDR
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2043BDRG4
TPS2044BD
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2044BDG4
TPS2044BDR
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2044BDRG4
TPS2051BD
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2051BDBVR
TPS2051BDBVRG4
TPS2051BDBVT
TPS2051BDBVTG4
TPS2051BDG4
TPS2051BDGN
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
5
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
5
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
DGN
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2051BDGNG4
TPS2051BDGNR
TPS2051BDGNRG4
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
8
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2051BDR
TPS2051BDRG4
TPS2052BD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2052BDG4
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2009
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPS2052BDGN
TPS2052BDGNG4
TPS2052BDGNR
TPS2052BDGNRG4
ACTIVE
MSOP-
Power
PAD
DGN
8
8
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2052BDR
TPS2052BDRBR
TPS2052BDRBT
TPS2052BDRG4
TPS2053BD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
D
DRB
DRB
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
8
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
8
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2053BDG4
TPS2053BDR
TPS2053BDRG4
TPS2054BD
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2054BDG4
TPS2054BDR
TPS2054BDRG4
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2009
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2041B, TPS2042B, TPS2051B :
Automotive: TPS2041B-Q1, TPS2042B-Q1, TPS2051B-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Dec-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS2041BDBVR
TPS2041BDBVT
TPS2041BDGNR
SOT-23
SOT-23
DBV
DBV
DGN
5
5
8
3000
250
179.0
179.0
330.0
8.4
8.4
3.2
3.2
5.3
3.2
3.2
3.3
1.4
1.4
1.3
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q1
MSOP-
Power
PAD
2500
12.4
12.0
TPS2041BDR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.3
2.1
1.3
8.0
8.0
12.0
12.0
Q1
Q1
TPS2042BDGNR
MSOP-
Power
PAD
DGN
TPS2042BDR
TPS2042BDRBR
TPS2042BDRBT
TPS2043BDR
SOIC
SON
D
8
8
2500
3000
250
330.0
330.0
180.0
330.0
330.0
179.0
179.0
330.0
12.4
12.4
12.4
16.4
16.4
8.4
6.4
3.3
3.3
6.5
6.5
3.2
3.2
5.3
5.2
3.3
2.1
1.0
1.0
2.1
2.1
1.4
1.4
1.3
8.0
8.0
8.0
8.0
8.0
4.0
4.0
8.0
12.0
12.0
12.0
16.0
16.0
8.0
Q1
Q2
Q2
Q1
Q1
Q3
Q3
Q1
DRB
DRB
D
SON
8
3.3
SOIC
16
16
5
2500
2500
3000
250
10.3
10.3
3.2
TPS2044BDR
SOIC
D
TPS2051BDBVR
TPS2051BDBVT
TPS2051BDGNR
SOT-23
SOT-23
DBV
DBV
DGN
5
8.4
3.2
8.0
MSOP-
Power
PAD
8
2500
12.4
3.3
12.0
TPS2051BDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Dec-2008
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS2052BDGNR
MSOP-
Power
PAD
DGN
8
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
TPS2052BDR
TPS2052BDRBR
TPS2052BDRBT
TPS2053BDR
SOIC
SON
SON
SOIC
SOIC
D
DRB
DRB
D
8
8
2500
3000
250
330.0
330.0
180.0
330.0
330.0
12.4
12.4
12.4
16.4
16.4
6.4
3.3
3.3
6.5
6.5
5.2
3.3
2.1
1.0
1.0
2.1
2.1
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
16.0
16.0
Q1
Q2
Q2
Q1
Q1
8
3.3
16
16
2500
2500
10.3
10.3
TPS2054BDR
D
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2041BDBVR
TPS2041BDBVT
TPS2041BDGNR
TPS2041BDR
SOT-23
SOT-23
DBV
DBV
DGN
D
5
5
3000
250
195.0
195.0
370.0
340.5
370.0
340.5
370.0
195.0
333.2
200.0
200.0
355.0
338.1
355.0
338.1
355.0
200.0
345.9
45.0
45.0
55.0
20.6
55.0
20.6
55.0
45.0
28.6
MSOP-PowerPAD
SOIC
8
2500
2500
2500
2500
3000
250
8
TPS2042BDGNR
TPS2042BDR
MSOP-PowerPAD
SOIC
DGN
D
8
8
TPS2042BDRBR
TPS2042BDRBT
TPS2043BDR
SON
DRB
DRB
D
8
SON
8
SOIC
16
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Dec-2008
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2044BDR
TPS2051BDBVR
TPS2051BDBVT
TPS2051BDGNR
TPS2051BDR
SOIC
SOT-23
D
DBV
DBV
DGN
D
16
5
2500
3000
250
333.2
195.0
195.0
370.0
340.5
370.0
340.5
370.0
195.0
333.2
333.2
345.9
200.0
200.0
355.0
338.1
355.0
338.1
355.0
200.0
345.9
345.9
28.6
45.0
45.0
55.0
20.6
55.0
20.6
55.0
45.0
28.6
28.6
SOT-23
5
MSOP-PowerPAD
SOIC
8
2500
2500
2500
2500
3000
250
8
TPS2052BDGNR
TPS2052BDR
MSOP-PowerPAD
SOIC
DGN
D
8
8
TPS2052BDRBR
TPS2052BDRBT
TPS2053BDR
SON
DRB
DRB
D
8
SON
8
SOIC
16
16
2500
2500
TPS2054BDR
SOIC
D
Pack Materials-Page 3
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