TPS2042BQDRQ1 [TI]
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES; 电流限制的配电开关
| 型号： | TPS2042BQDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES |
| 文件： | 总29页 (文件大小：622K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
www.ti.com
SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
Check for Samples: TPS2041B-Q1, TPS2042B-Q1, TPS2051B-Q1
1
FEATURES
APPLICATIONS
•
•
Heavy Capacitive Loads
Short-Circuit Protection
•
•
•
•
•
Qualified for Automotive Applications
70-mΩ High-Side MOSFET
500-mA Continuous Current
TPS2041B
DBV PACKAGE
(TOP VIEW)
Thermal and Short-Circuit Protection
Accurate Current Limit:
0.75 A (Min), 1.25 A (Max)
OUT
GND
OC
1
2
3
5
IN
•
•
•
•
•
•
Operating Range: 2.7 V to 5.5 V
0.6-ms Typical Rise Time
4
EN
Undervoltage Lockout
TPS2042B
D PACKAGE
(TOP VIEW)
TPS2051B
D PACKAGE
(TOP VIEW)
Deglitched Fault Report (OC)
No OC Glitch During Power Up
Maximum Standby Supply Current:
1 mA (Single, Dual) or 2 mA (Triple, Quad)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
GND
IN
OC1
GND
OUT
OUT
OUT
OC
OUT1
OUT2
OC2
IN
IN
•
•
•
Bidirectional Switch
EN1
EN2
EN
Junction Temperature Range: –40°C to 125°C
ESD Protection Level Per AEC-Q100
Classification
•
UL Recognized, File Number E169910
DESCRIPTION
The TPS204xB/TPS205xB power-distribution switches are intended for applications where heavy capacitive
loads and short circuits are likely to be encountered. These devices incorporate 70-mΩ N-channel MOSFET
power switches for power-distribution systems that require multiple power switches in a single package. Each
switch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to
control the power-switch rise times and fall times to minimize current surges during switching. The charge pump
requires no external components and allows operation from supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the device limits the output current
to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When
continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction
temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal
shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains
off until valid input voltage is present. This power-distribution switch is designed to set current limit at 1 A (typ).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
GENERAL SWITCH CATALOG
TPS2042B 500 mA
TPS2052B 500 mA
80 mΩ, dual
80 mΩ, quad
33 mΩ, single
80 mΩ, single
80 mΩ, dual
TPS201xA 0.2 A − 2 A
80 mΩ, triple
80 mΩ, quad
TPS2046
TPS2056
TPS2062
TPS2066
TPS2060
TPS2064
250 mA
250 mA
1 A
1 A
1.5 A
1.5 A
TPS202x
TPS203x
0.2 A − 2 A
0.2 A − 2 A
TPS2080
500 mA
500 mA
500 mA
250 mA
250 mA
250 mA
TPS2081
TPS2082
TPS2090
TPS2091
TPS2092
TPS2043B 500 mA
TPS2053B 500 mA
TPS2047 250 mA
TPS2057 250 mA
TPS2085
500 mA
500 mA
500 mA
250 mA
260 mΩ
1.3 Ω
TPS2014
TPS2015
600 mA
1 A
TPS2100/1
TPS2044B 500 mA
TPS2054B 500 mA
TPS2048 250 mA
TPS2058 250 mA
TPS2086
TPS2087
TPS2095
IN1 500 mA
IN2 10 mA
IN1
IN2
TPS2041B 500 mA
TPS2051B 500 mA
OUT
TPS2102/3/4/5
IN1 500 mA
IN2 100 mA
TPS2045
TPS2055
TPS2061
TPS2065
250 mA
250 mA
1 A
TPS2096 250 mA
TPS2097 250 mA
1 A
ORDERING INFORMATION(1)
NO. OF
SWITCHES
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TJ
ENABLE
PACKAGE(2)
Active high
Single
SOIC – D
Reel of 2500
Reel of 3000
Reel of 2500
TPS2051BQDRQ1
TPS2041QDBVRQ1
TPS2042BQDRQ1
2051BQ
–40°C to 125°C
Single
SOT-23 – DBV
SOIC – D
PLIQ
Active low
Dual
2042B
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2
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Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
www.ti.com
SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range unless otherwise noted
VI(IN)
Input voltage range (IN)(2)
–0.3 V to 6 V
–0.3 V to 6 V
VO(OUT)
,
Output voltage range (OUT, OUTx)(2)
VO(OUTx)
VI( ENx )
VI(EN)
VI( OC )
VI( OCx )
IO(OUT)
,
Input voltage range (ENx, EN)
Voltage range (OC, OCx)
Continuous output current
–0.3 V to 6 V
–0.3 V to 6 V
,
,
Internally limited
IO(OUTx)
Continuous total power dissipation
Operating virtual-junction temperature range
Storage temperature range
See Dissipation Ratings
–40°C to 125°C
TJ
Tstg
–65°C to 150°C
Lead temperature, soldering
1,6 mm (1/16 in) from case for 10 s
Human-Body Model (HBM) (H2)
TPS2041B Machine Model (MM) (M0)
Charged-Device Model (CDM) (C5)
260°C
2500 V
50 V
1500 V
2500 V
50 V
Human-Body Model (HBM) (H2)
TPS2042B Machine Model (MM) (M0)
Charged-Device Model (CDM) (C5)
Human-Body Model (HBM) (H2)
Electrostatic discharge (ESD)
protection
1500 V
2000 V
50 V
TPS2051B Machine Model (MM) (M0)
Charged-Device Model (CDM) (C5)
1500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
DISSIPATING RATINGS
T
A ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
585.82 mW
285 mW
D-8
5.8582 mW/°C
2.85 mW/°C
322.20 mW
155 mW
234.32 mW
114 mW
DBV-5
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
UNIT
VI(IN)
Input voltage (IN)
2.7
5.5
V
VI( ENx )
VI(EN)
,
Input voltage (ENx, EN)
0
5.5
V
IO(OUT)
IO(OUTx)
,
Continuous output current (OUT, OUTx)
Operating virtual-junction temperature
0
500
125
mA
°C
TJ
–40
Copyright © 2007–2010, Texas Instruments Incorporated
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TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.5 A, VI(ENx) = 0 V (unless otherwise noted)
PARAMETER
Power Switch
TEST CONDITIONS(1)
MIN TYP MAX UNIT
Static drain-source on-state
resistance, 5-V or 3.3-V
operation
VI(IN) = 5 V or 3.3 V, IO = 0.5 A
–40°C ≤ TJ ≤ 125°C
–40°C ≤ TJ ≤ 125°C
70 135
rDS(on)
mΩ
Static drain-source on-state
resistance, 2.7-V operation(2)
VI(IN) = 2.7 V, IO = 0.5 A
75 150
VI(IN) = 5.5 V
VI(IN) = 2.7 V
VI(IN) = 5.5 V
VI(IN) = 2.7 V
0.6
0.4
1.5
1
tr
tf
Rise time, output(2)
Fall time, output(2)
CL = 1 mF,
RL = 10 Ω
TJ = 25°C
ms
0.05
0.05
0.5
0.5
Enable Input (EN, ENx )
VIH
VIL
II
High-level input voltage
2.7 V ≤ VI(IN) ≤ 5.5 V
2.7 V ≤ VI(IN) ≤ 5.5 V
VI( ENx ) = 0 V or 5.5 V
CL = 100 mF, RL = 10 Ω
CL = 100 mF, RL = 10 Ω
2
V
V
Low-level input voltage
Input current
Turn-on time(2)
Turn-off time(2)
0.8
–0.5
0.5 mA
ms
10 ms
ton
toff
3
Current Limit
TJ = 25°C
0.65
0.6
1
1
1.25
VI(IN) = 5 V, OUT connected to GND,
device enabled into short-circuit
IOS
Short-circuit output current
A
–40°C ≤ TJ ≤ 125°C
1.3
Supply Current (TPS2041B/TPS2051B)
Supply current, low-level output
TJ = 25°C
0.5
0.5
43
1
5
No load on OUT,
VI(EN) = 5.5 V or VI(EN) = 0 V
mA
mA
–40°C ≤ TJ ≤ 125°C
TJ = 25°C
60
70
No load on OUT,
VI(EN) = 0 V or VI(EN) = 5.5 V
Supply current, high-level output
Leakage current
–40°C ≤ TJ ≤ 125°C
43
OUT connected to ground,
VI(EN) = 5.5 V or VI(EN) = 0 V
VI(OUTx) = 5.5 V, IN = ground(2)
–40°C ≤ TJ ≤ 125°C
1
0
mA
mA
Reverse leakage current
TJ = 25°C
Supply Current (TPS2042B)
TJ = 25°C
0.5
0.5
50
50
1
1
5
Supply current, low-level output
Supply current, high-level output
No load on OUT, VI( ENx ) = 5.5 V
No load on OUT, VI( ENx ) = 0 V
mA
mA
–40°C ≤ TJ ≤ 125°C
TJ = 25°C
70
90
–40°C ≤ TJ ≤ 125°C
–40°C ≤ TJ ≤ 125°C
TJ = 25°C
Leakage current
OUT connected to ground, VI( ENx ) = 5.5 V
VI(OUTx) = 5.5 V, IN = ground(2)
mA
mA
Reverse leakage current
Undervoltage Lockout
Low-level input voltage, IN, INx
Hysteresis, IN, INx
0.2
2
4
2.5
V
TJ = 25°C
75
8
mV
Overcurrent (OC, OCx )
Output low voltage, VOL(/OCx)
Off-state current(2)
IO( OCx ) = 5 mA
0.4
1
V
VO( OCx ) = 5 V or 3.3 V
OCx assertion or deassertion
mA
OC deglitch(2)
15 ms
Thermal Shutdown(3)
Thermal shutdown threshold(2)
Recovery from thermal shutdown(2)
Hysteresis(2)
135
125
°C
°C
°C
10
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be accounted for separately.
(2) Specified by design
(3) The thermal shutdown only reacts under overcurrent conditions.
4
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Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
www.ti.com
SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
DEVICE INFORMATION
Terminal Functions (TPS2041B)
TERMINAL
I/O
DESCRIPTION
NAME
EN
NO.
4
I
Enable input, logic low turns on power switch
GND
IN
2
Ground
5
I
Input voltage
OC
3
O
O
Overcurrent, open-drain output, active low
Power-switch output
OUT
1
Functional Block Diagram (TPS2041B)
(See Note A)
CS
OUT
IN
Charge
Pump
Current
Limit
EN
Driver
OC
UVLO
Deglitch
Thermal
Sense
GND
A. CS = Current sense
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TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
www.ti.com
Terminal Functions (TPS2042B)
TERMINAL
I/O
DESCRIPTION
NAME
EN1
NO.
3
I
I
Enable input, logic low turns on power switch IN-OUT1
Enable input, logic low turns on power switch IN-OUT2
Ground
EN2
GND
IN
4
1
2
I
Input voltage
OC1
OC2
OUT1
OUT2
8
O
O
O
O
Overcurrent, open-drain output, active low, IN-OUT1
Overcurrent, open-drain output, active low, IN-OUT2
Power-switch output, IN-OUT1
5
7
6
Power-switch output, IN-OUT2
Functional Block Diagram (TPS2042B)
OC1
Thermal
Deglitch
Sense
GND
EN1
Current
Driver
Limit
Charge
Pump
(See Note A)
CS
OUT1
OUT2
UVLO
(See Note A)
IN
CS
Charge
Pump
Current
Driver
Limit
OC2
EN2
Thermal
Sense
Deglitch
A. CS = Current sense
6
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Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
www.ti.com
SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
Terminal Functions (TPS2051B)
TERMINAL
I/O
DESCRIPTION
NAME
EN
NO.
4
I
Enable input, logic high turns on power switch
GND
IN
1
Ground
2, 3
5
I
Input voltage
OC
O
O
Overcurrent open-drain output, active low
Power-switch output
OUT
6, 7, 8
Functional Block Diagram (TPS2051B)
(See Note A)
CS
OUT
IN
Charge
Pump
Current
Limit
EN
Driver
OC
UVLO
Deglitch
Thermal
Sense
GND
A. CS = Current sense
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TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
OUT
t
f
t
r
R
L
C
L
V
90%
10%
O(OUT)
90%
10%
TEST CIRCUIT
50%
90%
50%
50%
50%
V
V
I(EN)
I(EN)
t
off
t
off
t
on
t
on
90%
V
V
O(OUT)
O(OUT)
10%
10%
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
R = 10 W,
L
V
V
V
V
I(EN)
I(EN)
C = 1 mF
L
I(EN)
I(EN)
T = 255C
A
5 V/div
5 V/div
R = 10 W,
L
V
O(OUT)
C = 1 mF
L
2 V/div
T = 255C
A
V
O(OUT)
2 V/div
t − Time − 500 ms/div
t − Time − 500 ms/div
Figure 2. Turn-On Delay and Rise Time With 1-mF
Figure 3. Turn-Off Delay and Fall Time With 1-mF
Load
Load
8
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TPS2051B-Q1
www.ti.com
SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
PARAMETER MEASUREMENT INFORMATION (continued)
R
= 10 W,
L
V
V
I(EN)
V
C = 100 mF
I(EN)
L
I(EN)
V
I(EN)
T
A
= 255C
5 V/div
5 V/div
R
= 10 W,
L
V
O(OUT)
C = 100 mF
L
2 V/div
T
A
= 255C
V
O(OUT)
2 V/div
t − Time − 500 ms/div
t − Time − 500 ms/div
Figure 4. Turn-On Delay and Rise Time With 100-mF Figure 5. Turn-Off Delay and Fall Time With 100-mF
Load
Load
V = 5 V,
I
V
V
V
V
I(EN)
I(EN)
R
L
= 10 W,
= 255C
I(EN)
I(EN)
T
A
5 V/div
5 V/div
220 mF
470 mF
I
O(OUT)
I
O(OUT)
500 mA/div
500 mA/div
100 mF
t − Time − 500 ms/div
t − Time − 500 ms/div
Figure 6. Short-Circuit Current,
Device Enabled Into Short
Figure 7. Inrush Current With Different
Load Capacitance
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TPS2051B-Q1
SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
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PARAMETER MEASUREMENT INFORMATION (continued)
V
O(OC)
V
O(OC)
2 V/div
2 V/div
I
I
O(OUT)
O(OUT)
500 mA/div
500 mA/div
t − Time − 2 ms/div
t − Time − 2 ms/div
Figure 8. 3-Ω Load Connected to Enabled Device
Figure 9. 2-Ω Load Connected to Enabled Device
10
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SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
TYPICAL CHARACTERISTICS
TURN-ON TIME
vs
TURN-OFF TIME
vs
INPUT VOLTAGE
INPUT VOLTAGE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
3.3
C = 100 mF,
C = 100 mF,
L
L
L
R
T
A
= 10 W,
= 255C
R
T
A
= 10 W,
= 255C
L
3.2
3.1
3
2.9
2.8
0.1
0
2
3
4
5
6
2
3
4
5
6
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 10.
Figure 11.
RISE TIME
vs
FALL TIME
vs
INPUT VOLTAGE
INPUT VOLTAGE
0.25
0.2
0.6
0.5
0.4
C
R
T
= 1 mF,
= 10 W,
= 255C
C
= 1 mF,
= 10 W,
= 255C
L
L
L
R
T
L
A
A
0.15
0.1
0.3
0.2
0.05
0
0.1
0
2
3
4
5
6
2
3
4
5
6
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 12.
Figure 13.
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TPS2042B-Q1
TPS2051B-Q1
SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
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TYPICAL CHARACTERISTICS (continued)
TPS2041B/TPS2051B
SUPPLY CURRENT, OUTPUT ENABLED
vs
TPS2042B
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
60
50
40
30
20
70
60
50
40
30
20
10
0
V = 5.5 V
I
V = 5.5 V
I
V = 5 V
I
V = 5 V
I
V = 3.3 V
I
V = 2.7 V
I
V = 2.7 V
I
V = 3.3 V
I
10
0
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 14.
Figure 15.
TPS2041B/TPS2051B
SUPPLY CURRENT, OUTPUT DISABLED
vs
TPS2042B
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
0.5
0.45
0.4
0.5
V = 5.5 V
V = 5.5 V
0.45
I
I
V = 5 V
I
0.4
0.35
0.3
V = 5 V
I
0.35
0.3
V = 3.3 V
I
V = 3.3 V
I
V = 2.7 V
I
V = 2.7 V
I
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0.05
0
0
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 16.
Figure 17.
12
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SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
TYPICAL CHARACTERISTICS (continued)
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
SHORT-CIRCUIT OUTPUT CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.08
1.06
1.04
1.02
1.0
120
100
80
I
O
= 0.5 A
V = 2.7 V
I
V = 2.7 V
I
V = 3.3 V
I
V
I
= 3.3 V
60
0.98
0.96
0.94
V
I
= 5 V
V = 5 V
I
40
V = 5.5 V
I
20
0
0.92
0.9
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 18.
Figure 19.
THRESHOLD TRIP CURRENT
UNDERVOLTAGE LOCKOUT
vs
vs
INPUT VOLTAGE
JUNCTION TEMPERATURE
2
1.8
1.6
1.4
2.3
T
= 255C
A
Load Ramp = 1 A/10 ms
UVLO Rising
UVLO Falling
2.26
2.22
2.18
1.2
1
2.14
2.1
2.5
3
3.5
4
4.5
5
5.5
6
−50
0
50
100
150
V − Input Voltage − V
I
T − Junction Temperature − 5C
J
Figure 20.
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
100
80
V = 5 V,
T = 255C
A
I
60
40
20
0
0
2.5
5
7.5
10
12.5
Peak Current − A
Figure 22.
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SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
APPLICATION INFORMATION
Power-Supply Considerations
TPS2042B
2
Power Supply
2.7 V to 5.5 V
IN
7
Load
OUT1
0.1 µF
0.1 µF
0.1 µF
22 µF
22 µF
8
OC1
3
5
6
EN1
OC2
Load
OUT2
4
EN2
GND
1
Figure 23. Typical Application (Example, TPS2042B)
A 0.01-mF to 0.1-mF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the
output with a 0.01-mF to 0.1-mF ceramic capacitor improves the immunity of the device to short-circuit transients.
Overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 14 and Figure 15). The TPS204xB/TPS205xB
senses the short and immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current
mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 16 and Figure 17). The TPS204xB/TPS205xB is capable of delivering current up to the
current-limit threshold without damaging the device. Once the threshold has been reached, the device switches
into its constant-current mode.
OC Response
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition
is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or
overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a
momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit.
The TPS204xB/TPS205xB is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch
eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch
is turned off due to an overtemperature shutdown.
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V+
R
pullup
TPS2042B
GND
OC1
OUT1
OUT2
OC2
IN
EN1
EN2
Figure 24. Typical Circuit for the OC Pin (Example, TPS2042B)
Power Dissipation and Junction Temperature
The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large
currents. The thermal resistances of these packages are high compared to those of power packages; it is good
design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the
N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read rDS(on) from Figure 18. Using this value, the power
dissipation per switch can be calculated by:
PD = rDS(on) × I2
Multiply this number by the number of switches being used. This step renders the total power dissipation from
the N-channel MOSFETs.
Finally, calculate the junction temperature:
TJ = PD × RqJA + TA
Where:
TA = Ambient temperature (°C)
RqJA = Thermal resistance
PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
Thermal Protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The TPS204xB/TPS205xB implements a thermal sensing to monitor the operating
junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction
temperature rises due to excessive power dissipation. Once the die temperature rises to approximately 140°C
due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the
power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled
approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or
input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown
or overcurrent occurs.
Undervoltage Lockout (UVLO)
The UVLO ensures that the power switch is in the off state at power up. Whenever the input voltage falls below
approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion systems
where it is not possible to turn off the power switch before input power is removed. The UVLO also keeps the
switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. On
reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage overshoots.
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SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
Universal Serial Bus (USB) Applications
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
•
•
•
•
•
Hosts/self-powered hubs (SPHs)
Bus-powered hubs (BPHs)
Low-power bus-powered functions
High-power bus-powered functions
Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The
TPS204xB/TPS205xB can provide power-distribution solutions to many of these classes of devices.
Hosts/Self-Powered Hubs and Bus-Powered Hubs
Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports (see Figure 25). This power supply must provide from 5.25 V to 4.75 V to the board side of the
downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have
current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop
PCs, monitors, printers, and stand-alone hubs.
Power Supply
Downstream
USB Ports
3.3 V
5 V
TPS2051B
D+
D-
2, 3
0.1 µF
IN
6, 7, 8
V
BUS
OUT
0.1 µF
120 µF
GND
5
4
OC
EN
USB
Control
GND
1
Figure 25. Typical One-Port USB Host/Self-Powered Hub
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are
required to power up with less than one unit load. The BPH usually has one embedded function, and power is
always available to the controller of the hub. If the embedded function and hub require more than 100 mA on
power up, the power to the embedded function may need to be kept off until enumeration is completed. This can
be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the
embedded function is not necessary if the aggregate power draw for the function and controller is less than one
unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
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Low-Power and High-Power Bus-Powered Functions
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 mF at power up, the device must implement inrush current limiting (see Figure 26).
Power Supply
D+
D−
3.3 V
TPS2042B
2
8
IN
V
BUS
7
10 µF
0.1 µF
Internal
Function
OUT1
GND
0.1 µF
10 µF
OC1
EN1
OC2
EN2
3
5
USB
Control
6
4
OUT2
GND
Internal
Function
0.1 µF
10 µF
1
Figure 26. High-Power Bus-Powered Function (Example, TPS2042B)
USB Power-Distribution Requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
•
•
Hosts/self-powered hubs must:
–
–
Current-limit downstream ports
Report overcurrent conditions on USB VBUS
Bus-powered hubs must:
–
–
–
Enable/disable power to downstream ports
Power up at <100 mA
Limit inrush current (<44 Ω and 10 mF)
•
Functions must:
–
–
Limit inrush currents
Power up at <100 mA
The feature set of the TPS204xB/TPS205xB allows them to meet each of these requirements. The integrated
current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and
controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input
ports for bus-powered functions (see Figure 27 and Figure 28).
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SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
TUSB2046
Hub Controller
SN75240
Tie to TPS2051B EN Input
BUSPWR
Downstream
Ports
Upstream
Port
A
B
C
D
GANGED
DP1
DM1
D +
D -
DP0
DM0
D +
D -
Ferrite Beads
A
B
C
D
GND
5 V
GND
SN75240
DP2
DM2
TPS2051B
OC EN
33 µF
(see Note A)
5-V Power
Supply
DP3
DM3
5 V
IN OUT
1 µF
D +
D -
A
B
C
D
Ferrite Beads
TPS76333
IN
SN75240
GND
5 V
DP4
DM4
0.1 µF
4.7 µF
V
CC
3.3 V
GND
4.7 µF
TPS2051B
33 µF
(see Note A)
PWRON1
EN
OC
IN
GND
OVRCUR1
0.1 µF
0.1 µF
OUT
D +
D -
TPS2051B
48-MHz
Crystal
PWRON2
EN
OC
IN
XTAL1
XTAL2
Ferrite Beads
OVRCUR2
GND
5 V
OUT
Tuning
Circuit
TPS2051B
33 µF
(see Note A)
PWRON3
EN
OC
IN
0.1 µF
0.1 µF
OVRCUR3
OCSOFF
GND
OUT
D +
D -
TPS2051B
Ferrite Beads
PWRON4
EN
OC
IN
GND
5 V
OVRCUR4
OUT
33 µF
(see Note A)
A. USB rev 1.1 requires 120 mF per hub.
Figure 27. Hybrid Self-Powered/Bus-Powered Hub Implementation (TPS2051B)
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www.ti.com
TUSB2046
Hub Controller
SN75240
BUSPWR
Tie to TPS2051B EN Input
Downstream
Ports
Upstream
Port
A
B
C
D
GANGED
DP1
DM1
D +
D -
DP0
DM0
D +
D -
Ferrite Beads
A
B
C
D
GND
5 V
GND
SN75240
DP2
DM2
TPS2051B
OC EN
33 µF
(see Note A)
5-V Power
Supply
DP3
DM3
5 V
IN OUT
D +
D -
A
B
C
D
Ferrite Beads
TPS76333
IN
SN75240
GND
5 V
DP4
DM4
0.1 µF
4.7 µF
V
CC
3.3 V
GND
4.7 µF
TPS2042B
33 µF
(see Note A)
PWRON1
GND
EN1
OC1
OUT1
OUT2
OVRCUR1
PWRON2
OVRCUR2
48-MHz
Crystal
EN2
OC2
XTAL1
XTAL2
D +
D -
IN
0.1 µF
Ferrite Beads
Tuning
Circuit
GND
5 V
TPS2042B
EN1
PWRON3
OUT1
OCSOFF
GND
OC1 OUT2
EN2
OVRCUR3
33 µF
(see Note A)
PWRON4
OC2
IN
OVRCUR4
D +
D -
0.1 µF
Ferrite Beads
GND
5 V
33 µF
(see Note A)
A. USB rev 1.1 requires 120 mF per hub.
Figure 28. Hybrid Self-Powered/Bus-Powered Hub Implementation (TPS2042B)
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TPS2051B-Q1
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SLVS782A –NOVEMBER 2007–REVISED JUNE 2010
Generic Hot-Plug Applications
In many applications, it may be necessary to remove modules or PC boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS204xB/TPS205xB, these devices can
be used to provide a softer startup to devices being hot-plugged into a powered system. The UVLO feature of the
TPS204xB/TPS205xB also ensures that the switch is off after the card has been removed, and that the switch is
off during the next insertion. The UVLO feature ensures a soft start with a controlled rise time for every insertion
of the card or module.
PC Board
TPS2042B
Power
Supply
Block of
Circuitry
OC1
GND
2.7 V to 5.5 V
IN
OUT1
OUT2
0.1 µF
EN1
EN2
1000 µF
Optimum
OC2
Block of
Circuitry
Overcurrent Response
Figure 29. Typical Hot-Plug Implementation (Example, TPS2042B)
By placing the TPS204xB/TPS205xB between the VCC input and the rest of the circuitry, the input power reaches
these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow
voltage ramp at the output of the device. This implementation controls system surge currents and provides a
hot-plugging mechanism for any device.
DETAILED DESCRIPTION
Power Switch
The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the
power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a
minimum current of 500 mA.
Charge Pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
little supply current.
Driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage.
Enable (ENx)
The logic enable pin disables the power switch and the bias for the charge pump, driver, and other circuitry to
reduce the supply current. The supply current is reduced to less than 1 mA or 2 mA when a logic high is present
on EN. A logic zero input on EN restores bias to the drive and control circuits and turns the switch on. The
enable input is compatible with both TTL and CMOS logic levels.
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Enable (EN)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current. The supply current is reduced to less than 1 mA or 2 mA when a logic low is present on EN. A
logic high input on EN restores bias to the drive and control circuits and turns the switch on. The enable input is
compatible with both TTL and CMOS logic levels.
Overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A
10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown
occurs, the OCx is asserted instantaneously.
Current Sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its
saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.
Thermal Sense
The TPS204xB/TPS205xB implements a thermal sensing to monitor the operating temperature of the power
distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises. When the die
temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns
off the switch, thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the
device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on
until the fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an
overtemperature shutdown or overcurrent occurs.
Undervoltage Lockout (UVLO)
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS2041BQDBVRQ1
TPS2042BQDRQ1
TPS2051BQDRQ1
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOIC
DBV
D
5
8
8
3000
2500
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Request Free Samples
SOIC
D
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2041B-Q1, TPS2042B-Q1, TPS2051B-Q1 :
Catalog: TPS2041B, TPS2042B, TPS2051B
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2010
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jun-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2041BQDBVRQ1
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jun-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
195.0 200.0 45.0
TPS2041BQDBVRQ1
5
3000
Pack Materials-Page 2
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