TPS2046DRG4 [TI]
0.345A, 2.7-5.5V Dual (1In/2Out) Hi-Side MOSFET, Fault Report, Act-Low Enable 8-SOIC -40 to 85;
| 型号： | TPS2046DRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 0.345A, 2.7-5.5V Dual (1In/2Out) Hi-Side MOSFET, Fault Report, Act-Low Enable 8-SOIC -40 to 85 光电二极管 |
| 文件： | 总26页 (文件大小：600K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
features
typical applications
135-mΩ -Maximum (5-V Input) High-Side
MOSFET Switch
Notebook, Desktop and Palmtop PCs
Monitors, Keyboards, Scanners, and
Printers
250 mA Continuous Current per Channel
Independent Short-Circuit and Thermal
Protection With Overcurrent Logic Output
Digital Cameras, Phones, and PBXs
Hot-Insertion Applications
Operating Range . . . 2.7-V to 5.5-V
Logic-Level Enable Input
2.5-ms Typical Rise Time
TPS2046
D OR P PACKAGE
(TOP VIEW)
TPS2056
D OR P PACKAGE
(TOP VIEW)
Undervoltage Lockout
10 µA Maximum Standby Supply Current
Bidirectional Switch
GND
IN
OC1
GND
IN
OC1
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
OUT1
OUT2
OC2
OUT1
OUT2
OC2
Available in 8-pin SOIC and PDIP Packages
Ambient Temperature Range, –40°C to 85°C
EN1
EN2
EN1
EN2
2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection
description
The TPS2046 and TPS2056 dual power-distribution switches are intended for applications where heavy
capacitive loads and short circuits are likely. These devices incorporate in single packages two 135-mΩ
N-channel MOSFET high-side power switches for power-distribution systems that require multiple power
switches. Each switch is controlled by a logic enable compatible with 5-V and 3-V logic. Gate drive is provided
by an internal charge pump that controls the power-switch rise times and fall times to minimize current surges
during switching. The charge pump requires no external components and allows operation from supplies as low
as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS2046 and TPS2056 limit
the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic
output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch
causingthejunctiontemperaturetorise, athermalprotectioncircuitshutsofftheswitchinovercurrenttoprevent
damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal
circuitry ensures the switch remains off until valid input voltage is present.
The TPS2046 and TPS2056 are designed to limit at 0.44-A load. These power distribution switches, available
in 8-pin small-outline integrated circuit (SOIC) and 8-pin plastic dual-in-line packages (PDIP), operate over an
ambient temperature range of –40°C to 85°C.
AVAILABLE OPTIONS
RECOMMENDED
MAXIMUM CONTINUOUS
LOAD CURRENT
(A)
TYPICAL
SHORT-CIRCUIT CURRENT
LIMIT AT 25°C
PACKAGED DEVICES
T
A
ENABLE
SOIC
PDIP
(P)
†
(D)
(A)
–40°C to 85°C Active low
–40°C to 85°C Active high
0.25
0.25
0.44
0.44
TPS2046D TPS2046P
TPS2056D TPS2056P
†
The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2046DR)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
TPS2046 functional block diagram
OC1
Thermal
GND
Sense
EN1
Current
Driver
Limit
Charge
Pump
†
CS
OUT1
OUT2
UVLO
Power Switch
†
IN
CS
Charge
Pump
Current
Limit
Driver
†
Current sense
OC2
EN2
Thermal
Sense
Terminal Functions
TERMINAL
NO.
D OR P
I/O
DESCRIPTION
NAME
TPS2046
TPS2056
EN1
EN2
EN1
EN2
GND
IN
3
4
–
–
1
2
8
5
7
6
–
–
3
4
1
2
8
5
7
6
I
I
Enable input. Logic low turns on power switch, IN-OUT1.
Enable input. Logic low turns on power switch, IN-OUT2.
Enable input. Logic high turns on power switch, IN-OUT1.
Enable input. Logic high turns on power switch, IN-OUT2.
Ground
I
I
I
I
Input voltage
OC1
OC2
OUT1
OUT2
O
O
O
O
Overcurrent. Logic output active low, for power switch, IN-OUT1
Overcurrent. Logic output active low, for power switch, IN-OUT2
Power-switch output
Power-switch output
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (V
= 5 V).
I(IN)
Configured as a high-side switch, the power switch prevents current flow from OUTx to IN and IN to OUTx when
disabled. The power switch can supply a minimum of 250 mA per switch.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
enable (ENx or ENx)
Thelogicenabledisablesthepowerswitchandthebiasforthechargepump, driver, andothercircuitrytoreduce
the supply current to less than 10 µA when a logic high is present on ENx (TPS2046) or a logic low is present
on ENx (TPS2056). A logic zero input on ENx or logic high on ENx restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.
overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.
thermal sense
The TPS2046 and TPS2056 implement a dual-threshold thermal trip to allow fully independent operation of the
power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When
thedietemperaturerisestoapproximately140°C, theinternalthermalsensecircuitrycheckstodeterminewhich
power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting
operation of the adjacent power switches. Hysteresis is built into the thermal sense, and after the device has
cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the
fault is removed. The (OCx) open-drain output is asserted (active low) when overtemperature or overcurrent
occurs.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage range, V
Output voltage range, V
Input voltage range, V
Continuous output current, I
(see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
I(IN)
(see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
O(OUTx)
I(ENx)
I(IN)
or V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
I(ENx)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
O(OUTx)
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
J
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C . . . . . . . . . . . . . . . . . . . . . 2 kV
Machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 kV
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
DERATING FACTOR
T
≤ 25°C
T
A
= 70°C
T = 85°C
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
D
P
725 mW
5.8 mW/°C
9.4 mW/°C
464 mW
752 mW
377 mW
611 mW
1175 mW
recommended operating conditions
TPS2046
TPS2056
UNIT
MIN
2.7
0
MAX
5.5
MIN
2.7
0
MAX
Input voltage, V
Input voltage, V
5.5
5.5
V
V
I(IN)
or V
5.5
I(ENx)
I(ENx)
Continuous output current, I
O(OUTx)
0
250
125
0
250
125
mA
°C
Operating virtual junction temperature, T
–40
–40
J
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
electrical characteristics over recommended operating junction temperature range, V
= 5.5 V,
I(IN)
I = rated current, V
= 0 V, V
= Hi (unless otherwise noted)
O
I(ENx)
I(ENx)
power switch
TPS2046
†
TPS2056
TYP
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
V
= 5 V,
T = 25°C,
J
I(IN)
= 0.1 A
80
95
80
90
95
I
O
Static drain-source on-state
resistance, 5-V operation
V
= 5 V,
= 0.1 A
T = 85°C,
J
I(IN)
I(IN)
I(IN)
I(IN)
I(IN)
I(IN)
90
100
85
120
135
105
135
150
120
135
105
135
150
I
O
V
= 5 V,
= 0.1 A
T = 125°C,
J
100
85
mΩ
I
O
r
DS(on)
V
= 3.3 V, T = 25°C,
J
= 0.1 A
I
O
Static drain-source on-state
resistance, 3.3-V operation
V
= 3.3 V, T = 85°C,
J
= 0.1 A
100
115
2.5
3
100
115
2.5
3
I
O
V
= 3.3 V, T = 125°C,
J
= 0.1 A
I
O
V
C
= 5.5 V, T = 25°C,
J
= 1 µF,
R = 20 Ω
L
L
t
t
Rise time, output
Fall time, output
ms
ms
r
V
C
= 2.7 V, T = 25°C,
J
= 1 µF,
I(IN)
R = 20 Ω
L
L
V
C
= 5.5 V, T = 25°C,
J
I(IN)
L
4.4
2.5
4.4
2.5
= 1 µF,
R = 20 Ω
L
f
V
C
= 2.7 V, T = 25°C,
J
I(IN)
= 1 µF,
R = 20 Ω
L
L
†
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input ENx or ENx
TPS2046
MIN TYP
TPS2056
MIN TYP
PARAMETER
TEST CONDITIONS
UNIT
MAX
MAX
V
V
High-level input voltage
Low-level input voltage
2.7 V ≤ V
4.5 V ≤ V
≤ 5.5 V
≤ 5.5 V
≤ 4.5 V
2
2
V
V
IH
I(IN)
I(IN)
I(IN)
0.8
0.4
0.5
0.8
0.4
IL
2.7 V≤ V
TPS2046
TPS2056
V
V
= 0 V or V
= V
I(IN)
= 0 V
–0.5
I(ENx)
I(ENx)
or V
I
I
Input current
µA
= V
–0.5
0.5
20
40
I(ENx)
I(IN)
I(ENx)
t
t
Turn-on time
Turn-off time
C
C
= 100 µF,
= 100 µF,
R
R
= 20 Ω
= 20 Ω
20
40
ms
on
L
L
L
L
off
current limit
TPS2046
MIN TYP
TPS2056
MIN TYP
†
PARAMETER
UNIT
TEST CONDITIONS
MAX
MAX
V
= 5 V, OUT connected to GND,
I(IN)
Device enable into short circuit.
I
Short-circuit output current
0.345
0.44 0.525 0.345
0.44 0.525
A
OS
†
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
electrical characteristics over recommended operating junction temperature range, V
= 5.5 V,
I(IN)
I = rated current, V
= 0 V, V
= Hi (unless otherwise noted) (continued)
O
I(ENx)
I(ENx)
supply current
TPS2046
TYP MAX
TPS2056
MIN TYP MAX
PARAMETE
R
TEST CONDITIONS
T = 25°C
UNIT
MIN
0.015
1
J
Supply
TPS2046
TPS2056
TPS2046
TPS2056
V
V
= V
I(ENx)
I(IN)
–40°C ≤ T ≤ 125°C
10
No Load
on OUTx
J
current,
low-level
output
µA
µA
T = 25°C
0.015
1
J
= 0 V
= 0 V
I(ENx)
–40°C ≤ T ≤ 125°C
10
J
T = 25°C
J
80
100
Supply
V
V
I(ENx)
–40°C ≤ T ≤ 125°C
100
No Load
on OUTx
J
current,
high-level
output
T = 25°C
80
100
J
= V
= V
I(ENx)
I(IN)
–40°C ≤ T ≤ 125°C
100
J
OUTx
connected
to ground
V
V
V
V
–40°C ≤ T ≤ 125°C TPS2046
100
0.3
I(ENx)
I(ENx)
I(ENx)
I(ENx)
I(IN)
J
Leakage
current
µA
µA
= 0 V
= 0 V
= Hi
–40°C ≤ T ≤ 125°C TPS2056
100
0.3
J
Reverse
leakage
current
TPS2046
IN = high
impedance
T = 25°C
J
TPS2056
undervoltage lockout
TPS2046
TYP
TPS2056
TYP MAX
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
Low-level input voltage
2
2.5
2
2.5
V
Hysteresis
T = 25°C
J
100
100
mV
overcurrent OCx
TPS2046
TYP
TPS2056
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
10
MIN
MAX
10
†
Sink current
V
= 5 V
mA
V
O
Output low voltage
I
= 5 mA,
V
V
0.5
1
0.5
1
O
OL(OCx)
= 3.3 V
†
Off-state current
†
V
= 5 V,
µA
O
O
Specified by design, not production tested.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
PARAMETER MEASUREMENT INFORMATION
OUTx
t
t
f
r
RL
CL
V
90%
10%
O(OUTx)
90%
10%
TEST CIRCUIT
50%
90%
50%
50%
50%
V
V
I(ENx)
I(ENx)
t
t
off
t
t
on
off
on
90%
V
V
O(OUTx)
O(OUTx)
10%
10%
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
V
I(ENx)
V
I(ENx)
(5 V/div)
(5 V/div)
V
T
C
= 5 V
= 25°C
= 0.1 µF
V
T
C
= 5 V
= 25°C
= 0.1 µF
I(IN)
A
L
I(IN)
A
L
V
O(OUTx)
(2 V/div)
V
O(OUTx)
(2 V/div)
0
1000
2000
3000
4000
5000
0
1
2
3
4
5
6
7
8
9
10
t – Time – ms
t – Time – ms
Figure 2. Turnon Delay and Rise Time
Figure 3. Turnoff Delay and Fall Time
with 0.1-µF Load
with 0.1-µF Load
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
PARAMETER MEASUREMENT INFORMATION
V
I(ENx)
V
I(ENx)
(5 V/div)
(5 V/div)
V
= 5 V
I(IN)
= 25°C
V
= 5 V
I(IN)
= 25°C
T
A
T
A
V
O(OUTx)
(2 V/div)
V
C
R
= 1 µF
= 20 Ω
O(OUTx)
(2 V/div)
L
L
C
R
= 1 µF
= 20 Ω
L
L
0
1
2
3
4
5
6
7
8
9
10
0
2
4
6
8
10 12 14 16 18 20
t – Time – ms
t – Time – ms
Figure 4. Turnon Delay and Rise Time
Figure 5. Turnoff Delay and Fall Time
with 1-µF Load
with 1-µF Load
V
T
A
= 5 V
I(IN)
= 25°C
V
T
A
= 5 V
I(IN)
= 25°C
V
I(ENx)
(5 V/div)
V
O(OUTx)
(2 V/div)
I
I
O(OUTx)
(0.2 A/div)
O(OUTx)
(0.5 A/div)
0
1
2
3
4
5
6
7
8
9
10
0
10 20 30 40 50 60 70 80 90 100
t – Time – ms
t – Time – ms
Figure 6. TPS2046, Short-Circuit Current,
Device Enabled into Short
Figure 7. TPS2046, Threshold Trip Current
with Ramped Load on Enabled Device
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
PARAMETER MEASUREMENT INFORMATION
V
= 5 V
I(IN)
= 25°C
T
A
R
= 20 Ω
L
V
V
I(ENx)
(5 V/div)
O(OCx)
(5 V/div)
220 µF
47 µF
100 µF
I
O(OUTx)
(0.5 A/div)
I
V
T
= 5 V
O(OUTx)
I(IN)
= 25°C
(0.2 A/div)
A
0
2
4
6
8
10 12 14 16 18 20
0
20 40 60 80 100 120 140 160 180 200
t – Time – ms
t – Time – ms
Figure 8. Inrush Current with 220-µF, 100-µF
and 47-µF Load Capacitance
Figure 9. Ramped Load on Enabled Device
V
T
A
= 5 V
V
= 5 V
I(IN)
= 25°C
I(IN)
T = 25°C
A
V
V
O(OCx)
(5 V/div)
O(OCx)
(5 V/div)
I
I
O(OUTx)
(0.5 A/div)
O(OUTx)
(0.5 A/div)
0
200
400
600
800
1000
0
200
400
600
800
1000
t – Time – µs
t – Time – µs
Figure 10. 4-Ω Load Connected
Figure 11. 1-Ω Load Connected
to Enabled Device
to Enabled Device
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
TYPICAL CHARACTERISTICS
TURNON DELAY
vs
INPUT VOLTAGE
TURNOFF DELAY
vs
INPUT VOLTAGE
6
5.5
5
15
13
11
C
R
T
= 1 µF
= 20 Ω
= 25°C
C
R
T
= 1 µF
= 20 Ω
= 25°C
L
L
A
L
L
A
4.5
4
9
7
3.5
3
2.5
3
3.5
4
4.5
5
5.5
6
2.5
3
3.5
4
4.5
5
5.5
6
V – Input Voltage – V
I
V – Input Voltage – V
I
Figure 12
Figure 13
RISE TIME
vs
FALL TIME
vs
LOAD CURRENT
LOAD CURRENT
2.7
2.6
2.5
2.85
2.8
V
T
= 5 V
= 25°C
V
T
= 5 V
I (IN)
A
I (IN)
= 25°C
A
2.75
2.4
2.3
2.7
2.65
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
– Load Current – A
I
L
– Load Current – A
I
L
Figure 14
Figure 15
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
TYPICAL CHARACTERISTICS
SUPPLY CURRENT, OUTPUT ENABLED
SUPPLY CURRENT, OUTPUT DISABLED
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
200
180
160
2000
1800
V
= 5.5 V
I(IN)
V
= 5.5 V
= 5 V
1600
1400
I(IN)
V
I(IN)
= 5 V
V
I(IN)
V
= 4 V
I(IN)
1200
1000
800
V
I(IN)
= 4 V
V
I(IN)
= 2.7 V
V
= 2.7 V
I(IN)
140
120
100
600
V
= 3.3 V
I(IN)
400
200
0
–200
–50 –25
0
25
50
75 100 125 150
–50 –25
0
25
50
75
100 125 150
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 16
Figure 17
SUPPLY CURRENT, OUTPUT DISABLED
SUPPLY CURRENT, OUTPUT ENABLED
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
2000
1600
200
180
160
T
J
= 125°C
T
J
= 125°C
T
J
= 85°C
1200
800
T
J
= 25°C
140
400
0
T
J
= 0°C
T
J
= 25°C
T
4
= 85°C
J
T
J
= –40°C
120
100
T
J
= –40°C
T
J
= 0°C
–400
2.5
3
3.5
4.5
5
5.5
6
2.5
3
3.5
4
4.5
5
5.5
6
V – Input Voltage – V
I
V – Input Voltage – V
I
Figure 19
Figure 18
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
vs
JUNCTION TEMPERATURE
INPUT VOLTAGE
175
150
125
175
150
125
I
O
= 0.25 A
I
O
= 0.25 A
V
= 2.7 V
I(IN)
V
I(IN)
= 3.3 V
T
J
= 125°C
T
J
= 85°C
100
75
100
75
V
I(IN)
= 4.5 V
T
J
= 25°C
T
J
= 0°C
V
I(IN)
= 5 V
T
J
= –40°C
50
–50 –25
50
2.5
0
25
50
75
100 125 150
3
3.5
4
4.5
5
5.5
6
T
J
– Junction Temperature – °C
V – Input Voltage – V
I
Figure 20
Figure 21
INPUT-TO-OUTPUT VOLTAGE
SHORT-CURCUIT OUTPUT CURRENT
vs
vs
LOAD CURRENT
INPUT VOLTAGE
45
490
T
A
= 25°C
40
35
30
25
20
15
10
470
450
V
= 2.7 V
I(IN)
T
= –40°C
J
V
= 3.3 V
I(IN)
T
J
= 25°C
430
410
390
370
350
T
J
= 125°C
V
= 4.5 V
I(IN)
V
I(IN)
= 5 V
5
0
0.1
0.14
0.18
0.22
0.26
0.3
2.5
3
3.5
4
4.5
5
5.5
I
L
– Load Current – A
V – Input Voltage – V
I
Figure 22
Figure 23
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
TYPICAL CHARACTERISTICS
THRESHOLD TRIP CURRENT
SHORTCIRCUIT OUTPUT CURRENT
vs
vs
INPUT VOLTAGE
JUNCTION TEMPERATURE
0.73
0.71
450
T
= 25°C
A
V
= 5 V
Load Ramp = 1 A/10 ms
I(IN)
445
440
435
430
425
420
415
V
I(IN)
= 4 V
V
I(IN)
= 2.7 V
0.69
0.67
0.65
410
405
2.5
3
3.5
4
4.5
5
5.5
6
–50 –25
0
25
50
75
100
125
V – Input Voltage – V
I
T
J
– Junction Temperature – °C
Figure 24
Figure 25
UNDERVOLTAGE LOCKOUT
vs
CURRENT-LIMIT RESPONSE
vs
JUNCTION TEMPERATURE
PEAK CURRENT
2.5
2.4
500
350
250
100
0
V
T
A
= 5 V
I(INx)
= 25°C
Start Threshold
Stop Threshold
2.3
2.2
2.1
2
–50 –25
0
25
50
75
100 125 150
0
2
4
6
8
10
T
J
– Junction Temperature – °C
Peak Current – A
Figure 26
Figure 27
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
TYPICAL CHARACTERISTICS
OVERCURRENT (OCx) RESPONSE TIME
vs
PEAK CURRENT
10
V
T
A
= 5 V
I(IN)
= 25°C
8.5
7
5.5
4
0
2
4
6
8
10
Peak Current – A
Figure 28
APPLICATION INFORMATION
TPS2046
2
Power Supply
2.7 V to 5.5 V
IN
7
Load
Load
OUT1
OUT2
0.1 µF
0.1 µF
0.1 µF
22 µF
22 µF
8
OC1
EN1
OC2
EN2
3
5
6
4
GND
1
Figure 29. Typical Application
power-supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing
the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit
transients.
14
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TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
APPLICATION INFORMATION
overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do
not increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs
only if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before V
and immediately switch into a constant-current output.
has been applied (see Figure 6). The TPS2046 and TPS2056 sense the short
I(IN)
In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high
currents may flow for a short time before the current-limit circuit can react. After the current-limit circuit has
tripped (reached the overcurrent trip threshhold) the device switches into constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 7). The TPS2046 and TPS2056 are capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
OCx response
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connectingaheavycapacitiveloadtoanenableddevicecancausemomentaryfalseovercurrentreportingfrom
the inrush current flowing through the device, charging the downstream capacitor. An RC filter (see Figure 30)
can be connected to the OCx pin to reduce false overcurrent reporting caused by hot-plug switching events or
extremely high capacitive loads. Using low-ESR electrolytic capacitors on the output lowers the inrush current
flow through the device during hot-plug events by providing a low impedance energy source, thereby reducing
erroneous overcurrent reporting.
V+
V+
R
R
pullup
pullup
TPS2046
TPS2046
R
filter
To USB
Controller
GND
OC1
OUT1
OUT2
OC2
GND
OC1
OUT1
OUT2
OC2
IN
IN
C
filter
EN1
EN2
EN1
EN2
Figure 30. Typical Circuits for OC Pin and RC Filter for Damping Inrush OC Responses
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
APPLICATION INFORMATION
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to that of power packages; it is
good design practice to check power dissipation and junction temperature. The first step is to find r
input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature
at the
DS(on)
of interest and read r
from Figure 21. Next, calculate the power dissipation using:
DS(on)
2
I
P
r
D
DS(on)
Finally, calculate the junction temperature:
T
P
R
T
J
D
JA
A
Where:
T = Ambient Temperature °C
A
θJA
R
= Thermal resistance SOIC = 172°C/W, PDIP = 106°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extendedperiodsoftime. ThefaultsforcetheTPS2046andTPS2056intoconstantcurrentmode, whichcauses
the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch
is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels.
The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the
thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The
switch continues to cycle in this manner until the load fault or input power is removed.
The TPS2046 and TPS2056 implement a dual thermal trip to allow fully independent operation of the power
distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die
temperature rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is
in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation
of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach
160°C, both switches turn off. The OC open-drain output is asserted (active low) when overtemperature or
overcurrent occurs.
undervoltage lockout (UVLO)
Anundervoltagelockoutensuresthatthepowerswitchisintheoffstateatpowerup. Whenevertheinputvoltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce
EMI and voltage overshoots.
16
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TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
APPLICATION INFORMATION
Universal Serial Bus (USB) applications
The Universal Serial Bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
Hosts/self-powered hubs (SPH)
Bus-powered hubs (BPH)
Low-power, bus-powered functions
High-power, bus-powered functions
Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS2046 and
TPS2056 can provide power-distribution solutions for many of these classes of devices.
bus-powered hubs
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs
are required to power up with less than one unit load. The BPH usually has one embedded function, and power
is always available to the controller of the hub. If the embedded function and hub require more than 100 mA
on power up, the power to the embedded function may need to be kept off until enumeration is completed. This
can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching
the embedded function is not necessary if the aggregate power draw for the function and controller is less than
one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
low-power bus-powered functions and high-power bus-powered functions
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA, and high-power functions must draw less than 100 mA at power up
and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination
of 44 Ω and 10 µF at power up, the device must implement inrush current limiting (see Figure 31).
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
APPLICATION INFORMATION
Power Supply
D+
3.3 V
TPS2046
D–
2
V
IN
BUS
GND
7
10 µF
0.1 µF
Internal
OUT1
Function
0.1 µF
10 µF
8
OC1
EN1
OC2
EN2
3
5
USB
Control
4
6
Internal
Function
OUT2
GND
0.1 µF
10 µF
1
Figure 31. High-Power Bus-Powered Function
USB power-distribution requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power distribution features must be implemented.
Bus-Powered Hubs must:
–
–
–
Enable/disable power to downstream ports
Power up at <100 mA
Limit inrush current (<44 Ω and 10 µF)
Functions must:
–
–
Limit inrush currents
Power up at <100 mA
The feature set of the TPS2046 and TPS2056 allows them to meet each of these requirements. The integrated
current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable
and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as the input
ports for bus-power functions (see Figure 32).
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
APPLICATION INFORMATION
TUSB2040
Hub Controller
SN75240
BUSPWR
Downstream
Upstream
Port
A
B
C
D
Ports
GANGED
DP1
DM1
D +
D –
DP0
DM0
D +
D –
Ferrite Beads
A
B
C
D
GND
5 V
GND
SN75240
DP2
DM2
†
33 µF
DP3
DM3
5 V
D +
D –
A
B
C
D
1 µF
Ferrite Beads
TPS76333
IN
SN75240
GND
DP4
DM4
0.1 µF
4.7 µF
V
3.3 V
GND
5 V
†
CC
4.7 µF
TPS2046
PWRON1
GND
EN1
OC1
OUT1
33 µF
OUT2
IN
OVRCUR1
PWRON2
OVRCUR2
EN2
OC2
D +
D –
48-MHz
Crystal
XTAL1
XTAL2
Ferrite Beads
0.1 µF
GND
5 V
TPS2046
Tuning
Circuit
EN1
OC1
PWRON3
OUT1
OUT2
OVRCUR3
†
33 µF
PWRON4
EN2
OC2
OCSOFF
GND
OVRCUR4
IN
D +
D –
0.1 µF
Ferrite Beads
GND
5 V
†
33 µF
†
USB rev 1.1 requires 120 µF per hub.
Figure 32. Bus-Powered Hub Implementation
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
APPLICATION INFORMATION
generic hot-plug applications (see Figure 33)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS2046 and TPS2056, these devices
can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
oftheTPS2046andTPS2056alsoensurestheswitchwillbeoffafterthecardhasbeenremoved, andtheswitch
will be off during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every
insertion of the card or module.
PC Board
Power
Supply
TPS2046
GND
OC1
Block of
Circuitry
IN
OUT1
2.7 V to 5.5 V
0.1 µF
1000 µF
Optimum
OUT2
OC2
EN1
EN2
Block of
Circuitry
Overcurrent Response
Figure 33. Typical Hot-Plug Implementation
By placing the TPS2046 and TPS2056 between the V
input and the rest of the circuitry, the input power will
CC
reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providng
aslowvoltagerampattheoutputofthedevice. Thisimplementaioncontrolssystemsurgecurrentsandprovides
a hot-plugging mechanism for any device.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2046, TPS2056
DUAL CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
SLVS183 – APRIL 1999
MECHANICAL DATA
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
4040082/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Aug-2008
PACKAGING INFORMATION
Orderable Device
TPS2046D
Status (1)
NRND
NRND
NRND
NRND
NRND
NRND
NRND
NRND
NRND
NRND
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2046DG4
TPS2046DR
TPS2046DRG4
TPS2046P
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
D
D
D
P
P
D
D
D
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TPS2046PE4
TPS2056D
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2056DG4
TPS2056DR
TPS2056DRG4
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS2046DR
TPS2056DR
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2046DR
TPS2056DR
SOIC
SOIC
D
D
8
8
2500
2500
340.5
346.0
338.1
346.0
20.6
29.0
Pack Materials-Page 2
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相关型号：
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0.345A, 2.7-5.5V Dual (1In/2Out) Hi-Side MOSFET, Fault Report, Act-Low Enable 8-PDIP -40 to 85
TI
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