TPS2060CDGNR [TI]
Dual Channel, Current-Limited, Power-Distribution Switches; 双通道，限流配电开关
| 型号： | TPS2060CDGNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual Channel, Current-Limited, Power-Distribution Switches |
| 文件： | 总25页 (文件大小：1945K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
Dual Channel, Current-Limited, Power-Distribution Switches
Check for Samples: TPS2062C, TPS2066C, TPS2060C, TPS2064C, TPS2002C, TPS2003C
1
FEATURES
2
•
•
•
•
•
•
•
•
•
Dual Power Switch Family
•
•
•
Built-in Softstart
Rated Currents of 1 A, 1.5 A, 2 A
Accurate ±20% Current-limit Tolerance
Fast Overcurrent Response – 2 µs (Typical)
70-mΩ (Typical) High-Side N-Channel MOSFET
Operating Range: 4.5 V to 5.5 V
Pin for Pin with Existing TI Switch Portfolio
Ambient Temperature Range: –40°C to 85°C
APPLICATIONS
•
•
•
•
USB Ports/Hubs, Laptops, Desktops
High-Definition Digital TVs
Set Top Boxes
Deglitched Fault Reporting (FLTx)
Output Discharge When Disabled
Reverse Current Blocking
Short-Circuit Protection
DESCRIPTION
The TPS20xxC dual power-distribution switch family is intended for applications such as USB where heavy
capacitive loads and short-circuits may be encountered. This family offers multiple devices with fixed current-limit
thresholds for applications between 1 A and 2 A.
The TPS20xxC dual family limits the output current to a safe level by operating in a constant-current mode when
the output load exceeds the current-limit threshold. This provides a predictable fault current under all conditions.
The fast overcurrent response time eases the burden on the main 5 V supply to provide regulated power when
the output is shorted. The power-switch rise and fall times are controlled to minimize current surges during turn-
on and turn-off.
DRC
(Top View)
DGN
(Top View)
D
(Top View)
10
9
1
2
3
4
5
FLT 1
OUT 1
OUT 2
NC
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
GND
FLT 1
OUT 1
OUT 2
FLT 2
FLT 1
OUT 1
OUT 2
FLT 2
GND
IN
GND
IN
IN
IN
PAD
PAD
8
EN 1 or EN 1
EN 2 or EN 2
EN 1 or EN 1
EN 2 or EN 2
7
EN 1 or EN 1
6
FLT 2
EN 2 or EN 2
V
0.1 mF
IN
IN
V
OUT 1
OUT1
R
R
V
OUT 2
FLT1
10 kW
FLT2
OUT2
10 kW
150 mF x 2
FLT1
FLT2
Fault Signals
GND
Pad
EN1 or EN1
EN2 or EN2
Control Signals
Figure 1. TYPICAL APPLICATION
(1)
Table 1. Devices
STATUS
RATED CURRENT
DEVICES
MSOP-8 (PowerPad™)
SON -10
SOIC-8
1 A
1.5 A
2 A
TPS2062C and 66C
TPS2060C and 64C
TPS2002C and 03C
Active and Active
-
Active and Active
Active and Active
-
-
-
-
Preview / Preview
(1) For more details, see the DEVICE INFORMATION table
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE INFORMATION(1)(2)
PACKAGE DEVICES(3)
MAXIMUM
OPERATING
CURRENT
OUTPUT
DISCHARGE
BASE PART
NUMBER
MSOP-8
(DGN)
PowerPAD™
ENABLE
MARKING
SOIC-8
(D)
SON-10
(DRC)
1
1
Low
High
Low
High
Low
High
Y
Y
Y
Y
Y
Y
TPS2062C
TPS2066C
TPS2060C
TPS2064C
TPS2002C
TPS2003C
√
√
–
–
–
–
√
√
√
√
–
–
–
–
–
–
√
√
VRBQ
VRDQ
VRAQ
VRCQ
VREQ
VRFQ
1.5
1.5
2
2
(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package code for MSOP-8 is “DGN” and for SON is “DRC”.
(3) “–” indicates the device is not available in this package.
ABSOLUTE MAXIMUM RATINGS(1)(2)
VALUE
UNIT
MIN
–0.3
–6
MAX
Voltage range on IN, OUTx, ENx or ENx, FLTx(3)
Voltage range from IN to OUT
6
6
V
V
Maximum junction temperature, TJ
Human Body Model
Internally Limited
°C
kV
V
2
ESD
Charged Device Model
500
IEC 61000-4-2, Contact / Air(4)
8 / 15
kV
(1) Absolute maximum ratings apply over recommended junction temperature range.
(2) All voltages are with respect to GND unless otherwise noted.
(3) See INPUT AND OUTPUT CAPACITANCE section.
(4) VOUT was surged on a PCB with input and output bypassing per Figure 1 (except input capacitor was 22 µF) with no device failure.
THERMAL INFORMATION
D
8 PINS
129.9
83.5
70.4
36.6
66.9
n/a
DGN
8 PINS
57.2
110.5
60.7
7.8
DRC
10 PINS
45.4
58
THERMAL METRIC(1)(2)
UNITS
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
21.1
1.9
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
24
21.3
9.1
θJCbot
14.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
2
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX
5.5
5.5
1
UNIT
VIN
Input voltage, IN
4.5
0
V
VEnable Input voltage, ENx or ENx
TPS2062C and 66C
TPS2060C and 64C
TPS2002C and 03C
IOUTx
Continuous ouput current, OUTx
1.5
2
A
TJ
Operating junction temperature
Sink current into FLTx
–40
0
125
5
°C
IFLTx
mA
ELECTRICAL CHARACTERISTICS(1)(2)
TJ = TA = 25°C，VIN = 5 V, VENx = VIN or VENx = 0V (unless otherwise noted)
PARAMETER
POWER SWITCH
TEST CONDITIONS
MIN
TYP
MAX UNIT
TPS2062C and 66C (1 A)
DGN
DGN
D
70
70
90
90
84
95
TPS2062C and 66C (1 A),
–40°C ≤ (TJ, TA ) ≤ 85°C
TPS2062C and 66C (1 A)
108
TPS2062C and 66C (1 A),
–40°C ≤ (TJ, TA ) ≤ 85°C
D
122
rDS(on)
On-resistance
mΩ
TPS2060C and 64C (1.5 A)
70
70
70
70
84
95
84
95
TPS2060C and 64C (1.5 A), –40°C ≤ (TJ, TA ) ≤ 85°C
TPS2002C and 03C (2 A)
TPS2002C and 03C (2 A), –40°C ≤ (TJ, TA ) ≤ 85°C
CURRENT LIMIT
TPS2062C and 66C (1 A)
TPS2060C and 64C (1.5 A)
TPS2002C and 03C (2 A)
VIN = 5 V (see Figure 6),
1.28
1.83
2.43
1.61
2.29
2.96
1.94
2.75
3.49
IOS
Current limit, See Figure 7
A
One-half full load → R(SHORT) = 50 mΩ, Measure from
application to when current falls below 120% of final
value
tIOS
Short-circuit response time
2
µs
SUPPLY CURRENT
ISD
Supply current, device disabled
I(OUTx) = 0 mA
0.01
60
1
IS1E
Supply current, single switch enabled I(OUTx) = 0 mA
75
µA
Supply current, both switches
enabled
IS2E
ILKG
I(OUTx) = 0 mA
100
120
1
Reverse leakage current
VOUT = 5.5 V, VIN = 0 V, measured IOUTx
0.15
OUTPUT DISCHARGE
RPD
Output pull-down resistance(2)
VIN = V(OUTx) = 5 V, disabled
400
470
600
Ω
(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
(2) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
Copyright © 2011–2012, Texas Instruments Incorporated
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3
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
–40°C ≤ (TJ = TA) ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A, typical values are at 5 V and 25°C
(unless otherwise noted)
PARAMETER
POWER SWITCH
TEST CONDITIONS(1)
MIN
TYP
MAX UNIT
DGN
D
70
90
70
70
112
TPS2062C and 66C (1 A)
135
mΩ
112
rDS(on)
On-resistance
TPS2060C and 64C (1.5 A)
TPS2002C and 03C (2 A)
112
ENABLE INPUT (ENx or ENx)
ENx (ENx), High-level input
voltage
VIH
4.5 V ≤ VIN ≤ 5.5 V
2
ENx (ENx), Low-level input
Voltage
V
VIL
0.8
Hysteresis
VIN = 5 V
0.14
0
Leakage current
VENx = 5.5 V or 0 V, VENx = 0 V or 5.5 V
-1
1
µA
ms
VIN = 5 V, CL = 1 µF, RL = 100 Ω, ENx ↑ or
ENx ↓, See Figure 4, Figure 5, and Figure 2
ton
Turn-on time
Turn-off time
1 A, 1.5 A, 2 A Rated
1.4
1.9
2.4
VIN = 5 V, CL = 1 µF, RL = 100 Ω, ENx ↑ or
EN ↓, See Figure 4, Figure 5, and Figure 2
toff
ms
1 A, 1.5 A, 2 A Rated
1.95
0.58
0.33
2.60
0.82
0.47
3.25
1.15
0.66
CL = 1 µF, RL = 100 Ω, see Figure 3
1 A, 1.5 A, 2 A Rated
tr
tf
Rise time, output
Fall time, output
ms
ms
CL = 1 µF, RL = 100 Ω, see Figure 3
1 A, 1.5 A, 2 A Rated
CURRENT LIMIT
TPS2062C/66C (1 A)
1.12
1.72
2.22
1.61
2.29
2.96
2.10
2.86
3.7
IOS
Current-limit, See Figure 7
TPS2060C and 64C (1.5 A)
TPS2002C and 03C (2 A)
A
VIN = 5 V (see Figure 6), One-half full load → R(SHORT)
50 mΩ, measure from application to when current falls
below 120% of final value
=
tIOS
Short-circuit response time(2)
2
µs
SUPPLY CURRENT
ISD
Supply current, switch disabled
Standard conditions, I(OUTx) = 0 mA
Standard conditions, I(OUTx) = 0 mA
0.01
10
90
Supply current, single switch
enabled
IS1E
µA
Supply current, both switches
enabled
IS2E
ILKG
Standard conditions, I(OUTx) = 0 mA
150
Reverse leakage current
VOUT = 5.5 V, VIN = 0 V, measured I(OUTx)
0.20
0.14
UNDERVOLTAGE LOCKOUT
UVLO
Low-level input voltage, IN
Hysteresis, IN(2)
VIN rising
3.4
4.0
V
V
FLTx
Output low voltage, FLTx
Off-state leakage
FLTx deglitch
I(FLTx) = 1 mA
0.2
1
V
V(FLTx) = 5.5 V
µA
ms
FLTx overcurrent assertion/deassertion
7
10
13
(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
(2) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
4
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS (continued)
–40°C ≤ (TJ = TA) ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A, typical values are at 5 V and 25°C
(unless otherwise noted)
PARAMETER
OUTPUT DISCHARGE
TEST CONDITIONS(1)
MIN
TYP
MAX UNIT
VIN = 5 V, VOUT = 5 V, disabled
300
350
470
560
800
Ω
1200
Output pull-down resistance(3)
THERMAL SHUTDOWN
VIN = 4 V, VOUT = 5 V, disabled
In current limit
135
155
Junction thermal shutdown
threshold
°C
°C
Not in current limit
Hysteresis(3)
20
(3) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
OUTx
R
L
C
L
90%
t
t
r
f
V
OUT
10%
Figure 2. Output Rise / Fall Test Load
Figure 3. Power-On and Off Timing
SPACER
V
EN
50%
50%
50%
50%
V
t
EN
off
t
on
t
t
off
on
90%
90%
V
OUT
V
10%
OUT
10%
Figure 4. Enable Timing, Active High Enable
Figure 5. Enable Timing, Active Low Enable
SPACER
V
IN
Decreasing
Load
Slope = -r
Resistance
DS(on)
120% x I
I
OS
OUT
I
OS
0 V
0A
I
OUT
0 A
I
t
OS
IOS
Figure 6. Output Short Circuit Parameters
SPACER
Figure 7. Output Characteristic Showing Current
Limit
Copyright © 2011–2012, Texas Instruments Incorporated
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5
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
CS
IN
OUT1
Current
Sense
Disable+UVLO
Charge
Pump
Current
Limit
EN1
or
Driver
EN1
FLT1
UVLO
OTSD
10-ms
Deglitch
Thermal
Sense
UVLO
CS
OUT2
Current
Sense
Disable+UVLO
Current
Limit
EN2
or
Driver
UVLO
EN2
FLT2
OTSD
Thermal
10-ms
Deglitch
GND
Sense
6
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
DEVICE INFORMATION
PIN FUNCTIONS – MSOP-8 PACKAGES
NAME
GND
IN
TPS2066C/64C TPS2062C/60C
I/O
Pwr
I
DESCRIPTION
1
2
1
2
Ground connection
Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to
GND close to the IC
EN1
EN1
EN2
EN2
FLT2
3
-
-
3
-
I
I
Enable input channel 1, logic high turns on power switch
Enable input channel 1, logic low turns on power switch
Enable input channel 2, logic high turns on power switch
Enable input channel 2, logic low turns on power switch
4
-
I
4
5
I
5
O
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 2
OUT2
OUT1
FLT1
6
7
8
6
7
8
O
O
O
Power-switch output channel 2, connected to load
Power-switch output channel 1, connected to load
Active-low open-drain output, asserted during over-current, or overtemperature conditions on
channel 1
PowerPAD™
PAD
PAD
Pwr
Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect
PAD to GND plane as a heatsink.
PIN FUNCTIONS – SOIC-8 PACKAGES
NAME
GND
IN
TPS2066C
TPS2062C
I/O
Pwr
I
DESCRIPTION
1
2
1
2
Ground connection
Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to
GND close to the IC
EN1
EN1
EN2
EN2
FLT2
3
-
-
I
I
Enable input channel 1, logic high turns on power switch
Enable input channel 1, logic low turns on power switch
Enable input channel 2, logic high turns on power switch
Enable input channel 2, logic low turns on power switch
3
-
4
-
I
4
5
I
5
O
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 2
OUT2
OUT1
FLT1
6
7
8
6
7
8
O
O
O
Power-switch output channel 2, connected to load
Power-switch output channel 1, connected to load
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 1
PIN FUNCTIONS – SON-10 PACKAGES
NAME
GND
IN
TPS2003C
TPS2002C
I/O
Pwr
I
DESCRIPTION
1
1
Ground connection
2, 3
2, 3
Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to
GND close to the IC
EN1
EN1
EN2
EN2
FLT2
4
–
5
–
6
–
4
–
5
6
I
I
Enable input channel 1, logic high turns on power switch
Enable input channel 1, logic low turns on power switch
Enable input channel 2, logic high turns on power switch
Enable input channel 2, logic low turns on power switch
I
I
O
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 2
NC
7
8
7
8
No connect – leave floating.
OUT2
OUT1
FLT1
O
O
O
Power-switch output channel 2, connect to load
Power-switch output channel 1, connect to load
9
9
10
10
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 1
PowerPAD™
PAD
PAD
Pwr
Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect
PAD to GND plane as a heatsink.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
www.ti.com
TYPICAL CHARACTERISTICS
IOUT1 IOUT2
0.1 F
VIN
IN
VOUT1
VOUT2
OUT1
OUT2
3.01 k
3.01 k
RLoad1
RLoad2
FLT1
FLT2
GND
Pad
CL1
CL2
Fault Signals
EN1 or EN1
EN2 or EN2
Control Signals
Figure 8. Test Circuit for System Operation in Typical Characteristics Section
8
6
8
VIN = 5 V,CLx = 1 µF,RLoadx = 5 Ω, TPS2062C
VIN = 5 V,CLx = 1 µF,RLoadx = 5 Ω, TPS2062C
6
4
4
ENx
OUTx
OUTx
2
2
ENx
0
0
−2
−2
−3m −2m −1m
0
1m
2m
3m
4m
5m
−3m −2m −1m
0
1m
2m
3m
4m
5m
Time (s)
Time (s)
Figure 9. TPS2062C Turn on Delay and
Figure 10. TPS2062C Turn off Delay and
Rise Time With 1-μF Load
Fall Time With 1-μF Load
8
6
8
6
VIN = 5 V,CLx = 150 µF,RLoadx = 5 Ω, TPS2062C
VIN = 5 V,CLx = 150 µF,RLoadx = 5 Ω, TPS2062C
4
4
ENx
OUTx
OUTx
2
2
ENx
0
0
−2
−2
−3m −2m −1m
0
1m
2m
3m
4m
5m
−3m −2m −1m
0
1m
2m
3m
4m
5m
Time (s)
Time (s)
Figure 11. TPS2062C Turn on Delay and
Figure 12. TPS2062C Turn off Delay and
Rise Time With 150-μF Load
Fall Time With 150-μF Load
8
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
TYPICAL CHARACTERISTICS (continued)
8
6
6.0
5.0
4.0
3.0
2.0
1.0
0.0
−1.0
7
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−0.5
VIN = 5 V,CLx = 150 µF,RLoadx = 0 Ω, TPS2062C
VIN = 5 V,RLoadx = 5.0 Ω, TPS2062C
5
FLTx
3
4
FLTx
OUTx
ENx
1
2
ENx
−1
−3
−5
−7
−9
1000 µF
220 µF
0
OUTx
−2
−4
−6
OUTx Current
680 µF
150 µF
−10m
0
10m
20m
30m
40m
50m
−2m
0
2m
4m
6m
8m
10m
Time (s)
Time (s)
Figure 13. TPS2062C Enable Into Short
Figure 14. TPS2062C Inrush Current
With Different Load Capacitance
8
6
6.0
5.0
4.0
3.0
2.0
1.0
0.0
−1.0
8
6
6.0
5.0
4.0
3.0
2.0
1.0
0.0
−1.0
VIN = 5 V,CLx = 150 µF,RLoadx = 5 Ω, TPS2062C
VIN = 5 V,CLx = 150 µF,RLoadx = 5 Ω, TPS2062C
VIN
VIN
4
4
FLTx
2
2
OUTx
FLTx
0
0
OUTx
−2
−4
−6
−2
−4
−6
IOUTx
IOUTx
−8m
−4m
0
4m
8m
12m
−4m
0
4m
8m
12m
16m
Time (s)
Time (s)
Figure 15. TPS2062C Power Up – Enabled
Figure 16. TPS2062C Power Down – Enabled
8
6
4.2
3.6
3.0
2.4
1.8
1.2
0.6
0.0
VIN = 5 V, CLx = 150 μF, RLoadx = 2.0 Ω, TPS2062C
FLTx
ENx
4
2
OUTx
0
−2
−4
−6
−8
IOUTx
−0.6
8m 10m 12m 14m
−4m −2m
0
2m
4m
6m
Time (s)
Figure 17. TPS2062C Enable With 2-Ω Load
Figure 18. TPS2062C Enable With 1-Ω Load
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
8
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−0.5
8
6
4.2
3.6
3.0
2.4
1.8
1.2
0.6
0.0
−0.6
VIN = 5 V, CLx = 150 μF, RLoadx = 10 Ω, TPS2062C
VIN = 5 V, CLx = 150 μF, RLoadx = 0 Ω, TPS2062C
6
FLTx
4
4
FLTx
OUTx
2
2
ENx
0
0
ENx
OUTx
−2
−4
−6
−8
−2
−4
−6
−8
IOUTx
IOUTx
−8m −4m
0
4m 8m 12m 16m 20m 24m 28m 32m
−2m
0
2m 4m 6m 8m 10m 12m 14m 16m 18m
Time (s)
Time (s)
Figure 19. TPS2062C Enable/Disable
into Output Short
Figure 20. TPS2062C Enable/Disable
into 10-Ω Load
8
6
12.0
10.0
8.0
8
6
7
VIN = 5 V,CLx = 150 µF,RLoadx = 3.3 Ω, TPS2064C
VIN = 5 V, CLx = 150 μF, RLoadx = 0 Ω, TPS2064C
6
FLTx
4
5
4
OUTx
ENx
2
4
ENx
2
6.0
OUTx
0
3
0
4.0
−2
−4
−6
−8
2
1
−2
−4
−6
2.0
IOUTx
IOUTx
0
0.0
−1
5m
−4m −3m −2m −1m
0
1m
2m
3m
4m
−2.0
Time (s)
−6m −4m −2m
0
2m 4m 6m 8m 10m 12m 14m
Time (s)
Figure 21. TPS2064C Enable into Short
Figure 22. TPS2064C Enable into 3.3 Ω and 150-μF Laod
7
5
42
36
30
24
18
12
6
8
6
12.0
VIN = 5 V, CLx = 0 μF, RLoadx = 50 mΩ, TPS2064C
VIN = 5 V, CLx = 150 μF, RLoadx = 0 Ω, TPS2003C
10.0
FLTx
IOUTx
4
8.0
OUTx
ENx
2
6.0
OUTx
3
0
4.0
−2
−4
−6
2.0
IOUTx
1
0.0
0
−1
−3μ
−6
−2.0
−2μ
−1μ
0
1μ
2μ
3μ
−6m −4m −2m
0
2m 4m 6m 8m 10m 12m 14m
Time (s)
Time (s)
Figure 23. TPS2064C Short Applied
Figure 24. TPS2003C Enable into Short
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Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
TYPICAL CHARACTERISTICS (continued)
8
7
3.4
3.2
3
2.0 A rated
1.5 A rated
VIN = 5 V, CLx = 150 μF, RLoadx = 2.5 Ω, TPS2003C
VIN = 5.5 V
6
4
6
5
2.8
2.6
2.4
2.2
2
OUTx
ENx
2
4
0
3
−2
−4
−6
−8
2
1.8
1.6
1.4
1.2
1
1.0 A rated
IOUTx
0
−1
−3m −2m −1m
0
1m 2m 3m 4m 5m 6m 7m
−40
−20
0
20
40
60
80
100
120
Time (s)
Junction Temperature (°C)
Figure 25. TPS2003C Enable into 2.5 Ω and 150-μF Laod
Figure 26. Current Limit (IOS) vs Temperature
100
2.5
2
VIN = 5 V
VIN = 5 V
1.0 A rated
2 A rated
90
80
1.5
1
1.5 A rated
2.0 A rated
1 A rated
70
60
0.5
0
1.5 A rated
50
40
−40
−0.5
−20
0
20
40
60
80
100
120
−40
−20
0
20
40
60
80
100
120
Junction Temperature (°C)
Junction Temperature (°C)
Figure 27. Input - output Resistance (RDS(ON)) vs
Temperature
Figure 28. Supply Current (Device Disable) - ISD vs
Temperature
130
VIN = 5 V
1.0 A rated(IS2E
)
120
2.0 A rated(IS2E
)
110
100
90
1.5 A rated(IS2E
)
2.0 A rated(IS1E
)
80
1.5 A rated(IS1E
)
70
60
1.0 A rated(IS1E
)
50
−40
−20
0
20
40
60
80
100
120
Junction Temperature (°C)
Figure 29. Supply Current (Enable) - ISE vs Temperature
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
www.ti.com
DETAILED DESCRIPTION
OVERVIEW
The TPS20xxC dual are current-limited, power-distribution switches providing between 1 A and 2 A of continuous
load current in 5-V circuits. These parts use N-channel MOSFETs for low resistance, maintaining output voltage
load regulation. They are designed for applications where short circuits or heavy capacitive loads will be
encountered. Device features include UVLO, ON/OFF control (Enable), reverse blocking when disabled, output
discharge when disabled, overcurrent protection, over-temperature protection, and deglitched fault reporting.
They are pin for pin with existing TI Switch Portfolio.
UNDERVOLTAGE LOCKOUT (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch when the input voltage is below the UVLO
threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large current
surges. FLTx is high impedance when the TPS20xxC dual is in UVLO.
ENABLE (ENx or ENx)
The logic input of ENx or ENx disables all of the internal circuitry while maintaining the power switch OFF. The
supply current of the device can be reduced to less than 1 µA when both switches are disabled. A logic low input
on ENx or a logic high input on ENx enables the driver, control circuits, and power switch of corresponding
channel.
The ENx or ENx input voltage is compatible with both TTL and CMOS logic levels. The FLTx is immediately
cleared and the output discharge circuit is enabled when the device is disabled.
DEGLITCHED FAULT REPORTING
FLTx is an open-drain output that asserts (active low) during an overcurrent or overtemperature condition on
each corresponding channel. The FLTx output remains asserted until the fault condition is removed or the
channel is disabled. The TPS20xxC dual eliminates false FLTx reporting by using internal delay circuitry after
entering or leaving an overcurrent condition. The “deglitch” time is typically 10 ms. This ensures that FLTx is not
accidentally asserted under overcurrent conditions with a short time, such as starting into a heavy capacitive
load. Over temperature conditions are not deglitched. The FLTx pin is high impedance when the device is
disabled and in undervoltage lockout (UVLO). The fault circuits are independent so that another channel
continues to operate when one channel is in a fault condition.
OVERCURRENT PROTECTION
The TPS20xxC dual responds to overloads by limiting each channel output current to the static IOS levels shown
in the Electrical Characteristics table. When an overload condition is present, the device maintains a constant
current (IOS) and reduces the output voltage accordingly, with the output voltage falling to (IOS x RSHORT). Three
possible overload conditions can occur. In the first condition, the output has been shorted before the device is
enabled or before voltage is applied to IN. The device senses over-current and immediately switches into a
constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At
the instant a short -circuit occurs, high currents may flow for several microseconds (tIOS) before the current-limit
circuit reacts. The device operates in constant-current mode after the current-limit circuit has responded. In the
third condition, the load is increased gradually beyond the recommended operating current. The current is
permitted to rise until the current-limit threshold is reached. The devices are capable of delivering current up to
the current-limit threshold without damage. Once the threshold is reached, the device switches into constant-
current mode. For all of the above three conditions, the device may begin thermal cycling if the overcurrent
condition persists.
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Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
OVERTEMPERATURE PROTECTION
The TPS20xxC dual includes per channel overtemperature protection circuitry, which activates at 135°C (min)
junction temperature while in current limit. There is an overall thermal shutdown of 155°C (min) junction
temperature when the TPS20xxC dual is not in current limit. The device remains off until the junction temperature
cools 20°C and then restarts. Thermal shutdown may occur during an overload due to the relatively large power
dissipation [(VIN – VOUT) × IOS] driving the junction temperature up. The power switch cycles on and off until the
fault is removed. This topology allows one channel to continue normal operation even if the other channel is in an
over-temperature condition.
SOFTSTART, REVERSE BLOCKING AND DISCHARGE OUTPUT
The power MOSFET driver incorporates circuitry that controls the rise and fall times of the output voltage to limit
large current and voltage surges on the input supply, and provides built-in soft-start functionality.
The TPS20xxC dual power switch will block current from OUT to IN when turned off by the UVLO or disabled.
The TPS20xxC dual includes an output discharge function on each channel. A 470Ω (typ.) discharge resistor will
dissipate stored charge and leakage current on OUTx when the device is in UVLO or disabled. However as this
circuit is biased from IN, the output discharge will not be active when IN voltage is close to 0 V.
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
www.ti.com
APPLICATION INFORMATION
INPUT AND OUTPUT CAPACITANCE
Input and output capacitance improves the performance of the device. For all applications, a 0.1 µF or greater
ceramic bypass capacitor between IN and GND is recommended as close to the device as possible for local
noise de-coupling. The actual capacitance should be optimized for the particular application. This precaution
reduces ringing on the input due to power-supply transients. Additional input capacitance may be needed on the
input to reduce the overshoot voltage from exceeding the absolute maximum voltage of the device during heavy
transients.
A 120 µF minimum output capacitance is required when implementing USB standard applications. Typically this
uses a 150 µF electrolytic capacitor. If the application does not require 120 µF of output capacitance, a minimum
of 10 µF ceramic capacitor on the output is recommended in order to reduce the transient negative voltage on
OUTx pin caused by load inductance during a short circuit. The transient negative voltage should be less than
1.5 V for 10 µs.
POWER DISSIPATION AND JUNCTION TEMPERATURE
It is good design practice to estimate power dissipation and maximum expected junction temperature of the
TPS20xxC dual. The system designer can control choices of package, proximity to other power dissipating
devices, and printed circuit board (PCB) design based on these calculations. These have a direct influence on
maximum junction temperature. Other factors such as airflow and maximum ambient temperature are often
determined by system considerations.
Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and
maintain the junction temperature as low as practical.
The following procedure requires iteration because power loss is due to the two internal MOSFETs 2 × I2 ×
rDS(on), and rDS(on) is a function of the junction temperature. As an initial estimate, use the rDS(on) at 125°C from the
typical characteristics, and the preferred package thermal resistance for the preferred board construction from
the thermal parameters section.
TJ = TA + [(2 × IOUT2 × rDS(on) × θJA]
Where:
IOUT = rated OUT pin current (A)
rDS(on) = Power switch on-resistance at an assumed TJ (Ω)
TA = Maximum ambient temperature (°C)
TJ = Maximum junction temperature (°C)
θJA = Thermal resistance (°C/W)
If the calculated TJ is substantially different from the original assumption, look up a new value of rDS(on) and
recalculate.
If the resulting TJ is not less than 125°C, try a PCB construction and/or package with lower θJA.
14
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Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
TPS2062C, TPS2066C
TPS2060C, TPS2064C
TPS2002C, TPS2003C
www.ti.com
SLVSAX6C –OCTOBER 2011–REVISED JUNE 2012
REVISION HISTORY
Changes from Original (October 2011) to Revision A
Page
•
•
•
Changed devices TPS2062C and TPS2066C MSOP-8 package From: Preview to Active ................................................. 1
Changed the IOS current limit values for TPS2062C and 66C (1 A). .................................................................................... 3
Changed the IOS current limit values for TPS2062C/66C (1 A). ........................................................................................... 4
Changes from Revision A (March 2012) to Revision B
Page
•
Changed device TPS2060C MSOP-8 package From: Preview to Active ............................................................................ 1
Changes from Revision B (March 2012) to Revision C
Page
•
•
•
Changed devices TPS2062C and TPS2066C SOIC-8 package From: Preview to Active ................................................... 1
Changed the TPS2062C and 66C rDS(on) D package TYP value From: 84 to 90 mΩ and added the MAX value ................ 3
Changed the TPS2062C and 66C rDS(on) D package TYP value From: 84 to 90 mΩ .......................................................... 4
Copyright © 2011–2012, Texas Instruments Incorporated
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15
Product Folder Link(s): TPS2062C TPS2066C TPS2060C TPS2064C TPS2002C TPS2003C
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jun-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS2002CDRCR
TPS2002CDRCT
TPS2003CDRCR
PREVIEW
PREVIEW
PREVIEW
SON
SON
SON
DRC
DRC
DRC
10
10
10
3000
250
TBD
TBD
Call TI
Call TI
Call TI
Call TI
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAUAGLevel-1-260C-UNLIM
CU NIPDAUAGLevel-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAUAGLevel-1-260C-UNLIM
CU NIPDAUAGLevel-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAUAGLevel-1-260C-UNLIM
CU NIPDAUAGLevel-1-260C-UNLIM
TPS2003CDRCT
TPS2060CDGN
TPS2060CDGNR
TPS2062CD
PREVIEW
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
SON
DRC
DGN
DGN
D
10
8
3000
80
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
8
2500
75
Green (RoHS
& no Sb/Br)
SOIC
8
Green (RoHS
& no Sb/Br)
TPS2062CDGN
TPS2062CDGNR
TPS2062CDR
MSOP-
PowerPAD
DGN
DGN
D
8
80
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
8
2500
2500
80
Green (RoHS
& no Sb/Br)
SOIC
8
Green (RoHS
& no Sb/Br)
TPS2064CDGN
TPS2064CDGNR
MSOP-
PowerPAD
DGN
DGN
8
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
8
2500
Green (RoHS
& no Sb/Br)
TPS2066CD
PREVIEW
ACTIVE
SOIC
D
8
8
75
80
TBD
Call TI
Call TI
TPS2066CDGN
MSOP-
PowerPAD
DGN
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-1-260C-UNLIM
TPS2066CDGNR
TPS2066CDR
ACTIVE
MSOP-
PowerPAD
DGN
D
8
8
2500
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-1-260C-UNLIM
PREVIEW
SOIC
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jun-2012
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
2500
2500
2500
2500
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2060CDGNR
TPS2062CDGNR
TPS2064CDGNR
TPS2066CDGNR
MSOP-
Power
PAD
DGN
DGN
DGN
DGN
8
8
8
8
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
3.4
3.4
3.4
3.4
1.4
1.4
1.4
1.4
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
MSOP-
Power
PAD
MSOP-
Power
PAD
MSOP-
Power
PAD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2060CDGNR
TPS2062CDGNR
TPS2064CDGNR
TPS2066CDGNR
MSOP-PowerPAD
MSOP-PowerPAD
MSOP-PowerPAD
MSOP-PowerPAD
DGN
DGN
DGN
DGN
8
8
8
8
2500
2500
2500
2500
364.0
364.0
360.0
364.0
364.0
364.0
162.0
364.0
27.0
27.0
98.0
27.0
Pack Materials-Page 2
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amplifier.ti.com
dataconverter.ti.com
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www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
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Interface
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interface.ti.com
logic.ti.com
www.ti.com/industrial
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www.ti.com/security
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Power Mgmt
Microcontrollers
RFID
power.ti.com
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microcontroller.ti.com
www.ti-rfid.com
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