TPS2064CDGNR-2 [TI]
高电平有效且具有反向阻断功能的双通道、1.5A 负载、4.5-5.5V、70mΩ USB 电源开关 | DGN | 8 | -40 to 125;
| 型号： | TPS2064CDGNR-2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高电平有效且具有反向阻断功能的双通道、1.5A 负载、4.5-5.5V、70mΩ USB 电源开关 | DGN | 8 | -40 to 125 开关 电源开关 光电二极管 输出元件 |
| 文件： | 总44页 (文件大小：3719K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
www.ti.com.cn
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
双通道、限流、配电开关
查询样品: TPS2052C, TPS2062C, TPS2062C-2, TPS2066C, TPS2066C-2, TPS2060C, TPS2064C, TPS2064C-2, TPS2002C, TPS2003C
1
特性
2
•
双电源开关系列
•
•
•
•
反向电流阻断
•
•
•
•
0.5A，1A，1.5A，2A 的额定电流
准确度为 ±20% 的电流限值容限
快速过流响应 - 2µs（典型值）
内置软启动
与现有的TI 开关系列产品引脚到引脚相对应
环境温度范围：-40°C 至 85°C
70mΩ（典型值）高侧 N 通道金属氧化物半导体场
效应晶体管 (MOSFET)
应用范围
•
•
•
•
USB 端口/集线器、笔记本、台式机
•
•
•
工作电压范围：4.5V 至 5.5V
去尖峰脉冲故障报告 (FLTx)
高清数字电视
机顶盒
所选的具有 (TPS20xxC) 和不具有 (TPS20xxC-2)
输出放电的部件
短路保护功能
说明
TPS20xxC 和 TPS20xxC-2 双配电开关系列产品用于诸如 USB 等有可能遇到高电容负载和短路的应用。 这一系列
产品为电流介于 0.5A 和 2A 之间的应用提供具有固定电流限值阀值的多种器件。
当输出负载超过电流限值阀值时，TPS20xxC 和 TPS20xxC-2 通过运行在恒定电流模式下来将输出电流限制在安全
的水平上。 这就在所有条件下提供了一个可预计的故障电流。 当输出被短接时，快速过载响应时间减轻了主 5V
电源提供稳压电源的负担。 为了大大减少打开和关闭期间的电流冲击，电源开关的上升和下降次数受到控制。
DRC
(Top View)
DGN
(Top View)
D
(Top View)
DRB
(Top View)
10
9
1
2
3
4
5
FLT1
OUT1
OUT 2
NC
8
7
6
5
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
GND
1
2
3
4
FLT1
OUT1
OUT2
FLT2
FLT1
OUT1
OUT2
FLT2
FLT1
OUT1
OUT2
FLT2
GND
IN
GND
IN
GND
IN
IN
IN
PAD
PAD
PAD
8
EN1 or EN1
EN2 or EN2
EN1 or EN1
EN2 or EN2
EN1 or EN1
EN2 or EN2
7
EN1 or EN1
6
FLT2
EN2 or EN2
V
0.1 mF
IN
IN
V
OUT 1
OUT 2
OUT1
R
R
V
OUT2
FLT1
10 kW
FLT2
10 kW
150 mF x 2
FLT1
FLT2
Fault Signals
GND
Pad
EN1 or EN1
EN2 or EN2
Control Signals
Figure 1. TYPICAL APPLICATION
Table 1. Devices
STATUS
RATED CURRENT
DEVICES
MSOP-8 (PowerPad™)
Active
SON -10
SOIC-8
SON-8
—
0.5 A
1 A
TPS2052C
TPS2062C and 66C
TPS2062C-2 and 66C-2
TPS2060C and 64C
TPS2064C-2
—
—
Active and Active
— and Active
Active and Active
Active
—
Active and Active
—
1 A
—
—
—
—
—
Active and —
1.5 A
1.5 A
2 A
—
—
—
—
—
TPS2002C and 03C
—
Active and Active
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
English Data Sheet: SLVSAX6
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE INFORMATION(1)(2)
PACKAGE DEVICES and MARKING(3)
MAXIMUM
OPERATING
CURRENT
OUTPUT
BASE PART
NUMBER
ENABLE
SOIC-8
(D)
MSOP-8 (DGN)
PowerPAD™
SON-10
(DRC)
SON-8
(DRB)
DISCHARGE
0.5
1
High
Low
Low
High
High
Low
High
High
Low
High
Y
Y
N
Y
N
Y
Y
N
Y
Y
TPS2052C
TPS2062C
TPS2062C-2
TPS2066C
TPS2066C-2
TPS2060C
TPS2064C
TPS2064C-2
TPS2002C
TPS2003C
–
PYNI
VRBQ
–
–
–
2062C
–
–
1
–
–
PYVI
1
2066C
VRDQ
PYUI
VRAQ
VRCQ
PYTI
–
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
1.5
1.5
1.5
2
–
–
–
VREQ
VRFQ
2
–
(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package code for MSOP-8 is “DGN” and for SON is “DRC”.
(3) “–” indicates the device is not available in this package.
ABSOLUTE MAXIMUM RATINGS(1)(2)
VALUE
UNIT
MIN
–0.3
–6
MAX
Voltage range on IN, OUTx, ENx or ENx, FLTx(3)
Voltage range from IN to OUT
6
6
V
V
Maximum junction temperature, TJ
Human Body Model
Internally Limited
°C
kV
V
2
ESD
Charged Device Model
500
IEC 61000-4-2, Contact / Air(4)
8 / 15
kV
(1) Absolute maximum ratings apply over recommended junction temperature range.
(2) All voltages are with respect to GND unless otherwise noted.
(3) See INPUT AND OUTPUT CAPACITANCE section.
(4) VOUT was surged on a PCB with input and output bypassing per Figure 1 (except input capacitor was 22 µF) with no device failure.
THERMAL INFORMATION
D
8 PINS
129.9
83.5
70.4
36.6
66.9
n/a
DGN
8 PINS
57.2
110.5
60.7
7.8
DRC
10 PINS
45.4
58
DRB
8-PINS
50.8
60.3
26.3
2.1
THERMAL METRIC(1)(2)
UNITS
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
21.1
1.9
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
24
21.3
9.1
26.5
9.8
θJCbot
14.3
(1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。
(2) 有关该器件的基于印刷电路板 (PCB) 覆铜区的热评估信息， 请参阅TI PCB 热应力 计算。
2
Copyright © 2011–2013, Texas Instruments Incorporated
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
www.ti.com.cn
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX
5.5
5.5
0.5
1
UNIT
VIN
Input voltage, IN
4.5
0
V
VEnable Input voltage, ENx or ENx
TPS2052C
TPS2062C, 62C-2, 66C, and 66C-2
TPS2060C, 64Cand 64C-2
TPS2002C and 03C
IOUTx
Continuous ouput current, OUTx
A
1.5
2
TJ
Operating junction temperature
Sink current into FLTx
–40
0
125
5
°C
IFLTx
mA
ELECTRICAL CHARACTERISTICS(1)
TJ = TA = 25°C，VIN = 5 V, VENx = VIN or VENx = 0V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SWITCH
TPS2052C (0.5 A)
DGN
DGN
DGN
DGN
D
70
70
70
70
90
90
73
73
70
70
84
95
TPS2052C (0.5 A)
–40°C ≤ (TJ, TA ) ≤ 85°C
TPS2062C, 66C, and 66C-2 (1 A)
84
TPS2062C, 66C, and 66C-2 (1 A),
–40°C ≤ (TJ, TA ) ≤ 85°C
95
TPS2062C and 66C (1 A)
108
122
87
TPS2062C and 66C (1 A),
–40°C ≤ (TJ, TA ) ≤ 85°C
D
rDS(on)
On-resistance
mΩ
TPS2062C-2 (1 A)
DRB
DRB
TPS2062C-2 (1 A)
–40°C ≤ (TJ, TA ) ≤ 85°C
101
84
TPS2060C, 64C, and 64C-2 (1.5 A)
TPS2060C, 64C, and 64C-2 (1.5 A), –40°C ≤ (TJ,
TA ) ≤ 85°C
95
TPS2002C and 03C (2 A)
70
70
84
95
TPS2002C and 03C (2 A), –40°C ≤ (TJ, TA ) ≤ 85°C
CURRENT LIMIT
TPS2052C (0.5 A)
0.75
1.28
1.83
2.55
1
1.61
2.29
3.15
1.25
1.94
2.75
3.77
TPS2062C, 62C-2, 66C, and 66C-2 (1 A)
TPS2060C, 64C, and 64C-2 (1.5 A)
TPS2002C and 03C (2 A)
IOS
Current limit, See Figure 7
Short-circuit response time
A
VIN = 5 V (see Figure 6),
One-half full load → R(SHORT) = 50 mΩ, Measure from
application to when current falls below 120% of final
value
tIOS
2
µs
SUPPLY CURRENT
ISD
Supply current, device disabled
I(OUTx) = 0 mA
I(OUTx) = 0 mA
I(OUTx) = 0 mA
0.01
60
1
75
IS1E
IS2E
Supply current, single switch enabled
Supply current, both switches enabled
100
120
µA
VOUT = 0 V, VIN = 5.5 V, disabled,
TPS20xxC-2
Leakage current
0.05
0.15
1
1
measured IVIN
ILKG
Reverse leakage current
VOUT = 5.5 V, VIN = 0 V, measured IOUTx
OUTPUT DISCHARGE
RPD
Output pull-down resistance(2)
VIN = V(OUTx) = 5 V, disabled
TPS20xxC
400
470
600
Ω
(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
(2) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
Copyright © 2011–2013, Texas Instruments Incorporated
3
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS
–40°C ≤ (TJ = TA) ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A, typical values are at 5 V and 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
POWER SWITCH
TPS2052C (0.5 A)
DGN
DGN
D
70
70
90
73
70
70
112
112
135
115
112
112
TPS2062C, 66C, and 66C-2 (1 A)
TPS2062C and 66C (1 A)
TPS2062C-2 (1 A)
rDS(on)
On-resistance
mΩ
DRB
DGN
DRC
TPS2060C, 64C, and 64C-2 (1.5 A)
TPS2002C and 03C (2 A)
ENABLE INPUT (ENx or ENx)
VIH
VIL
ENx (ENx), High-level input voltage
4.5 V ≤ VIN ≤ 5.5 V
2
ENx (ENx), Low-level input Voltage
Hysteresis
0.8
1
V
VIN = 5 V
0.14
0
Leakage current
VENx = 5.5 V or 0 V, VENx = 0 V or 5.5 V
-1
µA
ms
VIN = 5 V, CL = 1 µF, RL = 100 Ω, ENx ↑ or
ENx ↓, See Figure 4, Figure 5, and Figure 2
(2)
ton
Turn-on time
1 A, 1.5 A, 2 A Rated
1.4
1.9
2.4
VIN = 5 V, CL = 1 µF, RL = 100 Ω, ENx ↑ or
EN ↓, See Figure 4, Figure 5, and Figure 2
(2)
toff
Turn-off time
ms
1 A, 1.5 A, 2 A Rated
1.95
0.58
0.33
2.60
0.82
0.47
3.25
1.15
0.66
CL = 1 µF, RL = 100 Ω, see Figure 3
1 A, 1.5 A, 2 A Rated
(2)
tr
tf
Rise time, output
ms
ms
CL = 1 µF, RL = 100 Ω, see Figure 3
1 A, 1.5 A, 2 A Rated
(2)
Fall time, output
CURRENT LIMIT
TPS2052C (0.5A)
0.7
1.12
1.72
2.35
1
1.61
2.29
3.15
1.3
2.10
2.86
3.95
TPS2062C, 62C-2, 66C, and 66C-2 (1 A)
TPS2060C, 64C, and 64C-2 (1.5 A)
TPS2002C and 03C (2 A)
IOS
Current-limit, See Figure 7
A
VIN = 5 V (see Figure 6), One-half full load → R(SHORT)
50 mΩ, measure from application to when current falls
below 120% of final value
=
tIOS
Short-circuit response time
2
µs
SUPPLY CURRENT
ISD
Supply current, switch disabled
Standard conditions, I(OUTx) = 0 mA
Standard conditions, I(OUTx) = 0 mA
Standard conditions, I(OUTx) = 0 mA
0.01
10
90
IS1E
IS2E
Supply current, single switch enabled
Supply current, both switches enabled
150
µA
VOUT = 0 V, VIN = 5.5 V, disabled,
TPS20xxC-2
Leakage current
0.05
0.20
measured IVIN
ILKG
Reverse leakage current
VOUT = 5.5 V, VIN = 0 V, measured I(OUTx)
UNDERVOLTAGE LOCKOUT
UVLO
Low-level input voltage, IN
VIN rising
3.4
4.0
V
V
Hysteresis, IN
0.14
FLTx
Output low voltage, FLTx
Off-state leakage
I(FLTx) = 1 mA
0.2
1
V
V(FLTx) = 5.5 V
µA
ms
(2)
FLTx deglitch
FLTx overcurrent assertion and deassertion
7
10
13
(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
(2) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
4
Copyright © 2011–2013, Texas Instruments Incorporated
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
www.ti.com.cn
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
ELECTRICAL CHARACTERISTICS (continued)
–40°C ≤ (TJ = TA) ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A, typical values are at 5 V and 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
OUTPUT DISCHARGE
VIN = 5 V, VOUT = 5 V, disabled
TPS20xxC
TPS20xxC
300
350
470
560
800
Output pull-down resistance(3)
THERMAL SHUTDOWN
Ω
VIN = 4 V, VOUT = 5 V, disabled
1200
In current limit
135
155
Junction thermal shutdown threshold
Hysteresis
°C
°C
Not in current limit
20
(3) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
OUTx
R
L
C
L
90%
t
t
r
f
V
OUT
10%
Figure 2. Output Rise / Fall Test Load
Figure 3. Power-On and Off Timing
SPACER
V
EN
50%
50%
50%
50%
V
t
EN
off
t
on
t
t
off
on
90%
90%
V
OUT
V
10%
OUT
10%
Figure 4. Enable Timing, Active High Enable
Figure 5. Enable Timing, Active Low Enable
SPACER
V
IN
Decreasing
Load
Slope = -r
Resistance
DS(on)
120% x I
I
OS
OUT
I
OS
0 V
0A
I
OUT
0 A
I
t
OS
IOS
Figure 6. Output Short Circuit Parameters
SPACER
Figure 7. Output Characteristic Showing Current
Limit
Copyright © 2011–2013, Texas Instruments Incorporated
5
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
www.ti.com.cn
FUNCTIONAL BLOCK DIAGRAM
CS
IN
OUT1
Current
Sense
Disable+UVLO
Charge
Pump
Current
Limit
EN1
or
Driver
EN1
FLT1
UVLO
OTSD
10-ms
Deglitch
Thermal
Sense
UVLO
CS
OUT2
Current
Sense
Disable+UVLO
Current
Limit
EN2
or
Driver
UVLO
EN2
FLT2
OTSD
Thermal
10-ms
Deglitch
GND
Sense
Figure 8. TPS20xxC FUNCTIONAL BLOCK DIAGRAM
CS
Current
Sense
IN
OUT1
Charge
Pump
Current
Limit
EN1
or
Driver
EN1
FLT1
UVLO
OTSD
10-ms
Deglitch
Thermal
Sense
UVLO
CS
OUT2
Current
Sense
Current
Limit
EN2
or
Driver
UVLO
EN2
FLT2
OTSD
Thermal
10-ms
Deglitch
GND
Sense
Figure 9. TPS20xxC-2 FUNCTIONAL BLOCK DIAGRAM
6
Copyright © 2011–2013, Texas Instruments Incorporated
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
www.ti.com.cn
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
DEVICE INFORMATION
PIN FUNCTIONS – MSOP-8 PACKAGES
TPS2052C
TPS2066C
TPS2066C-2
TPS2064C
TPS2064C-2
TPS2062C
TPS2060C
NAME
I/O
DESCRIPTION
GND
IN
1
2
1
2
Pwr
I
Ground connection
Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to
GND close to the IC
EN1
EN1
EN2
EN2
FLT2
3
-
-
3
-
I
I
Enable input channel 1, logic high turns on power switch
Enable input channel 1, logic low turns on power switch
Enable input channel 2, logic high turns on power switch
Enable input channel 2, logic low turns on power switch
4
-
I
4
5
I
5
O
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 2
OUT2
OUT1
FLT1
6
7
8
6
7
8
O
O
O
Power-switch output channel 2, connected to load
Power-switch output channel 1, connected to load
Active-low open-drain output, asserted during over-current, or overtemperature conditions on
channel 1
PowerPAD™
PAD
PAD
Pwr
Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect
PAD to GND plane as a heatsink.
PIN FUNCTIONS – SOIC-8 PACKAGES
NAME
GND
IN
TPS2066C
TPS2062C
I/O
Pwr
I
DESCRIPTION
1
2
1
2
Ground connection
Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to
GND close to the IC
EN1
EN1
EN2
EN2
FLT2
3
-
-
I
I
Enable input channel 1, logic high turns on power switch
Enable input channel 1, logic low turns on power switch
Enable input channel 2, logic high turns on power switch
Enable input channel 2, logic low turns on power switch
3
-
4
-
I
4
5
I
5
O
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 2
OUT2
OUT1
FLT1
6
7
8
6
7
8
O
O
O
Power-switch output channel 2, connected to load
Power-switch output channel 1, connected to load
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 1
PIN FUNCTIONS – SON-10 PACKAGES
NAME
GND
IN
TPS2003C
TPS2002C
I/O
Pwr
I
DESCRIPTION
1
1
Ground connection
2, 3
2, 3
Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to
GND close to the IC
EN1
EN1
EN2
EN2
FLT2
4
–
5
–
6
–
4
–
5
6
I
I
Enable input channel 1, logic high turns on power switch
Enable input channel 1, logic low turns on power switch
Enable input channel 2, logic high turns on power switch
Enable input channel 2, logic low turns on power switch
I
I
O
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 2
NC
7
8
7
8
No connect – leave floating.
OUT2
OUT1
FLT1
O
O
O
Power-switch output channel 2, connect to load
Power-switch output channel 1, connect to load
9
9
10
10
Active-low open-drain output, asserted during overcurrent, or overtemperature conditions on
channel 1
PowerPAD™
PAD
PAD
Pwr
Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect
PAD to GND plane as a heatsink.
Copyright © 2011–2013, Texas Instruments Incorporated
7
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
www.ti.com.cn
PIN FUNCTIONS – SON-8 PACKAGES
NAME
GND
IN
TPS2062C-2
I/O
Pwr
I
DESCRIPTION
1
2
Ground connection
Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from
IN to GND close to the IC
EN1
EN2
FLT2
3
4
5
I
Enable input channel 1, logic low turns on power switch
Enable input channel 2, logic low turns on power switch
I
O
Active-low open-drain output, asserted during over-current, or over-temperature conditions
on channel 2
OUT2
OUT1
FLT1
6
7
8
O
O
O
Power-switch output channel 2, connect to load
Power-switch output channel 1, connect to load
Active-low open-drain output, asserted during over-current, or over-temperature conditions
on channel 1
PowerPAD™
PAD
Pwr
Internally connected to GND; used to heat-sink the part to the circuit board traces.
Connect PAD to GND plane as a heatsink.
spacer
TYPICAL CHARACTERISTICS
IOUT1 IOUT2
0.1 F
VIN
IN
VOUT1
VOUT2
OUT1
OUT2
3.01 k
3.01 k
RLoad1
RLoad2
FLT1
FLT2
GND
Pad
CL1
CL2
Fault Signals
EN1 or EN1
EN2 or EN2
Control Signals
Figure 10. Test Circuit for System Operation in Typical Characteristics Section
8
6
8
VIN = 5 V,CLx = 1 µF,RLoadx = 5 Ω, TPS2062C
VIN = 5 V,CLx = 1 µF,RLoadx = 5 Ω, TPS2062C
6
4
4
ENx
OUTx
OUTx
2
2
ENx
0
0
−2
−2
−3m −2m −1m
0
1m
2m
3m
4m
5m
−3m −2m −1m
0
1m
2m
3m
4m
5m
Time (s)
Time (s)
Figure 11. TPS2062C Turn on Delay and
Figure 12. TPS2062C Turn off Delay and
Rise Time With 1-μF Load
Fall Time With 1-μF Load
8
Copyright © 2011–2013, Texas Instruments Incorporated
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
www.ti.com.cn
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
TYPICAL CHARACTERISTICS (continued)
8
6
8
VIN = 5 V,CLx = 150 µF,RLoadx = 5 Ω, TPS2062C
VIN = 5 V,CLx = 150 µF,RLoadx = 5 Ω, TPS2062C
6
4
4
ENx
OUTx
OUTx
2
2
ENx
0
0
−2
−2
−3m −2m −1m
0
1m
2m
3m
4m
5m
−3m −2m −1m
0
1m
2m
3m
4m
5m
Time (s)
Time (s)
Figure 13. TPS2062C Turn on Delay and
Figure 14. TPS2062C Turn off Delay and
Rise Time With 150-μF Load
Fall Time With 150-μF Load
8
6
6.0
5.0
4.0
3.0
2.0
1.0
0.0
7
5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIN = 5 V,CLx = 150 µF,RLoadx = 0 Ω, TPS2062C
VIN = 5 V,RLoadx = 5.0 Ω, TPS2062C
FLTx
3
4
FLTx
OUTx
ENx
1
2
ENx
−1
−3
−5
−7
−9
1000 µF
220 µF
0
OUTx
−2
−4
−6
OUTx Current
680 µF
150 µF
−1.0
50m
−0.5
10m
−10m
0
10m
20m
30m
40m
−2m
0
2m
4m
Time (s)
6m
8m
Time (s)
Figure 15. TPS2062C Enable Into Short
Figure 16. TPS2062C Inrush Current
With Different Load Capacitance
8
6
6.0
5.0
4.0
3.0
2.0
1.0
0.0
−1.0
8
6.0
5.0
4.0
3.0
2.0
1.0
0.0
−1.0
VIN = 5 V,CLx = 150 µF,RLoadx = 5 Ω, TPS2062C
VIN = 5 V,CLx = 150 µF,RLoadx = 5 Ω, TPS2062C
6
4
VIN
VIN
4
FLTx
2
2
OUTx
FLTx
0
0
OUTx
−2
−4
−6
−2
−4
−6
IOUTx
IOUTx
−8m
−4m
0
4m
8m
12m
−4m
0
4m
8m
12m
16m
Time (s)
Time (s)
Figure 17. TPS2062C Power Up – Enabled
Figure 18. TPS2062C Power Down – Enabled
Copyright © 2011–2013, Texas Instruments Incorporated
9
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
4.2
VIN = 5 V, CLx = 150 μF, RLoadx = 2.0 Ω, TPS2062C
8
6
3.6
3.0
2.4
1.8
1.2
0.6
0.0
−0.6
FLTx
ENx
4
2
OUTx
0
−2
−4
−6
−8
IOUTx
−4m −2m
0
2m
4m
6m
8m 10m 12m 14m
Time (s)
Figure 19. TPS2062C Enable With 2-Ω Load
Figure 20. TPS2062C Enable With 1-Ω Load
8
6
4.2
3.6
3.0
2.4
1.8
1.2
0.6
0.0
−0.6
8
6
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−0.5
VIN = 5 V, CLx = 150 μF, RLoadx = 0 Ω, TPS2062C
VIN = 5 V, CLx = 150 μF, RLoadx = 10 Ω, TPS2062C
FLTx
4
4
FLTx
OUTx
2
ENx
2
0
0
ENx
OUTx
−2
−4
−6
−8
−2
−4
−6
−8
IOUTx
IOUTx
−8m −4m
0
4m 8m 12m 16m 20m 24m 28m 32m
−2m
0
2m 4m 6m 8m 10m 12m 14m 16m 18m
Time (s)
Time (s)
Figure 21. TPS2062C Enable/Disable
into Output Short
Figure 22. TPS2062C Enable/Disable
into 10-Ω Load
8
6
7
8
6
12.0
10.0
8.0
VIN = 5 V,CLx = 150 µF,RLoadx = 3.3 Ω, TPS2064C
VIN = 5 V, CLx = 150 μF, RLoadx = 0 Ω, TPS2064C
6
FLTx
4
5
OUTx
ENx
4
2
4
ENx
2
6.0
0
3
OUTx
0
4.0
−2
−4
−6
−8
2
1
−2
−4
−6
2.0
IOUTx
IOUTx
0
0.0
−1
5m
−4m −3m −2m −1m
0
1m
2m
3m
4m
−2.0
Time (s)
−6m −4m −2m
0
2m 4m 6m 8m 10m 12m 14m
Time (s)
Figure 23. TPS2064C Enable into Short
Figure 24. TPS2064C Enable into 3.3 Ω and 150-μF Laod
10
Copyright © 2011–2013, Texas Instruments Incorporated
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
www.ti.com.cn
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
TYPICAL CHARACTERISTICS (continued)
7
42
36
30
24
18
12
6
8
12.0
10.0
8.0
VIN = 5 V, CLx = 0 μF, RLoadx = 50 mΩ, TPS2064C
VIN = 5 V, CLx = 150 μF, RLoadx = 0 Ω, TPS2003C
6
FLTx
IOUTx
5
3
4
OUTx
ENx
2
6.0
OUTx
0
4.0
−2
−4
−6
2.0
IOUTx
1
0.0
0
−1
−3μ
−6
−2.0
−2μ
−1μ
0
1μ
2μ
3μ
−6m −4m −2m
0
2m 4m 6m 8m 10m 12m 14m
Time (s)
Time (s)
Figure 25. TPS2064C Short Applied
Figure 26. TPS2003C Enable into Short
8
6
7
3.4
3.2
3
2.0 A rated
VIN = 5.5 V
VIN = 5 V, CLx = 150 μF, RLoadx = 2.5 Ω, TPS2003C
6
4
5
2.8
2.6
2.4
2.2
2
OUTx
ENx
2
4
1.5 A rated
1.0 A rated
0
3
−2
−4
−6
−8
2
1.8
1.6
1.4
1.2
1
IOUTx
0
−1
−3m −2m −1m
0
1m 2m 3m 4m 5m 6m 7m
−40
−20
0
20
40
60
80
100
120
Time (s)
Junction Temperature (°C)
Figure 27. TPS2003C Enable into 2.5 Ω and 150-μF Laod
Figure 28. Current Limit (IOS) vs Temperature
100
2.5
2
VIN = 5 V
VIN = 5 V
1.0 A rated
2 A rated
90
80
1.5
1
1.5 A rated
2.0 A rated
1 A rated
70
60
0.5
0
1.5 A rated
50
40
−40
−0.5
−20
0
20
Junction Temperature (°C)
Figure 29. Input - output Resistance (RDS(ON)) vs
Temperature
40
60
80
100
120
−40
−20
0
20
Junction Temperature (°C)
Figure 30. Supply Current (Device Disable) - ISD vs
Temperature
40
60
80
100
120
Copyright © 2011–2013, Texas Instruments Incorporated
11
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
130
120
110
100
90
VIN = 5 V
1.0 A rated(IS2E
)
2.0 A rated(IS2E
)
1.5 A rated(IS2E
)
2.0 A rated(IS1E
)
80
1.5 A rated(IS1E
)
70
60
1.0 A rated(IS1E
)
50
−40
−20
0
20
40
60
80
100
120
Junction Temperature (°C)
Figure 31. Supply Current (Enable) - ISE vs Temperature
12
Copyright © 2011–2013, Texas Instruments Incorporated
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
www.ti.com.cn
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
DETAILED DESCRIPTION
OVERVIEW
The TPS20xxC and TPS20xxC-2 dual are current-limited, power-distribution switches providing between 0.5 A
and 2 A of continuous load current in 5-V circuits. These parts use N-channel MOSFETs for low resistance,
maintaining output voltage load regulation. They are designed for applications where short circuits or heavy
capacitive loads are encountered. Device features include UVLO, ON/OFF control (Enable), reverse blocking
when disabled, output discharge when TPS20xxC disabled, overcurrent protection, overtemperature protection,
and deglitched fault reporting. They are pin for pin with existing TI Switch Portfolio.
UNDERVOLTAGE LOCKOUT (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch when the input voltage is below the UVLO
threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large current
surges. FLTx is high impedance when the TPS20xxC and TPS20xxC-2 dual are in UVLO.
ENABLE (ENx or ENx)
The logic input of ENx or ENx disables all of the internal circuitry while maintaining the power switch OFF. The
supply current of the device can be reduced to less than 1 µA when both switches are disabled. A logic low input
on ENx or a logic high input on ENx enables the driver, control circuits, and power switch of corresponding
channel.
The ENx or ENx input voltage is compatible with both TTL and CMOS logic levels. The FLTx is immediately
cleared and the output discharge circuit is enabled when the device is disabled.
DEGLITCHED FAULT REPORTING
FLTx is an open-drain output that asserts (active low) during an overcurrent or overtemperature condition on
each corresponding channel. The FLTx output remains asserted until the fault condition is removed or the
channel is disabled. The TPS20xxC and TPS20xxC-2 dual eliminates false FLTx reporting by using internal
delay circuitry after entering or leaving an overcurrent condition. The “deglitch” time is typically 10 ms. This
ensures that FLTx is not accidentally asserted under overcurrent conditions with a short time, such as starting
into a heavy capacitive load. Over temperature conditions are not deglitched. The FLTx pin is high impedance
when the device is disabled and in undervoltage lockout (UVLO). The fault circuits are independent so that
another channel continues to operate when one channel is in a fault condition.
OVERCURRENT PROTECTION
The TPS20xxC and TPS20xxC-2 dual responds to overloads by limiting each channel output current to the static
IOS levels shown in the Electrical Characteristics table. When an overload condition is present, the device
maintains a constant current (IOS) and reduces the output voltage accordingly, with the output voltage falling to
(IOS x RSHORT). Three possible overload conditions can occur. In the first condition, the output has been shorted
before the device is enabled or before voltage is applied to IN. The device senses over-current and immediately
switches into a constant-current output. In the second condition, a short or an overload occurs while the device is
enabled. At the instant a short -circuit occurs, high currents may flow for several microseconds (tIOS) before the
current-limit circuit reacts. The device operates in constant-current mode after the current-limit circuit has
responded. In the third condition, the load is increased gradually beyond the recommended operating current.
The current is permitted to rise until the current-limit threshold is reached. The devices are capable of delivering
current up to the current-limit threshold without damage. Once the threshold is reached, the device switches into
constant-current mode. For all of the above three conditions, the device may begin thermal cycling if the
overcurrent condition persists.
Copyright © 2011–2013, Texas Instruments Incorporated
13
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
www.ti.com.cn
OVERTEMPERATURE PROTECTION
The TPS20xxC and TPS20xxC-2 dual includes per channel overtemperature protection circuitry, which activates
at 135°C (min) junction temperature while in current limit. There is an overall thermal shutdown of 155°C (min)
junction temperature when the TPS20xxC and TPS20xxC-2 dual are not in current limit. The device remains off
until the junction temperature cools 20°C and then restarts. Thermal shutdown may occur during an overload due
to the relatively large power dissipation [(VIN – VOUT) × IOS] driving the junction temperature up. The power switch
cycles on and off until the fault is removed. This topology allows one channel to continue normal operation even
if the other channel is in an over-temperature condition.
SOFTSTART, REVERSE BLOCKING AND DISCHARGE OUTPUT
The power MOSFET driver incorporates circuitry that controls the rise and fall times of the output voltage to limit
large current and voltage surges on the input supply, and provides built-in soft-start functionality.
The TPS20xxC and TPS20xxC-2 dual power switch will block current from OUT to IN when turned off by the
UVLO or disabled.
The TPS20xxC dual includes an output discharge function on each channel. A 470Ω (typ.) discharge resistor will
dissipate stored charge and leakage current on OUTx when the device is in UVLO or disabled. However as this
circuit is biased from IN, the output discharge will not be active when IN voltage is close to 0 V.
The TPS20xxC-2 does not have this function. The output is be controlled by an external loadings when the
device is in ULVO or disabled.
14
Copyright © 2011–2013, Texas Instruments Incorporated
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
www.ti.com.cn
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
APPLICATION INFORMATION
INPUT AND OUTPUT CAPACITANCE
Input and output capacitance improves the performance of the device. For all applications, a 0.1 µF or greater
ceramic bypass capacitor between IN and GND is recommended as close to the device as possible for local
noise de-coupling. The actual capacitance should be optimized for the particular application. This precaution
reduces ringing on the input due to power-supply transients. Additional input capacitance may be needed on the
input to reduce the overshoot voltage from exceeding the absolute maximum voltage of the device during heavy
transients.
A 120 µF minimum output capacitance is required when implementing USB standard applications. Typically this
uses a 150 µF electrolytic capacitor. If the application does not require 120 µF of output capacitance, a minimum
of 10 µF ceramic capacitor on the output is recommended in order to reduce the transient negative voltage on
OUTx pin caused by load inductance during a short circuit. The transient negative voltage should be less than
1.5 V for 10 µs.
POWER DISSIPATION AND JUNCTION TEMPERATURE
It is good design practice to estimate power dissipation and maximum expected junction temperature of the
TPS20xxC and TPS20xxC-2 dual. The system designer can control choices of package, proximity to other power
dissipating devices, and printed circuit board (PCB) design based on these calculations. These have a direct
influence on maximum junction temperature. Other factors such as airflow and maximum ambient temperature
are often determined by system considerations.
Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and
maintain the junction temperature as low as practical.
The following procedure requires iteration because power loss is due to the two internal MOSFETs 2 × I2 ×
rDS(on), and rDS(on) is a function of the junction temperature. As an initial estimate, use the rDS(on) at 125°C from the
typical characteristics, and the preferred package thermal resistance for the preferred board construction from
the thermal parameters section.
TJ = TA + [(2 × IOUT2 × rDS(on) × θJA]
Where:
IOUT = rated OUT pin current (A)
rDS(on) = Power switch on-resistance at an assumed TJ (Ω)
TA = Maximum ambient temperature (°C)
TJ = Maximum junction temperature (°C)
θJA = Thermal resistance (°C/W)
If the calculated TJ is substantially different from the original assumption, look up a new value of rDS(on) and
recalculate.
If the resulting TJ is not less than 125°C, try a PCB construction and/or package with lower θJA.
Copyright © 2011–2013, Texas Instruments Incorporated
15
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
www.ti.com.cn
REVISION HISTORY
Changes from Original (October 2011) to Revision A
Page
•
•
•
Changed devices TPS2062C and TPS2066C MSOP-8 package From: Preview to Active ................................................. 1
Changed the IOS current limit values for TPS2062C and 66C (1 A). .................................................................................... 3
Changed the IOS current limit values for TPS2062C/66C (1 A). ........................................................................................... 4
Changes from Revision A (March 2012) to Revision B
Page
•
Changed device TPS2060C MSOP-8 package From: Preview To: Active .......................................................................... 1
Changes from Revision B (March 2012) to Revision C
Page
•
•
•
Changed devices TPS2062C and TPS2066C SOIC-8 package From: Preview To: Active ................................................ 1
Changed the TPS2062C and 66C rDS(on) D package TYP value From: 84 to 90 mΩ and added the MAX value ................ 3
Changed the TPS2062C and 66C rDS(on) D package TYP value From: 84 to 90 mΩ .......................................................... 4
Changes from Revision C (June 2012) to Revision D
Page
•
Changed the Device Information table, Package Devices and Marking columns ................................................................ 2
Changes from Revision D (July 2012) to Revision E
Page
•
•
•
•
Changed devices TPS2002C and TPS2003C SON-10 package From: Preview To: Active ............................................... 1
Changed the IOS current limit values for TPS2002C and 03C (2 A). .................................................................................... 3
Corrected Note 2 references in the ELECTRICAL CHARACTERISTICS table ................................................................... 4
Changed the IOS current limit values for TPS2002C and 03C (2 A). .................................................................................... 4
Changes from Revision E (August 2012) to Revision F
Page
•
•
•
•
•
•
将特性从 1A，1.5A，2A 的额定电流改为：0.5A，1A，1.5A，2A 的额定电流 .................................................................... 1
将特性从：禁用时输出放电改为：所选的具有 (TPS20xxC) 和不具有 (TPS20xxC-2)输出放电的部件 ................................. 1
Added DRB pin option .......................................................................................................................................................... 1
Added TPS2052C, TPS2062C-2, TPS2064C-2, and TPS2066C-2 devices to Table 1 ....................................................... 1
Added TPS2052C, TPS2062C-2, TPS2064C-2, and TPS2066C-2 devices to .................................................................... 2
Added TPS2052C, TPS2062C-2, TPS2064C-2, and TPS2066C-2 devices to RECOMMENDED OPERATING
CONDITIONS table ............................................................................................................................................................... 3
•
•
•
•
•
•
•
•
Added TPS2052C and TPS2066C-2 devices to rDS(on) ......................................................................................................... 3
Added the TPS2052C and TPS2064C-2 devices to IOS ....................................................................................................... 3
Added Leakage Current ........................................................................................................................................................ 3
Added TPS2052C and TPS2066C-2 devices to rDS(on) ......................................................................................................... 4
Added the TPS2052C and TPS2064C-2 devices to IOS ....................................................................................................... 4
Added Leakage Current ........................................................................................................................................................ 4
Added text to the SOFTSTART, REVERSE BLOCKING AND DISCHARGE OUTPUT section ........................................ 14
Added last paragraph in the DISCHARGE OUTPUT section ............................................................................................. 14
16
Copyright © 2011–2013, Texas Instruments Incorporated
TPS2052C, TPS2062C, TPS2062C-2
TPS2066C, TPS2066C-2, TPS2060C, TPS2064C
TPS2064C-2, TPS2002C, TPS2003C
www.ti.com.cn
ZHCS265G –OCTOBER 2011–REVISED JANUARY 2013
Changes from Revision F (November 2012) to Revision G
Page
•
•
Changed device TPS2062C-2 SON-8 packages From: Preview To: Active. ....................................................................... 1
Changed devices TPS2066C-2, and TPS2064C-2 MSOP-8 package From: Preview To: Active ....................................... 1
Copyright © 2011–2013, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS2002CDRCR
TPS2002CDRCT
TPS2003CDRCR
TPS2003CDRCT
TPS2052CDGN
TPS2052CDGNR
TPS2060CDGN
TPS2060CDGNR
TPS2062CD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
DRC
DRC
DRC
DRC
DGN
DGN
DGN
DGN
D
10
10
10
10
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
VFEQ
VFEQ
VRFQ
VRFQ
PYNI
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
VSON
VSON
250
80
RoHS & Green
RoHS & Green
NIPDAU
HVSSOP
HVSSOP
HVSSOP
HVSSOP
SOIC
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAU
8
2500 RoHS & Green
80 RoHS & Green
2500 RoHS & Green
PYNI
8
VRAQ
VRAQ
2062C
VRBQ
VRBQ
2062C
PYVI
8
8
75
80
RoHS & Green
RoHS & Green
TPS2062CDGN
TPS2062CDGNR
TPS2062CDR
HVSSOP
HVSSOP
SOIC
DGN
DGN
D
8
NIPDAUAG
NIPDAUAG
NIPDAU
8
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
8
TPS2062CDRBR-2
TPS2062CDRBT-2
TPS2064CDGN
TPS2064CDGN-2
TPS2064CDGNR
TPS2064CDGNR-2
TPS2065CDBVR-2
TPS2065CDBVT-2
SON
DRB
DRB
DGN
DGN
DGN
DGN
DBV
DBV
8
NIPDAU
SON
8
250
80
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
PYVI
HVSSOP
HVSSOP
HVSSOP
HVSSOP
SOT-23
SOT-23
8
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAU
VRCQ
PYTI
8
80
8
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
VRCQ
PYTI
8
5
PYQI
PYQI
5
250
RoHS & Green
NIPDAU
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS2065CDGN-2
TPS2065CDGNR-2
TPS2066CD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HVSSOP
HVSSOP
SOIC
DGN
DGN
D
8
8
8
8
8
8
8
8
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 85
PYRI
PYRI
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
2500 RoHS & Green
NIPDAUAG
NIPDAU
75
80
80
RoHS & Green
RoHS & Green
RoHS & Green
2066C
VRDQ
PYUI
TPS2066CDGN
TPS2066CDGN-2
TPS2066CDGNR
TPS2066CDGNR-2
TPS2066CDR
HVSSOP
HVSSOP
HVSSOP
HVSSOP
SOIC
DGN
DGN
DGN
DGN
D
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAU
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
VRDQ
PYUI
2066C
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2002CDRCR
TPS2002CDRCT
TPS2003CDRCR
TPS2003CDRCT
TPS2052CDGNR
TPS2060CDGNR
TPS2062CDGNR
TPS2062CDR
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
10
10
10
10
8
3000
250
330.0
180.0
330.0
180.0
330.0
330.0
330.0
330.0
330.0
330.0
180.0
330.0
330.0
180.0
178.0
178.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
8.4
3.3
3.3
3.3
3.3
5.3
5.3
5.3
6.4
6.4
3.3
3.3
5.3
5.3
3.2
3.23
3.23
3.3
3.3
3.3
3.3
3.4
3.4
3.4
5.2
5.2
3.3
3.3
3.4
3.4
3.2
3.17
3.17
1.1
1.1
1.1
1.1
1.4
1.4
1.4
2.1
2.1
1.1
1.1
1.4
1.4
1.4
1.37
1.37
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
4.0
4.0
4.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
8.0
Q2
Q2
Q2
Q2
Q1
Q1
Q1
Q1
Q1
Q2
Q2
Q1
Q1
Q3
Q3
Q3
3000
250
HVSSOP DGN
HVSSOP DGN
HVSSOP DGN
2500
2500
2500
2500
2500
3000
250
8
8
SOIC
SOIC
SON
SON
D
8
TPS2062CDR
D
8
TPS2062CDRBR-2
TPS2062CDRBT-2
TPS2064CDGNR
TPS2064CDGNR-2
TPS2065CDBVR-2
TPS2065CDBVR-2
TPS2065CDBVT-2
DRB
DRB
8
8
HVSSOP DGN
HVSSOP DGN
8
2500
2500
3000
3000
250
8
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
5
5
9.0
8.0
5
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2065CDBVT-2
TPS2065CDGNR-2
TPS2066CDGNR
TPS2066CDGNR-2
TPS2066CDR
SOT-23
DBV
5
8
8
8
8
250
180.0
330.0
330.0
330.0
330.0
8.4
3.2
5.3
5.3
5.3
6.4
3.2
3.4
3.4
3.4
5.2
1.4
1.4
1.4
1.4
2.1
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q1
Q1
Q1
Q1
HVSSOP DGN
HVSSOP DGN
HVSSOP DGN
2500
2500
2500
2500
12.4
12.4
12.4
12.4
12.0
12.0
12.0
12.0
SOIC
D
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2002CDRCR
TPS2002CDRCT
TPS2003CDRCR
TPS2003CDRCT
TPS2052CDGNR
TPS2060CDGNR
TPS2062CDGNR
TPS2062CDR
VSON
VSON
DRC
DRC
DRC
DRC
DGN
DGN
DGN
D
10
10
10
10
8
3000
250
346.0
210.0
346.0
210.0
366.0
364.0
364.0
356.0
340.5
335.0
182.0
364.0
366.0
210.0
180.0
180.0
210.0
366.0
346.0
185.0
346.0
185.0
364.0
364.0
364.0
356.0
336.1
335.0
182.0
364.0
364.0
185.0
180.0
180.0
185.0
364.0
33.0
35.0
33.0
35.0
50.0
27.0
27.0
35.0
25.0
25.0
20.0
27.0
50.0
35.0
18.0
18.0
35.0
50.0
VSON
3000
250
VSON
HVSSOP
HVSSOP
HVSSOP
SOIC
2500
2500
2500
2500
2500
3000
250
8
8
8
TPS2062CDR
SOIC
D
8
TPS2062CDRBR-2
TPS2062CDRBT-2
TPS2064CDGNR
TPS2064CDGNR-2
TPS2065CDBVR-2
TPS2065CDBVR-2
TPS2065CDBVT-2
TPS2065CDBVT-2
TPS2065CDGNR-2
SON
DRB
DRB
DGN
DGN
DBV
DBV
DBV
DBV
DGN
8
SON
8
HVSSOP
HVSSOP
SOT-23
SOT-23
SOT-23
SOT-23
HVSSOP
8
2500
2500
3000
3000
250
8
5
5
5
5
250
8
2500
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2066CDGNR
TPS2066CDGNR-2
TPS2066CDR
HVSSOP
HVSSOP
SOIC
DGN
DGN
D
8
8
8
2500
2500
2500
364.0
366.0
340.5
364.0
364.0
336.1
27.0
50.0
25.0
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPS2052CDGN
TPS2060CDGN
TPS2062CD
DGN
DGN
D
HVSSOP
HVSSOP
SOIC
8
8
8
8
8
8
8
8
8
8
80
80
75
80
80
80
80
75
80
80
330
330
507
330
330
330
330
507
330
330
6.55
6.55
8
500
500
3940
500
500
500
500
3940
500
500
2.88
2.88
4.32
2.88
2.88
2.88
2.88
4.32
2.88
2.88
TPS2062CDGN
TPS2064CDGN
TPS2064CDGN-2
TPS2065CDGN-2
TPS2066CD
DGN
DGN
DGN
DGN
D
HVSSOP
HVSSOP
HVSSOP
HVSSOP
SOIC
6.55
6.55
6.55
6.55
8
TPS2066CDGN
TPS2066CDGN-2
DGN
DGN
HVSSOP
HVSSOP
6.55
6.55
Pack Materials-Page 5
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
DIM A
OPT 1
(0.1)
OPT 2
(0.2)
1.5 0.1
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
0.37
0.25
8X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
(0.65)
0.05
0.5
0.3
8X
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31)
1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
(
0.2) VIA
(0.23)
TYP
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
4X
(0.725)
8
1
8X (0.31)
(2.674)
(1.55)
SYMM
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.846
1.646
4225480/B 12/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
(1.89)
9
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225480/B 12/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(1.89)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
0.125
0.15
0.175
1.33 X 1.60
4225480/B 12/2022
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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