TPS2206IDBR_技术文档

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

DB OR DF PACKAGE

(TOP VIEW)

D

Fully Integrated V

and V Switching for

CC pp

Dual-Slot PC Card Interface

2

P C 3-Lead Serial Interface Compatible With

CardBus Controllers

1

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

5V

DATA

5V

NC

12V

BVPP

BVCC

NC

OC

3.3V

2

3

3.3 V Low-Voltage Mode

4

CLOCK

LATCH

RESET

12V

AVPP

AVCC

GND

Meets PC Card Standards

5

RESET for System Initialization of PC Cards

6

12-V Supply Can Be Disabled Except During

12-V Flash Programming

7

8

9

Short Circuit and Thermal Protection

10

11

12

13

14

15

30-Pin SSOP (DB) and 32-Pin TSSOP (DAP)

Compatible With 3.3-V, 5-V and 12-V PC Cards

NC

RESET

3.3V

Low r

3.3-V V

(140-mΩ 5-V V

Switch; 110-mΩ

DS(on)

CC

Switch)

D

Break-Before-Make Switching

DAP PACKAGE

(TOP VIEW)

description

The TPS2206 PC Card power-interface switch

provides an integrated power-management solution

for two PC Cards. All of the discrete power

MOSFETs, a logic section, current limiting, and

thermal protection for PC Card control are

combined on a single integrated circuit (IC), using

the Texas Instruments LinBiCMOS process.

The circuit allows the distribution of 3.3-V, 5-V,

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

5V

NC

5V

NC

12V

BVPP

BVCC

OC

NC

3.3V

2

3

4

DATA

CLOCK

LATCH

RESET

12V

AVPP

AVCC

GND

5

6

7

8

2

and/or 12-V card power by means of the P C

9

(PCMCIA Peripheral-Control) Texas Instruments

nonproprietary serial interface. The current-limiting

feature eliminates the need for fuses, which

reduces component count and improves reliability.

10

11

12

13

14

15

16

RESET

NC

The TPS2206 is backward compatible with the

TPS2202 and TPS2202A, except that there is no

3.3V

V

connection. Bias current is derived from

DD

either the 3.3-V input pin or the 5-V input pin. The

TPS2206 also eliminates the APWR_GOOD and

BPWR_GOOD pins of the TPS2202 and

TPS2202A.

NC − No internal connection

The TPS2206 features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V. This

facilitates low-power system designs such as sleep mode and pager mode where only 3.3 V is available.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

LinBiCMOS and P C are trademarks of Texas Instruments.

PC Card and CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association).

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Copyright  2001, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

description (continued)

The TPS2206 incorporates a reset function, selectable by one of two inputs, to help alleviate system errors. The

reset function enables PC Card initialization concurrent with host platform initialization, allowing a system reset.

Reset is accomplished by grounding the V

discharges residual card voltage.

and V (flash-memory programming voltage) outputs, which

CC

pp

End equipment for the TPS2206 includes notebook computers, desktop computers, personal digital assistants

(PDAs), digital cameras and bar-code scanners.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

CHIP FORM (Y)

PLASTIC SMALL OUTLINE (DB)

PLASTIC SMALL OUTLINE (DF)

TSSOP (DAP)

−40°C to 85°C

TPS2206IDB

TPS2206IDFR

TPS2206IDAPR

TPS2206Y

The DB package is available taped and reeled (add an R suffix to the device type, e.g., TPS2206IDBR). The DF and DAP packages are only

available taped and reeled, indicated by the R suffix.

typical PC card power-distribution application

Power Supply

TPS2206

12V

5V

12 V

5 V

AVPP

V

pp1

pp2

CC

PC

Card A

3.3V

3.3 V

AVCC

CC

RESET

Supervisor

3

BVPP

V

pp1

pp2

CC

Serial Interface

OC

PCMCIA

Controller

PC

Card B

BVCC

CC

2

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

TPS2206Y chip information

This chip, when properly assembled, displays characteristics similar to those of the TPS2206. Thermal

compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. The chips may be

mounted with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

1

5V

TPS2206Y

4

5

3

2

5V

23

22

21

20

19

18

17

16

15

14

13

3

12V

DATA

1

4

2

23

BVPP

BVCC

CLOCK

LATCH

5

6

RESET

12V

6

7

8

7

8

OC

AVPP

AVCC

22

21

9

3.3V

RESET

10

11

12

AVCC

GND

144

20

9

CHIP THICKNESS: 15 TYPICAL

19

10

BONDING PADS: 4 × 4 MINIMUM

11

18

17

T

max = 150°C

J

15

TOLERANCES ARE 10%.

13

12

14

16

ALL DIMENSIONS ARE IN MILS.

142

3

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

Terminal Functions

TERMINAL

NAME

NO.

I/O

DESCRIPTION

DB, DF

DAP

3.3V

15, 16, 17

16, 17, 18

I

3.3-V V

input for card power

input for card power and/or chip power

CC

5V

1, 2, 30

1, 2, 32

5-V V

CC

12V

7, 24

8, 25

I

12-V V input for card power

pp

AVCC

AVPP

BVCC

BVPP

CLOCK

DATA

GND

LATCH

NC

9, 10, 11

10, 11, 12

O

I

Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance to card

Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance to card

Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance

Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance

Logic-level clock for serial data word

8

9

20, 21, 22

21, 22, 23

23

4

24

5

3

4

I

Logic-level serial data word

12

5

13

6

Ground

I

Logic-level latch for serial data word

13, 19, 25,

26, 27,

28, 29

3, 19, 26,

27, 28, 29,

30, 31

No internal connection

OC

18

6

20

7

O

I

Logic-level overcurrent. OC reports output that goes low when an overcurrent condition exists

Logic-level RESET input active high. Do not connect if terminal 14 is used.

Logic-level RESET input active low. Do not connect if terminal 6 is used.

RESET

14

I

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Input voltage range for card power: V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 14 V

I(5V)

V

I(3.3V)

I(12V)

Logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Output current (each card): I

I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited

O(xVCC)

O(xVPP)

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C

J

Operating free-air temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

A

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

‡

T

A

≤ 25°C

DERATING FACTOR

T

= 70°C

T = 85°C

A

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

A

DB

DF

1024 mW

8.2 mW/°C

9.26 mW/°C

13 mW/°C

655 mW

741 mW

1040 mW

3869 mW

532 mW

602 mW

845 mW

3143 mW

1158 mW

No backplane

1625 mW

DAP

§

Backplane

6044 mW

48.36 mW/°C

‡

§

These devices are mounted on an FR4 board with no special thermal considerations.

2-oz backplane with 2-oz traces; 5.2-mm × 11-mm thermal pad with 6-mil solder; 0.18-mm diameter vias in a 3×6 array.

4

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

recommended operating conditions

MIN

0

MAX

5.25

13.5

1

UNIT

V

I(5V)

0

V

Input voltage range, V

I(3.3V)

I(12V)

I

0

V

I

at 25°C

A

O(xVCC)

Output current

150

2.5

mA

MHz

°C

O(xVPP)

Clock frequency

0

Operating virtual junction temperature, T

−40

125

J

electrical characteristics, T = 25°C, V

= 5 V (unless otherwise noted)

A

I(5V)

dc characteristics

TPS2206

TYP

103

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

140

110

180

6

5 V to xVCC

3.3 V to xVCC

V

= 5 V,

= 0,

V

= 3.3 V

69

mΩ

I(5V)

I(3.3 V)

96

I(5V)

I(3.3V)

†

Switch resistances

5 V to xVPP

3.3 V to xVPP

12 V to xVPP

6

Ω

1

V

Clamp low voltage

I

at 10 mA

= 25°C

0.8

10

V

O(xVPP)

pp

O(xVCC)

CC

T

1

A

I

high-impedance state

pp

T

= 85°C

50

A

I

Leakage current

µA

lkg

T

= 25°C

10

A

CC

T

= 85°C

50

A

V

= V

= 5 V,

= 12 V

O(AVCC)

O(AVPP)

O(BVCC)

O(BVPP)

V

= 5 V

= 0,

117

131

150

1

I(5V)

µA

V

= V

= 3.3 V,

= 0

I(5V)

I(3.3V)

O(AVCC)

O(AVPP)

O(BVCC)

O(BVPP)

I

Input current

I

= 3.3 V

V

= V

O(AVCC)

= Hi-Z

= V

O(AVPP)

O(BVCC)

Shutdown mode

= V

O(BVPP)

I

1

2.2

A

Short-circuit

output-current limit

O(xVCC)

T = 85°C,

J

Output powered up into a short to GND

OS

I

120

400

mA

O(xVPP)

†

Pulse-testing techniques are used to maintain junction temperature close to ambient temperature; thermal effects must be taken into account

separately.

logic section

TPS2206

MIN

PARAMETER

TEST CONDITIONS

UNIT

MAX

Logic input current

Logic input high level

Logic input low level

1

µA

V

2

0.8

0.4

V

= 5 V,

= 0,

I

= 1mA

= 1mA,

V

−0.4

I(5V)

O

Logic output high level

Logic output low level

V

I(5V)

I(3.3V)

= 1mA

O

V

−0.4

I(3.3V)

= 3.3 V

I

O

5

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

†‡

switching characteristics

TPS2206

TYP

1.2

5

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

V

O(xVCC)

O(xVPP)

O(xVCC)

O(xVPP)

t

Output rise time

Output fall time

r

ms

10

f

14

t

4.4

18

ms

on

off

on

off

on

off

LATCH↑ to V

O(xVPP)

6.5

20

(3.3 V), V

(5 V)

= 5 V

O(xVCC)

I(5V)

t

pd

Propagation delay (see Figure 1)

5.7

25

t

on

off

6.6

21

ms

(3.3 V), V

= 0

I(5V)

t

†

‡

Refer to Parameter Measurement Information

Switching Characteristics are with C = 150 µF.

L

electrical characteristics, T = 25°C, V

= 5 V (unless otherwise noted)

A

I(5V)

dc characteristics

TPS2206Y

TYP

103

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

5 V to xVCC

3.3 V to xVCC

V

= 5 V,

= 0,

V

= 3.3 V

69

mΩ

I(5V)

I(3.3 V)

96

I(5V)

I(3.3V)

§

Switch resistances

5 V to xVPP

3.3 V to xVPP

12 V to xVPP

4.74

0.724

0.275

1

Ω

V

Clamp low voltage

I

at 10 mA

= 25°C

A

V

O(xVPP)

pp

O(xVCC)

CC

I

High-impedance state

T

pp

I

Leakage current

µA

lkg

T

A

= 25°C

1

CC

V

= V

= 5 V,

= 12 V

O(AVCC)

O(AVPP)

O(BVCC)

O(BVPP)

V

= 5 V

= 0,

117

131

I(5V)

I

Input current

µA

V

= V

= 3.3 V,

= 0

I(5V)

I(3.3V)

O(AVCC)

O(AVPP)

O(BVCC)

O(BVPP)

= 3.3 V

§

Pulse-testing techniques are used to maintain junction temperature close to ambient temperature; thermal effects must be taken into account

separately.

6

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

†‡

switching characteristics

TPS2206Y

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

1.2

5

MAX

V

O(xVCC)

t

Output rise time

Output fall time

r

O(xVPP)

O(xVCC)

O(xVPP)

ms

10

f

14

t

4.4

18

ms

on

off

on

off

on

off

LATCH↑ to V

O(xVPP)

6.5

20

(3.3 V), V

(5 V)

= 5 V

O(xVCC)

I(5V)

t

pd

Propagation delay (see Figure 1)

5.7

25

t

on

off

6.6

21

ms

(3.3 V), V

= 0

I(5V)

t

†

‡

Refer to Parameter Measurement Information

Switching Characteristics are with C = 150 µF.

L

PARAMETER MEASUREMENT INFORMATION

V

pp

V

CC

C

L

LOAD CIRCUIT

V

DD

V

DD

50%

LATCH

GND

t

off

t

on

V

I(12V)

I(5V)

90%

V

O(xVCC)

V

O(xVPP)

10%

GND

VOLTAGE WAVEFORMS

Figure 1. Test Circuits and Voltage Waveforms

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

PARAMETER MEASUREMENT INFORMATION

Table of Timing Diagrams

FIGURE

Serial-Interface Timing

xVCC Propagation Delay and Rise Time With 1-µF Load, 3.3-V Switch, V

2

3

= 5 V

I(5V)

= 5 V

xVCC Propagation Delay and Fall Time With 1-µF Load, 3.3-V Switch, V

4

I(5V)

xVCC Propagation Delay and Rise Time With 150-µF Load, 3.3-V Switch, V

= 5 V

5

I(5V)

xVCC Propagation Delay and Fall Time With 150-µF Load, 3.3-V Switch, V

I(5V)

6

xVCC Propagation Delay and Rise Time With 1-µF Load, 3.3-V Switch, V

= 0

7

I(5V)

xVCC Propagation Delay and Fall Time With 1-µF Load, 3.3-V Switch, V

I(5V)

8

xVCC Propagation Delay and Rise Time With 150-µF Load, 3.3-V Switch, V

= 0

9

I(5V)

xVCC Propagation Delay and Fall Time With 150-µF Load, 3.3-V Switch, V

xVCC Propagation Delay and Rise Time With 1-µF Load, 5-V Switch

xVCC Propagation Delay and Fall Time With 1-µF Load, 5-V Switch

xVCC Propagation Delay and Rise Time With 150-µF Load, 5-V Switch

xVCC Propagation Delay and Fall Time With 150-µF Load, 5-V Switch

xVPP Propagation Delay and Rise Time With 1-µF Load, 12-V Switch

xVPP Propagation Delay and Fall Time With 1-µF Load, 12-V Switch

xVPP Propagation Delay and Rise Time With 150-µF Load, 12-V Switch

xVPP Propagation Delay and Fall Time With 150-µF Load, 12-V Switch

10

11

12

13

14

15

16

17

18

I(5V)

D8

D7

D6

D5

D4

D3

D2

D1

D0

DATA

LATCH

CLOCK

NOTE A: Data is clocked in on the positive leading edge of the clock. The latch should occur before the next positive leading edge of

the clock. For definition of D0 to D8, see the control logic table.

Figure 2. Serial-Interface Timing

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

PARAMETER MEASUREMENT INFORMATION

LATCH (2 V/div)

xVCC (2 V/div)

0

1

2

3

4

5

6

7

8

9

0

5

10 15 20 25 30 35 40 45

t − Time − ms

Figure 3. xVCC Propagation Delay and

Figure 4. xVCC Propagation Delay and

Rise Time With 1-µF Load, 3.3-V Switch,

Fall Time With 1-µF Load, 3.3-V Switch,

(V

= 5 V)

(V

= 5 V)

I(5V)

LATCH (2 V/div)

xVCC (2 V/div)

0

1

2

3

4

5

6

7

8

9

0

5

10 15 20 25 30 35 40 45

t − Time − ms

Figure 5. xVCC Propagation Delay and

Rise Time With 150-µF Load, 3.3-V Switch,

= 5 V

Figure 6. xVCC Propagation Delay and

Fall Time With 150-µF Load, 3.3-V Switch,

V

= 5 V

I(5V)

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

PARAMETER MEASUREMENT INFORMATION

LATCH (2 V/div)

xVCC (2 V/div)

0

1

2

3

4

5

6

7

8

9

0

5

10 15 20 25 30 35 40 45

t − Time − ms

Figure 7. xVCC Propagation Delay and

Figure 8. xVCC Propagation Delay and

Rise Time With 1-µF Load, 3.3-V Switch,

Fall Time With 1-µF Load, 3.3-V Switch,

V

= 0

V

= 0

I(5V)

LATCH (2 V/div)

xVCC (2 V/div)

0

5

10 15 20 25 30 35 40 45

t − Time − ms

0

1

2

3

4

5

6

7

8

9

t − Time − ms

Figure 10. xVCC Propagation Delay and

Figure 9. xVCC Propagation Delay and

Rise Time With 150-µF Load, 3.3-V Switch,

= 0

Fall Time With 150-µF Load, 3.3-V Switch,

V

= 0

V

I(5V)

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

PARAMETER MEASUREMENT INFORMATION

LATCH (2 V/div)

xVCC (2 V/div)

0

1

2

3

4

0

5

10 15 20 25 30 35 40 45

t − Time − ms

Figure 11. xVCC Propagation Delay and

Figure 12. xVCC Propagation Delay and

Rise Time With 1-µF Load, 5-V Switch

Fall Time With 1-µF Load, 5-V Switch

LATCH (2 V/div)

xVCC (2 V/div)

0

1

2

3

4

5

6

7

8

9

0

5

10 15 20 25 30 35 40 45

t − Time − ms

Figure 13. xVCC Propagation Delay and

Rise Time With 150-µF Load, 5-V Switch

Figure 14. xVCC Propagation Delay and

Fall Time With 150-µF Load, 5-V Switch

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

PARAMETER MEASUREMENT INFORMATION

LATCH (2 V/div)

xVPP (5 V/div)

0

1

2

3

4

5

6

7

8

9

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

t − Time − ms

Figure 16. xVPP Propagation Delay and

Figure 15. xVPP Propagation Delay and

Fall Time With 1-µF Load, 12-V Switch

Rise Time With 1-µF Load, 12-V Switch

LATCH (2 V/div)

xVPP (5 V/div)

0

1

2

3

4

5

6

7

8

9

0

5

10 15 20 25 30 35 40 45

t − Time − ms

Figure 18. xVPP Propagation Delay and

Fall Time With 150-µF Load, 12-V Switch

Figure 17. xVPP Propagation Delay and

Rise Time With 150-µF Load, 12-V Switch

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

I

Supply current, V

= 5 V

= 0

vs Junction temperature

vs Output current

19

20

21

22

23

24

25

26

27

28

29

30

31

DD

I(5V)

DD

I(5V)

r

Static drain-source on-state resistance, 3.3-V switch, V

Static drain-source on-state resistance, 5-V switch

Static drain-source on-state resistance, 12-V switch

Output voltage, 5-V switch

= 5 V

= 0

DS(on)

I(5V)

V

O(xVCC)

O(xVPP)

Output voltage, 3.3-V switch, V

Output voltage, 12-V switch

= 5 V

= 0

vs Output current

I(5V)

vs Output current

I(5V)

vs Output current

I

Short-circuit current, 5-V switch

Short-circuit current, 3.3-V switch

Short-circuit current, 12-V switch

vs Junction temperature

OS(xVCC)

OS(xVPP)

SUPPLY CURRENT

vs

SUPPLY CURRENT

vs

JUNCTION TEMPERATURE

155

V

= V

= 3.3 V

= 0 V

V

= V

= 5 V

O(BVCC)

O(AVCC)

O(AVPP)

I(5V)

O(BVCC)

O(BVPP)

O(AVCC)

O(AVPP)

= V

= 12 V

150

145

O(BVPP)

150

145

140

135

130

125

120

= 0

No load

140

135

130

125

120

115

110

115

110

−50 −25

0

25

50

75

100

125

−50 −25

0

25

50

75

100

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 19

Figure 20

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SLVS138D − MAY 1996 − REVISED JANUARY 2001

TYPICAL CHARACTERISTICS

3.3-V SWITCH

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

3.3-V SWITCH

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs

JUNCTION TEMPERATURE

220

V

= 5 V

= 3.3 V

V

= 0

= 3.3 V

I(5V)

I(3.3V)

= 3.3 V

I(5V)

I(3.3V)

= 3.3 V

200

CC

180

160

180

160

140

120

100

80

140

120

100

80

60

−50 −25

0

25

50

75

100

125

−50 −25

0

25

50

75

100

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 21

Figure 22

12-V SWITCH

5-V SWITCH

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs

JUNCTION TEMPERATURE

1100

vs

JUNCTION TEMPERATURE

240

V

= 5 V

V

= 5 V

I(5V)

= 5 V

I(5V)

= 12 V

220

200

180

160

CC

pp

1000

900

800

700

140

120

100

600

500

80

60

−50 −25

0

25

50

75

100

125

−50 −25

0

25

50

75

100

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 24

Figure 23

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ꢎ

ꢐ

ꢀ

ꢓ

ꢍ

ꢏ

ꢂ

ꢏ

ꢀ

ꢒ

ꢋꢍ

ꢂ

ꢏ

ꢍ

ꢐ

ꢈ

ꢉ

ꢁ

ꢌ

ꢔ

ꢌ

ꢐ

ꢈ

ꢌ

ꢋ

ꢑ

ꢀ

ꢍ

ꢋ

ꢉ

ꢏ

ꢍ

SLVS138D − MAY 1996 − REVISED JANUARY 2001

TYPICAL CHARACTERISTICS

3.3-V SWITCH

OUTPUT VOLTAGE

vs

5-V SWITCH

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

3.3

3.27

3.24

3.21

5

4.95

4.9

25°C

−40°C

25°C

−40°C

85°C

125°C

4.85

4.8

3.18

3.15

V

= 5 V

I(5V)

V

= 5 V

I(5V)

CC

= 3.3 V

I(3.3V)

CC

0

0.2

0.4

O(xVCC)

0.6

0.8

1

0

0.2

I

0.4

0.6

0.8

1

I

− Output Current − A

O(xVCC)

Figure 25

Figure 26

12-V SWITCH

3.3-V SWITCH

OUTPUT VOLTAGE

vs

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

3.3

12

11.98

11.96

11.94

11.92

11.9

−40°C

25°C

3.25

85°C

3.2

3.15

3.1

125°C

V

= 5 V

I(5 V)

= 12 V

V

= 0 V

= 3.3 V

I(5 V)

CC

PP

0

0.03

I

0.06

0.09

0.12

0

0.2

0.4

0.6

0.8

1

− Output Current − A

I

− Output Current − A

O(xVPP)

O(xVCC)

Figure 27

Figure 28

15

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ꢎꢐ ꢀ ꢓ ꢍ ꢏꢂꢏ ꢀ ꢒ ꢋ ꢍ ꢂ ꢏꢍ ꢐ ꢈꢉ ꢁ ꢌꢔꢌ ꢐ ꢈ ꢌꢋ ꢑꢀ ꢍꢋ ꢉ ꢉꢏ ꢍ

SLVS138D − MAY 1996 − REVISED JANUARY 2001

TYPICAL CHARACTERISTICS

5-V SWITCH

3.3-V SWITCH

SHORT-CIRCUIT CURRENT

vs

SHORT-CIRCUIT CURRENT

vs

JUNCTION TEMPERATURE

2

1.8

1.6

1.4

1.2

2

1.8

1.6

1.4

1.2

V

= 5 V

V

= 0

I(5V)

= 5 V

I(5V)

= 3.3 V

CC

I(3.3V)

= 3.3 V

CC

1

0.8

−50 −25

0.8

−50 −25

0

25

50

75

100

125

0

25

50

75

100

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 29

Figure 30

12-V SWITCH

SHORT-CIRCUIT CURRENT

vs

JUNCTION TEMPERATURE

0.32

0.3

V

= 5 V

I(5V)

= 12 V

pp

0.28

0.26

0.24

0.22

0.2

−50

−25

0

25

50

75

100

125

T

J

− Junction Temperature − °C

Figure 31

16

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ꢎ ꢐꢀ ꢓ ꢍꢏꢂ ꢏꢀ ꢒ ꢋꢍ ꢂꢏ ꢍꢐꢈ ꢉ ꢁꢌ ꢔꢌꢐ ꢈ ꢌꢋ ꢑ ꢀꢍ ꢋꢉ ꢉꢏ ꢍ

SLVS138D − MAY 1996 − REVISED JANUARY 2001

APPLICATION INFORMATION

overview

PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with

limited on-board memory. The idea of add-in cards quickly took hold; modems, wireless LANs, Global

Positioning Satellite System (GPS), multimedia, and hard-disk versions were soon available. As the number

of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure

compatibility across platforms. To this end, the PCMCIA was established, comprised of members from leading

computer, software, PC Card, and semiconductor manufacturers. One key goal was to realize the plug-and-play

concept. Cards and hosts from different vendors should be compatible—able to communicate with one another

transparently.

PC Card power specification

System compatibility also means power compatibility. The most current set of specifications (PC Card Standard)

set forth by the PCMCIA committee states that power is to be transferred between the host and the card through

eight of the 68 terminals of the PC Card connector. This power interface consists of two V , two V , and four

CC

pp

ground terminals. Multiple V

and ground terminals minimize connector-terminal and line resistance. The two

CC

V

terminals were originally specified as separate signals but are commonly tied together in the host to form

a single node to minimize voltage losses. Card primary power is supplied through the V

pp

terminals;

CC

flash-memory programming and erase voltage is supplied through the V terminals.

pp

designing for voltage regulation

The current PCMCIA specification for output-voltage regulation (V

) of the 5-V output is 5% (250 mV). In

O(reg)

a typical PC power-system design, the power supply has an output-voltage regulation (V

) of 2% (100 mV).

PS(reg)

Also, a voltage drop from the power supply to the PC Card will result from resistive losses (V

) in the PCB

PCB

traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than

1% (50 mV) of the output voltage. Therefore, the allowable voltage drop (V ) for the TPS2206 would be the

DS

PCMCIA voltage regulation less the power supply regulation and less the PCB and connector resistive drops:

V

+ V

–V

Ǔ

(1)

ǒ

Ǔ

ǒ

DS

O reg PS reg PCB

Typically, this would leave 100 mV for the allowable voltage drop across the TPS2206. The voltage drop is the

output current multiplied by the switch resistance of the TPS2206. Therefore, the maximum output current that

can be delivered to the PC Card in regulation is the allowable voltage drop across the TPS2206 divided by the

output switch resistance.

V

DS

ǒ

I max +

(2)

r

O

Ǔ

DS on

The xVCC outputs have been designed to deliver 700 mA at 5 V within regulation over the operating temperature

range. Current proposals for the PCMCIA specifications are to limit the power dissipated in the PCMCIA slot

to 3 W. With an input voltage of 5 V, 700 mA continuous is the maximum current that can be delivered to the

PC Card. The TPS2206 is capable of delivering up to 1 A continuously, but during worst-case conditions the

output may not be within regulation. This is generally acceptable because the majority of PC Cards require less

than 700 mA continuous. Some cards require higher peak currents (disk drives during initial platter spin-up),

but it is generally acceptable for small voltage sags to occur during these peak currents.

The xVCC outputs have been designed to deliver 1 A continuously at 3.3 V within regulation over the operating

temperature range. The PCMCIA specification for output voltage regulation of the 3.3-V output is 300 mV. Using

the voltage drop percentages (2%) for power supply regulation and PCB resistive loss (1%), the allowable

voltage drop for the 3.3 V switch is 200 mV.

The xVPP outputs have been designed to deliver 150 mA continuously at 12 V.

17

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ꢎꢐ ꢀ ꢓ ꢍ ꢏꢂꢏ ꢀ ꢒ ꢋ ꢍ ꢂ ꢏꢍ ꢐ ꢈꢉ ꢁ ꢌꢔꢌ ꢐ ꢈ ꢌꢋ ꢑꢀ ꢍꢋ ꢉ ꢉꢏ ꢍ

SLVS138D − MAY 1996 − REVISED JANUARY 2001

APPLICATION INFORMATION

overcurrent and overtemperature protection

PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection

against short-circuited cards that could lead to power supply or PCB-trace damage. Even systems robust

enough to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card,

resulting in the rather sudden and unacceptable loss of system power. Most hosts include fuses for protection.

However, the reliability of fused systems is poor, as blown fuses require troubleshooting and repair, usually by

the manufacturer.

The TPS2206 takes a two-pronged approach to overcurrent protection. First, instead of fuses, sense FETs

monitor each of the power outputs. Excessive current generates an error signal that linearly limits the output

current, preventing host damage or failure. Sense FETs, unlike sense resistors or polyfuses, have an added

advantage in that they do not add to the series resistance of the switch and thus produce no additional voltage

losses. Second, when an overcurrent condition is detected, the TPS2206 asserts a signal at OC that can be

monitored by the microprocessor to initiate diagnostics and/or send the user a warning message. In the event

that an overcurrent condition persists, causing the IC to exceed its maximum junction temperature,

thermal-protection circuitry activates, shutting down all power outputs until the device cools to within a safe

operating region.

12-V supply not required

Most PC Card switches use the externally supplied 12-V V power for switch-gate drive and other chip functions,

pp

which requires that power be present at all times. The TPS2206 offers considerable power savings by using

an internal charge pump to generate the required higher voltages from the 5-V or 3.3-V input; therefore, the

external 12-V supply can be disabled except when needed for flash-memory functions, thereby extending

battery lifetime. Do not ground the 12-V input if the 12-V input is not used. Additional power savings are realized

by the TPS2206 during a software shutdown in which quiescent current drops to a maximum of 1 µA.

backward compatibility and 3.3-V low-voltage mode

The TPS2206 is backward compatible with the TPS2202 AND TPS2202A products, with the following

considerations. Pin 25 (V

on TPS2202/TPS2202A) is a no connect because bias current is derived from

DD

either the 3.3-V input pin or the 5-V input pin. Also, the TPS2206 does not have the APWR_GOOD or

BPWR_GOOD VPP reporting outputs. These are left as no connects.

The TPS2206 operates in 3.3-V low-voltage mode when 3.3 volts is the only available input voltage (V

=0).

I(5V)

This allows host and PC Cards to be operated in low-power 3.3-V-only modes such as sleep modes or pager

modes. Note that in this operation mode, the TPS2206 derives its bias current from the 3.3-V input pin and only

3.3 V can be delivered to the PC Card. The 3.3-V switch resistance increases, but the added switch resistance

should not be critical, because only a small amount of current is delivered in this mode. If 6% (198 mV) is allowed

for the 3.3-V switch voltage drop, a 500-mΩ switch could deliver over 350 mA to the PC Card.

voltage transitioning requirement

PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space,

and increase logic speeds. The TPS2206 is designed to meet all combinations of power delivery as currently

defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering

the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the

capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This ensures

that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. The

TPS2206 offers a selectable V

specifications, to fully discharge the card capacitors while switching between V

and V ground state, in accordance with PCMCIA 3.3-V/5-V switching

CC

pp

voltages.

CC

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢃ ꢄꢅ

ꢆꢇꢈ ꢉꢊꢂ ꢉꢋ ꢀ ꢁꢌ ꢌꢈꢍ ꢆ ꢁꢋ ꢎ ꢏꢍꢊꢐ ꢑꢀ ꢏꢍꢒꢈꢌ ꢏ ꢂ ꢎꢐ ꢀꢌ ꢓ

ꢎ ꢐꢀ ꢓ ꢍꢏꢂ ꢏꢀ ꢒ ꢋꢍ ꢂꢏ ꢍꢐꢈ ꢉ ꢁꢌ ꢔꢌꢐ ꢈ ꢌꢋ ꢑ ꢀꢍ ꢋꢉ ꢉꢏ ꢍ

SLVS138D − MAY 1996 − REVISED JANUARY 2001

APPLICATION INFORMATION

output ground switches

Several PCMCIA power-distribution switches on the market do not have an active-grounding FET switch. These

devices do not meet the PC Card specification requiring a discharge of V within 100 ms. PC Card resistance

CC

can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible

high-impedance isolation by power-management schemes. A method commonly shown to alleviate this

problem is to add to the switch output an external 100-kΩ resistor in parallel with the PC Card. Considering that

this is the only discharge path to ground, a timing analysis shows that the RC time constant delays the required

discharge time to more than 2 seconds. The only way to ensure timing compatibility with PC Card standards

is to use a power-distribution switch that has an internal ground switch, like that of the TPS22xx family, or add

an external ground FET to each of the output lines with the control logic necessary to select it.

In summary, the TPS2206 is a complete single-chip dual-slot PC Card power interface. It meets all currently

defined PCMCIA specifications for power delivery in 5-V, 3.3-V, and mixed systems, and offers a serial control

interface. The TPS2206 offers functionality, power savings, overcurrent and thermal protection, and fault

reporting in one 30-pin SSOP surface-mount package for maximum value added to new portable designs.

power-supply considerations

The TPS2206 has multiple pins for each of its 3.3-V, 5-V, and 12-V power inputs and for the switched V

CC

outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in

parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops and

lost power. Both 12-V inputs must be connected for proper V switching; it is recommended that all input and

pp

output power pins be paralleled for optimum operation.

Although the TPS2206 is fairly immune to power input fluctuations and noise, it is generally considered good

design practice to bypass power supplies typically with a 1-µF electrolytic or tantalum capacitor paralleled by

a 0.047-µF to 0.1-µF ceramic capacitor. It is strongly recommended that the switched V

and V outputs be

CC

pp

bypassed with a 0.1-µF or larger capacitor; doing so improves the immunity of the TPS2206 to electrostatic

discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the TPS2206 and

the load. High switching currents can produce large negative-voltage transients, which forward biases substrate

diodes, resulting in unpredictable performance. Similary, no pin should be taken below −0.3 V.

RESET or RESET inputs

To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should

be reset at the same time as the host by applying a low impedance to the V

and V terminals. A

CC

pp

low-impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance,

permitting the system (host and PC Cards) to be powered up concurrently. The RESET or RESET input closes

internal switches S1, S4, S7, and S10 with all other switches left open (see TPS2206 control-logic table). The

TPS2206 remains in the low-impedance output state until the signal is deasserted and further data is clocked

in and latched. RESET or RESET is provided for direct compatibility with systems that use either an active-low

or active-high reset voltage supervisor. The unused pin is internally pulled up or down and should be left

unconnected.

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃ ꢃꢄ ꢅ

ꢆ ꢇꢈꢉ ꢊꢂꢉ ꢋꢀ ꢁꢌ ꢌꢈ ꢍꢆ ꢁ ꢋꢎ ꢏꢍ ꢊꢐ ꢑꢀ ꢏꢍ ꢒꢈꢌꢏ ꢂꢎ ꢐ ꢀꢌ ꢓ

ꢎꢐ ꢀ ꢓ ꢍ ꢏꢂꢏ ꢀ ꢒ ꢋ ꢍ ꢂ ꢏꢍ ꢐ ꢈꢉ ꢁ ꢌꢔꢌ ꢐ ꢈ ꢌꢋ ꢑꢀ ꢍꢋ ꢉ ꢉꢏ ꢍ

SLVS138D − MAY 1996 − REVISED JANUARY 2001

APPLICATION INFORMATION

overcurrent and thermal protection

The TPS2206 uses sense FETs to check for overcurrent conditions in each of the V

and V outputs. Unlike

pp

CC

sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage

and power losses are reduced. Overcurrent sensing is applied to each output separately. When an overcurrent

condition is detected, only the power output affected is limited; all other power outputs continue to function

normally. The OC indicator, normally a logic high, is a logic low when any overcurrent condition is detected,

providing for initiation of system diagnostics and/or sending a warning message to the user.

During power up, the TPS2206 controls the rise time of the V and V outputs and limits the current into a faulty

CC

pp

card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card), current

is initially limited only by the impedance between the short and the power supply. In extreme cases, as much

as 10 A to 15 A may flow into the short before the current limiting of the TPS2206 engages. If the V

or V

pp

CC

outputs are driven below ground, the TPS2206 may latch nondestructively in an off state. Cycling power will

reestablish normal operation.

Overcurrent limiting for the V

outputs is designed to activate, if powered up, into a short in the range of

CC

1 A to 2.2 A, typically at about 1.6 A. The V outputs limit from 120 mA to 400 mA, typically around 280 mA.

pp

The protection circuitry acts by linearly limiting the current passing through the switch rather than initiating a full

shutdown of the supply. Shutdown occurs only during thermal limiting.

Thermal limiting prevents destruction of the IC from overheating if the package power-dissipation ratings are

exceeded. Thermal limiting disables all power outputs (both A and B slots) until the device has cooled.

calculating junction temperature

The switch resistance, r

is dependent on both r

, is dependent on the junction temperature, T , of the die. The junction temperature

J

DS(on)

and the current through the switch. To calculate T , first find r

from Figures

J

DS(on)

21, 22, 23, and 24 using an initial temperature estimate about 50°C above ambient. Then calculate the power

dissipation for each switch, using the formula:

2

P

+ r

I

(3)

D

DS(on)

Next, sum the power dissipation and calculate the junction temperature:

_TJ₊ǒ_{S P}

_qJAǓ_{) T , R}

A qJA

°

+ 108 CńW

R

(4)

D

Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not

within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.

logic input and outputs

The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive leading

edge of the clock (see Figure 2). The 9-bit (D0 through D8) serial data word is loaded during the positive edge

of the latch signal. The latch signal should occur before the next positive leading edge of the clock.

The shutdown bit of the data word places all V

and V outputs in a high-impedance state and reduces chip

pp

CC

quiescent current to 1 µA to conserve battery power.

The TPS2206 serial interface is designed to be compatible with serial-interface PCMCIA controllers and current

PCMCIA and Japan Electronic Industry Development Association (JEIDA) standards.

An overcurrent output (OC) is provided to indicate an overcurrent condition in any of the V

previously discussed.

or V outputs as

pp

CC

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢃ ꢄꢅ

ꢆꢇꢈ ꢉꢊꢂ ꢉꢋ ꢀ ꢁꢌ ꢌꢈꢍ ꢆ ꢁꢋ ꢎ ꢏꢍꢊꢐ ꢑꢀ ꢏꢍꢒꢈꢌ ꢏ ꢂ ꢎꢐ ꢀꢌ ꢓ

ꢎ ꢐꢀ ꢓ ꢍꢏꢂ ꢏꢀ ꢒ ꢋꢍ ꢂꢏ ꢍꢐꢈ ꢉ ꢁꢌ ꢔꢌꢐ ꢈ ꢌꢋ ꢑ ꢀꢍ ꢋꢉ ꢉꢏ ꢍ

SLVS138D − MAY 1996 − REVISED JANUARY 2001

APPLICATION INFORMATION

TPS2206

Card A

S7

V

pp1

S8

S9

S1

S2

pp2

V

CC

S3

3.3V

CS

CC

See Note A

CS

Card B

CC

S4

S5

S6

3.3V

CS

V

CC

S10

5V

S11

S12

V

pp1

CS

pp2

5V

12V

See Note A

Internal

Current Monitor

RESET

Supervisor

Controller

RESET

Thermal

DATA

CLOCK

LATCH

Serial

Interface

GND

CPU

OC

NOTE A: MOSFET switches S9 and S12 have a back-gate diode from the source to the drain. Unused switch inputs should never be grounded.

Figure 32. Internal Switching Matrix

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃ ꢃꢄ ꢅ

ꢆ ꢇꢈꢉ ꢊꢂꢉ ꢋꢀ ꢁꢌ ꢌꢈ ꢍꢆ ꢁ ꢋꢎ ꢏꢍ ꢊꢐ ꢑꢀ ꢏꢍ ꢒꢈꢌꢏ ꢂꢎ ꢐ ꢀꢌ ꢓ

ꢎꢐ ꢀ ꢓ ꢍ ꢏꢂꢏ ꢀ ꢒ ꢋ ꢍ ꢂ ꢏꢍ ꢐ ꢈꢉ ꢁ ꢌꢔꢌ ꢐ ꢈ ꢌꢋ ꢑꢀ ꢍꢋ ꢉ ꢉꢏ ꢍ

SLVS138D − MAY 1996 − REVISED JANUARY 2001

APPLICATION INFORMATION

TPS2206 control logic

AVPP

CONTROL SIGNALS

INTERNAL SWITCH SETTINGS

S8

OUTPUT

VAVPP

0 V

D8 SHDN

D0 A_VPP_PGM D1 A_VPP_VCC

S7

S9

1

0

1

X

0

1

0

1

X

CLOSED

OPEN

CLOSED

OPEN

CLOSED

OPEN

†

VCC

VPP(12 V)

Hi-Z

OPEN

Hi-Z

BVPP

CONTROL SIGNALS

INTERNAL SWITCH SETTINGS

S11

OUTPUT

VBVPP

0 V

D8 SHDN

D4 B_VPP_PGM D5 B_VPP_VCC

S10

S12

OPEN

CLOSED

OPEN

1

0

1

X

0

1

0

1

X

CLOSED

OPEN

CLOSED

OPEN

‡

VCC

VPP(12 V)

Hi-Z

OPEN

Hi-Z

AVCC

CONTROL SIGNALS

INTERNAL SWITCH SETTINGS

S2

OUTPUT

VAVCC

0 V

D8 SHDN

D3 A_VCC3

D2 A_VCC5

S1

S3

1

0

1

X

0

1

0

1

X

CLOSED

OPEN

CLOSED

OPEN

CLOSED

OPEN

3.3 V

5 V

OPEN

CLOSED

OPEN

0 V

OPEN

Hi-Z

BVCC

CONTROL SIGNALS

INTERNAL SWITCH SETTINGS

S5

OUTPUT

VBVCC

0 V

D8 SHDN

D6 B_VCC3

D7 B_VCC5

S4

S6

1

0

1

X

0

1

0

1

X

CLOSED

OPEN

CLOSED

OPEN

CLOSED

OPEN

3.3 V

5 V

OPEN

CLOSED

OPEN

0 V

OPEN

Hi-Z

†

‡

Output depends on AVCC

Output depends on BVCC

ESD protection

All TPS2206 inputs and outputs incorporate ESD-protection circuitry designed to withstand a 2-kV

human-body-model discharge as defined in MIL-STD-883C, Method 3015. The V and V outputs can be

CC

pp

exposed to potentially higher discharges from the external environment through the PC Card connector.

Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV.

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂ ꢃꢃ ꢄꢅ

ꢆꢇꢈ ꢉꢊꢂ ꢉꢋ ꢀ ꢁꢌ ꢌꢈꢍ ꢆ ꢁꢋ ꢎ ꢏꢍꢊꢐ ꢑꢀ ꢏꢍꢒꢈꢌ ꢏ ꢂ ꢎꢐ ꢀꢌ ꢓ

ꢎ ꢐꢀ ꢓ ꢍꢏꢂ ꢏꢀ ꢒ ꢋꢍ ꢂꢏ ꢍꢐꢈ ꢉ ꢁꢌ ꢔꢌꢐ ꢈ ꢌꢋ ꢑ ꢀꢍ ꢋꢉ ꢉꢏ ꢍ

SLVS138D − MAY 1996 − REVISED JANUARY 2001

APPLICATION INFORMATION

AVCC

V

CC

0.1 µF

AVCC

PC Card

Connector A

12 V

12V

+

V

pp1

V

pp2

0.1 µF

10 µF

BVCC

V

CC

TPS2206

0.1 µF

V

PC Card

Connector B

V

pp1

V

pp2

AVPP

5V

5 V

+

0.1 µF

33 µF

BVPP

0.1 µF

3.3V

3.3 V

DATA

CLOCK

LATCH

CLOCK

LATCH

System Voltage

Supervisor

or

RESET

PCMCIA

Controller

PCI Bus Reset

OC

To CPU

GND

CS

Shutdown Signal

From CPU

Figure 33. Detailed Interconnections and Capacitor Recommendations

23

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ꢀ ꢁ ꢂ ꢃ ꢃꢄ ꢅ

ꢆ ꢇꢈꢉ ꢊꢂꢉ ꢋꢀ ꢁꢌ ꢌꢈ ꢍꢆ ꢁ ꢋꢎ ꢏꢍ ꢊꢐ ꢑꢀ ꢏꢍ ꢒꢈꢌꢏ ꢂꢎ ꢐ ꢀꢌ ꢓ

ꢎꢐ ꢀ ꢓ ꢍ ꢏꢂꢏ ꢀ ꢒ ꢋ ꢍ ꢂ ꢏꢍ ꢐ ꢈꢉ ꢁ ꢌꢔꢌ ꢐ ꢈ ꢌꢋ ꢑꢀ ꢍꢋ ꢉ ꢉꢏ ꢍ

SLVS138D − MAY 1996 − REVISED JANUARY 2001

APPLICATION INFORMATION

12-V flash memory supply

The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as

2.7 V. The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower

supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 1, the only

external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter

2

capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in of PCB

space when implemented with surface-mount components. An enable input is provided to shut the converter

down and reduce the supply current to 3 µA when 12 V is not needed.

The TPS6734 is a 170-kHz current-mode PWM ( pulse-width modulation) controller with an n-channel MOSFET

power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area

needed to realize the 0.7-Ω MOSFET and improve efficiency at input voltages below 5 V. Soft start is

accomplished with the addition of one small capacitor. A 1.22-V reference (pin 2) is brought out for external use.

For additional information, see the TPS6734 data sheet (SLVS127).

3.3 V or 5 V

R1

10 kΩ

TPS6734

AVCC

1

8

V

EN

CC

+

L1

ENABLE

(see Note A)

C1

18 µH

33 µF, 20 V

2

3

4

7

6

5

FB

OUT

GND

REF

SS

U1

D1

C5

12 V

BVCC

12V

COMP

+

C2

0.01 µF

TPS2206

33 µF, 20 V

AVPP

C4 0.001 µF

BVPP

5V

5 V

0.1 µF

33 µF

DATA

CLOCK

LATCH

3.3V

3.3 V

0.1 µF

33 µF

RESET

OC

To CPU

GND

NOTE A: The enable terminal can be tied to a generall purpose I/O terminal on the PCMCIA controller or tied high.

Figure 34. TPS2206 with TPS6734 12-V, 120-mA Supply

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Feb-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS2206IDAPR

TPS2206IDBR

HTSSOP

SSOP

DAP

DB

32

30

2000

330.0

24.4

16.4

8.6

8.2

11.5

10.5

1.6

2.5

12.0

24.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Feb-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS2206IDAPR

TPS2206IDBR

HTSSOP

SSOP

DAP

DB

32

30

2000

367.0

45.0

38.0

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS2206IDBR
厂家：	TEXAS INSTRUMENTS
描述：	DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER 带复位用于串行PCMCIA控制器的双槽PC卡开机界面切换控制器 PC
文件：	总33页 (文件大小：1204K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS2206IDBR [TI]

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